Soft switching circuit conduction loss optimization method and application

Abstract

The invention provides a soft switching circuit conduction loss optimization method and application thereof, and the soft switching circuit comprises an energy storage capacitor and an inductor, and is used for charging an equivalent parasitic capacitor of a switching node of a power level circuit to realize zero-voltage switching of the power level circuit. The soft switching circuit conduction loss optimization method comprises the following steps: S1, determining a time sequence waveform of soft switching circuit inductive current at different stages in a switching period; s2, obtaining a theoretical value of the conduction loss of the soft switch in a switching period according to the time sequence waveform of the inductive current; s3, determining the relation between the soft switching conduction loss and the energy storage capacitor voltage according to the time sequence waveform of the inductive current and the conduction loss theoretical value, and determining an energy storage capacitor voltage regulation and control target; and S4, adjusting the charging time of the energy storage capacitor according to the regulation and control target so as to stabilize the voltage of the energy storage capacitor at the regulation and control target, and optimizing the conduction loss of the soft switching circuit in real time.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technology, and in particular to a method and application for optimizing conduction loss of a soft switching circuit. Background Art

[0002] When the high-voltage DC-DC converter works in hard switching mode, the switching loss caused by the large input voltage and high-voltage power tube parasitic capacitance seriously limits the conversion efficiency. Soft switching technology is usually used to eliminate switching losses and improve conversion efficiency. The existing soft switching control method achieves an ideal soft switching state through charge control, that is, no partial or excessive soft switching state occurs, but does not optimize the conduction loss of the soft switching circuit. Summary of the invention

[0003] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides a method and application for optimizing conduction loss of a soft switching circuit.

[0004] In order to achieve the above purpose, the technical solution of the present invention is as follows:

[0005] According to an embodiment of one aspect of the present disclosure, a method for optimizing conduction losses of a soft switching circuit is provided. The soft switching circuit includes an energy storage capacitor and an inductor, and is used to charge the equivalent parasitic capacitance of the switch node of the power stage circuit to realize zero voltage switching of the power stage circuit. The method for optimizing conduction losses of the soft switching circuit includes operations S1-S4: Operation S1: determining the timing waveform of the inductor current of the soft switching circuit at different stages in a switching cycle; Operation S2: obtaining a theoretical value of the conduction loss of the soft switch in a switching cycle according to the timing waveform of the inductor current; Operation S3: determining the relationship between the conduction loss of the soft switch and the voltage of the energy storage capacitor according to the timing waveform of the inductor current and the theoretical value of the conduction loss, and determining a voltage control target of the energy storage capacitor; Operation S4: adjusting the charging time of the energy storage capacitor according to the control target to stabilize the voltage of the energy storage capacitor at the control target, thereby realizing real-time optimization of the conduction loss of the soft switching circuit.

[0006] According to an embodiment of the present disclosure, operation S1 includes: operation S11: dividing a switching cycle into four time periods: a pre-magnetization period, a dead period, a power replenishment period, and a demagnetization period; and operation S12: respectively determining the waveforms of the inductor current in the four time periods to obtain a timing waveform of the inductor current within a switching cycle.

[0007] According to the embodiment of the present disclosure, the pre-magnetization period represents the time period when the current in the inductor rises; the dead period represents the time period when the equivalent parasitic capacitance of the power stage circuit switch node is charged; the replenishment period represents the time period when the energy storage capacitor is replenished; and the demagnetization period represents the time period when the current in the inductor decreases.

[0008] According to the embodiment of the present disclosure, the timing waveform expression of the inductor current of the soft switching circuit at different stages in a switching cycle is:

[0009]

[0010] Among them, V IN Indicates input voltage, V CZVS Represents the voltage of the energy storage capacitor, L ZVS represents inductance, w ZVS represents the resonant frequency of the equivalent parasitic capacitance of the inductor and the switch node, t represents time, t1~t2 represents the pre-magnetization period, t2~t3 represents the dead time period, t3~t4 represents the charging period, t4~t5 represents the demagnetization period, I0 represents the load current, I L1 represents the initial current during the dead time period, I L2 Indicates the initial current during the charging period, I L3 Indicates the initial current during the demagnetization period.

[0011] According to an embodiment of the present disclosure, in operation S2, a theoretical value of soft switch conduction loss is obtained by integrating the square of the soft switch current in one switching cycle.

[0012] According to the embodiment of the present disclosure, in operation S3, the soft switch conduction loss is related to |V IN -2V CZVS | Proportional to the input voltage V IN unchanged, so the energy storage capacitor voltage V CZVS The regulation target is 0.5 times the input voltage.

[0013] According to an embodiment of the present disclosure, operation S4 includes: operation S41: detecting in real time whether the voltage value of the energy storage capacitor deviates from the control target; and operation S42: adjusting the energy stored in the energy storage capacitor by increasing or decreasing the charging time so that the voltage of the energy storage capacitor is stable at the control target.

[0014] According to an embodiment of the present disclosure, the soft switching circuit further includes an auxiliary switch network and a control circuit, wherein the control circuit is used to control the on and off of the auxiliary switch network to achieve low conduction loss operation of the soft switching circuit.

[0015] According to the embodiment of the present disclosure, the power stage circuit is of boost type, buck type or boost / buck type.

[0016] According to an embodiment of another aspect of the present disclosure, there is provided an application of the above-mentioned soft switching circuit conduction loss optimization method in a converter, wherein the converter is selected from a buck converter, a boost converter, a boost / buck converter, and a combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0018] Figure 1 It is a conventional step-down DC-DC converter;

[0019] Figure 2 is a schematic diagram of a soft-switching DC-DC converter in the prior art;

[0020] Figure 3 It is a schematic diagram of the working principle of the soft switch control circuit in the prior art;

[0021] Figure 4 is a schematic diagram of a soft switching circuit and a power stage circuit according to an embodiment of the present disclosure;

[0022] Figure 5 A flow chart of a method for optimizing conduction loss of a soft switching circuit according to an embodiment of the present disclosure;

[0023] Figure 6 A schematic diagram of the timing waveform of the inductor current and the voltage of the switch tube in the power stage circuit according to an embodiment of the present disclosure;

[0024] Figure 7a Schematic diagram of soft switch working waveform under different energy storage capacitor voltages according to an embodiment of the present disclosure;

[0025] Figure 7b A schematic diagram of conduction loss of a soft switching circuit under different energy storage capacitor voltages according to an embodiment of the present disclosure;

[0026] Figure 8 A schematic diagram of the principle of adjusting the charging time of the energy storage capacitor according to an embodiment of the present disclosure;

[0027] Fig. 9 In the embodiment of the present disclosure, when the load current jumps from light load to heavy load, the charging time is adjusted to adjust the energy storage capacitor voltage V CZVS Modulated at 0.5V IN Schematic diagram of DETAILED DESCRIPTION

[0028] The present disclosure provides a method and application for optimizing conduction loss of a soft switching circuit, which optimizes the additional conduction loss caused by the soft switching circuit by modulating the voltage value of an energy storage capacitor, thereby improving conversion efficiency.

[0029] When the high-voltage DC-DC converter works in hard switching mode, the switching loss caused by the large parasitic capacitance of the high-voltage power tube seriously limits the conversion efficiency. For traditional step-down DC-DC converters, such as Figure 1 As shown, the equivalent parasitic capacitance of the switch node SW is C SW, the switching loss caused by the large input capacitor charging the parasitic capacitor is:

[0030] ;

[0031] Switching loss and switch node parasitic capacitance C SW , switching frequency f s 、Input voltage V IN The switching loss cannot be ignored under high voltage and high frequency conditions. In addition, during the switching process of the power tube, there is also VI overlap loss caused by the source-drain voltage and the drain current. This loss is proportional to the current and input voltage. The overlap loss cannot be ignored under high voltage conditions, which limits the conversion efficiency.

[0032] In high-voltage and high-frequency applications, soft switching technology is usually used to eliminate the switching loss of the power tube to improve conversion efficiency. Using lossless inductive energy storage elements, the inductive current is introduced to build an efficient charging and discharging path, and the parasitic capacitance C of the switch node is increased during the dead time. SW Charge and discharge, so that the source-drain voltage is zero, achieving zero voltage switching, thereby eliminating the switching loss of the power tube. Soft switching circuits will introduce additional conduction losses. How to achieve optimal loss control is of great significance to improving the efficiency of soft switching DC-DC converters. Reference paper: [J. Yuan, Q. Min, Z. Liu, X. Han and L.Cheng, "A 12V-to-42V Input Zero-Voltage Switching Buck Converter Achieving Upto 4.5% Efficiency Improvement," 2024 IEEE European Solid-State ElectronicsResearch Conference (ESSERC), Bruges, Belgium, 2024, pp.69-72, doi:10.1109 / ESSERC62670.20 24.10719417.].

[0033] Existing soft-switching DC-DC converters such as Figure 2 As shown, it includes: a power stage circuit 101, a soft switch circuit 102. The soft switch circuit 102 is composed of an auxiliary switch network 1021, a soft switch control circuit 1022 and an auxiliary inductor L ZVS , energy storage capacitor C ZVS Its working principle is as follows Figure 3 As shown: By detecting the switching state of the switch node SW, the charging and replenishing time of the soft switching circuit is adjusted to adjust the energy storage capacitor C in the soft switching circuit ZVSThe stored energy can realize the ideal soft switching process under different conditions. If it is detected that the switch node SW is in a partial soft switching state, that is, the switch node voltage V SW Always less than the input voltage V IN , indicating that the amount of charge stored in the soft switching circuit topology is too small. The next cycle will extend the soft switching circuit charging time to increase the soft switching topology storage energy. If the switch node is detected to be in an excessive soft switching state, that is, the switch node voltage V SW Higher than the input voltage V IN , indicating that the soft switching circuit topology stores too much charge. The next cycle will shorten the soft switching charging time and reduce the energy stored in the soft switching topology.

[0034] The above method detects the switch state of the switch node SW and adjusts the charging time of the soft switch circuit to adjust the energy storage capacitor C of the soft switch circuit. ZVS The stored energy realizes the soft switching process under different conditions. Although this work ensures the precise control of the charge, that is, soft switching is realized without excess charge, it does not analyze the conduction loss of the soft switching circuit, does not optimize the conduction loss of the soft switching circuit, and the conversion efficiency needs to be further improved.

[0035] Therefore, the present invention provides a method and application for optimizing the conduction loss of a soft switching circuit, which is used to reduce the additional conduction loss caused by the soft switching circuit, thereby improving the conversion efficiency of a converter based on the soft switching circuit (such as a soft switching DC-DC converter). The inventor analyzes the conduction loss of the soft switching circuit and finds that the conduction loss of the soft switching circuit is related to |V IN -2V CZVS | is positively correlated, so by modulating the energy storage capacitor C ZVS The voltage drop is reduced and the additional conduction loss caused by the soft switching circuit is optimized, thereby improving the conversion efficiency.

[0036] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0037] In the embodiment of the present disclosure, Figure 5 and Figure 4 As shown, a method for optimizing conduction loss of a soft switching circuit is provided. The soft switching circuit is used to optimize the equivalent parasitic capacitance C of the switch node SW of the power stage circuit. SWCharging is performed to realize zero voltage switching of the power stage circuit 201. The above-mentioned soft switching circuit conduction loss optimization method includes operations S1-S4: Operation S1: determining the timing waveform of the inductor current of the soft switching circuit at different stages in a switching cycle; Operation S2: obtaining the theoretical value of the soft switching conduction loss in a switching cycle according to the timing waveform of the inductor current; Operation S3: determining the relationship between the soft switching conduction loss and the energy storage capacitor voltage according to the timing waveform of the inductor current and the conduction loss theoretical value and determining the energy storage capacitor voltage control target; Operation S4: adjusting the energy storage capacitor replenishment time according to the control target to make the energy storage capacitor voltage stable at the control target, so as to realize real-time optimization of the soft switching circuit conduction loss.

[0038] According to the embodiment of the present disclosure, operation S1 includes: dividing a switching cycle into four time periods: a pre-magnetization period, a dead time period, a charging period, and a demagnetization period; and: determining the waveforms of the inductor current in the four time periods respectively, and obtaining the timing waveform of the inductor current in a switching cycle. Figure 6 As shown, t1~t2 represents the pre-magnetization period, which represents the time period when the current in the inductor rises; t2~t3 represents the dead time period, which represents the time period for charging the equivalent parasitic capacitance of the power stage circuit switch node; t3~t4 represents the replenishment period, which represents the time period for replenishing the energy storage capacitor; t4~t5 represents the demagnetization period, which represents the time period when the current in the inductor decreases.

[0039] According to the embodiment of the present disclosure, Figure 4 As shown, the above soft switching circuit includes an energy storage capacitor C ZVS 、Inductance L ZVS , an auxiliary switch network 2021 and a conduction loss optimization control circuit 2022, wherein the conduction loss optimization control circuit is used to control the on and off of the auxiliary switch network to achieve low conduction loss operation of the soft switching circuit.

[0040] The power stage circuit 201 is used to convert high-voltage direct current into stable low-voltage direct current with ripples, thereby realizing a voltage conversion function. Here, a step-down DC-DC converter is used as an example. The soft-switching DC-DC converter loss optimization control method proposed in the present invention can also be applied to a step-up DC-DC converter and a step-up / step-down DC-DC converter without limitation. The step-down DC-DC converter power stage includes power stage switches Q1 and Q2, a filter inductor L and an output capacitor C. In each switching cycle, the power switches Q1 and Q2 are alternately turned on to control the power output, and a stable voltage with ripples is output after filtering. The soft-switching circuit 202 includes an auxiliary switch network 2021, a conduction loss optimization control circuit 2022, and an inductor L ZVS , and energy storage capacitor C ZVS The auxiliary switch network 2021 is connected to the inductor L ZVS and the switch node SW, as a storage capacitor CZVS Provides charge and input voltage V to the switch node SW IN To the energy storage capacitor C ZVS The charge path for replenishing the charge. Inductance L ZVS Connected to the energy storage capacitor C ZVS and the auxiliary switch network 2021. The conduction loss optimization control circuit 2022 is used to control the auxiliary switch network to achieve the soft switching with the lowest loss: using the inductor current I LZVS , the parasitic capacitance C on the switch node SW Charging, realizing soft switching of power tube Q1; and modulating energy storage capacitor C ZVS The voltage drop is reduced and the additional conduction loss caused by the soft switching circuit is optimized, thereby improving the conversion efficiency of the soft switching DC-DC converter.

[0041] By analyzing the conduction loss of the soft switching circuit, the conduction loss and the energy storage capacitor C are studied. ZVS The relationship between the voltage drop and the energy storage capacitor C ZVS The voltage drop is modulated at the optimal value to optimize the additional conduction loss caused by the soft switching circuit. The relevant voltage and current timing waveforms are as follows: Figure 6 As shown, the inductor current of the soft switching circuit The waveform expression is:

[0042]

[0043] The resonant frequency w of the inductor and the equivalent parasitic capacitance of the switch node ZVS for:

[0044] ;

[0045] Among them, V IN Indicates input voltage, V CZVS Represents the voltage of the energy storage capacitor, I LZVS Indicates the inductor current, L ZVS Inductance, C SW is the equivalent parasitic capacitance of the switch node, w ZVS represents the resonant frequency of the equivalent parasitic capacitance of the inductor and the switch node, t represents time, t1~t2 represents the pre-magnetization period, t2~t3 represents the dead time period, t3~t4 represents the charging period, t4~t5 represents the demagnetization period, I0 represents the load current, I L1 represents the initial current during the dead time period, I L2 Indicates the initial current during the charging period, I L3 Indicates the initial current during the demagnetization period.

[0046] According to the embodiment of the present disclosure, in operation S2, the soft switch conduction loss theoretical value can be obtained by integrating the square of the soft switch current in one switching cycle. In operation S3, the soft switch conduction loss is related to |V IN -2V CZVS | Proportional to the input voltage V IN unchanged, so the energy storage capacitor voltage V CZVS The control target is 0.5 times the input voltage. At this time, the switch circuit conduction loss is the lowest. Figure 7a and Figure 7b As shown, V IN is the input voltage, I O is the load current, V OUT is the output voltage, Figure 7a The horizontal axis is time t, and the vertical axis is the switch node voltage V SW and the inductor current I LZVS , through V CZVS =V IN , V CZVS =0.5V IN , V CZVS =V OUT The simulation results of the soft switching waveform under three different conditions show that the inductor current peak value is too high under high energy storage capacitor voltage, and the conduction time is too long under low energy storage capacitor voltage. The two cannot bring about optimized conduction loss. The conduction loss should be optimal when the energy storage capacitor voltage is at an intermediate value. Figure 7b In the figure, the horizontal axis is the voltage V of the energy storage capacitor. CZVS , the vertical axis is the conduction loss, the data condition is the input voltage V IN is 42V, the output voltage V OUT is 5V, the load current I O For 1A, the theoretical data shows that V CZVS =0.5V IN The conduction loss is optimal and the simulation data is consistent with the theoretical data.

[0047] Combination Figure 8 and Fig. 9 , Figure 4 As shown, the input voltage V IN and the energy storage capacitor voltage V CZVS After the voltage is divided by the voltage divider (VoltageDivider), the voltage V is input into the error amplifier (EA) of type-Ⅰ compensation. EA , and the ramp signal V RAMP Compared to determine the charging time t charge .like Fig. 9 As shown, taking the load current jumping from light load to heavy load as an example, since the discharge charge of the energy storage capacitor is greater than the replenishment charge, the energy storage capacitor voltage V CZVSThe power supply time is adaptively extended after the control loop modulation. ZVS The voltage is finally modulated at 0.5V IN , and returns to the completely soft switching state.

[0048] According to an embodiment of the present disclosure, operation S4 includes: detecting in real time whether the voltage value of the energy storage capacitor deviates from the control target (V CVZS =0.5 V IN ); By increasing or decreasing the charging time, the energy stored in the energy storage capacitor is adjusted to stabilize the voltage of the energy storage capacitor at the control target and achieve a steady state. If a deviation occurs, repeat the above steps to restore the steady state.

[0049] According to the embodiment of the present disclosure, the power stage circuit may be a boost type, a buck type, or a boost / buck type.

[0050] In another aspect, the present disclosure provides an application of the soft switching circuit conduction loss optimization method as described above in a converter, wherein the converter is selected from a buck converter, a boost converter, a buck / boost converter, and a combination thereof.

[0051] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0052] Based on the above description, those skilled in the art should have a clear understanding of the soft switching circuit conduction loss optimization method and application disclosed in the present invention.

[0053] In summary, the present disclosure provides a method and application for optimizing the conduction loss of a soft switching circuit, by modulating the energy storage capacitor C ZVS The voltage drop is 0.5V IN , optimize the additional conduction loss caused by the soft switching circuit, thereby improving the conversion efficiency. Compared with the existing optimal control method, the present invention not only controls the charge amount to achieve a precise soft switching state; ZVS The voltage drop is reduced to achieve optimal control of conduction loss, reducing the limitation of conduction loss of soft switching circuit on efficiency improvement.

[0054] In this document, unless otherwise specified, the so-called feature A "or" or "and / or" (and / or) feature B means that A exists alone, B exists alone, or A and B exist at the same time; the so-called feature A "and" (and) or "and" (and) or "and" (and) feature B means that A and B exist at the same time; the so-called "include", "comprise", "have" and "contain" mean including but not limited to these.

[0055] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0056] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for optimizing conduction loss of a soft switching circuit, wherein the soft switching circuit comprises an energy storage capacitor and an inductor, and is used to charge an equivalent parasitic capacitor of a switch node of a power stage circuit to achieve zero voltage switching of the power stage circuit, and the method for optimizing conduction loss of the soft switching circuit comprises: Operation S1: determining the timing waveform of the inductor current of the soft switching circuit at different stages within a switching cycle; Operation S2: obtaining a theoretical value of soft switch conduction loss in one switching cycle according to the timing waveform of the inductor current; Operation S3: determining the relationship between the soft switch conduction loss and the energy storage capacitor voltage and determining the energy storage capacitor voltage control target according to the timing waveform of the inductor current and the conduction loss theoretical value; and Operation S4: adjusting the charging time of the energy storage capacitor according to the control target to stabilize the voltage of the energy storage capacitor at the control target, thereby optimizing the conduction loss of the soft switching circuit in real time.

2. The method for optimizing conduction loss of a soft switching circuit according to claim 1, wherein operation S1 comprises: A switching cycle is divided into four periods: pre-magnetization period, dead period, power replenishment period, and demagnetization period; as well as The waveforms of the inductor current in four time periods are determined respectively to obtain the timing waveform of the inductor current in one switching cycle.

3. The method for optimizing conduction loss of a soft switching circuit according to claim 2, wherein: The pre-magnetization period represents the time period during which the current in the inductor rises; The dead time period represents a time period for charging the equivalent parasitic capacitance of the switch node of the power stage circuit; The charging period refers to the time period for charging the energy storage capacitor; The demagnetization period refers to a time period during which the current in the inductor decreases.

4. According to the method for optimizing conduction loss of a soft switching circuit as claimed in claim 3, the timing waveform expression of the inductor current of the soft switching circuit at different stages in a switching cycle is: in, V IN Indicates input voltage, V CZVS Represents the voltage of the energy storage capacitor, L ZVS represents inductance, w ZVS represents the resonant frequency of the equivalent parasitic capacitance of the inductor and the switch node, t represents time, t1~t2 represents the pre-magnetization period, t2~t3 represents the dead time period, t3~t4 represents the charging period, t4~t5 represents the demagnetization period, I0 represents the load current, I L1 represents the initial current during the dead time period, I L2 Indicates the initial current during the charging period, I L3 Indicates the initial current during the demagnetization period.

5. The method for optimizing conduction loss of a soft switching circuit according to claim 1, wherein in operation S2, a theoretical value of conduction loss of the soft switching circuit is obtained by integrating the square of the soft switching current in one switching cycle.

6. The method for optimizing the conduction loss of a soft switch circuit according to claim 1, wherein in operation S3, the conduction loss of the soft switch is related to |V IN -2V CZVS | Proportional to the input voltage V IN unchanged, so the energy storage capacitor voltage V CZVS The regulation target is 0.5 times the input voltage.

7. The method for optimizing conduction loss of a soft switching circuit according to claim 1, wherein operation S4 comprises: Real-time detection of whether the voltage value of the energy storage capacitor deviates from the control target; as well as By increasing or decreasing the charging time, the energy stored in the energy storage capacitor is adjusted so that the voltage of the energy storage capacitor is stabilized at the control target.

8. According to the method for optimizing conduction loss of a soft switching circuit as described in claim 1, the soft switching circuit further comprises an auxiliary switching network and a control circuit, and the conduction loss optimization control circuit is used to control the on and off of the auxiliary switching network to achieve low conduction loss operation of the soft switching circuit. 9 . The method for optimizing conduction loss of a soft switching circuit according to claim 1 , wherein the power stage circuit is a boost type, a buck type, or a boost / buck type.

10. Application of the soft switching circuit conduction loss optimization method according to any one of claims 1 to 9 in a converter, wherein the converter is selected from a buck converter, a boost converter, a boost / buck converter, and a combination thereof.

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