PWM controller with fixed turn-off time, control chip and control circuit

Abstract

The invention relates to the technical field of switching power supply control, and discloses a PWM (Pulse Width Modulation) controller with fixed turn-off time, a control chip and a control circuit, the PWM controller comprises a power supply unit, a band-gap reference unit, an MOS (Metal Oxide Semiconductor) driving unit, a clamping unit, a triangular wave generator, a comparator CMP1, a comparator CMP2, an SR latch and an internal resistor Rn; according to the PWM controller structure, the turn-off time of peripheral MOS transistors driven by the MOS driving unit is fixed in the actual use process, the PWM controller structure is good in forward topology overload consistency when applied to forward topology, the maximum load is slightly influenced by input voltage fluctuation, and the reliability of forward is improved. When the method is applied to flyback topology, current disturbance can be automatically eliminated without slope compensation when the duty ratio exceeds 50%.

Description

Technical Field

[0001] The invention relates to the technical field of switch power supply control, and in particular to a PWM controller with a fixed off-time, a control chip and a control circuit. Background Art

[0002] In the existing current-type PWM controller based on the NCP1252 chip (hereinafter referred to as the control chip), the entire switching cycle is fixed by the chip, that is, the switching cycle is the same under different loads and input voltages. The control chip adjusts the peak value of the primary current to control the duty cycle, thereby controlling the output voltage.

[0003] The control chip is applied to the circuit of the forward topology, such as Figure 1 As shown, its working process is as follows:

[0004] After the input power passes through the rectifier bridge and the large capacitor (hereinafter referred to as Cbus), the pulsating voltage is filtered into a fluctuating DC voltage (hereinafter referred to as Vbus). The DC voltage charges the capacitor in parallel with the VCC pin of the control chip through a resistor. When the VCC pin reaches the operating voltage, the DRV pin of the control chip starts to output a duty cycle waveform to the Gate pin of the MOS tube (hereinafter referred to as Q1). When the DRV pin outputs a high level, Q1 is turned on. Vbus is loaded on the primary of the transformer (hereinafter referred to as N1), and the secondary of the transformer (hereinafter referred to as N2) outputs a voltage, the voltage value of which is the input voltage of N1 divided by the ratio of the number of primary winding coils to the number of secondary winding coils (hereinafter referred to as turns ratio). The output voltage of N2 is supplied to the load through the filter inductor Lm, and the output current is limited by the inductor Lm and can only rise linearly from the starting value. In addition, the output current will be reflected to the primary side, that is, the primary current will be composed of two parts: one part is the excitation current of the inductor formed by the primary coil, and the other part is the current reflected back to the primary by the secondary current, and its value is equal to the filter inductor current divided by the turns ratio. Since the inductance of the transformer is relatively large, the inductance is designed so that the excitation current is much smaller than the reflected current, accounting for only about 5%-10% of the reflected current. The entire primary current passes through the resistor Rcs, and the voltage drop of the resistor Rcs (hereinafter referred to as Vcs) is collected by the control chip, so the control chip indirectly collects the primary current. When the DRV pin output is low, Q1 is turned off, and the entire transformer demagnetizes the capacitor Cbus through the demagnetization winding. The current of the filter inductor Lm forms a loop through the load and the diode D2 to continue to flow through the current and discharge.

[0005] In addition, the load voltage is detected and converted into a signal, which is transmitted to the control chip through an optocoupler (hereinafter referred to as Opt) and converted into a control value. When the peak voltage of Vcs reaches this control value, the control chip turns off Q1. At the same time, the control chip will start a fixed-cycle clock signal at the same time as the last high level of the DRV pin. When this clock signal completes a cycle time, it generates a pulse to turn on Q1 again.

[0006] Combined with the above content, Figure 1 The circuit shown works repeatedly. According to the transformer principle, the primary current reflects the secondary current, and the secondary current is the load current, so adjusting the size of the primary current is in disguise to adjust the size of the load current. When the load current is large, the circuit will lower the output voltage, and the feedback system will increase the control amount to increase the primary current to output more current to the load to stabilize the output voltage. Conversely, the control amount will be reduced to stabilize the output voltage. Therefore, the core idea of ​​the control chip is to control the primary peak current to stabilize the output voltage. Obviously, when the input voltage remains unchanged, the greater the current required by the load, the higher the peak current required to flow through the primary, that is, the higher the control amount required.

[0007] The control chip determines whether the load current exceeds the design specification by detecting whether the voltage of the resistor Rcs reaches the internal maximum value. However, when the input voltage is inconsistent under the forward topology, the peak current of the primary is inconsistent under the same load current. Therefore, if the load is judged to be overloaded by detecting whether the peak value of the resistor Rcs reaches the maximum value, the overload point detection will be inconsistent under different input voltages. Figure 1 When the circuit is fully loaded, the filter inductor current and VCS are as follows: Figure 3 As shown, I1 is the secondary filter inductor current when the high voltage input is fully loaded, I2 is the secondary filter inductor current when the low voltage input is fully loaded, Vcs1 is the primary sampling voltage when the high voltage input is fully loaded, and Vcs2 is the primary sampling voltage when the low voltage input is fully loaded. The calculation results show that when the input voltage changes from 180V to 265V and the load is rated load, the sampled Vcs peak voltage changes by 5%-8%, which is specifically related to the size of the Cbus capacitor. Therefore, if the Vcs value is used to determine whether the system is overloaded, the overload value will change under different input voltages, affecting the reliability of the system.

[0008] The schematic diagram of the control chip when applied to the flyback topology is as follows: Figure 2 As shown, its working process is as follows:

[0009] After the input power passes through the rectifier bridge and Cbus, the pulsating voltage is filtered into Vbus. This voltage charges the capacitor in parallel with the VCC pin of the control chip through a resistor. When VCC reaches the operating voltage, the DRV pin of the control chip begins to output a duty cycle waveform to the Gate pin of Q1. When the DRV pin outputs a high level, Q1 is turned on. Vbus is loaded on the power inductor Lm, the voltage is charged through the N1 side, and the current flows through the resistor Rcs at the same time and is detected by the control chip. When the DRV pin is at a low level, Q1 is turned off, the inductor Lm is discharged through the N2 coil, flows through the load, and the ripple current is filtered by the output capacitor Co. The output voltage control method is similar to the forward principle.

[0010] When the flyback topology is 50%, it is easy to have subharmonic oscillation problems. When the inductor Lm is charged, if a disturbance occurs, that is, the inductor current is charged prematurely, after two switching cycles, the inductor current and the previously stable signal waveform have undergone greater changes, such as Figure 4 As shown. So after NCP1252 adds slope compensation, once the inductor has disturbance, after several switching cycles, the disturbance is eliminated. Figure 5 However, after adding slope compensation, the control amount needs a higher initial value. A higher initial value requires the system to be equipped with devices with high voltage resistance requirements. Summary of the invention

[0011] In view of the shortcomings of the background technology, the present invention provides a PWM controller, a control chip and a control circuit with a fixed off time, and the technical problem to be solved is that the reliability of the existing PWM controller is poor.

[0012] To solve the above technical problems, in a first aspect, the present invention provides the following technical solutions: a PWM controller with a fixed off-time includes a power supply unit, a bandgap reference unit, a MOS drive unit, a clamp unit, a triangle wave generator, a comparator CMP1, a comparator CMP2, an SR latch and an internal resistor Rn;

[0013] The output end of the power supply unit is electrically connected to the bandgap reference unit, and the bandgap reference unit is electrically connected to a reference source REF and a reference source REF2 respectively;

[0014] The positive input terminal of the comparator CMP1 is used to input an external sampling voltage, the reference source REF2 is electrically connected to one end of the internal resistor Rn, the other end of the resistor Rn is electrically connected to the input terminal of the clamping unit, the output terminal of the clamping unit is electrically connected to the negative input terminal of the comparator CMP1, and the clamping unit outputs the input voltage when the input voltage of its own input terminal does not exceed the clamping voltage value, and outputs the clamping voltage value when the input voltage of its own input terminal is higher than the clamping voltage value;

[0015] The output end of the comparator CMP1 is electrically connected to the R input end of the SR latch, the QP output end of the SR latch is electrically connected to the MOS driving unit, and the MOS driving unit outputs a driving signal based on the signal level state of the QP output end; the QN output end of the SR latch is electrically connected to the triangular wave generator, and the triangular wave generator inputs a triangular wave to the positive input end of the comparator CMP2 based on the signal level state of the QN output end, the negative input end of the comparator CMP2 is electrically connected to the reference source REF, and the output end of the comparator CMP2 is electrically connected to the S input end of the SR latch.

[0016] In a certain embodiment of the first aspect, the voltage outputted by the output terminal of the power supply unit is recorded as Vc, and the MOS driving unit outputs the voltage Vc when the signal at the QP output terminal is at a high level, and the MOS driving unit outputs zero voltage when the signal at the QP output terminal is at a low level.

[0017] In a certain implementation of the first aspect, the triangular wave generator starts to output the triangular wave when the signal at the QN output end is at a high level, and stops outputting the triangular wave when the signal at the QN output end is at a low level.

[0018] In a second aspect, the present invention provides a control chip, including a chip body, on which the above-mentioned fixed off-time PWM controller is provided.

[0019] In a certain embodiment of the second aspect, the chip body is provided with an HV pin, a VCC pin, a CS pin, a COMP pin, a GND pin and a GATE pin, the HV pin is electrically connected to the input end of the power supply unit, the VCC pin is electrically connected to the output end of the power supply unit, the CS pin is electrically connected to the positive input end of the comparator CMP1, the COMP pin is electrically connected to the other end of the internal resistor Rn, the GND pin is used for grounding, and the GATE pin is electrically connected to the output end of the MOS driving unit.

[0020] In a certain implementation of the second aspect, the HV pin, VCC pin, COMP pin and GND pin are located on the same side of the chip body, and the GATE pin and CS pin are located on the same side of the chip body.

[0021] In certain implementations of the second aspect, the HV pin and the DRV pin are located on opposite sides of the chip body.

[0022] In a third aspect, the present invention provides a control circuit, comprising the above-mentioned control chip, and also comprising an EMI filter, wherein an AC power source AC is electrically connected to an AC input end of a rectifier bridge BD1 through the EMI filter, a first DC connection end of the rectifier bridge BD1 is electrically connected to one end of an energy storage capacitor C1, one end of a starting resistor R1, a cathode of a diode D1, and one end of a primary winding N1 of a transformer T1, respectively, the other end of the energy storage capacitor C1 and a second DC connection end of the rectifier bridge BD1 are both grounded, the other end of the starting resistor R1 is electrically connected to an HV pin of a control chip, an anode of the diode D1 is grounded through a demagnetization winding N3 of the transformer T1, the other end of the primary winding N1 is electrically connected to a drain of a MOS tube Q1, a gate of the MOS tube Q1 is electrically connected to a GATE pin of a control chip, a source of the MOS tube Q1 is electrically connected to a CS pin of a control chip and one end of a sampling resistor R6, respectively, and the other end of the sampling resistor R6 is grounded;

[0023] One end of the secondary winding N2 of the transformer T1 is electrically connected to the anode of the rectifier diode D2, the cathode of the rectifier diode D2 is electrically connected to the cathode of the freewheeling diode D3 and one end of the filter inductor L1 respectively, the other end of the filter inductor L1 is electrically connected to one end of the output capacitor C2, one end of the output resistor R2, one end of the current limiting resistor R3 and one end of the feedback resistor R4 respectively, the other end of the output capacitor C2, the other end of the output resistor R2, the anode of the freewheeling diode D3 and the other end of the secondary winding N2 are all grounded;

[0024] The other end of the current limiting resistor R3 is electrically connected to the primary side input end of the photocoupler OPT1, the other end of the feedback resistor R4 is electrically connected to one end of the compensation capacitor C3, one end of the feedback resistor R5 and the input end of the voltage regulator D4, the other end of the compensation capacitor C3 is electrically connected to the primary side output end of the photocoupler OPT1 and the cathode end of the voltage regulator D4, and the anode end of the voltage regulator D4 and the other end of the feedback resistor R5 are both grounded;

[0025] The secondary side input end of the photoelectric coupler OPT1 is electrically connected to one end of the feedback capacitor C4 and the COMP pin of the control chip respectively, the other end of the feedback capacitor C4, the GND pin of the control chip and the secondary side output end of the photoelectric coupler OPT1 are all grounded, the VCC pin of the control chip is electrically connected to the cathode of the charging diode D5 and one end of the capacitor C5 respectively, the anode of the charging diode D5 is grounded through the power supply winding N4 of the transformer, and the other end of the capacitor C5 is grounded.

[0026] In a fourth aspect, the present invention provides a control circuit of another structure, comprising the above-mentioned control chip, and also comprising an EMI filter, wherein the AC power supply AC is electrically connected to the AC input end of the rectifier bridge BD2 through the EMI filter, and the first DC connection end of the rectifier bridge BD2 is electrically connected to one end of the energy storage capacitor C20, one end of the starting resistor R20, one end of the leakage inductance absorption resistor R21, one end of the leakage inductance absorption capacitor C21 and one end of the primary winding N21 of the transformer T20, respectively, the other end of the energy storage capacitor C20 is grounded, the other end of the starting resistor R20 is electrically connected to the HV pin of the control chip, the other end of the leakage inductance absorption resistor is electrically connected to the other end of the leakage inductance absorption capacitor C21 and the cathode of the leakage inductance absorption diode D21, the other end of the primary winding N21 is electrically connected to the anode of the leakage inductance absorption diode D21 and the drain of the MOS tube Q1, the gate of the MOS tube Q1 is electrically connected to the GATE pin of the control chip, and the source of the MOS tube Q1 is electrically connected to the CS pin of the control chip and the sampling resistor R26

[0027] One end is electrically connected, and the other end of the sampling resistor R26 is grounded;

[0028] One end of the secondary winding N22 of the transformer T20 is electrically connected to the anode of the secondary rectifier diode D20, the cathode of the secondary rectifier diode D20 is electrically connected to one end of the output capacitor C22, one end of the load resistor R22, one end of the current limiting resistor R23 and one end of the feedback resistor R24 ​​respectively, the other end of the output capacitor C22, the other end of the load resistor R22 and the other end of the secondary winding N22 are all grounded, the other end of the current limiting resistor R23 is electrically connected to the primary side input end of the photoelectric coupler OPT2, the other end of the feedback resistor R24 ​​is electrically connected to one end of the compensation capacitor C23, one end of the feedback resistor R25 and the input end of the voltage regulator D23 respectively, the other end of the feedback resistor R25 and the anode of the voltage regulator D23 are both grounded, and the other end of the feedback capacitor C23 is electrically connected to the primary side output end of the photoelectric coupler OPT2 and the cathode of the voltage regulator D23 respectively;

[0029] The secondary side input end of the photoelectric coupler OPT2 is electrically connected to one end of the feedback capacitor C24 and the COMP pin of the control chip respectively, the other end of the feedback capacitor C24, the GND pin of the control chip and the secondary side output end of the photoelectric coupler OPT2 are all grounded, the VCC pin of the control chip is electrically connected to the cathode of the charging diode D22 and one end of the capacitor C25 respectively, the anode of the charging diode D22 is grounded through the power supply winding N23 of the transformer, and the other end of the capacitor C25 is grounded.

[0030] In certain implementation manner of the third aspect or the fourth aspect, the MOS transistor Q1 is an NMOS transistor.

[0031] Compared with the prior art, the present invention has the following beneficial effects: in actual use, the structure of the present invention makes the MOS driving unit drive the peripheral MOS tube to have a fixed off time, thereby making the consistency of the PWM controller better, making the PWM controller less affected by input voltage fluctuations, and improving the reliability of the PWM controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is the application circuit diagram of the existing forward topology based on the NCP1252 chip;

[0033] Figure 2 This is the application circuit diagram of the existing flyback topology based on the NCP1252 chip;

[0034] Figure 3 for Figure 1 Waveforms of filter inductor current and transformer primary current in the circuit;

[0035] Figure 4 for Figure 2 The waveform of the equivalent current of the primary inductor of the circuit after being disturbed without slope compensation;

[0036] Figure 5 for Figure 2 The waveform of the equivalent current of the primary inductor of the circuit after being disturbed with slope compensation;

[0037] Figure 6 It is a structural diagram of the PWM controller in the first embodiment;

[0038] Figure 7 This is a schematic diagram of the structure of the control chip in the second embodiment;

[0039] Figure 8 is a circuit diagram of the control circuit in Embodiment 3;

[0040] Fig. 9 is a circuit diagram of the control circuit in Embodiment 4;

[0041] Fig.10 for Figure 8 The waveform of the primary CS voltage and the secondary filter inductor current when the circuit is at low voltage input;

[0042] Fig.11 for Figure 8 The waveform of the primary CS voltage and the secondary filter inductor current when the circuit is at high voltage input;

[0043] Fig.12 for Fig. 9 Lm equivalent current waveform when the circuit duty cycle exceeds 50% and is disturbed. DETAILED DESCRIPTION

[0044] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0045] Embodiment 1

[0046] like Figure 6 As shown, the PWM controller with a fixed off time includes a power supply unit 1, a bandgap reference unit 2, a MOS driving unit 4, a clamping unit 5, a triangle wave generator 6, a comparator CMP1, a comparator CMP2, an SR latch 3 and an internal resistor Rn;

[0047] The output end of the power supply unit 1 is electrically connected to the bandgap reference unit 2, and the bandgap reference unit 2 is electrically connected to the reference source REF and the reference source REF2 respectively;

[0048] The positive input terminal of the comparator CMP1 is used to input an external sampling voltage, the reference source REF2 is electrically connected to one end of the internal resistor Rn, the other end of the resistor Rn is electrically connected to the input terminal of the clamping unit 5, the output terminal of the clamping unit 5 is electrically connected to the negative input terminal of the comparator CMP1, and the clamping unit 5 outputs the input voltage when the input voltage of its own input terminal does not exceed the clamping voltage value, and outputs the clamping voltage value when the input voltage of its own input terminal is higher than the clamping voltage value;

[0049] The output end of the comparator CMP1 is electrically connected to the R input end of the SR latch 3, the QP output end of the SR latch 3 is electrically connected to the MOS driving unit 4, and the MOS driving unit 4 outputs a driving signal based on the signal level state of the QP output end; the QN output end of the SR latch 3 is electrically connected to the triangular wave generator 6, and the triangular wave generator 6 inputs a triangular wave to the positive input end of the comparator CMP2 based on the signal level state of the QN output end, the negative input end of the comparator CMP2 is electrically connected to the reference source REF, and the output end of the comparator CMP2 is electrically connected to the S input end of the SR latch 3.

[0050] Specifically, in this embodiment, the voltage outputted from the output end of the power supply unit 1 is recorded as Vc. When the signal at the QP output end is high, the MOS driving unit 4 outputs the voltage Vc. When the signal at the QP output end is low, the MOS driving unit 4 outputs zero voltage.

[0051] Specifically, in this embodiment, the triangular wave generator 6 starts to output the triangular wave when the signal at the QN output terminal is at a high level, and stops outputting the triangular wave when the signal at the QN output terminal is at a low level.

[0052] Specifically, in this embodiment, the signal outputted from the QP output terminal of the SR latch 3 and the signal outputted from the QN output terminal are complementary signals, that is, when the signal outputted from the QP output terminal is at a high level, the signal outputted from the QN output terminal is at a low level, and when the signal outputted from the QP output terminal is at a low level, the signal outputted from the QN output terminal is at a high level.

[0053] Second, as Figure 7 As shown, the present invention provides a control chip, including a chip body 100, on which the above-mentioned fixed off-time PWM controller is provided.

[0054] In addition Figure 7 In the embodiment, the chip body 100 is provided with an HV pin, a VCC pin, a CS pin, a COMP pin, a GND pin and a GATE pin, the HV pin is electrically connected to the input end of the power supply unit 1, the VCC pin is electrically connected to the output end of the power supply unit 1, the CS pin is electrically connected to the positive input end of the comparator CMP1, the COMP pin is electrically connected to the other end of the internal resistor Rn, the GND pin is used for grounding, and the GATE pin is electrically connected to the output end of the MOS driving unit 4.

[0055] In addition, in some implementations, the HV pin, the VCC pin, the COMP pin, and the GND pin are located on the same side of the chip body 100 , and the GATE pin and the CS pin are located on the same side of the chip body 100 .

[0056] In addition, in some implementations, the HV pin and the DRV pin are located on opposite sides of the chip body 100 .

[0057] Embodiment three, as Figure 8 As shown, this embodiment provides a control circuit, which is a forward topology application of a control chip U1, including the control chip U1 in the second embodiment, wherein the HV pin, VCC pin, COMP pin and GND pin in the control chip U1 are located on the same side of the chip body 100, the GATE pin and the CS pin are located on the same side of the chip body 100, and the HV pin and the DRV pin are located on opposite sides of the chip body 100;

[0058] It also includes an EMI filter, the AC power supply AC is electrically connected to the AC input end of the rectifier bridge BD1 through the EMI filter, the first DC connection end of the rectifier bridge BD1 is electrically connected to one end of the energy storage capacitor C1, one end of the starting resistor R1, the cathode of the diode D1 and one end of the primary winding N1 of the transformer T1, the other end of the energy storage capacitor C1 and the second DC connection end of the rectifier bridge BD1 are both grounded, the other end of the starting resistor R1 is electrically connected to the HV pin of the control chip U1, the anode of the diode D1 is grounded through the demagnetization winding N3 of the transformer T1, the other end of the primary winding N1 is electrically connected to the drain of the MOS tube Q1, the gate of the MOS tube Q1 is electrically connected to the GATE pin of the control chip U1, the source of the MOS tube Q1 is electrically connected to the CS pin of the control chip U1 and one end of the sampling resistor R6, and the other end of the sampling resistor R6 is grounded; wherein the MOS tube Q1 is an NMOS tube;

[0059] One end of the secondary winding N2 of the transformer T1 is electrically connected to the anode of the rectifier diode D2, the cathode of the rectifier diode D2 is electrically connected to the cathode of the freewheeling diode D3 and one end of the filter inductor L1 respectively, the other end of the filter inductor L1 is electrically connected to one end of the output capacitor C2, one end of the output resistor R2, one end of the current limiting resistor R3 and one end of the feedback resistor R4 respectively, the other end of the output capacitor C2, the other end of the output resistor R2, the anode of the freewheeling diode D3 and the other end of the secondary winding N2 are all grounded;

[0060] The other end of the current limiting resistor R3 is electrically connected to the primary input end of the photocoupler OPT1, the other end of the feedback resistor R4 is electrically connected to one end of the compensation capacitor C3, one end of the feedback resistor R5 and the input end of the voltage regulator D4 respectively, the other end of the compensation capacitor C3 is electrically connected to the primary output end of the photocoupler OPT1 and the cathode end of the voltage regulator D4 respectively, the anode end of the voltage regulator D4 and the other end of the feedback resistor R5 are both grounded; the model of the voltage regulator D4 is TL431;

[0061] The secondary side input end of the photocoupler OPT1 is electrically connected to one end of the feedback capacitor C4 and the COMP pin of the control chip U1 respectively, the other end of the feedback capacitor C4, the GND pin of the control chip U1 and the secondary side output end of the photocoupler OPT1 are all grounded, the VCC pin of the control chip U1 is electrically connected to the cathode of the charging diode D5 and one end of the capacitor C5 respectively, the anode of the charging diode D5 is grounded through the power supply winding N4 of the transformer, and the other end of the capacitor C5 is grounded.

[0062] for Figure 8In the circuit shown, the AC power source AC forms a fluctuating bus voltage after passing through the rectifier bridge BD1, and the bus voltage is connected to the HC pin after passing through the resistor R1, and then charges the capacitor C5 after passing through the power supply unit 1, wherein the capacitor C5 is used to control the power supply of the entire system. When the voltage on the capacitor C5 is established, the circuit starts to work; the output voltage of the circuit, that is, the voltage on the Vo+ terminal, forms a current flowing out of the COMP pin after passing through the photocoupler OPT1. After this current passes through the internal resistor Rn, the voltage on the COMP pin can reflect the state of the output voltage of the circuit;

[0063] In actual use, when the QP output of the SR latch 3 allows the Gate pin to output a high voltage to turn on the MOS tube Q1, the bus voltage supplies power to the filter inductor L1 and the load through the transformer T1 ratio, and the current will be reflected to the primary and flow through the sampling resistor R6. When the peak voltage obtained by the sampling resistor R6 is consistent with the voltage at the COMP pin, the control circuit pulls down the Gate pin according to the previously described logic and starts the triangular wave generator internally. At this stage, the filter inductor L1 continues to supply power to the load through the freewheeling channel. When the amplitude of the triangular wave reaches the reference source REF, the output of the comparator CMP2 is immediately reversed and the QP output of the SR latch 3 is immediately high, and then the MOS tube Q1 is immediately started to restart the next cycle. At the same time, the QN output of the SR latch 3 is low to reset the triangular wave generator for use in the next cycle. Obviously, if the rising slope of the triangular wave is fixed, the time required for the triangular wave amplitude to start from 0 to a certain reference voltage must be fixed, so the triangular wave generator acts as a timer. Since the triangle wave generator of the control circuit starts to start after the MOS tube Q1 is turned on, and turns on the MOS tube Q1 again after the timing is completed, this control method is called a fixed off-time control mode.

[0064] right Figure 8 The clamping unit in the electrical control circuit shown in the figure is set to 1.2V and then simulated, wherein the simulation waveforms of the voltage and current related to the bus high voltage input and the bus low voltage input are as follows: Fig.10 and Fig.11 As shown, Fig.10 and Fig.11 They respectively represent the voltage waveforms of the primary CS and the current waveforms of the secondary filter inductor L1 when the control circuit is applied to the forward topology bus voltage at 375V and 190V and the load is in the rated load state, where ILm is the current flowing through the filter inductor L1, CS is the voltage at the pin CS, and VBUS is the bus circuit; Fig.10 and Fig.11From the simulation data in , it can be obtained that when the bus voltage difference is close to double, the CS peak voltage under rated load is 1.187V and 1.195V respectively, which differs by only 0.7% and is close to the clamping voltage. The consistency of CS peak value under rated load under different input voltages is improved. Therefore, if the CS detection value reaches the 1.2V overload mark, the maximum and minimum input bus voltages have only a 0.7% error, which greatly improves the reliability of the load.

[0065] Embodiment 4

[0066] like Fig. 9 As shown, this embodiment provides a control circuit of another structure, which is a flyback topology application of the control chip U1, including the above-mentioned control chip U1, and also includes an EMI filter. The AC power supply AC is electrically connected to the AC input end of the rectifier bridge BD2 through the EMI filter, and the first DC connection end of the rectifier bridge BD2 is electrically connected to one end of the energy storage capacitor C20, one end of the starting resistor R20, one end of the leakage inductance absorption resistor R21, one end of the leakage inductance absorption capacitor C21 and one end of the primary winding N21 of the transformer T20, respectively. The primary winding N21 is equivalent to the inductance Lm, and the other end of the energy storage capacitor C20 is connected to ground, the other end of the starting resistor R20 is electrically connected to the HV pin of the control chip U1, the other end of the leakage inductance absorption resistor is electrically connected to the other end of the leakage inductance absorption capacitor C21 and the cathode of the leakage inductance absorption diode D21 respectively, the other end of the primary winding N21 is electrically connected to the anode of the leakage inductance absorption diode D21 and the drain of the MOS tube Q1 respectively, the gate of the MOS tube Q1 is electrically connected to the GATE pin of the control chip U1, the source of the MOS tube Q1 is electrically connected to the CS pin of the control chip U1 and one end of the sampling resistor R26 respectively, and the other end of the sampling resistor R26 is grounded; in addition, the MOS tube Q1 is an NMOS tube;

[0067] One end of the secondary winding N22 of the transformer T20 is electrically connected to the anode of the secondary rectifier diode D20, and the cathode of the secondary rectifier diode D20 is electrically connected to one end of the output capacitor C22, one end of the load resistor R22, one end of the current limiting resistor R23 and one end of the feedback resistor R24 ​​respectively. The other end of the output capacitor C22, the other end of the load resistor R22 and the other end of the secondary winding N22 are all grounded, and the other end of the current limiting resistor R23 is electrically connected to the primary side input end of the photoelectric coupler OPT2. The other end of the feedback resistor R24 ​​is electrically connected to one end of the compensation capacitor C23, one end of the feedback resistor R25 and the input end of the voltage regulator D23 respectively. The other end of the feedback resistor R25 and the anode of the voltage regulator D23 are grounded, and the other end of the feedback capacitor C23 is electrically connected to the primary side output end of the photoelectric coupler OPT2 and the cathode of the voltage regulator D23 respectively; the model of the voltage regulator D23 is TL431;

[0068] The secondary side input end of the photocoupler OPT2 is electrically connected to one end of the feedback capacitor C24 and the COMP pin of the control chip U1 respectively, the other end of the feedback capacitor C24, the GND pin of the control chip U1 and the secondary side output end of the photocoupler OPT2 are all grounded, the VCC pin of the control chip U1 is electrically connected to the cathode of the charging diode D22 and one end of the capacitor C25 respectively, the anode of the charging diode D22 is grounded through the power supply winding N23 of the transformer T20, and the other end of the capacitor C25 is grounded.

[0069] and Fig. 9 The circuit shown works differently, Fig.10 When the circuit is working, if the MOS tube N1 is turned on, the bus voltage, that is, the voltage output by the rectifier bridge BD2, charges the primary winding N21 of the transformer T20. When the MOS tube Q1 is turned off, the primary winding N21 of the transformer T20 supplies power to the load through the secondary winding N22.

[0070] right Fig. 9 The circuit is simulated, where the duty cycle exceeds 50% and the Lm equivalent current waveform after disturbance is as follows Fig.12 As shown, the current rising stage is the time period when the control circuit turns on the MOS tube Q1, and the current falling stage is the time period when the control circuit turns off the MOS tube Q1. Under normal conditions, the peak current of the equivalent inductor is controlled by the control circuit. When the control circuit is disturbed, the primary equivalent current peak of the inductor Lm will drop in advance. After several switching cycles, the peak current returns to a stable value, and the control circuit does not need to make additional compensation to the control end.

[0071] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A fixed off-time PWM controller, characterized in that: It includes a power supply unit, a bandgap reference unit, a MOS driving unit, a clamping unit, a triangle wave generator, a comparator CMP1, a comparator CMP2, an SR latch and an internal resistor Rn; The output end of the power supply unit is electrically connected to the bandgap reference unit, and the bandgap reference unit is electrically connected to a reference source REF and a reference source REF2 respectively; The positive input terminal of the comparator CMP1 is used to input an external sampling voltage, the reference source REF2 is electrically connected to one end of the internal resistor Rn, the other end of the resistor Rn is electrically connected to the input terminal of the clamping unit, the output terminal of the clamping unit is electrically connected to the negative input terminal of the comparator CMP1, and the clamping unit outputs the input voltage when the input voltage at the input terminal does not exceed the clamping voltage value, and outputs the clamping voltage value when the input voltage at the input terminal is higher than the clamping voltage value; The output end of the comparator CMP1 is electrically connected to the R input end of the SR latch, the QP output end of the SR latch is electrically connected to the MOS driving unit, and the MOS driving unit outputs a driving signal based on the signal level state of the QP output end; The QN output terminal of the SR latch is electrically connected to a triangular wave generator, and the triangular wave generator inputs a triangular wave to the positive input terminal of the comparator CMP2 based on the signal level state of the QN output terminal. The negative input terminal of the comparator CMP2 is electrically connected to the reference source REF, and the output terminal of the comparator CMP2 is electrically connected to the S input terminal of the SR latch.

2. The fixed off-time PWM controller according to claim 1, characterized in that: The voltage outputted from the output end of the power supply unit is recorded as Vc. When the signal at the output end of the QP is at a high level, the MOS driving unit outputs the voltage Vc. When the signal at the output end of the QP is at a low level, the MOS driving unit outputs zero voltage.

3. The fixed off-time PWM controller according to claim 1 or 2, characterized in that: The triangular wave generator starts to output the triangular wave when the signal at the QN output end is at a high level, and stops outputting the triangular wave when the signal at the QN output end is at a low level.

4. A control chip, characterized in that: The invention comprises a chip body, on which is arranged a PWM controller with a fixed off time as claimed in any one of claims 1 to 3.

5. The control chip according to claim 4, characterized in that: The chip body is provided with an HV pin, a VCC pin, a CS pin, a COMP pin, a GND pin and a GATE pin, the HV pin is electrically connected to the input end of the power supply unit, the VCC pin is electrically connected to the output end of the power supply unit, the CS pin is electrically connected to the positive input end of the comparator CMP1, the COMP pin is electrically connected to the other end of the internal resistor Rn, the GND pin is used for grounding, and the GATE pin is electrically connected to the output end of the MOS driving unit.

6. The control chip according to claim 5, characterized in that: The HV pin, the VCC pin, the COMP pin and the GND pin are located on the same side of the chip body, and the GATE pin and the CS pin are located on the same side of the chip body.

7. The control chip according to claim 5, characterized in that: The HV pin and the DRV pin are located on opposite sides of the chip body.

8. A control circuit, characterized in that A control chip comprising the control chip according to any one of claims 4 to 7, and further comprising an EMI filter, wherein an AC power source AC is electrically connected to an AC input end of a rectifier bridge BD1 through the EMI filter, a first DC connection end of the rectifier bridge BD1 is electrically connected to one end of an energy storage capacitor C1, one end of a starting resistor R1, a cathode of a diode D1, and one end of a primary winding N1 of a transformer T1, respectively, the other end of the energy storage capacitor C1 and a second DC connection end of the rectifier bridge BD1 are both grounded, the other end of the starting resistor R1 is electrically connected to an HV pin of the control chip, an anode of the diode D1 is grounded through a demagnetization winding N3 of the transformer T1, the other end of the primary winding N1 is electrically connected to a drain of a MOS tube Q1, a gate of the MOS tube Q1 is electrically connected to a GATE pin of the control chip, a source of the MOS tube Q1 is electrically connected to a CS pin of the control chip and one end of a sampling resistor R6, respectively, and the other end of the sampling resistor R6 is grounded; One end of the secondary winding N2 of the transformer T1 is electrically connected to the anode of the rectifier diode D2, the cathode of the rectifier diode D2 is electrically connected to the cathode of the freewheeling diode D3 and one end of the filter inductor L1 respectively, the other end of the filter inductor L1 is electrically connected to one end of the output capacitor C2, one end of the output resistor R2, one end of the current limiting resistor R3 and one end of the feedback resistor R4 respectively, the other end of the output capacitor C2, the other end of the output resistor R2, the anode of the freewheeling diode D3 and the other end of the secondary winding N2 are all grounded; The other end of the current limiting resistor R3 is electrically connected to the primary side input end of the photocoupler OPT1, the other end of the feedback resistor R4 is electrically connected to one end of the compensation capacitor C3, one end of the feedback resistor R5 and the input end of the voltage regulator D4, the other end of the compensation capacitor C3 is electrically connected to the primary side output end of the photocoupler OPT1 and the cathode end of the voltage regulator D4, and the anode end of the voltage regulator D4 and the other end of the feedback resistor R5 are both grounded; The secondary side input end of the photoelectric coupler OPT1 is electrically connected to one end of the feedback capacitor C4 and the COMP pin of the control chip respectively, the other end of the feedback capacitor C4, the GND pin of the control chip and the secondary side output end of the photoelectric coupler OPT1 are all grounded, the VCC pin of the control chip is electrically connected to the cathode of the charging diode D5 and one end of the capacitor C5 respectively, the anode of the charging diode D5 is grounded through the power supply winding N4 of the transformer, and the other end of the capacitor C5 is grounded.

9. A control circuit, characterized in that A control chip comprising any one of claims 4 to 7, and further comprising an EMI filter, wherein an AC power source AC is electrically connected to an AC input end of a rectifier bridge BD2 through the EMI filter, a first DC connection end of the rectifier bridge BD2 is electrically connected to one end of an energy storage capacitor C20, one end of a starting resistor R20, one end of a leakage inductance absorption resistor R21, one end of a leakage inductance absorption capacitor C21, and one end of a primary winding N21 of a transformer T20, respectively, the other end of the energy storage capacitor C20 is grounded, the other end of the starting resistor R20 is electrically connected to an HV pin of the control chip, the other end of the leakage inductance absorption resistor is electrically connected to the other end of the leakage inductance absorption capacitor C21 and the cathode of a leakage inductance absorption diode D21, the other end of the primary winding N21 is electrically connected to the anode of the leakage inductance absorption diode D21 and the drain of a MOS tube Q1, the gate of the MOS tube Q1 is electrically connected to a GATE pin of the control chip, the source of the MOS tube Q1 is electrically connected to a CS pin of the control chip and one end of a sampling resistor R26, respectively, and the other end of the sampling resistor R26 is grounded; One end of the secondary winding N22 of the transformer T20 is electrically connected to the anode of the secondary rectifier diode D20, the cathode of the secondary rectifier diode D20 is electrically connected to one end of the output capacitor C22, one end of the load resistor R22, one end of the current limiting resistor R23 and one end of the feedback resistor R24 ​​respectively, the other end of the output capacitor C22, the other end of the load resistor R22 and the other end of the secondary winding N22 are all grounded, the other end of the current limiting resistor R23 is electrically connected to the primary side input end of the photoelectric coupler OPT2, the other end of the feedback resistor R24 ​​is electrically connected to one end of the compensation capacitor C23, one end of the feedback resistor R25 and the input end of the voltage regulator D23 respectively, the other end of the feedback resistor R25 and the anode of the voltage regulator D23 are both grounded, and the other end of the feedback capacitor C23 is electrically connected to the primary side output end of the photoelectric coupler OPT2 and the cathode of the voltage regulator D23 respectively; The secondary side input end of the photoelectric coupler OPT2 is electrically connected to one end of the feedback capacitor C24 and the COMP pin of the control chip respectively, the other end of the feedback capacitor C24, the GND pin of the control chip and the secondary side output end of the photoelectric coupler OPT2 are all grounded, the VCC pin of the control chip is electrically connected to the cathode of the charging diode D22 and one end of the capacitor C25 respectively, the anode of the charging diode D22 is grounded through the power supply winding N23 of the transformer, and the other end of the capacitor C25 is grounded.

10. The control circuit according to claim 8 or 9, characterized in that: The MOS tube Q1 is an NMOS tube.

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