Zero-temperature duty cycle adjustable oscillation circuit and adjustment method

Abstract

The application belongs to the field of chips, and provides a zero-temperature duty cycle adjustable oscillation circuit. The circuit comprises a first NAND gate, a first input end of the first NAND gate is connected with an output end of a first NOT gate, an output end is connected with a gate of a first NMOS tube, a drain of the first NMOS tube is connected with a gate of a second NMOS tube, a drain of the second NMOS tube is connected with an input end of a second NOT gate, an output end of the second NOT gate is connected with an input end of a third NOT gate, an output end of the third NOT gate is connected with a first input end of a second NAND gate, an output end of the second NAND gate is connected with a gate of a third NMOS tube, a drain of the third NMOS tube is connected with a gate of a fourth NMOS tube, a drain of the fourth NMOS tube is connected with an input end of a fourth NOT gate, an output end of the fourth NOT gate is connected with an input end of the first NOT gate, and the drains of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are respectively connected with a current source and a grounding capacitor. The first input end and the second input end of the first NAND gate and the second NAND gate are connected with a first input end and a second input end of a logic control chip, a first output end and a second output end of the logic control chip are respectively connected with a second input end of the first NAND gate and the second NAND gate, and the logic control chip has a reset end. The application can realize that the output frequency does not change with temperature and power voltage without increasing the chip area, and the back lock mechanism is introduced to eliminate the indefinite state in the circuit, which may cause the output frequency change problem.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip, in particular to a zero-temperature duty cycle adjustable oscillation circuit and adjusting method. BACKGROUND

[0002] At present, the frequency generation circuit inside the chip mainly has the following two ways:

[0003] Method 1: using ring oscillation to generate a fixed frequency, as shown in the following figure, the working principle of the circuit is as follows: a ring oscillation is formed through a 5-stage inverter circuit, current I1 charges the capacitor C to reach the flip threshold of the next stage of inverter circuit or current I2 discharges the capacitor C to be lower than the flip threshold of the next stage of inverter circuit, and the ring oscillation circuit continuously flips. Figure 1

[0004] Method 2: as shown in the following figure, the oscillation circuit of the comparator plus current charging method, when the comparator output is high, the capacitor C0 is charged through the current Ic, when the voltage reaches Vref1, the comparator output flips to low, and the positive voltage of the comparator switches to Vref2, the capacitor C0 is discharged through the current Idc, when the negative voltage of the comparator is lower than Vref2, the comparator output is low, through this method, the cycle is repeated, and a CLK frequency output is realized. Figure 2

[0005] The defects of the prior art are as follows:

[0006] The problems of the ring oscillation of method 1 are as follows:

[0007] 1. The frequency changes obviously with VDD;

[0008] 2. The output frequency duty cycle is greatly affected by temperature and process, and a controlled duty cycle frequency cannot be effectively output;

[0009] The defects of method 2 are as follows:

[0010] 1. Method 2 introduces a comparator to solve the problem of frequency change with power supply voltage, but the speed of the comparator limits the highest frequency of the output, if the CLK frequency is required to be higher, the speed of the comparator also needs to be larger, and a larger power consumption is introduced;

[0011] 2. Because method 2 introduces a comparator, there is a minimum working voltage limit, and the minimum working voltage of the circuit must ensure the normal work of the comparator;

[0012] 3. Because method 2 introduces two Vref1 and Vref2 voltage values, another circuit is required to provide corresponding voltages. SUMMARY

[0013] ​​In view of the above technical problems, the present application provides a zero-temperature duty cycle adjustable oscillation circuit and an adjusting method, which can realize the output frequency not changing with temperature and power voltage without increasing the chip area, and introduces a back lock mechanism to eliminate the indefinite state in the circuit which may cause the output frequency to change.

[0014] Other features and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0015] Based on one aspect of the present application, a zero-temperature duty cycle adjustable oscillation circuit is disclosed, which comprises a first NAND gate, a first input end of the first NAND gate is connected to an output end of a first NAND gate, an output end is connected to a gate of a first NMOS tube, a drain of the first NMOS tube is connected to a gate of a second NMOS tube, a drain of the second NMOS tube is connected to an input end of a second NAND gate, an output end of the second NAND gate is connected to an input end of a third NAND gate, an output end of the third NAND gate is connected to a first input end of a second NAND gate, an output end of the second NAND gate is connected to a gate of a third NMOS tube, a drain of the third NMOS tube is connected to a gate of a fourth NMOS tube, a drain of the fourth NMOS tube is connected to an input end of a fourth NAND gate, an output end of the fourth NAND gate is connected to an input end of the first NAND gate, the drains of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are further respectively connected to a current source and a ground capacitor, the first input end and the second input end of the first NAND gate and the second NAND gate are connected to a first input end and a second input end of a logic control chip, the first output end and the second output end of the logic control chip are respectively connected to a second input end of the first NAND gate and the second NAND gate, and the logic control chip has a reset end.

[0016] Further, the current source adopts a Cascode structure.

[0017] Further, the sources of the second NMOS tube and the fourth NMOS tube are connected to a compensation module.

[0018] Further, the compensation module comprises a fifth NMOS tube and a sixth NMOS tube constituting a current mirror structure, the source of the second NMOS tube or the fourth NMOS tube is connected to a drain of the fifth NMOS tube, and a drain of the sixth NMOS tube is connected to another current source.

[0019] Further, the compensation module is a ground positive temperature resistance.

[0020] According to another aspect of the present application, there is provided a method for adjusting a zero-temperature duty cycle adjustable oscillation circuit, which is applied to the circuit as described above, and the method controls the logic control chip to keep the output state of the circuit unchanged to realize a back lock, the first input end of the logic control chip is connected to the first input end of the first NAND gate, the second input end is connected to the first input end of the second NAND gate, the first output end is connected to the second input end of the first NAND gate, and the second output end is connected to the second input end of the second NAND gate.

[0021] The technical solution of the present application has the following beneficial effects:

[0022] By adopting the negative feedback mechanism, an output frequency close to zero temperature change is realized; the circuit can work under low power voltage; by controlling the current for charging the capacitor, the duty cycle can be adjusted at will; the back lock is introduced to ensure the reliability of the output frequency of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A schematic diagram of a ring oscillation circuit in the background art of the present application;

[0024] Figure 2 A schematic diagram of a comparator oscillation circuit in the background art of the present application;

[0025] Figure 3 A schematic diagram of a zero-temperature duty cycle adjustable oscillation circuit in the embodiment of the present application;

[0026] Figure 4 A schematic diagram of each port of the logic control chip in the embodiment of the present application;

[0027] Figure 5 A truth table of the back lock mechanism in the embodiment of the present application;

[0028] Figure 6 A state diagram of the oscillation circuit in the embodiment of the present application;

[0029] Figure 7 A diagram of the output frequency of the oscillation circuit in the embodiment of the present application;

[0030] Figure 8 A schematic diagram of a positive temperature resistance realizing a negative feedback compensation mechanism in the embodiment of the present application;

[0031] Figure 9 A schematic diagram of a MOS transistor realizing a negative feedback compensation mechanism in the embodiment of the present application. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other methods, components, devices, steps, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0033] like Figure 3 As shown, an embodiment of the present specification provides a zero-temperature duty cycle adjustable oscillator circuit, which includes a first NAND gate Y1, wherein a first input terminal of the first NAND gate Y1 is connected to an output terminal of a first NMOS transistor F1, an output terminal of the first NMOS transistor Y1 is connected to a gate of a first NMOS transistor MN1, a drain terminal of the first NMOS transistor MN1 is connected to a gate of a second NMOS transistor MN2, a drain terminal of the second NMOS transistor MN2 is connected to an input terminal of a second NMOS transistor F2, an output terminal of the second NMOS transistor F2 is connected to an input terminal of a third NMOS transistor F3, an output terminal of the third NMOS transistor F3 is connected to a first input terminal of a second NAND gate Y2, an output terminal of the second NAND gate Y2 is connected to a gate terminal of a third NMOS transistor MN3, a drain terminal of the third NMOS transistor MN3 is connected to a gate terminal of a fourth NMOS transistor MN4, and a fourth NMOS transistor MN5 is connected to a gate terminal of a fourth NMOS transistor MN6. The drain of the NMOS transistor MN4 is connected to the input of the fourth NOT gate F4, and the output of the fourth NOT gate F4 is connected to the input of the first NOT gate F1. The drains of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are also connected to a current source (I0, I1, I2) and a grounding capacitor (C1, C2), respectively. The first inputs of the first NAND gate Y1 and the second NAND gate Y2 are connected to the first input Seta and the second input Setb of a logic control chip. The first output OUT and the second output OUTB of the logic control chip are connected to the second inputs of the first NAND gate Y1 and the second NAND gate Y2, respectively. The logic control chip has a reset terminal Reset.

[0034] The various ports of the logic control chip are as follows Figure 4 As shown, the circuit maintains an output state unchanged by controlling the logic control chip to achieve back-locking. The first input terminal of the logic control chip is connected to the first input terminal of the first NAND gate, the second input terminal of the logic control chip is connected to the first input terminal of the second NAND gate, the first output terminal of the logic control chip is connected to the second input terminal of the first NAND gate, and the second output terminal of the logic control chip is connected to the second input terminal of the second NAND gate.

[0035] The present invention is mainly used to generate frequency signals inside the chip. On the basis of not increasing the chip area, it can realize that the output frequency does not change with temperature and power supply voltage. At the same time, it introduces a back-lock mechanism to eliminate the problem of unstable state in the circuit that may cause output frequency change. The overall architecture is as follows: Figure 3 As shown, since the structure does not use a comparator circuit, the current source input can use a Cascode structure. Since the current source has a low requirement for the VDD voltage, the oscillation circuit can operate at a lower VDD power supply voltage.

[0036] The truth table of the lockback mechanism is as follows Figure 5 As shown, 0 represents a low-level input / output signal, 1 represents a high-level input / output signal, Seta / Setb is Figure 3 The output signal of the oscillation circuit, that is, the signal of the first input terminal of the first NAND gate and the second NAND gate, is used to generate the signal OUT / OUTB; Reset is the initial reset signal of the reset terminal, OUT is the output signal of the oscillation circuit, that is, the signal of the second input terminal of the first NAND gate, which is used for other module circuits inside the chip. At the same time, OUT / OUTB is fed back to the internal module of the circuit to complete the backlock function.

[0037] The working process of the circuit is as follows Figure 6 As shown, there are 5 states in total. The 5 working states form a cycle to generate the OUT frequency signal. Specifically, the states are as follows:

[0038] State 1: When the chip is not working, the Reset signal is 0, OUT=0, OUTB=1, and the frequency waveform OUT output is always low. When the Reset signal is 1, Seta=1, Setb=0, Figure 5 As shown in the truth table, OUT=1, OUTB=0.

[0039] State 2: OUTB = 0, which will cause the gate of MN3 tube to be high level, pulling down the voltage of point B of the circuit, resulting in Setb = 1, and Seta = 1. Figure 5 As shown in the truth table, the output OUT=1, OUTB=0 is maintained, and the capacitor C1 is charged by the current source I1 (charging time t1). When the voltage at point A reaches Vx, the voltage at point C of the circuit will be pulled down to close to 0.

[0040] State 3: When the voltage at point C of the circuit is low, Seta is low level 0, and Setb is high level 1. Figure 5 As shown in the truth table, OUT=0, OUTB=1.

[0041] State 4: When OUTB = 0, the voltage of point A of the circuit is pulled down to 0 by MN1 MOS tube, Seta = 1, Setb = 1, so the output remains OUT = 0, OUT = 1, and the point C2 is charged by the current source I2 (charging time t2), when the voltage of point B reaches Vx, it will cause the voltage of point D to be pulled down to nearly 0.

[0042] State 5: When the voltage of point D is low 0, Setb is low 0, and Seta is high 1, the next state will return to state 1.

[0043] The trigger of the backlock mechanism will be beneficial to the duty cycle adjustment and the elimination of the undefined state, as shown in Figure 7 which will cause the initial state of each CLK clock high (t1) and low (t2) to be consistent, and the capacitor C is charged by the current I1 or I0, so for the error of the duty cycle, only the current I1 or I0 needs to be corrected.

[0044] It can be seen from Figure 7 that the working principle of the circuit is that the frequency output formed by states 1 to 5 is as shown in Figure 7 When the capacitances C of points A and B of the circuit and the flip voltage Vx are consistent, the relationship between the frequency f of the output frequency OUT and the voltage Vx, the current I1 and I0 is as shown in the following formula, if it is required to ensure that the frequency f is constant, the t1 and t2 time can be controlled by controlling the current I1 / I2 ratio, so as to control the output frequency and the duty cycle.

[0045] C*Vx = I1*t1;

[0046] C*Vx = I2*t2;

[0047]

[0048] In the above formula, the currents I1 and I2 are temperature-independent currents, the capacitance C value is also temperature-independent, and if Vx is temperature-independent, then the frequency f is temperature-independent; due to the characteristics of MOS tubes MN2 and MN4, the threshold voltage and electron mobility of the MOS tube will decrease when the temperature rises, as shown in the following formula, the threshold voltage Vth and the electron mobility μ n are negative temperature characteristics.

[0049]

[0050]

[0051] The threshold voltage Vth and the electron mobility μ nThe impact on the Vx node is an opposite relationship. The reduction of the threshold voltage will cause the Vx node voltage to drop, and the reduction of the electron mobility will cause the Vx voltage to rise. However, the impact of Vth is greater than the impact of the electron mobility, so it will cause the voltage of the Vx point to drop, which in turn affects the frequency to become faster. This embodiment introduces a negative feedback compensation mechanism to reduce the change of Vx with temperature, so that the frequency basically does not change with temperature. There are many forms of negative feedback mechanisms, two of which are Figure 8 and Figure 9 shown.

[0052] The source of the second NMOS transistor and the fourth NMOS transistor is connected to a compensation module, which is a grounded positive temperature resistor. Figure 8 The negative feedback compensation mechanism implemented by the resistor is shown in the following formula. The current I0 is a zero-temperature current. By introducing a positive temperature resistor whose resistance changes with temperature, when the temperature rises, the resistance of the resistor R1 continues to increase, which will cause the voltage on the resistor R1 to increase, maintaining the voltage of Vx unchanged.

[0053]

[0054] In one embodiment, the compensation module includes a fifth NMOS transistor and a sixth NMOS transistor forming a current mirror structure, the source of the second NMOS transistor or the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, and the drain of the sixth NMOS transistor is connected to another current source. Figure 9 As shown in the figure, it is a negative feedback compensation mechanism based on MOS tube. MOS forms a positive temperature resistor to compensate for the reduction of Vx voltage caused by the reduction of threshold voltage. The I3 current is a zero-temperature current. The Vgs6 voltage of MN6 tube conforms to the following formula:

[0055]

[0056]

[0057] When the Vx voltage just rises, the MOM tube MN5 is in the linear region, and its Ron conforms to the formula of the linear region. Assuming that the size of MN6 is K times that of MN5, the calculation formula of MN6 is as follows:

[0058]

[0059] When the Vx voltage gradually rises, the voltage at point C will gradually decrease. When it reaches the next level of flip threshold, it will immediately enter the next state. At this time, MN2 is in the saturation region. The current balance equation can be obtained as follows:

[0060]

[0061] In the above formula, μn Substitute into Vx, the relationship between Vx voltage and Ron can be obtained, and the following formula is obtained:

[0062]

[0063] Assuming I3=k1*I0, MN6 tube size is K2 times the size of MN2 tube, combined with the above formula can be obtained as follows: From the formula, when the temperature rises, Vth decreases, and the electron mobility Un also decreases, but the algebraic term related to the electron mobility is increasing, which is compensated by the MOS tube. Adjust the value of K / (2*K1*K2) to increase the coefficient proportional to the temperature in the following formula to compensate for the decrease of Vx caused by the negative temperature characteristic of Vth.

[0064]

[0065] When the Vx voltage does not change with temperature, an output frequency that does not change with temperature can be achieved.

[0066] The technical solutions of the present disclosure have the following beneficial effects:

[0067] By adopting a negative feedback mechanism, an output frequency close to zero temperature change is achieved; it can work at low power voltage; by controlling the current for charging the capacitor, the duty cycle can be adjusted at will; by introducing a back lock, the reliability of the circuit output frequency is ensured.

[0068] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptive changes to the present disclosure that adhere to the general principles of the present disclosure and include common knowledge or conventional techniques in the art that are not disclosed by the present disclosure. The specification and embodiments are only considered exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A zero-temperature duty cycle adjustable oscillator circuit, characterized in that: The circuit comprises a first NAND gate, a first input end of the first NAND gate is connected with an output end of a first NAND gate, an output end is connected with a gate of a first NMOS tube, a drain of the first NMOS tube is connected with a gate of a second NMOS tube, a drain of the second NMOS tube is connected with an input end of a second NAND gate, an output end of the second NAND gate is connected with an input end of a third NAND gate, an output end of the third NAND gate is connected with a first input end of a second NAND gate, an output end of the second NAND gate is connected with a gate of a third NMOS tube, a drain of the third NMOS tube is connected with a gate of a fourth NMOS tube, a drain of the fourth NMOS tube is connected with an input end of a fourth NAND gate, an output end of the fourth NAND gate is connected with an input end of the first NAND gate, the drains of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are respectively connected with a current source and a grounding capacitor, the sources of the second NMOS tube and the fourth NMOS tube are connected with a compensation module, the compensation module comprises a fifth NMOS tube and a sixth NMOS tube forming a current mirror structure, the source of the second NMOS tube or the fourth NMOS tube is connected with a drain of the fifth NMOS tube, a drain of the sixth NMOS tube is connected with another current source, the sources of the first NMOS tube and the third NMOS tube are grounded, the first NAND gate and the second NAND gate have only two input ends, wherein the first input ends of the first NAND gate and the second NAND gate are connected with a first input end Seta and a second input end Setb of a logic control chip, a first output end OUT and a second output end OUTB of the logic control chip are respectively connected with the second input ends of the first NAND gate and the second NAND gate, the logic control chip has a reset end Reset.

2. A zero temperature duty cycle adjustable oscillator circuit according to claim 1, characterized in that The current source adopts a Cascode structure.

3. A method of adjusting a zero-temperature duty cycle adjustable oscillation circuit, characterized by, The method is applied to the circuit of any one of claims 1-2, the method keeps the output state of the circuit unchanged by controlling the logic control chip, so as to realize the back locking, the first input end Seta of the logic control chip is connected with the first input end of the first NAND gate, the second input end Setb is connected with the first input end of the second NAND gate, the first output end OUT is connected with the second input end of the first NAND gate, and the second output end OUTB is connected with the second input end of the second NAND gate.

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