Narrow pulse signal broadening circuit and signal broadening method

Abstract

The invention discloses a narrow pulse signal broadening circuit. The narrow pulse signal broadening circuit comprises a first narrow pulse broadening signal generation unit, a second narrow pulse broadening signal generation unit and a broadening signal synthesis unit, input signals including adjacent front and back narrow pulse signals are simultaneously input to the first narrow pulse broadening signal generation unit and the second narrow pulse broadening signal generation unit; a first periodic signal is input into the second narrow pulse broadening signal generation unit, and a second periodic signal is input into the first narrow pulse broadening signal generation unit and the second narrow pulse broadening signal generation unit at the same time; the first narrow pulse broadening signal generation unit generates a first narrow pulse broadening signal, and the second narrow pulse broadening signal generation unit generates a second narrow pulse broadening signal; and the first narrow pulse broadening signal and the second narrow pulse broadening signal are input into a broadening signal synthesis unit to generate an output signal after narrow pulse broadening for the input signal.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and in particular to a narrow pulse signal stretching circuit and a signal stretching method. Background Art

[0002] In digital signal processing, it is often necessary to send periodic narrow pulse signals to digital circuits for subsequent processing. If the clock signal of the digital circuit is not sufficient to capture the narrow pulse signal, the narrow pulse signal needs to be widened to a signal that the digital circuit can recognize (usually a pulse width of more than two clock cycles is required). However, if the two narrow pulse signals appear close to each other, such as Figure 1 As shown in the figure, simply widening the front narrow pulse signal and the rear narrow pulse signal will cause the front and rear pulse signals to overlap after widening and then synthesize into one pulse signal, thereby causing the two adjacent narrow pulse signals to be recognized as one pulse signal after the widening process.

[0003] It can be seen that a new narrow pulse signal widening circuit and widening method is needed in the prior art. Based on this circuit and method, it can be ensured that closely connected narrow pulse signals can be accurately identified and widened into two pulse signals. Summary of the invention

[0004] The technical purpose to be achieved by the present invention is to provide a narrow pulse signal stretching circuit, based on which adjacent narrow pulses can be accurately identified and stretched, thereby avoiding overlapping of the stretched signals due to adjacent narrow pulses being too close.

[0005] Based on the above technical purpose, the present invention provides a narrow pulse signal stretching circuit, the narrow pulse signal stretching circuit comprising: a first narrow pulse stretching signal generating unit, a second narrow pulse stretching signal generating unit and a stretching signal synthesizing unit;

[0006] An input signal including adjacent front and rear narrow pulse signals is simultaneously input to the first narrow pulse stretch signal generating unit and the second narrow pulse stretch signal generating unit;

[0007] The first periodic signal is input to the second narrow pulse stretch signal generating unit, and the second periodic signal is simultaneously input to the first narrow pulse stretch signal generating unit and the second narrow pulse stretch signal generating unit;

[0008] The first narrow pulse stretching signal generating unit generates a first narrow pulse stretching signal, and the second narrow pulse stretching signal generating unit generates a second narrow pulse stretching signal;

[0009] The first narrow pulse stretch signal and the second narrow pulse stretch signal are input to a stretch signal synthesis unit to generate an output signal after narrow pulse stretching of the input signal.

[0010] In one embodiment, the first periodic signal is a narrow pulse periodic signal with a certain period, and the second periodic signal is a periodic signal with the same period as the first periodic signal, which is obtained by widening the narrow pulse of the first periodic signal.

[0011] In one embodiment, the duty cycle of the second periodic signal is greater than the pulse duty cycle of the first periodic signal.

[0012] In one embodiment, the second narrow pulse stretch signal generating unit includes: a first NAND gate, a first inverter, an RS flip-flop, a second inverter, a third inverter and a D flip-flop.

[0013] In one embodiment, the first input of the first NAND gate is connected to the input signal, the second input of the first NAND gate is connected to the second periodic signal, the output of the first NAND gate is connected to the first inverter, and the output of the first inverter is connected to the S input of the RS flip-flop. The R input of the RS flip-flop is connected to the first periodic signal; the Q output of the RS flip-flop is connected to the D input of the D flip-flop; the second periodic signal is input to the second inverter, and the output of the second inverter is connected to the clock input of the D flip-flop; the first periodic signal is input to the third inverter; the output of the third inverter is connected to the reset control terminal of the D flip-flop, and the front narrow pulse width signal is output from the Q output of the D flip-flop.

[0014] In one embodiment, the first narrow pulse stretching signal generating unit includes: a fourth inverter, a first NOR gate and a pulse stretching module.

[0015] In one embodiment, the input signal is input to the fourth inverter, the output of the fourth inverter is connected to the first input of the first NOR gate, and the second input of the first NOR gate is connected to the second periodic signal; the output of the first NOR gate is connected to the pulse stretching module, and the pulse stretching module outputs a first narrow pulse stretching signal.

[0016] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0018] Figure 1 It is a schematic diagram of the timing of narrow pulse signal widening processing signal in the prior art;

[0019] Figure 2 It is a schematic diagram of the architecture of the narrow pulse signal widening circuit system of the present invention;

[0020] Figure 3 It is a schematic diagram of the structure of the narrow pulse signal widening circuit of the present invention;

[0021] Figure 4 It is a schematic diagram of the signal timing of the narrow pulse signal widening circuit of the present invention; DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0023] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0024] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0025] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] Example 1

[0027] like Figure 2-3 The narrow pulse signal stretching circuit of the present invention is shown, and the narrow pulse signal stretching circuit of the present invention comprises a first narrow pulse stretching signal generating unit 100, a second narrow pulse stretching signal generating unit 200 and a stretching signal synthesizing unit 300. An input signal including adjacent front and rear narrow pulse signals is simultaneously input into the first narrow pulse stretching signal generating unit 100 and the second narrow pulse stretching signal generating unit 200. A first periodic signal is input into the second narrow pulse stretching signal generating unit 200, and a second periodic signal is simultaneously input into the first narrow pulse stretching signal generating unit 100 and the second narrow pulse stretching signal generating unit 200. The first narrow pulse stretching signal is generated by the first narrow pulse stretching signal generating unit 100, and the second narrow pulse stretching signal is generated by the second narrow pulse stretching signal generating unit 100. The first narrow pulse stretching signal and the second narrow pulse stretching signal are input into the stretching signal synthesizing unit 300 to generate an output signal after narrow pulse stretching of the input signal.

[0028] The first periodic signal is a narrow pulse periodic signal with a certain period, and the second periodic signal is a periodic signal with the same period as the first periodic signal, and the narrow pulse of the first periodic signal is widened. That is, the first periodic signal and the second periodic signal have the same period, and the rising edges of the pulses are aligned, but the duty cycle of the second periodic signal is greater than the pulse duty cycle of the first periodic signal. In this embodiment, the duty cycle of the second cycle signal is set to 50%, but it can also be set to other values ​​such as 20% or 80% according to actual needs.

[0029] Further, the second narrow pulse stretch signal generating unit 200 of the present embodiment includes: a first NAND gate 201, a first inverter 202, an RS trigger 203, a second inverter 204, a third inverter 205 and a D trigger 206. The first input of the first NAND gate 201 is connected to the input signal, the second input of the first NAND gate 201 is connected to the second periodic signal, the output of the first NAND gate 201 is connected to the first inverter 202, and the output of the first inverter 202 is connected to the S input of the RS trigger 203. The R input of the RS trigger 203 is connected to the first periodic signal. The Q output of the RS trigger 203 is connected to the D input of the D trigger 206. The second periodic signal is input to the second inverter 204, and the output of the second inverter 204 is connected to the clock input of the D trigger 206. The first periodic signal is input to the third inverter 205. The output terminal of the third inverter 205 is connected to the reset control terminal of the D flip-flop 206 , and the Q output terminal of the D flip-flop 206 outputs the front narrow pulse stretching signal.

[0030] Furthermore, the first narrow pulse stretching signal generating unit 100 of the present embodiment includes: a fourth inverter 101, a first NOR gate 102, i.e., a pulse stretching module 103. The input signal is input to the fourth inverter 101, the output end of the fourth inverter 101 is connected to the first input end of the first NOR gate 102, and the second input end of the first NOR gate 102 is connected to the second periodic signal. The output end of the first NOR gate 102 is connected to the pulse stretching module 103, and the pulse stretching module 103 is a common pulse stretching circuit used in the prior art, such as a common falling edge delay circuit, etc. The pulse stretching module 103 outputs a rear narrow pulse stretching signal.

[0031] In the present invention, two narrow pulse signals connected before and after the input signal are divided into two categories for processing, namely, narrow pulses appearing in the first half cycle and narrow pulses appearing in the second half cycle. The narrow pulses appearing in the second half cycle are processed through the upper half branch; the narrow pulses appearing in the first half cycle are processed through the lower half branch, and the input signal is widened to half the cycle width through the RS trigger and the D trigger, and appears in the second half cycle.

[0032] For the first narrow pulse stretching signal generating unit 100, when the second period signal is at a low level, the input signal is sent to the pulse stretching module 103, and after passing through the pulse stretching module 103, a first narrow pulse stretching signal with an unchanged rising edge and a delayed falling edge is generated. The delay time represents the width of the pulse after stretching. Controlling the delay time to be less than half a period can ensure that it will not overlap with the second narrow pulse stretching signal.

[0033] For the second narrow pulse stretching signal generating unit 200, when the second cycle signal is at a high level, the input signal is sent to the input S terminal of the RS trigger. When the second cycle signal trigger detects the rising edge of the input signal, the output Q becomes high and is sent to the input D terminal of the D trigger. When the second cycle signal changes from high to low, the clock input CLK terminal of the D trigger changes from low to high, and at the same time, the D terminal input signal of the D trigger is sent to the output Q terminal, and the previous narrow pulse stretching signal becomes high until the next cycle arrives. The first cycle signal becomes high and is sent to the reset control terminal RSTB of the D trigger through the third inverter to reset the second narrow pulse stretching signal to a low level.

[0034] The first narrow pulse stretch signal and the second narrow pulse stretch signal pass through the second NOR gate 301 and the fifth inverter 302 to form a stretched output signal.

[0035] like Figure 4 As shown in the timing diagram, even if there are two closely spaced narrow pulses in the input signal, they will not overlap after being stretched, thereby satisfying the requirement that the subsequent digital circuit can capture the two input narrow pulse signals at DET1 and DET2 respectively, so as to achieve the design purpose of the present invention.

[0036] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A narrow pulse signal widening circuit, characterized in that: The narrow pulse signal stretching circuit comprises: a first narrow pulse stretching signal generating unit, a second narrow pulse stretching signal generating unit and a stretching signal synthesizing unit; An input signal including adjacent front and rear narrow pulse signals is simultaneously input to the first narrow pulse stretch signal generating unit and the second narrow pulse stretch signal generating unit; The first periodic signal is input to the second narrow pulse stretch signal generating unit, and the second periodic signal is simultaneously input to the first narrow pulse stretch signal generating unit and the second narrow pulse stretch signal generating unit; The first narrow pulse stretching signal generating unit generates a first narrow pulse stretching signal, and the second narrow pulse stretching signal generating unit generates a second narrow pulse stretching signal; The first narrow pulse stretch signal and the second narrow pulse stretch signal are input to a stretch signal synthesis unit to generate an output signal after narrow pulse stretching of the input signal.

2. The narrow pulse signal stretching circuit according to claim 1, characterized in that: The first periodic signal is a narrow pulse periodic signal with a certain period, and the second periodic signal is a periodic signal having the same period as the first periodic signal, which is obtained by widening the narrow pulse of the first periodic signal.

3. The narrow pulse signal stretching circuit according to claim 2, characterized in that: The duty cycle of the second period signal is greater than the pulse duty cycle of the first period signal.

4. The narrow pulse signal stretching circuit according to claim 1, characterized in that: The second narrow pulse stretch signal generating unit includes: a first NAND gate, a first inverter, an RS trigger, a second inverter, a third inverter and a D trigger.

5. The narrow pulse signal stretching circuit according to claim 4, characterized in that: The first input terminal of the first NAND gate is connected to the input signal, the second input terminal of the first NAND gate is connected to the second periodic signal, the output terminal of the first NAND gate is connected to the first inverter, the output of the first inverter is connected to the S input terminal of the RS trigger, and the R input terminal of the RS trigger is connected to the first periodic signal; The Q output terminal of the RS trigger is connected to the D input terminal of the D trigger; the second periodic signal is input to the second inverter, and the output terminal of the second inverter is connected to the clock input terminal of the D trigger; the first periodic signal is input to the third inverter; the output terminal of the third inverter is connected to the reset control terminal of the D trigger, and the front narrow pulse widening signal is output by the Q output terminal of the D trigger.

6. The narrow pulse signal stretching circuit according to claim 1, characterized in that: The first narrow pulse stretching signal generating unit includes: a fourth inverter, a first NOR gate and a pulse stretching module.

7. The narrow pulse signal stretching circuit according to claim 6, characterized in that: The input signal is input to the fourth inverter, the output of the fourth inverter is connected to the first input of the first NOR gate, and the second input of the first NOR gate is connected to the second periodic signal; the output of the first NOR gate is connected to the pulse stretching module, and the pulse stretching module outputs a first narrow pulse stretching signal.

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