A frequency division synchronous circuit applied to a multi-channel analog-digital converter

Abstract

The application discloses a frequency division synchronous circuit applied to a multi-channel analog-digital converter, which is composed of three main modules of a frequency division reconstruction circuit, a synchronous signal generation circuit and a clock distribution circuit. The multi-channel analog-digital converter needs a reasonably designed clock system to provide a timing basis for the cooperative work of each module, but the existing clock system has problems of large jitter, fuzzy state and low efficiency, and the multi-channel analog-digital converter based on the clock system is difficult to meet the needs of the fast developing communication and detection array system. The application is an improved clock system, which reduces the sampling clock jitter through an edge reconstruction technology, thereby improving the sampling noise and improving the conversion precision; the phase ambiguity of the frequency division is eliminated through a synchronous strategy, which is beneficial to data processing and correction, and the clock system can be reset to a specific initial state under control, which is beneficial to array application; through a bus type clock distribution strategy, the number of clock transmission lines is reduced, and the circuit operation efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, in particular to a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter. BACKGROUND

[0002] An analog-to-digital converter is a tool for converting a received analog signal into a digital signal for processing, and the conversion accuracy, power consumption and synchronizability usually affect the implementation form and performance of the entire communication and detection system, so it is of great practical significance for the rapid development of communication and detection array systems to continuously improve the structure of the analog-to-digital converter, so that it has higher conversion accuracy and lower power consumption, and has more suitable synchronizability for array applications.

[0003] In high-speed and medium-high-precision analog-to-digital converters, a plurality of sampling and holding channels and a plurality of conversion channels are usually used for time interleaving design to achieve the target rate and accuracy. However, as the number of channels increases, the structure of the analog-to-digital converter becomes complex, and a reasonably designed clock system is needed to provide a timing basis for the cooperative work of each module, and at the same time ensure power efficiency and physical realizability.

[0004] However, the clock system of the traditional multi-channel analog-to-digital converter usually has the following problems:

[0005] 1. The multi-phase clock generated by the frequency divider has large jitter, which causes the sampling time to jitter and introduces noise, thereby reducing the signal-to-noise ratio;

[0006] 2. The initial state of the frequency divider is uncertain and cannot be reset, which causes the running order and working state of the channels to be ambiguous to some extent, which is not conducive to the correction of the data later and the application of the multi-converter array;

[0007] 3. With the increase in the number of channels and the number of clocks required by each channel, a large number of clock lines are used to transmit clock signals, resulting in low clock distribution efficiency and higher requirements for layout. SUMMARY

[0008] The multi-channel analog-to-digital converter needs a well-designed clock system to achieve time interleaving of high-quality sampling and holding and conversion channels to achieve the target accuracy, but the traditional clock system has the disadvantages of large jitter, ambiguous state, and low distribution efficiency, which makes it difficult to be well applied.

[0009] The present application aims to solve the above problems and provides a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter, so that the clock system has the advantages of state determination, reset, low jitter, low power consumption and low complexity.

[0010] The technical scheme of the present application is as follows:

[0011] The application comprises a frequency division reconstruction circuit, a synchronous signal generation circuit and a clock distribution circuit.

[0012] The frequency division reconstruction circuit is used to divide the externally input clock signal into multiple clock signals required by the multiple sampling and holding channels and the multiple conversion channels, and to reduce the clock jitter generated in the frequency division process by using a signal reconstruction technique.

[0013] The synchronous signal generation circuit is used to generate a synchronous signal to provide a resettable and determined starting time and initial state for the frequency division of the clock signal, so that the multiple clock signals after the frequency division run in a set state.

[0014] The clock distribution circuit is used to distribute the multiple clock signals after the frequency division into the corresponding sampling and holding channels and conversion channels.

[0015] In a preferred embodiment, the frequency division reconstruction circuit comprises two-stage frequency dividers, the first-stage frequency divider divides the externally input clock signal into multiple clock signals corresponding to the sampling and holding channels, and each clock signal is input into a second-stage frequency divider to continue to be divided into multiple clock signals required by the conversion channels.

[0016] In a preferred embodiment, in the first-stage frequency divider, the signal after the frequency division is reconstructed into a clock signal with low clock jitter after a logical operation with the input clock signal, and is output to the corresponding sampling and holding channel for low-jitter sampling to improve the signal-to-noise ratio of the sampling.

[0017] In a preferred embodiment, both the two-stage frequency dividers are composed of D flip-flop rings, and the required clock signals after the frequency division are generated by driving the D flip-flop rings with the clock signals before the frequency division.

[0018] In a preferred embodiment, the synchronous signal generation circuit is driven by an externally input synchronous source signal to generate a synchronous signal pulse for resetting the frequency division reconstruction circuit and has a deburring function.

[0019] In a preferred embodiment, the signal pulse generated by the synchronous signal generation circuit is divided into two types, one type has a length consistent with the period of the externally input clock signal and is used to reset the state of the first-stage frequency division circuit, and the other type has a length consistent with the period of the clock signal output by the first-stage frequency divider and is used to reset the state of the second-stage frequency division circuit.

[0020] In a preferred embodiment, the clock distribution circuit is divided into two stages, the first-stage clock distribution circuit distributes the multiple clock signals output by the first-stage frequency divider to the corresponding sampling and holding channels through a tree structure for signal sampling and second-stage frequency division.

[0021] In a preferred embodiment, the clock distribution circuit is divided into two stages, and the second stage clock distribution circuit distributes the multiple clock signals required by the conversion channel from the second stage frequency divider output to the conversion channel, and the distribution strategy is bus distribution and on-demand selection, that is, all the phase clocks of the second stage frequency divider output in the sample and hold channel are uniformly delivered to the vicinity of the conversion channel in the form of a bus, and each conversion channel obtains the clock of the required phase, thereby realizing clock distribution.

[0022] Compared with the prior art, the application has the following advantages:

[0023] (1) By means of the two-stage frequency division design of the sample and hold channel and the conversion channel, the layout of the clock link is more reasonable, and is more suitable for a multi-channel time-interleaved high-speed analog-to-digital converter with a sample and hold device.

[0024] (2) The signal reconstruction technology is applied to reconstruct the frequency-divided sample and hold channel clock, eliminate the clock jitter of the sampling edge caused in the frequency division process, improve the signal-to-noise ratio of the sampling process, and thus improve the overall performance of the analog-to-digital converter.

[0025] (3) A synchronization strategy is designed to eliminate the phase ambiguity in the frequency division process, so that the clocks of the channels have a determined corresponding relationship and a determined sequence, which is beneficial to data processing and correction; and the clock system can be reset to a specific initial state, which is used for the correction and synchronization of the running state offset, and is beneficial to the application of the analog-to-digital converter in a large-scale array.

[0026] (4) For the case that the number of conversion channels is large and each channel requires multiple clocks, a bus-type clock distribution strategy is proposed, that is, all the phase clocks are output to the clock bus by the clock module, and each channel obtains the required clock, which greatly reduces the number of clock transmission lines, is more beneficial to the layout, and improves the circuit running speed and power efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments described in the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0028] Figure 1 It is a structure diagram of a frequency division and synchronization circuit applied to a multi-channel analog-to-digital converter.

[0029] Figure 2 It is a first stage timing flow chart of a frequency division and synchronization circuit applied to a multi-channel analog-to-digital converter.

[0030] Figure 3 is a second stage timing flow chart of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter.

[0031] Figure 4 is a circuit schematic of a first stage frequency divider in a frequency division reconstruction circuit.

[0032] Figure 5 is a circuit schematic of a second stage frequency divider in a frequency division reconstruction circuit.

[0033] Figure 6 is a circuit schematic of a synchronization signal generation circuit.

[0034] Figure 7 is a timing flow chart of a synchronization strategy at a synchronization occurrence.

[0035] Figure 8 is a circuit schematic of a second stage clock distribution circuit. DETAILED DESCRIPTION

[0036] The present application will become more apparent in the following detailed description of preferred embodiments with reference to the attached drawings, wherein:

[0037] It should be noted that, in order not to obscure the present application with unnecessary details, only the structures and / or processing steps closely related to the scheme according to the present application are shown in the drawings, and other details not closely related to the present application are omitted.

[0038] In the description of the present application, if the terms "upper", "lower", "left", "right", and the like indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, they are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "highest", "first", and the like are only for the purpose of description and cannot be understood as indicating or implying relative importance.

[0039] It should be noted that the number of channels, the number of D flip-flops, and the associated frequency, phase, and the like described in the description are only the scheme of the preferred embodiment, and the circuit details are described based on this number for the sake of simplicity of description. The present application is also applicable to other channel numbers. The circuit behaviors such as "rising edge", "falling edge", and the like described in the description are only the implementation method and corresponding relationship selected by the preferred embodiment, and the purpose is to make the description concise, and are not used to limit the present application.

[0040] The application provides a frequency division synchronization circuit applied to a multi-channel analog-digital converter, which is composed of a frequency division reconstruction circuit, a synchronization signal generation circuit and a clock distribution circuit.

[0041] The main function of the frequency division reconstruction circuit is to divide the external input clock signal into driving clocks required by each part of the analog-digital converter, and to make the clock edges related to sampling have lower clock jitter by reconstruction, so as to obtain lower noise sampling.

[0042] The main function of the synchronization signal generation circuit is to generate synchronization pulses according to the external input synchronization source signal, and to deliver the synchronization pulses to two-stage frequency dividers, so as to reset the frequency divider states and serve as the frequency division starting points of the frequency dividers.

[0043] The clock distribution circuit distributes the part clocks generated by the frequency dividers to corresponding sampling and holding channels and analog-digital conversion channels.

[0044] In the preferred embodiment, the sampling and conversion part of the analog-to-digital converter is composed of 4 time-interleaved sample-and-hold channels 107, each of which includes 4 time-interleaved analog-to-digital conversion channels 105. Corresponding to the sampling and conversion part, the frequency division reconstruction circuit is divided into two stages. The first stage frequency divider 101 divides the externally input clock signal CLK_input (frequency f) by a flip-flop ring composed of 4 D flip-flops into 4 clock signals with frequency f / 4, phase difference of 90° in sequence, and duty cycle of 1 / 4, and reconstructs the falling edges of the 4 clock signals by a logic circuit to have lower clock jitter. The 4 reconstructed clock signals (102-A, 102-B, 102-C, 102-D) are distributed to each sample-and-hold channel 107 by a tree-shaped structure 109 of the first stage clock distribution circuit. Each sample-and-hold channel 107 receives one of the clock signals, which is used to drive the sampling and holding action in the sample-and-hold channel 107 and also enters the second stage frequency divider 103. The second stage frequency divider 103 has 4 frequency dividers, each of which is located in each sample-and-hold channel 107 and operates independently. From the timing point of view, the 4 frequency dividers are time-interleaved. Taking one of the second stage frequency dividers 103 as an example, the clock signal input to the sample-and-hold channel 107 is divided by a flip-flop ring composed of 4 D flip-flops into 4 clock signals (104-Xa, 104-Xb, 104-Xc, 104-Xd, where X represents one of A, B, C, and D) with frequency f / 16, phase difference of 90° in sequence, and duty cycle of 1 / 4. Since each conversion channel 105 needs 3 phase clock signals, the 4 conversion channels 105 in the sample-and-hold channel 107 need 12 clock signals. If all the clock signals are distributed by clock lines, the layout is complex. The second stage clock distribution circuit sends the 4 clock signals to the vicinity of all the conversion channels 105 in the sample-and-hold channel 107 by a clock bus 110, and the conversion channels 105 only need to take out the required 3 phase clock signals.

[0045] In the preferred embodiment, the synchronization signal generation circuit 108 generates a first stage synchronization clock SYNC1 with length of 1 / f from the rising edge of the externally input synchronization source signal and the externally input clock signal CLK_input, which is used to reset the state of the first stage frequency divider 101. Then, one of the 4 clock signals (102-A, 102-B, 102-C, 102-D) output by the first stage frequency divider 101 drives the generation of a second stage synchronization clock SYNC2 with length of 4 / f, which is used to reset the state of the second stage frequency divider 103.

[0046] The application is further described below in combination with the drawings and the preferred embodiment.

[0047] Figure 1is a structural schematic diagram of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter in the embodiment. The clock signal CLK_input is input from outside, and the first-stage frequency divider 101 in the frequency division reconstruction circuit divides and reconstructs the clock signal CLK_input into four clock signals 102-A, 102-B, 102-C and 102-D, which are input into the second-stage frequency dividers 103 and the sample-and-hold units 106 in the four sample-and-hold channels 107, respectively. The second-stage frequency dividers 103 divide the clock signals 102 into four clock signals 104-Xa, 104-Xb, 104-Xc and 104-Xd, respectively, where X represents one of A, B, C and D, and a total of 16 frequency-divided signals 104 are generated. Each conversion channel 105 needs three-phase clock signals, which are obtained from the clock bus 110 of the respective sample-and-hold channels 107.

[0048] The synchronization signal generation circuit 108 receives the external input synchronization source signal SYNC_input and generates the synchronization signals SYNC1 and SYNC2 for the first-stage and second-stage frequency dividers, respectively. The first-stage frequency divider 101 resets to the initial working state according to the SYNC1, and the second-stage frequency divider 103 resets to the initial working state according to the SYNC2.

[0049] The first-stage clock distribution circuit adopts the tree structure 109 to distribute the clock signals to the sample-and-hold channels 107. The layout orientation of the clock lines of the tree structure is consistent with that in the schematic diagram, and the four clock lines 102-A, 102-B, 102-C and 102-D are symmetrically arranged. Starting from the global center point, the clock lines are divided into two groups and extend in opposite directions. After extending to the center points on both sides, the clock lines are again divided into two groups and extend in opposite directions. For more channels, the above process is repeated, so as to ensure that the path lengths to the channels are the same. The second-stage clock distribution circuit adopts the clock bus 110 to distribute the clock signals to the conversion channels 105.

[0050] Figure 2 is a first-stage timing flowchart of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter in the embodiment. It is assumed that the frequency of the external input clock signal CLK_input is f, which is triggered by the rising edge of CLK_input, and the state of the clock signal 102 changes and the process is performed in the order of 102-A, 102-B, 102-C and 102-D, with the frequency being f / 4 and the phase difference being 90°.

[0051] Figure 3is a second stage timing flow chart of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter in the embodiment. Taking the sample-and-hold channel A as an example, the clock signal 102-A is frequency-divided by the second stage frequency divider, triggered by the rising edge of 102-A, the state of the clock 104 changes, and the cycle is performed in the order of 104-Aa, 104-Ab, 104-Ac, 104-Ad, with a frequency of f / 16 and a phase difference of 90° in turn, and a duty cycle of 1 / 4. The other three sample-and-hold channels have similar behaviors.

[0052] Figure 4 is a circuit principle diagram of the first stage frequency divider in the frequency division reconstruction circuit in the embodiment. The first stage frequency divider in the frequency division reconstruction circuit includes two parts: one is the frequency division part 401, which is composed of a trigger ring composed of four D flip-flops connected head to tail, and the other is the reconstruction part 402, which is composed of a logic circuit to reconstruct the sampling edge (in this embodiment, the falling edge of 102).

[0053] Further, in the embodiment, the D flip-flop ring is composed of 3 D flip-flops with a synchronous reset port (Reset) 403 and 1 D flip-flop with a synchronous set port (Set) 404. When the synchronization signal SYNC1 is high, the rising edge of the clock input CLK_input triggers the synchronous reset and the synchronous set, at this time the outputs QA, QB, QC, QD of the four D flip-flops are set to low, low, high, and low respectively, and the frequency divider is reset to the initial working state. When the synchronization signal SYNC1 is low, the frequency divider is in the normal working state, the four flip-flops are triggered by the rising edge of the clock input CLK_input, the output level of the previous flip-flop is read and output, thereby generating the signals QA, QB, QC, QD with a cycle, a frequency of f / 4, and a duty cycle of 1 / 4, as well as their corresponding inverse signals QNA, QNB, QNC, QND.

[0054] Because the clock jitter generated by the frequency divider is large, QA, QB, QC, QD are input into the reconstruction part 402, and QD is taken as an example for illustration here. QD and CLK_input are input into the non-inverter logic 406 through the output clock of the inverter 405. Since the falling edge of QD is slightly slower than that of the output clock of the inverter 405, the clock jitter of the rising edge of the output clock of the non-inverter logic 406 is determined by the output clock of the inverter 405, thereby eliminating the large clock jitter of this edge caused by the D flip-flop in the frequency division process. The output clock of the non-inverter logic 406 is input into the inverter 407 after being delayed, and then input into the non-inverter logic 408 with QND, thereby restoring the phase and duty cycle, and generating the signal 102-D with small falling edge clock jitter. This signal is used for sampling and second stage frequency division of the sample-and-hold in the sample-and-hold channel D, and the other channels also have similar behaviors.

[0055] Figure 5 is a circuit schematic of a second stage frequency divider in a frequency division reconstruction circuit in this embodiment. The second stage frequency divider is composed of a flip-flop ring composed of four D flip-flops connected head to tail, including one D flip-flop 501 with a synchronous set port (Set) and three D flip-flops 502 with a synchronous reset port (Reset). Taking the second stage frequency divider 103-A as an example, when the synchronous signal SYNC2 is high, the rising edge of the clock input 102-A triggers the synchronous reset and the synchronous set, at this time the outputs 104-Aa, 104-Ab, 104-Ac, 104-Ad of the four D flip-flops are set to high, low, low, and low respectively, and the frequency divider is reset to the initial working state. When the synchronous signal SYNC2 is low, the frequency divider is in the normal working state, and the four flip-flops are triggered by the rising edge of the clock input 102-A to read the output level of the previous flip-flop and output, thereby generating a cyclic signal 104-Aa, 104-Ab, 104-Ac, 104-Ad with a frequency of f / 16 and a duty cycle of 1 / 4. The phase difference of these signals is 90° in turn, which is used to sample and hold the drive of the four conversion channels corresponding to channel A.

[0056] Figure 6 is a circuit schematic of a synchronous signal generation circuit in this embodiment. The synchronous signal generation circuit generates synchronous pulses SYNC1, SYNC2 according to the rising edge of the input external synchronous signal SYNC_input, and delivers them to two stage frequency dividers, resetting the frequency divider state and serving as the frequency division starting point of the frequency divider. The input external clock CLK_input drives two D flip-flops 601 to work, and it can be seen that the output signal 611 is delayed by two beats (2 / f) from the external synchronous signal SYNC_input. The D flip-flop output signal 611 and the signal after the inverter 602 of SYNC_input are subjected to or logic 603, and the level of or logic output signal 612 is low only when the D flip-flop output signal 611 is low and SYNC_input is high. That is, the level of or logic output signal 612 is low only when the current SYNC_input is high and the SYNC_input two beats ago is low. The D flip-flop 604 with reset function is in a non-reset state, and the output SYNC1 becomes high after one beat driven by the clock, and the D flip-flop QN output signal 613 becomes low. SYNC1 returns to low at the next clock beat, and then the D flip-flop 604 returns to the reset state. Since the external synchronous signal SYNC_input is used to periodically reset the analog-to-digital converter, it is a low-frequency signal in the application scenario, so this structure can be regarded as a rising edge trigger with deburring function, and the rising edge of SYNC_input can trigger SYNC1 to generate a high-level pulse with a length of 1 / f.

[0057] SYNC1 is input to the first stage frequency divider, and after being delayed by one clock cycle by D flip-flop 605, it is input to the reset port of D flip-flop 608 driven by clock signal 102-D through absolute delay 606 and inverter 607. Only when SYNC1_D output by absolute delay 606 is high, D flip-flop 608 is not in the reset state, and at this time, triggered by the rising edge of clock signal 102-D, SYNC2 output becomes high, and D flip-flop QN output signal 614 becomes low, and the reset state is restored at the rising edge of the next clock signal 102-D. Thus, SYNC2 generates a high-level pulse with a length of 4 / f.

[0058] Figure 7 is a timing flow chart of a synchronization strategy in this embodiment when synchronization occurs. The shaded part in the figure is the phase ambiguity state. After SYNC1 becomes high, the first stage frequency divider is reset, 102-A, 102-B, 102-C, 102-D are set to low, low, high, and low respectively, and enter the normal cycle state. As can be seen, when SYNC1_D is high, it is triggered by the rising edge of 102-D, and SYNC2 generates a high-level pulse with a length of 4 / f. After SYNC2 is input to the four second stage frequency dividers, 104-Ax, 104-Bx, 104-Cx, 104-Dx (x represents a, b, c, d) are reset in turn as the rising edges of 102-A, 102-B, 102-C, 102-D arrive, thereby realizing the sequential operation of all conversion channels, and each sample-and-hold channel and conversion channel has a determined correspondence.

[0059] Figure 8 is a circuit principle diagram of a clock distribution circuit in this embodiment. Since each conversion channel 105 requires 3-phase clock (801), in the clock distribution of the second stage of each sample-and-hold channel, if these clocks are input respectively, 12 clock lines are required, which is 48 clock lines for the entire analog-to-digital converter in this embodiment, which is relatively complex and inefficient in layout layout. Taking sample-and-hold channel A as an example, the bus type clock distribution strategy proposed by the present application, four-phase clock (104-Aa, 104-Ab, 104-Ac, 104-Ad) forms a clock bus (110) to deliver to the vicinity of the four conversion channels (105), and the conversion channels obtain the required phase clock respectively, realizing the distribution of the clock. In this way, the entire clock distribution system is greatly simplified, and higher speed and higher power efficiency can be achieved.

[0060] Compared with the traditional clock system, the frequency division synchronization circuit applied to the multi-channel analog-to-digital converter matches the high-speed analog-to-digital converter architecture with a sample-and-hold channel through a hierarchical structure; reduces the sampling edge clock jitter through an edge reconstruction technology, thereby improving the sampling noise and improving the conversion precision; eliminates the phase ambiguity of frequency division through a synchronization strategy, so that the clocks of each channel have a determined corresponding relationship, which is beneficial to data processing and correction, and can be reset to a specific initial state by an external signal, which is beneficial to array application; through a bus type clock distribution strategy, the number of clock transmission lines is greatly reduced, which is more beneficial to layout, improves the circuit operation speed and power efficiency. It can be used for the design of a low-power, high-precision, synchronous multi-channel high-speed analog-to-digital converter, which provides more possibilities for the array design of various communication and detection systems and the realization of low-overhead high efficiency.

[0061] Those skilled in the art can understand that the above description is only preferred examples of the application and is not used to limit the application, although the application is described in detail with reference to the foregoing examples, those skilled in the art can still modify the technical solutions recorded in the foregoing examples or make equivalent replacement for part of the technical features. Any modification, equivalent replacement, etc. within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A frequency division synchronous circuit applied to a multi-channel analog-to-digital converter, comprising a frequency division reconstruction circuit, a synchronous signal generation circuit and a clock distribution circuit, characterized in that: the frequency division reconstruction circuit is configured to divide an externally input clock signal into multiple clock signals required by multiple sampling and holding channels and multiple conversion channels, and to apply a signal reconstruction technique to reduce clock jitter generated in the frequency division process; the synchronous signal generation circuit is configured to generate a synchronous signal to provide a resettable, determined starting time and initial state for the frequency division of the clock signal, so that the divided clock signals run in a set state; the clock distribution circuit is configured to distribute the divided clock signals to corresponding sampling and holding channels and conversion channels; the frequency division reconstruction circuit comprises two-stage frequency dividers, a first-stage frequency divider divides the externally input clock signal into multiple clock signals corresponding to the sampling and holding channels, and each clock signal is input to a second-stage frequency divider to be further divided into multiple clock signals required by the conversion channels; in the first-stage frequency divider, the divided signal is reconstructed into a clock signal with low clock jitter after logical operation with the input clock signal, and is output to the corresponding sampling and holding channel for low-jitter sampling to improve the signal-to-noise ratio of sampling; the synchronous signal generation circuit generates two types of signal pulses, one with a length consistent with the period of the externally input clock signal and used to reset the state of the first-stage frequency divider, and the other with a length consistent with the period of the output clock signal of the first-stage frequency divider and used to reset the state of the second-stage frequency divider; the clock distribution circuit comprises two stages, and a second-stage clock distribution circuit distributes the multiple clock signals required by the conversion channels and output by the second-stage frequency divider to the conversion channels, and the distribution strategy is bus distribution and on-demand selection, i.e., all the clocks of all phases output by the second-stage frequency divider in the sampling and holding channel are uniformly delivered to the vicinity of the conversion channel in a bus manner, and each conversion channel obtains the clock of the required phase to realize clock distribution.

2. The frequency division synchronization circuit for use in a multi-channel analog-to-digital converter according to claim 1, characterized in that, Both the two-stage frequency dividers are composed of D flip-flop rings, and the required divided clock signals are generated by driving the D flip-flop ring with the pre-division clock.

3. The frequency division synchronization circuit for use in a multi-channel analog-to-digital converter according to claim 1, wherein The synchronous signal generation circuit is driven by an externally input synchronous source signal to generate a synchronous signal pulse used to reset the frequency division reconstruction circuit, and has a deburring function.

4. The frequency division synchronization circuit for use in a multi-channel analog-to-digital converter according to claim 1, wherein The clock distribution circuit comprises two stages, and a first-stage clock distribution circuit distributes the multiple clock signals output by the first-stage frequency divider to the corresponding sampling and holding channels through a tree structure for signal sampling and second-stage frequency division.

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