Apparatus, method, and computer readable medium for clock synchronization

Abstract

The embodiment of the invention relates to a device for clock synchronization, a related method and a medium. In an aspect, based on performing a first set of addition or subtraction operations on a first bit value, a device obtains a quotient obtained by dividing the first bit value by a predetermined divisor, where the first bit value represents time in a first time unit. Based on the first bit value and performing a second set of addition or subtraction operations on the quotient, the device obtains a remainder obtained by dividing the first bit value by a predetermined divisor. The apparatus obtains a second bit value representing the time based on the quotient and the remainder, where the second bit value includes a first portion and a second portion, the first portion corresponding to the quotient and representing the time in a second time unit, and the second portion corresponding to the remainder and representing the time in a first time unit. According to the device for clock synchronization provided by the embodiment of the invention, the maximum clock frequency is improved on the basis of realizing the time format conversion function, and the requirement of reducing the cost is met.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the fields of communications and digital circuit technology, and more particularly to an apparatus, method, and computer-readable medium for clock synchronization. Background Art

[0002] In the IEEE1588V2 protocol implementation system, the exchanged standard IEEE1588V2 time information (IEEE1588V2 timestamp) is 80 bits, the upper 48 bits are seconds information, and the lower 32 bits are nanoseconds information.

[0003] If an 80-bit wide time counter is processed in a digital chip design, when the nanosecond field in the standard time reaches 1 second (i.e., 1000000000D=3B9ACA00H), a carry is performed on the second field. This may lead to frequent nanosecond carry processing in the design, such as addition and subtraction of asymmetric compensation, for example, by adding a compensation delay value to the standard IEEE1588V2 time or subtracting a compensation nanosecond delay value from the standard time; or as a current ToD generation calibration operation, adding the time offset of the Precision Time Protocol (PTP) slave to the standard IEEE1588V2 time counter, all of which require more hardware logic resources in the digital design and also affect the timing characteristics of the high-speed digital design. Summary of the invention

[0004] In general, the exemplary embodiments of the present disclosure relate to a technical solution for communication, for example, specifically to a high-performance digital decimal divider for obtaining time information required in a communication process.

[0005] The technical solution of the embodiment of the present disclosure can be used for a device that outputs a timestamp on a Precision Time Protocol (PTP) system port. By optimizing the corresponding calculation model, it satisfies high-bandwidth network applications and low-cost design, and at a higher maximum clock frequency F max A flexible balance is achieved between high throughput and lower conversion latency.

[0006] In a first disclosed aspect, a device for clock synchronization is provided. The device includes: at least one processor and at least one memory. The at least one memory stores instructions, which, when executed by the at least one processor, cause the device to at least: obtain a quotient obtained by dividing the first bit value by a predetermined divisor based on a first set of addition or subtraction operations performed on a first bit value, wherein the first bit value represents time in a first time unit; obtain a remainder obtained by dividing the first bit value by a predetermined divisor based on the first bit value and a second set of addition or subtraction operations performed on the quotient; and obtain a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponds to the quotient and represents time in a second time unit, and the second part corresponds to the remainder and represents time in a first time unit.

[0007] In a second aspect of the disclosure, a method for clock synchronization is provided. The method includes: obtaining a quotient obtained by dividing the first bit value by a predetermined divisor based on performing a first set of addition or subtraction operations on a first bit value, wherein the first bit value represents time using a first time unit; obtaining a remainder obtained by dividing the first bit value by the predetermined divisor based on the first bit value and performing a second set of addition or subtraction operations on the quotient; and generating a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponds to the quotient and represents time in the second time unit, and the second part corresponds to the remainder and represents time in the first time unit.

[0008] In a third aspect of the disclosure, a device is provided. The device includes: a component for obtaining a quotient obtained by dividing the first bit value by a predetermined divisor based on performing a first set of addition or subtraction operations on a first bit value, wherein the first bit value represents time using a first time unit; a component for obtaining a remainder obtained by dividing the first bit value by the predetermined divisor based on the first bit value and performing a second set of addition or subtraction operations on the quotient; and a component for generating a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponds to the quotient and represents time in the second time unit, and the second part corresponds to the remainder and represents time in the first time unit.

[0009] In a fourth aspect of the present disclosure, a non-transitory computer-readable medium is provided, comprising program instructions for causing an apparatus to execute at least the method in the second aspect.

[0010] In a fifth aspect of the present disclosure, a computer program is provided. When executed by a device, the computer program causes the device to perform at least the method in the second aspect.

[0011] In a sixth aspect of the present disclosure, a device is provided. The device includes: a first execution circuit configured to obtain a quotient obtained by dividing the first bit value by a predetermined divisor based on performing a first set of addition or subtraction operations on a first bit value, wherein the first bit value represents time in a first time unit; a second execution circuit configured to obtain a remainder obtained by dividing the first bit value by the predetermined divisor based on the first bit value and performing a second set of addition or subtraction operations on the quotient; and an acquisition circuit configured to obtain a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponds to the quotient and represents time in the second time unit, and the second part corresponds to the remainder and represents time in the first time unit.

[0012] It should be understood that the contents described in the Summary of the Invention are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without exceeding the scope of protection required by the present application.

[0014] Figure 1 A block diagram of an example PTP communication system is shown in which embodiments of the present disclosure may be implemented.

[0015] Figure 2 A schematic diagram of the working process of a device for clock synchronization according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A functional simulation timing diagram according to an embodiment of the present disclosure is shown.

[0017] Figure 4 A clock information interaction diagram of a PTP communication system according to an embodiment of the present disclosure is shown.

[0018] Figure 5 A block diagram of components for performing time format conversion on a PTP system port according to an embodiment of the present disclosure is shown.

[0019] Figure 6 The functional simulation timing diagram of the direct hardware language programming implementation is shown.

[0020] Figure 7 The functional simulation timing diagram of the frequency reduction method is shown.

[0021] Figure 8 The basic principle diagram of the implementation scheme based on the binary fast division calculation model is shown.

[0022] Fig. 9 The functional simulation timing diagram of the implementation scheme based on the binary fast division calculation model is shown.

[0023] Fig. 10A A logical schematic diagram of an implementation scheme based on a binary fast division calculation model is shown.

[0024] Fig. 10B A logical schematic diagram of a calculation model according to an embodiment of the present disclosure is shown.

[0025] Fig.11 A simplified block diagram of an electronic device suitable for implementing embodiments of the present disclosure is shown.

[0026] Fig.12 A schematic diagram of a computer-readable medium suitable for implementing an embodiment of the present disclosure is shown.

[0027] Throughout the drawings, the same or similar reference numerals refer to the same or similar elements. DETAILED DESCRIPTION

[0028] The principles and spirit of the present disclosure will be described below with reference to several exemplary embodiments shown in the accompanying drawings. It should be understood that these specific embodiments are described only to enable those skilled in the art to better understand and implement the present disclosure, and are not intended to limit the scope of the present disclosure in any way.

[0029] As used herein, the term "including" and similar terms should be understood as open inclusion, i.e., "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0030] As used herein, the term "determine" covers a variety of actions. For example, "determine" may include operation, calculation, processing, export, investigation, search (e.g., search in a table, a database or another data structure), ascertain, etc. In addition, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. In addition, "determine" may include parsing, selecting, selecting, establishing, etc. As used herein, "at least one of the following: " and "at least one of " and similar expressions, wherein a list of two or more elements is connected by "and" or "or", means at least any one of these elements, or at least any two or more of these elements, or at least all of them.

[0031] As used herein, the term "circuitry" refers to one or more of: (a) hardware circuit implementations only (such as implementations of analog and / or digital circuits only); and (b) combinations of hardware circuits and software, such as (where applicable): (i) a combination of analog and / or digital hardware circuits and software / firmware, and (ii) any portion of a hardware processor with software (including a digital signal processor, software, and memory that work together to enable an apparatus such as a radio frequency device or other computing device to perform various functions); and (c) hardware circuits and / or processors, such as a microprocessor or portion of a microprocessor, that require software (e.g., firmware) for operation, but may be without software when software is not required for operation.

[0032] The definition of circuitry applies to all uses of this term in this application, including in any claims. As another example, the term "circuitry" as used herein also covers an implementation of a hardware circuit or processor (or multiple processors), or a portion of a hardware circuit or processor, or accompanying software or firmware. For example, the term "circuitry" also covers a baseband integrated circuit or a processor integrated circuit or similar integrated circuit in other computing devices if applicable to the particular claim notation.

[0033] Precision Time Protocol (PTP) is a time synchronization protocol, also known as IEEE 1588 protocol, used to synchronize time and frequency for standard Ethernet terminal devices. A PTP system usually includes a PTP domain and a PTP port. A PTP domain refers to a network that uses the PTP protocol. There is only one synchronization clock in the domain, and all devices in the domain are synchronized with the clock. A PTP port refers to the port on the corresponding device that runs the PTP protocol.

[0034] In the precise time protocol implementation system, the standard for clock exchange is the IEEE1588V2 standard format, which contains 80 bits of time information, with the upper 48 bits representing seconds and the lower 32 bits representing nanoseconds. Its structure is as follows:

[0035] IEEE1588V2 Timestamp

[0036] {

[0037] UInt48 Second_Field;

[0038] UInt32 NanoSecond_Field;

[0039] }.

[0040] Figure 1 A block diagram of an example PTP communication system is shown. In the PTP communication system 100, the master device 110 (PTPMaster) is the clock synchronization source, and the clocks of other devices will be synchronized to the clock of the master device 110. The slave device 120 (PTPSlaves) is a device that needs to be clock-synchronized with the master device. The boundary device 130 (PTP Boundary) has multiple ports connected to the network clock, a slave port (S port) is connected to the PTP port of the upstream device (the M port of the master device 110), and the other ports (as shown in the figure) are connected to the slave port of the downstream device (the S port of the slave device 120) as the Master port. The downstream slave port is directly synchronized with the boundary clock using the same PTP protocol. The transparent device 140 (PTPTC), such as a switch, does not require time synchronization, but can forward and modify some passing PTP messages, record the time (i.e., forwarding time) used when the PTP message passes through this device, and add it to the correction field (Correction Field) of the PTP message. Among them, when the master device executes the PTP protocol for synchronizing the clock, it needs to output the IEEE1588V2 standard timestamp at the output port because they are exchanged through the PTP system on the telecommunications network.

[0041] At present, the design of digital chips usually adopts the method of simple binary time counter, that is, the system time maintenance and calculation operations in the chip adopt the 80-bit binary counter format, so that there is no whole second carry in the calculation operation of the time counter. This situation greatly simplifies the complexity of the design and the consumption of logic resources in the design, and improves the clock frequency of the logic implementation. Therefore, it is necessary to convert the time format at the output port of the PTP system, and convert the 80-bit binary nanosecond count format into the IEEE1588V2 standard time format, which requires a circuit with specific calculation logic to perform the calculation.

[0042] The embodiments of the present disclosure relate to a device, method, and computer-readable medium for clock synchronization, and specifically provide a device for outputting timestamps of PTP ports and a corresponding calculation model thereof. In the corresponding calculation model, the current output is only related to the current input, and has nothing to do with the output results of the previous one or more clock cycles, thereby canceling the corresponding feedback input circuit and reducing the number of clock cycles to complete the time format conversion (for example, the conversion from the binary nanosecond counter time format to the IEEE1588V2 standard time format). In this calculation model, further based on the theory of fast binary multiplication, the number of binary addition or subtraction operations is reduced, thereby reducing the consumption of hardware logic resources corresponding to a large number of operations, and greatly reducing the delay in realizing the time format conversion.

[0043] For example, when converting the 80-bit binary counter time format to the IEEE1588V2 standard time format on the PTP port, the calculation model is usually as follows: divide the nanosecond information output by the 80-bit binary counter time format by 1 second (hexadecimal 3B9ACA00), and the quotient obtained is the 48-bit second information in the IEEE1588V2 standard time format, and the remainder is the 32-bit nanosecond information in the IEEE1588V2 standard time format.

[0044] Figure 2 A schematic diagram of a working process 200 of a device for clock synchronization according to some embodiments of the present disclosure is shown. Figure 1 , taking the device located on the main device 110 side as the device in the exemplary process 200 as an example.

[0045] exist Figure 2 In the example process 200, first, at 210, the device performs a first set of addition or subtraction operations on a first bit value to obtain a quotient obtained by dividing the first bit value by a predetermined divisor, wherein the first bit value represents time in a first time unit. The first bit value is, for example, Figure 1The timing information inside the master device side, the first time unit is, for example, nanoseconds, and the internal timing information is, for example, time information in an 80-bit binary counter time format. It is easy for those skilled in the art to understand that the first bit value may also use other time formats and / or bit numbers suitable for a specific embodiment, and the first time unit may also be other time units such as milliseconds. The first group of addition or subtraction operations corresponds to the "division operation" in the calculation model on which the time format conversion is based, and the "division operation" is converted into the first group of addition or subtraction operations in the calculation model corresponding to this embodiment, so that the converted division operation does not need to wait for the feedback of the calculation result. In theory, through the circuit implementation of the corresponding calculation model, the quotient of the first bit value relative to the predetermined divisor can be obtained within one clock cycle. Optionally, the predetermined divisor corresponds to the conversion value of the time unit conversion for the first bit value. For example, the first bit value expressed in nanoseconds as the time unit is converted to a time unit expressed in seconds, then the predetermined divisor is 10 9 The quotient obtained is the integer seconds information after the time unit conversion. It is easy for those skilled in the art to understand that the first bit value can also be converted into other types of time units. For example, the first bit value represented by nanoseconds as the time unit is converted to milliseconds as the time unit. Then the predetermined divisor is 10. 6 The quotient obtained is the integer millisecond information after the time unit is converted.

[0046] Then, at 220, the device performs a second set of addition or subtraction operations on the first bit value and the quotient to obtain a remainder obtained by dividing the first bit value by a predetermined divisor. The second set of addition or subtraction operations corresponds to the "operation for obtaining the remainder" in the calculation model on which the time format conversion is based. In the calculation model corresponding to this embodiment, the "operation for obtaining the remainder" is converted into a second set of addition or subtraction operations performed on the quotient. Similarly, in theory, through the circuit implementation of the corresponding calculation model, the remainder obtained by dividing the first bit value by the predetermined divisor can be obtained within one clock cycle. Optionally, the predetermined divisor corresponds to a conversion value for converting the first bit value to a time unit. For example, to convert the first bit value expressed in nanoseconds as a time unit to a value expressed in seconds as a time unit, the predetermined divisor is 10. 9 The remainder obtained is the remaining nanosecond information after the time unit conversion. It is easy for those skilled in the art to understand that the first bit value can also be converted into other types of time units. For example, the first bit value represented by nanoseconds as the time unit is converted to milliseconds as the time unit. Then the predetermined divisor is 10. 6 , the remainder obtained is the remaining nanosecond information after the time unit conversion.

[0047] After obtaining the quotient and the remainder, at 230, the device obtains a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponds to the quotient and represents time in a second time unit, and the second part corresponds to the remainder and represents time in a first time unit. Optionally, the predetermined divisor is a conversion value between the first time unit and the second time unit, then the obtained quotient is integer time information representing time in the second time unit, and the obtained remainder is the remaining time information representing time in the first time unit. The obtained quotient and the obtained remainder are combined to form a standard time format required by the PTP system, for example, in accordance with the timestamp format (IEEE1588V2 standard time format) specified in the Institute of Electrical and Electronics Engineers (IEEE) 1558 protocol version 2. In some embodiments, the first time unit is nanoseconds, the second time unit is seconds, the first part of the second bit value corresponds to the obtained quotient as 48-bit integer seconds information, and the second part of the second bit value corresponds to the obtained remainder as the remaining 32-bit nanosecond information. Those skilled in the art will readily appreciate that the first time unit and / or the second time unit may also be other time measurement units such as picoseconds, nanoseconds, microseconds, milliseconds, seconds, minutes, etc.

[0048] The device for clock synchronization provided by one or more of the above embodiments of the present disclosure is implemented through the circuit of the corresponding calculation model, so that the output result is only related to the current input, and has nothing to do with the output result after processing in the previous one or more clock cycles. The process does not require pipeline operation. Without considering the consumption of hardware logic resources and the clock frequency, the output of the quotient and the remainder can be completed within two consecutive clock cycles, thereby outputting the time information in the required time format without waiting for the processing result through multiple clock cycles. The converted addition or subtraction operation can reduce the number of addition or subtraction operations, reduce the consumption of hardware logic resources by the operation, and greatly reduce the delay of the implementation. Therefore, the device for clock synchronization provided by one or more of the above embodiments of the present disclosure can still obtain a higher maximum clock frequency F on low-performance and medium-performance devices. max , in order to meet the requirements of reducing costs. At the same time, it is also suitable for high-speed and high-bandwidth application scenarios.

[0049] Next, the first bit value is the nanosecond time information in the 80-bit binary counter time format, and the predetermined divisor is 10. 9 Some embodiments are illustrative.

[0050] The first bit value expressed in nanoseconds as a time unit is converted into a value expressed in seconds as a time unit. In some embodiments of the present disclosure, the corresponding calculation model converts the binary division operation into a binary multiplication operation. This optimization of conversion greatly improves the conversion performance in circuit implementation.

[0051] First, convert "S = X / Y" to "S = X*(1 / Y)", that is, convert the binary division operation into a multiplication operation. Determine the predetermined divisor (10 9 ), that is, the binary reciprocal of 1 second in nanoseconds. That is:

[0052] 1 / y=1 / 3b9aca00(Hex)=1 / 10 9 (Dec)=0.0000000000000000000000000000010001001011100000101111101000001001101101011010010101(Bin)

[0053] Second, try to reduce the number of additions used in binary multiplication operations, taking advantage of the following computational properties of binary:

[0054] 2 -p +2 -(p+1) +…+2 -q =2 -(p-1) -2 -q

[0055] For example, the binary decimal: 0.0 0 1 1 1 1 1 1 1, the 6 addition operations can be simplified to 1 subtraction operation. After simplification: 1 2 3 4 5 6 7 8 9

[0057] 0.0 0 1 1 1 1 1 1 1=2 -2 -2 -9

[0058] For the binary decimal: 0.0 1 1 1 1 0 1 1, the 5 addition operations can also be simplified to 2 subtraction operations. After simplification: 1 2 3 4 5 6 7 8 9

[0060] 0.0 0 1 1 1 1 0 1 1=2 -2 -2 -9 -2 -7

[0061] According to the simplified method above, in the calculation model, the predetermined divisor (10 9) is divided into a plurality of segments, and multiple addition operations corresponding to at least one segment in the plurality of segments are converted into subtraction operations with a smaller number of times.

[0062] In order to reduce the number of calculations, the characteristics of binary calculations are used to combine the calculations as follows:

[0063]

[0064] Next, in the calculation model, a first set of addition or subtraction operations is determined based on the subtraction operation corresponding to at least one segment and the addition operations corresponding to the remaining segments in the plurality of segments, namely:

[0065] s_q=x / y=x*(1 / y)

[0066] =x*{2 -30 +2 -34 +[2 -36 -2 -41 -2 -38 ]+[2 -46 -2 -53 -2 -48 ]+2 -55 +2 -61 +(2 -63 -2 -68 -2 -66 ]+[2 -69 -2 -73 -2 -71 ]+2 -75 +2 -78 +2 -80 +2 -82}, wherein x is the first bit value, y is the predetermined divisor, and the obtained value s_q is the quotient.

[0067] From the above calculation formula, we can see that the 24 addition operations decomposed by binary multiplication are simplified to 19 addition or subtraction operations. And all logical operations are simplified to addition or subtraction operations of data shift, and there is no iterative calculation process of output feedback to input. At the same time, in the actual implementation process, simplified bit processing can be performed to further reduce the consumption of hardware logic resources.

[0068] The calculation model provided by some embodiments of the present disclosure and the corresponding circuit design eliminate the need to feed back the output results of the input iteration model, which facilitates the pipeline design of the calculation model and optimizes the timing characteristics of the implementation. In addition, by utilizing the characteristics of binary operations, the number of additions used in multiplication is reduced, thereby reducing the consumption of logic resources caused by addition, and at the same time improving the timing characteristics of the design to achieve a higher maximum clock frequency F max , shortening the conversion delay.

[0069] The first bit value is still the nanosecond time information in the 80-bit binary counter time format, and the predetermined divisor is 10 9 Some embodiments are illustrative.

[0070] The first bit value represented by nanoseconds as a time unit is converted to seconds as a time unit, and the remaining nanosecond information is displayed in a time format. In some embodiments of the present disclosure, first, a predetermined divisor (10 9 ) in binary.

[0071] 10 9 (Dec)=00 1110111 00 1 1 0 101100 1 0 1 000000000(Bin)

[0072] The predetermined divisor (10 9 ) is divided into multiple segments. The multiple addition operations corresponding to at least one segment in the multiple segments are converted into subtraction operations with fewer times. The binary segment merging method is still used:

[0073]

[0074] Based on the subtraction operation corresponding to at least one segment and the addition operation corresponding to the remaining segments in the plurality of segments, a second set of addition or subtraction operations is determined. For the quotient s_q obtained by the first set of addition or subtraction operations, the second set of addition or subtraction operations may be:

[0075] s_q*10 9

[0076] =s_q*{[2 30 -2 23 -2 26 ]+2 20 +2 19 +[2 18 -2 14 -2 16 ]+2 11 +2 9}

[0077] The original 13 addition operations corresponding to binary multiplication are simplified to 11 addition or subtraction operations.

[0078] In some embodiments of the present disclosure, the remainder is calculated by subtracting the result obtained after performing the second set of addition or subtraction operations on the quotient from the first bit value. That is, the result s_q*10 of the second set of addition or subtraction operations is subtracted from the first bit value. 9 , obtain the remainder obtained by dividing the first bit value by the predetermined divisor, that is, obtain the remaining nanosecond information displayed in the time information. That is:

[0079] s_r=x-s_q*10 9

[0080] In some embodiments of the present disclosure, a register is called to store a quotient or a remainder, wherein the number of bits of the register is determined by the number of bits of the first bit value and the number of bits of the binary reciprocal of the predetermined divisor.

[0081] Assume that the register tick_tod_count stores an 80-bit binary value A, then set the register s = A000…0 (the tail of A is extended with 82-bit binary '0'), and the bit width of s is 80+82=162. 80 bits are the number of bits of the output result of the binary time counter tick_tod_count, and 82 bits are the predetermined divisor 10. 9 Set register x for the shift operation based on the number of bits in the binary representation of .

[0082] After performing the first set of binary addition or subtraction operations, the high 48 bits of the obtained result 's', denoted as s_q, are stored in std_tod_count[79:32], that is, the 48-bit second information in the IEEE1588V2 standard format is obtained.

[0083] After performing the second set of binary addition or subtraction operations, the lower 32 bits of the obtained result 's', recorded as s_r, are stored in std_tod_count[31:0], and the 32-bit nanosecond information in the IEEE1588V2 standard format is obtained.

[0084] As shown below:

[0085] Std_tod_count[79:32] = tick_tod_count / 32'h3b9aca00; / / Get the whole quotient,

[0086] Std_tod_count[31:0]=tick_tod_count%32'h3b9aca00; / / Get the remainder.

[0087] In some embodiments of the present disclosure, a first set of addition or subtraction operations are performed on the first bit value within a first plurality of clock cycles, or a second set of addition or subtraction operations are performed on the quotient within a second plurality of clock cycles.

[0088] Theoretically, the device for time format conversion and the corresponding calculation model provided by the present disclosure can obtain the quotient within one clock cycle and obtain the remainder within the next clock cycle. Considering the consumption of hardware logic resources and hardware performance, the calculation operation can be split into multiple clock cycles, thereby increasing the clock frequency. Figure 3 As shown, in some embodiments of the present disclosure, the total delay for implementing the time format conversion is 5 clock cycles, wherein after 3 clock cycles, the converted second information is obtained, and after another 2 clock cycles, the converted nanosecond information can be obtained.

[0089] The device provided by one or more embodiments of the present disclosure performs addition and subtraction operations on the input completely through the pipeline circuit to obtain the calculation result. The pipeline addition and subtraction operations in the core algorithm can be split into any pipeline stages according to the project application scenario and hardware device characteristics, which is particularly beneficial for optimizing the timing characteristics of digital logic implementation and adapting to application scenarios with different speeds / bandwidths.

[0090] Some embodiments of the present disclosure are verified on Intel's Stratix 10 1ST085EN2F43I2LG device, which consumes 267 ALM logic units and has low hardware logic resource consumption. At the same time, its maximum clock frequency F max It can reach 270.64MHz, which meets the use scenarios of high bandwidth and large capacity (low conversion delay) and has very good timing characteristics. At the same time, it reserves a very large timing optimization space to reduce the cost of low-performance devices (the design timing can be further optimized by designing more pipeline stages).

[0091] In some embodiments of the present disclosure, a second bit value is inserted into a message of a communication network based on IEEE 1588 protocol version 2, wherein, optionally, the message includes a synchronization message and the first bit value corresponds to the start time of sending the synchronization message, and / or the message includes a delayed response message and the first bit value corresponds to the start time of receiving the delayed response message.

[0092] Figure 4 It shows that Figure 1 The clock information interaction diagram of the example PTP communication system shown. At time t1, the master device 110 sends a Sync message to the slave device 120, and carries its own clock t1; at time t2, the slave device 120 receives the Sync message and marks its own clock t2 at that time; at time t3, the slave device 120 sends a delay request (Delay_Req) ​​message to the master device 110, and carries its own clock t3 at that time; at time t4, the master device 110 receives the delay request message, and marks its own clock t4 at that time, and sends a delay request response (Delay_Resp) message to the slave device 120, and carries the clock t4. Through the interaction process of two messages between the master and the slave devices, the clock of the slave device can be calibrated, thereby achieving clock synchronization. Figure 4 In the described scenario, the situations where the IEEE1588V2 standard format timestamp needs to be output include at least:

[0093] a) At time t1, at the port of the master device 110, when the master device 110 sends a SYNC message to the slave device 120 (when sending the SYNC message to the outbound port of the PTP network), a timestamp in the IEEE1588V2 standard format needs to be inserted into the SYNC message;

[0094] b) At time t4, at the port of the master device 110, when the master device 110 receives the Delay_Req (delay request) message from the slave device 120 and sends a Delay_Resp (delay request response) message to the slave device 120, it is necessary to insert a timestamp in the IEEE1588V2 standard format into the Delay_Resp message to respond to the delay request reception time.

[0095] In some embodiments of the present disclosure, executing Figure 2 The device for the illustrated workflow includes a field programmable gate array (FPGA).

[0096] In some embodiments of the present disclosure, the apparatus converts the timing information inside the master device into time information in the IEEE1588V2 standard format and outputs a timestamp in the standard format. Figure 5 As shown, the timing component 410 inside the system, for example, includes a binary counter timer inside the chip, and the device 420 includes, for example, hardware resource components such as FPGA and ASIC, which are used to convert the time information output by the timing component 410 into time information in a standard format, for example, into the IEEE1588V2 standard time format. At the above-mentioned time t1, the device 420 adds a timestamp to the Sync message; at the above-mentioned time t4, the device 420 stamps the time stamp at the time of receiving the Delay_Req message.

[0097] The following is a comparison with other time format conversion methods to illustrate the technical advantages of the present disclosure over traditional solutions by way of example and not limitation.

[0098] For hardware language programming, the solution of directly implementing the time format conversion is as follows. Figure 6 As shown in the figure, the conversion of this scheme is simple, and only a delay of 2 clock cycles is required to obtain the conversion result. However, when this scheme is mapped to a digital programmable logic chip, a large amount of logic resources will be consumed. For the bit-width division conversion operation, for example, it was verified on Intel's Stratix10 1ST085EN2F43I2LG device and found that 1106 ALM logic units were consumed, and the logic resource consumption was very high. Secondly, even on such a high-performance FPGA device, its maximum clock frequency F maxIt can only reach 19.49MHz, which is far from the PTP processing clock frequency of 125MHz in basic applications.

[0099] For the processing solution that uses hardware language programming and reduces the clock frequency, the original time counter in the high-frequency system clock domain can be transferred to the 20MHz low-frequency clock domain, and then the hardware description language is used to perform direct division in the low-frequency clock domain, and then the result is sent back to the high-frequency system clock domain. Figure 7 The functional simulation timing diagram of the conversion under the system clock 125MHz and the low-frequency clock 20MHz is shown. The design of this method is relatively simple and can achieve the expected maximum clock frequency F max As a goal, this solution consumes a lot of hardware logic resources, has a large conversion delay, and requires about 33 clock cycles, which cannot meet the needs of new application scenarios with high speed and large bandwidth.

[0100] For the circuit implementation scheme of binary fast division as a calculation model (Binary Pipeline partitioning method), the basic principle of this method is as follows Figure 8 As shown, the binary time counter tick_tod_count to be converted is used as the dividend, and the value of 1 second (10 9 , in nanoseconds) as the divisor. The quotient and remainder obtained by implementing the algorithm using the pipeline method are the seconds and nanoseconds parts of the IEEE1588V2 standard format time counter, respectively. That is, std_tod_count[79:32] = quotient; Std_tod_count[31:0] = remainder.

[0101] Fig. 9 The functional simulation timing diagram of the time conversion implementation method based on the calculation model of binary fast division is shown. This method does not consume much hardware resources and can also meet the current application scenarios of low-rate PTP message processing. However, this method is based on the current input and the result of the previous operation, obtained through shifting and subtraction. The current result needs to be used as the feedback input for the next operation. This model is not suitable for the implementation of the logic pipeline. In order to achieve the purpose of optimizing the timing, the maximum clock frequency F of this method on a low-performance chip max The optimization is very limited, which makes it difficult to implement on low-cost, low-performance devices. At the same time, the conversion delay of this method is too large, and the calculation including processing overhead requires about 34 clock cycles to complete one conversion. It cannot be used in high-bandwidth, high-throughput data processing scenarios.

[0102] Fig. 10A and Fig. 10BThe difference in logic implementation between a calculation model based on binary fast division and a calculation model adopted by one or more embodiments of the present disclosure is shown. Fig. 10A As shown, the calculation model based on binary fast division requires the output result of the previous clock cycle (t-1) to be iterated to the current clock cycle (t) as the input of the logic shift subtractor 910; Fig. 10B As shown, the calculation model adopted by the embodiment of the present disclosure uses a pipeline adder or subtractor 920 for calculation, without iterative processing, and the output result of the current clock cycle (t) is only related to the current input.

[0103] It can be seen that, compared with the solution of direct hardware language implementation, the solution of frequency reduction processing and the solution of binary direct division, the device for time format conversion provided by some embodiments of the present disclosure has a very short conversion delay and is suitable for the latest network synchronization application scenarios with high speed and large bandwidth. The new feedback removal mode of the embodiments of the present disclosure can achieve a higher maximum clock frequency F max The optimized design facilitates implementation on low-performance logic devices and reduces implementation costs. The disclosed embodiments can be implemented using pure hardware logic resources without the need for specific hardware such as a digital signal processor (DSP). The design is simple, the cost is low, and the implementation can be easily transplanted.

[0104] Table 1 shown below compares the number of clock cycles, clock frequency, hardware resource consumption, etc. of the embodiment of the present disclosure with that of the traditional solution. As shown in Table 1:

[0105]

[0106] Table 1

[0107] In some example embodiments, a device capable of executing process 200 may include a component for executing each step of method 200. The component may be implemented in any suitable form. For example, the component may be implemented in a circuit or a software module.

[0108] In some example embodiments, the apparatus includes: a component for obtaining a quotient obtained by dividing the first bit value by a predetermined divisor based on performing a first set of addition or subtraction operations on the first bit value, wherein the first bit value represents time using a first time unit; a component for obtaining a remainder obtained by dividing the first bit value by the predetermined divisor based on the first bit value and performing a second set of addition or subtraction operations on the quotient; and a component for generating a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponding to the quotient and representing time in the second time unit, and the second part corresponding to the remainder and representing time in the first time unit.

[0109] In some example embodiments, a first set of addition or subtraction operations is determined based on: determining a binary reciprocal of a predetermined divisor; dividing the binary reciprocal of the predetermined divisor into a plurality of segments; converting a plurality of addition operations corresponding to at least one of the plurality of segments into a fewer number of subtraction operations; and determining the first set of addition or subtraction operations based on the subtraction operations corresponding to at least one segment and the addition operations corresponding to the remaining segments of the plurality of segments.

[0110] In some example embodiments, the second group of addition or subtraction operations is determined based on: determining a binary number of a predetermined divisor; dividing the binary number of the predetermined divisor into a plurality of segments; converting a plurality of addition operations corresponding to at least one of the plurality of segments into a fewer number of subtraction operations; and determining the second group of addition or subtraction operations based on the subtraction operations corresponding to at least one segment and the addition operations corresponding to the remaining segments of the plurality of segments.

[0111] In some example embodiments, the means for obtaining a remainder obtained by dividing the first bit value by a predetermined divisor includes means for subtracting a result obtained by performing a second set of addition or subtraction operations on the quotient from the first bit value to calculate the remainder.

[0112] In some example embodiments, at least one of the following: the first time unit is nanoseconds; the second time unit is seconds; the predetermined divisor is a conversion value between the first time unit and the second time unit; or the second bit value conforms to the timestamp format specified in the Institute of Electrical and Electronics Engineers (IEEE) 1558 protocol version 2.

[0113] In some example embodiments, the predetermined divisor is 109, the first set of addition or subtraction operations includes 19 addition or subtraction operations, and the second set of addition or subtraction operations includes 11 addition or subtraction operations.

[0114] In some example embodiments, the apparatus further comprises means for performing a first set of addition or subtraction operations on the first bit value within a first plurality of clock cycles, or means for performing a second set of addition or subtraction operations on the quotient within a second plurality of clock cycles.

[0115] In some example embodiments, the apparatus further comprises means for inserting the second bit value into a message of the communication network based on the IEEE 1588 protocol version 2.

[0116] In some example embodiments, the message comprises a synchronization message, and the first bit value corresponds to a start time instant for sending the synchronization message.

[0117] In some example embodiments, the message comprises a delayed response message, and the first bit value corresponds to a starting time instant of receiving the delayed response message.

[0118] In some example embodiments, the apparatus further comprises: means for invoking a register to store at least one of a quotient or a remainder, wherein the number of bits of the register is determined by the number of bits of the first bit value and the number of bits of a binary reciprocal of a predetermined divisor.

[0119] In some example embodiments, the apparatus comprises a field programmable gate array (FPGA).

[0120] In some example embodiments, the apparatus further comprises means for performing other steps in some embodiments of method 200. In some embodiments, the means comprises at least one processor and at least one memory storing computer program code. The at least one memory and the computer program code are configured to, together with the at least one processor, cause execution of the apparatus.

[0121] Fig.11 1 is a simplified block diagram of an electronic device 1100 suitable for implementing embodiments of the present disclosure. The device 1100 may be provided to implement the apparatus according to some embodiments of the present disclosure. As shown, the device 1100 includes one or more processors 1110, one or more memories 1120 are coupled to the processor 1110, and one or more communication modules 1140 are coupled to the processor 1110.

[0122] The communication module 1140 is used for two-way communication. For example, the communication module 1140 may include a transmitter, a receiver, or a transceiver used in the embodiments of the present disclosure. The communication interface may represent any interface necessary for communicating with other network elements.

[0123] Processor 1110 may be of any type suitable for the local technology network and may include, but is not limited to, one or more of a general purpose computer, a special purpose computer, a microcontroller, a digital signal processor (DSP), and a controller-based multi-core controller architecture. Device 1100 may have multiple processors, such as application specific integrated circuit chips, which are time-slaved to a clock synchronized with a main processor.

[0124] The memory 1120 may include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, read-only memory (ROM) 1024, erasable programmable read-only memory (EPROM), flash memory, hard disks, compact disks (CDs), digital video disks (DVDs), and other magnetic storage and / or optical storage. Examples of volatile memories include, but are not limited to, random access memory (RAM) 1122 and other volatile memories that do not persist over the duration of a power outage.

[0125] Computer program 1130 includes computer executable instructions executed by associated processor 1110. Program 1130 may be stored in ROM 1120. Processor 1110 may perform any suitable actions and processes by loading program 1130 into RAM 1122.

[0126] The embodiments of the present disclosure can be implemented with the help of program 1130, so that the device 1100 can execute the Figure 2 Any process of the present disclosure discussed. The embodiments of the present disclosure may also be implemented by hardware or by a combination of software and hardware.

[0127] In some embodiments, the program 1130 may be tangibly embodied in a computer-readable medium that may be included in the device 1100 (such as in the memory 1120) or other storage device accessible by the device 1100. The program 1130 may be loaded from the computer-readable medium to the RAM 1122 for execution. The computer-readable medium may include any type of tangible non-volatile memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, etc.

[0128] Fig.12 An example of a computer readable medium 1200 in the form of a CD or DVD is shown. The computer readable medium has a program 1130 stored thereon.

[0129] In general, various embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be performed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flow charts, or using some other graphical representation, it should be understood that the blocks, devices, systems, techniques, or methods described herein may be implemented as, by way of non-limiting example, hardware, software, firmware, dedicated circuits or logic, general purpose hardware or a controller or other computing device, or some combination thereof.

[0130] The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product includes computer executable instructions, such as instructions included in a program module, which are executed in a device on a real or virtual processor of the target to perform the method 1000 as described above with reference to Figure 10. Typically, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform specific tasks or implement specific abstract data types. In various embodiments, the functions of program modules can be combined or divided between program modules as needed. Machine executable instructions for program modules can be executed in local or distributed devices. In distributed devices, program modules can be located in local and remote storage media.

[0131] The computer program code for realizing the method of the present disclosure can be written in one or more programming languages. These computer program codes can be provided to the processor of general-purpose computer, special-purpose computer or other programmable data processing device, so that the program code, when being executed by computer or other programmable data processing device, causes the function / operation specified in flow chart and / or block diagram to be implemented. The program code can be executed completely on computer, partly on computer, as independent software package, partly on computer and partly on remote computer or completely on remote computer or server.

[0132] In the context of the present disclosure, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like. Examples of signals may include electrical, optical, radio, acoustic or other forms of propagation signals, such as carrier waves, infrared signals, and the like.

[0133] A computer-readable medium may be any tangible medium containing or storing a program for or about an instruction execution system, device or equipment. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination thereof. A more detailed example of a computer-readable storage medium includes an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof. As used herein, the term "non-transient" or "non-transient" is a limitation on the medium itself (i.e., tangible, not a signal), rather than a limitation on the persistence of data storage (e.g., RAM and ROM).

[0134] In addition, although the operation of the method of the present disclosure is described in a particular order in the accompanying drawings, this does not require or imply that these operations must be performed in this particular order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flow chart can change the order of execution. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution. It should also be noted that the features and functions of two or more devices according to the present disclosure can be embodied in one device. Conversely, the features and functions of a device described above can be further divided into being embodied by multiple devices.

[0135] Although the present disclosure has been described with reference to several specific embodiments, it should be understood that the present disclosure is not limited to the specific embodiments disclosed. The present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0136] In addition, although the operation of the method of the present disclosure is described in a particular order in the accompanying drawings, this does not require or imply that these operations must be performed in this particular order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flow chart can change the order of execution. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution. It should also be noted that the features and functions of two or more devices according to the present disclosure can be embodied in one device. Conversely, the features and functions of a device described above can be further divided into being embodied by multiple devices.

[0137] Although the present disclosure has been described with reference to several specific embodiments, it should be understood that the present disclosure is not limited to the specific embodiments disclosed. The present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A device for clock synchronization, comprising: at least one processor; as well as at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus to at least: Obtaining a quotient obtained by dividing a first bit value by a predetermined divisor based on performing a first set of addition or subtraction operations on the first bit value, wherein the first bit value represents time in a first time unit; Based on the first bit value and performing a second set of addition or subtraction operations on the quotient, obtaining a remainder obtained by dividing the first bit value by the predetermined divisor; and A second bit value representing time is obtained based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponds to the quotient and represents time in a second time unit, and the second part corresponds to the remainder and represents time in the first time unit.

2. The apparatus of claim 1 , wherein the first set of addition or subtraction operations is determined based on: determining a binary reciprocal of the predetermined divisor; dividing the binary reciprocal of the predetermined divisor into a plurality of segments; converting a plurality of addition operations corresponding to at least one of the plurality of segments into a smaller number of subtraction operations; and The first set of addition or subtraction operations is determined based on the subtraction operation corresponding to the at least one segment and the addition operations corresponding to the remaining segments in the plurality of segments.

3. The apparatus according to claim 1 or 2, wherein the second set of addition or subtraction operations is determined based on: determining a binary number of the predetermined divisor; dividing the binary number of the predetermined divisor into a plurality of segments; converting a plurality of addition operations corresponding to at least one of the plurality of segments into a smaller number of subtraction operations; and The second set of addition or subtraction operations is determined based on the subtraction operation corresponding to the at least one segment and the addition operations corresponding to the remaining segments in the plurality of segments.

4. The apparatus according to any one of claims 1 to 3, wherein the apparatus is configured to obtain the remainder by: The remainder is calculated by subtracting a result obtained after performing a second set of addition or subtraction operations on the quotient from the first bit value.

5. The device according to any one of claims 1 to 4, wherein at least one of the following: The first time unit is nanosecond; The second time unit is seconds; The predetermined divisor is a conversion value between the first time unit and the second time unit; or The second bit value complies with the timestamp format specified in the Institute of Electrical and Electronics Engineers (IEEE) 1558 protocol version 2.

6. The device according to any one of claims 1 to 5, wherein the predetermined divisor is 10 9 , the first set of addition or subtraction operations includes 19 addition or subtraction operations, and the second set of addition or subtraction operations includes 11 addition or subtraction operations.

7. The device according to any one of claims 1 to 6, wherein the device is further configured to at least one of the following: performing the first set of addition or subtraction operations on the first bit value within a first plurality of clock cycles; or The second set of addition or subtraction operations are performed on the quotient during a second plurality of clock cycles.

8. The device according to any one of claims 1 to 7, wherein the device is further configured to: The second bit value is inserted into a message of a communication network based on IEEE 1588 protocol version 2.

9. The apparatus of claim 8, wherein the message comprises a synchronization message, and the first bit value corresponds to a start time instant for sending the synchronization message.

10. The apparatus of claim 8, wherein the message comprises a delayed response message, and the first bit value corresponds to a start time instant of receiving the delayed response message.

11. The apparatus according to any one of claims 1 to 10, wherein the apparatus is further configured to: A register is called to store at least one of the quotient or the remainder, wherein the number of bits of the register is determined by the number of bits of the first bit value and the number of bits of the binary reciprocal of the predetermined divisor.

12. The apparatus of any one of claims 1-11, wherein the apparatus comprises a field programmable gate array (FPGA).

13. A method for clock synchronization, comprising: Obtaining a quotient obtained by dividing a first bit value by a predetermined divisor based on performing a first set of addition or subtraction operations on the first bit value, wherein the first bit value represents time using a first time unit; Based on the first bit value and performing a second set of addition or subtraction operations on the quotient, obtaining a remainder obtained by dividing the first bit value by the predetermined divisor; and A second bit value representing time is generated based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponds to the quotient and represents time in a second time unit, and the second part corresponds to the remainder and represents time in the first time unit.

14. The method of claim 13, wherein the first set of addition or subtraction operations is determined based on: determining a binary reciprocal of the predetermined divisor; dividing the binary reciprocal of the predetermined divisor into a plurality of segments; converting a plurality of addition operations corresponding to at least one of the plurality of segments into a smaller number of subtraction operations; and The first set of addition or subtraction operations is determined based on the subtraction operation corresponding to the at least one segment and the addition operations corresponding to the remaining segments in the plurality of segments.

15. The method of claim 13 or 14, wherein the second set of addition or subtraction operations is determined based on: determining a binary number of the predetermined divisor; dividing the binary number of the predetermined divisor into a plurality of segments; converting a plurality of addition operations corresponding to at least one of the plurality of segments into a smaller number of subtraction operations; and The second set of addition or subtraction operations is determined based on the subtraction operation corresponding to the at least one segment and the addition operations corresponding to the remaining segments in the plurality of segments.

16. The method according to any one of claims 13 to 15, wherein obtaining a remainder obtained by dividing the first bit value by the predetermined divisor further comprises: The remainder is calculated by subtracting a result obtained after performing a second set of addition or subtraction operations on the quotient from the first bit value.

17. The method according to any one of claims 13 to 16, wherein at least one of the following: The first time unit is nanosecond; The second time unit is seconds; The predetermined divisor is a conversion value between the first time unit and the second time unit; or The second bit value complies with the timestamp format specified in the Institute of Electrical and Electronics Engineers (IEEE) 1558 protocol version 2.

18. The method according to any one of claims 13 to 17, wherein the predetermined divisor is 10. 9 , the first set of addition or subtraction operations includes 19 addition or subtraction operations, and the second set of addition or subtraction operations includes 11 addition or subtraction operations.

19. The method according to any one of claims 13 to 18, further comprising: performing the first set of addition or subtraction operations on the first bit value during a first plurality of clock cycles; or The second set of addition or subtraction operations are performed on the quotient during a second plurality of clock cycles.

20. The method according to any one of claims 13 to 19, further comprising: The second bit value is inserted into a message of a communication network based on IEEE 1588 protocol version 2.

21. The method according to any one of claims 13-20, wherein the message comprises a synchronization message, and the first bit value corresponds to a start time instant of sending the synchronization message.

22. The method according to any one of claims 13-21, wherein the message comprises a delayed response message, and the first bit value corresponds to a starting time instant of receiving the delayed response message.

23. The method according to any one of claims 13 to 22, further comprising: A register is called to store at least one of the quotient or the remainder, wherein the number of bits of the register is determined by the number of bits of the first bit value and the number of bits of the binary reciprocal of the predetermined divisor.

24. The method of any one of claims 13-23, wherein the method is performed by a field programmable gate array (FPGA).

25. An apparatus comprising: means for obtaining a quotient obtained by dividing a first bit value by a predetermined divisor based on performing a first set of addition or subtraction operations on the first bit value, wherein the first bit value represents time using a first time unit; means for performing a second set of addition or subtraction operations on the quotient based on the first bit value to obtain a remainder obtained by dividing the first bit value by the predetermined divisor; as well as means for generating a second bit value representing time based on the quotient and the remainder, wherein the second bit value comprises a first portion and a second portion, the first portion corresponding to the quotient and representing time in a second time unit, and the second portion corresponding to the remainder and representing time in the first time unit.

26. A computer-readable medium having instructions stored thereon, which, when executed by at least one processing unit, causes the at least one processing unit to be configured to execute the method according to any one of claims 13-24.

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