Secret key random extraction method and device of feature-free Latch PUF unit and electronic equipment

Abstract

The invention discloses a secret key random extraction method and device of a feature-free Latch PUF unit and electronic equipment. The method comprises the steps that a random number sent by a host is acquired; splicing the random number, the PUF key and the chip ID to obtain a first message, and filling the first message through an SHA256 algorithm; the filled first message is divided into a plurality of message blocks, and the PUF key is located in the first message block; the multiple message blocks are expanded through an SHA256 algorithm, a message word Wt is obtained, and the PUF secret key is located in W8; and within the time when the W8 executes the shift operation, randomly extracting the PUF key. According to the method provided by the invention, the difficulty of predicting and positioning the PUF key generation time by an attacker can be greatly increased, the attacker is prevented from extracting the key through physical attack means such as detection and FIB, and the security of a chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of information security technology, and in particular to a method for randomly extracting a key from a featureless Latch PUF (Physical Unclonable Function) unit, a device for randomly extracting a key from a featureless Latch PUF unit, a computer-readable storage medium, and an electronic device. Background Art

[0002] With the widespread popularity of mobile phones and IoT devices, the demand for information transmission has grown rapidly, accompanied by increasingly severe information security challenges. The current trend of IoT security technology is to transfer security protection and intrusion detection functions from the traditional software layer to the hardware layer. However, their security often depends on the secure storage and computational complexity of keys. The traditional method of using non-volatile memory (such as EEPROM, Flash, etc.) to store security keys has the risk of being cracked by attackers and cannot fully guarantee the security of keys and sensitive information. For this reason, the physical unclonable function (PUF) has been developed. PUF uses the randomness of the hardware manufacturing process to generate a unique "fingerprint" for each device, thereby providing key generation and authentication services without relying on traditional storage of keys. PUF technology is particularly suitable for IoT devices with limited resources due to its advantages such as low hardware overhead, sensitivity to physical tampering, and no need for non-volatile memory to store private information. According to the size of the challenge-response pair (CRP) space, PUF can generally be divided into two categories: strong PUF and weak PUF. A strong PUF has a large number of CRPs, which makes it impossible to measure all of them, while a weak PUF has a limited number of CRPs.

[0003] Most of the existing lightweight identity authentication based on weak PUF uses structures such as SRAM PUF and Latch PUF for identity authentication. For example, the ATMEGA 2560-MCU IoT device authentication proof of concept based on SRAM PUF introduces hash functions and simple encryption operations, which can achieve identity authentication without complex operations or cumbersome interaction steps; another example is the SRAM PUF circuit combined with hash algorithms and BAN logic to improve security, thereby achieving identity authentication [2]. However, for this type of identity authentication, attackers can obtain the entire circuit through reverse engineering attacks, and then trace back to the key transmission line and PUF key circuit by analyzing the circuit using the key. Although this method is very costly, the possibility of attackers using it still exists. Subsequently, attackers may use physical attack methods such as probing and focused ion beam (FIB) to extract the PUF key, making the chip less secure. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art to at least a certain extent. To this end, the first purpose of the present invention is to propose a random key extraction method for a featureless latch PUF unit, by reusing the featureless latch PUF function and randomizing the timing of key extraction from the featureless latch PUF, thereby greatly increasing the difficulty for attackers to predict and locate the PUF key generation time, preventing attackers from extracting keys through physical attacks such as detection and FIB, and improving the security of the chip.

[0005] The second objective of the present invention is to provide a key random extraction device for a featureless Latch PUF unit.

[0006] A third object of the present invention is to provide a computer-readable storage medium.

[0007] A fourth objective of the present invention is to provide an electronic device.

[0008] To achieve the above-mentioned object, the first embodiment of the present invention proposes a method for randomly extracting a key of a featureless latch PUF unit, the method comprising: obtaining a random number sent by a host; concatenating the random number, a PUF key, and a chip ID to obtain a first message, and filling the first message by a SHA256 algorithm; dividing the filled first message into a plurality of message blocks, wherein the PUF key is located in the first message block; performing expansion processing on the plurality of message blocks by a SHA256 algorithm to obtain a message key W t , wherein the PUF key is located in W8; during the time when W8 performs the shift operation, the PUF key is randomly extracted.

[0009] According to the random key extraction method of the featureless latch PUF unit of the embodiment of the present invention, a random number sent by the host is first obtained, and then the random number, the PUF key, and the chip ID are spliced ​​to obtain a first message, and the first message is filled by the SHA256 algorithm, and the filled first message is divided into multiple message blocks, the PUF key is located in the first message block, and then the multiple message blocks are expanded by the SHA256 algorithm to obtain a message key W t , where the PUF key is located in W8; during the time when W8 performs the shift operation, the PUF key is randomly extracted. Therefore, this method reuses the function of the featureless latch PUF and randomizes the timing of extracting the featureless latch PUF key, thereby greatly increasing the difficulty for attackers to predict and locate the PUF key generation time, preventing attackers from extracting the key through physical attacks such as detection and FIB, and improving the security of the chip.

[0010] In addition, the key random extraction method of the featureless latch PUF unit according to the above embodiment of the present invention may also have the following additional technical features:

[0011] According to one embodiment of the present invention, within the time when W8 performs the shift operation, the PUF key is randomly extracted, including: obtaining the current round number of the SHA256 algorithm; when the current round number is equal to the preset round number, the featureless Latch PUF unit generates the PUF key as a Latch PUF.

[0012] According to an embodiment of the present invention, when the current round number is not equal to the preset round number, the featureless LatchPUF unit is used as a latch to store data.

[0013] According to an embodiment of the present invention, after the featureless Latch PUF unit generates the PUF key as a Latch PUF, the method further includes: updating the generated PUF key to W8 to participate in the calculation of a new W.

[0014] According to one embodiment of the present invention, the method further includes: determining whether W8 is used up; if W8 is not used up, the featureless Latch PUF unit continues to serve as a Latch PUF to generate the PUF key; if W8 is used up, the featureless Latch PUF unit serves as a latch to store data.

[0015] According to an embodiment of the present invention, the method further includes: obtaining a first hash value after completing SHA256 calculation on the first message; and returning the first hash value to the host for identity authentication.

[0016] According to one embodiment of the present invention, returning the first hash value to the host for identity authentication includes: the host concatenating the random number, the original key, and the chip ID to obtain a second message; hashing the second message through the SHA256 algorithm to obtain a second hash value; comparing the first hash value with the second hash value, if the first hash value is equal to the second hash value, the identity authentication is successful; if the first hash value is not equal to the second hash value, the identity authentication fails.

[0017] To achieve the above-mentioned purpose, the second embodiment of the present invention proposes a key random extraction device of a featureless latch PUF unit, the device comprising: an acquisition module, used to acquire a random number sent by a host; a splicing and filling module, used to splice the random number, the PUF key, and the chip ID to obtain a first message, and fill the first message through the SHA256 algorithm; a segmentation module, used to divide the filled first message into multiple message blocks, wherein the PUF key is located in the first message block; an expansion processing module, used to expand the multiple message blocks through the SHA256 algorithm to obtain a message key W t , wherein the PUF key is located in W8; a random extraction module is used to randomly extract the PUF key within the time when W8 performs a shift operation.

[0018] According to the key random extraction device of the featureless latch PUF unit of the embodiment of the present invention, the acquisition module acquires the random number sent by the host; the splicing and filling module splices the random number, the PUF key, and the chip ID to obtain a first message, and fills the first message through the SHA256 algorithm; the segmentation module divides the filled first message into multiple message blocks, and the PUF key is located in the first message block; the expansion processing module expands the multiple message blocks through the SHA256 algorithm to obtain the message key W t , where the PUF key is located in W8; the random extraction module randomly extracts the PUF key during the time when W8 performs the shift operation. Therefore, the device reuses the function of the featureless latch PUF and randomizes the timing of extracting the featureless latch PUF key, thereby greatly increasing the difficulty for attackers to predict and locate the PUF key generation time, preventing attackers from extracting the key through physical attacks such as detection and FIB, and improving the security of the chip.

[0019] To achieve the above-mentioned purpose, an embodiment of the third aspect of the present invention proposes a computer-readable storage medium, on which a key random extraction program for a featureless Latch PUF unit is stored. When the key random extraction program for the featureless Latch PUF unit is executed by a processor, the above-mentioned key random extraction method for the featureless Latch PUF unit is implemented.

[0020] According to the computer-readable storage medium of the embodiment of the present invention, by executing the above-mentioned random key extraction method of the featureless Latch PUF unit, it is possible to greatly increase the difficulty for attackers to predict and locate the PUF key generation time, prevent attackers from extracting keys through physical attack methods such as detection and FIB, and improve the security of the chip.

[0021] To achieve the above-mentioned purpose, an embodiment of the fourth aspect of the present invention proposes an electronic device, comprising: a memory and a processor, wherein the memory stores a program that can be run on the processor, and when the processor executes the program, the above-mentioned method for random key extraction of the featureless Latch PUF unit is implemented.

[0022] The electronic device according to the embodiment of the present invention can greatly increase the difficulty for attackers to predict and locate the PUF key generation time by executing the above-mentioned method for random key extraction of the featureless latch PUF unit, prevent attackers from extracting keys through physical attack methods such as detection and FIB, and improve the security of the chip.

[0023] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a flow chart of a method for randomly extracting a key from a featureless Latch PUF unit according to an embodiment of the present invention;

[0025] Figure 2 1 is a featureless latch PUF unit according to an embodiment of the present invention and an equivalent circuit diagram in different modes thereof;

[0026] Figure 3 A schematic diagram of a dynamic random key extraction framework of a SHA256 algorithm according to an embodiment of the present invention;

[0027] Figure 4 1 is a distribution diagram of a featureless latch PUF test in a HJ 0.18 μm CMOS process according to an embodiment of the present invention, wherein (a) is the bit error rate, (b) is the bias, (c) is the intra-chip HD, and (d) is the inter-chip HD;

[0028] Figure 5 Schematic diagram of a block diagram of a key random extraction device of a featureless Latch PUF unit according to an embodiment of the present invention;

[0029] Figure 6 FIG. 4 is a block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0031] The following describes a method for randomly extracting a key from a featureless Latch PUF unit, a device for randomly extracting a key from a featureless Latch PUF unit, a computer-readable storage medium, and an electronic device according to embodiments of the present invention with reference to the accompanying drawings.

[0032] The featureless latch PUF unit and its equivalent circuits in different modes are shown in Figure 2. Figure 2 As shown, the Latch PUF unit circuit includes an inverter, a buffer BUFFER, a first multiplexer MUX1, a second multiplexer MUX2, a first NAND gate NAND1 and a second NAND gate NAND2. Both the first multiplexer MUX1 and the second multiplexer MUX2 are controlled by the mode control signal MODE, which enables the Latch PUF unit circuit to switch between the two working modes of the Latch unit and the Latch PUF. When the mode is "1", OUT is equal to the input signal IN. Subsequently, when MODE is "0" and PUF_EN is "1", the featureless Latch PUF acts as a Latch unit to store the previous input signal IN. When MODE is "0" and PUF_EN is "0", the OUT output is not latched before the output, and the data becomes a constant "1" and prepares for the key generation of the Latch PUF. Subsequently, when MODE is "0" and PUF_EN is "1", the circuit works as a Latch PUF, and OUT is determined by the driving capability of the first NAND gate NAND1 and the second NAND gate NAND2. If the first NAND gate NAND1 has a stronger driving capability, OUT is "1", otherwise, OUT outputs "0".

[0033] If the featureless Latch PUF unit is fixed as the Latch PUF for key generation in the authentication protocol, an attacker may analyze the entire circuit through reverse engineering attacks and reveal the function of the Latch PUF unit in key generation. Subsequently, the attacker may use physical attack methods such as probing and FIB to extract the PUF key.

[0034] In order to solve the above technical problems, the present invention proposes a LatchPUF key random extraction method based on the SHA256 security algorithm, which makes it difficult for attackers to accurately determine the correct time of key generation, thereby increasing the difficulty of PUF key analysis.

[0035] Figure 1 The figure is a flow chart of a method for randomly extracting a key from a featureless Latch PUF unit according to an embodiment of the present invention.

[0036] like Figure 1 As shown, the key random extraction method of the featureless Latch PUF unit in the embodiment of the present invention may include the following steps:

[0037] S1, obtain the random number sent by the host.

[0038] S2, concatenate the random number, the PUF key, and the chip ID to obtain a first message, and fill the first message using the SHA256 algorithm.

[0039] S3, dividing the padded first message into multiple message blocks, wherein the PUF key is located in the first message block.

[0040] S4, expand multiple message blocks through the SHA256 algorithm to obtain the message word W t , where the PUF key is located in W8.

[0041] S5, randomly extract the PUF key during the time when W8 performs the shift operation.

[0042] Specifically, when the host performs an authentication function test on the chip, the host sends a random number (RND) to the chip, and the chip concatenates the random number (RND) received from the host, the PUF key (PUF_KEY), and the chip ID stored in the local non-volatile memory (NVM) to obtain the first message {RND, PUF_KEY, ID}, and then uses the SHA256 algorithm to fill the first message {RND, PUF_KEY, ID}, and then divides the filled first message into multiple message blocks: MessageBlock_1, Message Block_2, ..., Message Block_n. Each message block is 512 bits, and the SHA256 algorithm of the present invention runs as follows: Figure 3 shown.

[0043] It is important to understand that the featureless Latch PUF unit is used as a Latch PUF only when a key needs to be generated, and is used as a Latch unit to store 32 bits of data at other times. In order to achieve random extraction of PUF keys without affecting the normal operation of the SHA256 algorithm, the first thing to consider is the location of the PUF key in the message block. If PUF_KEY is placed in Message Block_n (where n≠1), it means that during the SHA-256 calculation process from Message Block_1 to Message Block_n-1, the featureless latch PUF will be stored as a latch unit. However, when performing a SHA256 calculation on a Message Block_n containing a PUF_KEY, the featureless Latch PUF will first clear the previously stored Then the key is generated as a Latch PUF unit. This will result in the need to convert Comp(Ai-Hi) and Add to generate Therefore, in order not to affect the normal operation of the SHA256 algorithm, the PUF key PUF_KEY should be located in the first message block Message Block_1.

[0044] Specifically, Figure 3 As shown, in the SHA256 algorithm, the message block is processed by the expander to generate the message word (W t). For the first 16 rounds of SHA256 encryption, the message word required by the compressor can be obtained directly from the first message block Message Block_1. For the remaining rounds of operations, the message word must come from the expansion of Message Block_1. It should be noted that the newly generated W t+16 Depends only on W t , W t+1 , W t+9 and W t+14 , while the other W words only perform shift operations. Therefore, by properly adjusting the position of the PUF key PUF_KEY in Message Block_1, the key can be randomly generated in the clock cycle where the W word only performs shift operations without affecting the normal operation of SHA256. 15 When PUF_KEY is located at W, it participates in the generation of the new W after a shift operation. 13 , it needs to perform 4 shift operations to participate in the calculation of the new W; similarly, if the PUF key PUF_KEY is located at W8, it needs to perform 7 shift operations to participate in the generation of the new W. Therefore, in order to maximize the randomness of key extraction, when Message Block_1 is divided into W0 to W 15 , the PUF key PUF_KEY is located in W8. By placing the key generated by the featureless Latch PUF unit in W8, the PUF key PUF_KEY will undergo 7 shift operations without participating in any calculations. This means that the PUF key PUF_KEY can be generated at any time during these seven shift operations without affecting the normal operation of SHA256.

[0045] According to an embodiment of the present invention, during the time when W8 performs the shift operation, the PUF key is randomly extracted, including: obtaining the current round number of the SHA256 algorithm; when the current round number is equal to the preset round number, the featureless Latch PUF unit generates the PUF key as the Latch PUF. The preset round number can be calibrated according to actual conditions, for example, the preset round number can be the lowest three digits RND[2:0] of the random number.

[0046] Further, according to an embodiment of the present invention, when the current round number is not equal to the preset round number, the featureless Latch PUF unit is used as a latch to store data.

[0047] Specifically, in order to achieve random extraction of the PUF key PUF_KEY within the time when W8 performs the shift operation, the lowest three bits RND[2:0] of the random number generated by the host can be used to control the key generation time of the featureless Latch PUF unit. If the current round number t is not equal to RND[2:0], the featureless Latch PUF unit acts as a latch to store data. However, if the current round number t is equal to RND[2:0], the featureless Latch PUF unit acts as a Latch PUF to generate a key, and then updates it to W8 to participate in the calculation of the new W.

[0048] According to an embodiment of the present invention, after the featureless Latch PUF unit is used as the Latch PUF to generate a PUF key, the method further includes: updating the generated PUF key to W8 to participate in the calculation of the new W.

[0049] According to one embodiment of the present invention, the method further includes: determining whether W8 is used up; if W8 is not used up, the featureless Latch PUF unit continues to be used as a Latch PUF to generate a PUF key; if W8 is used up, the featureless Latch PUF unit is used as a latch to store data.

[0050] Specifically, once the PUF key is generated, the mode of the featureless Latch PUF will be changed depending on whether W8 has been used up. If W8 has not been used up, it will continue to be used as a Latch PUF to generate keys; after W8 is used up, the featureless Latch PUF unit will be used as a latch again to store the 64 rounds of operations of each message block. And for arrive The storage is also carried out by using latch units instead of traditional D flip-flop storage.

[0051] According to an embodiment of the present invention, the above method further includes: obtaining a first hash value after completing SHA256 calculation on the first message; and returning the first hash value to the host for identity authentication.

[0052] Further, according to an embodiment of the present invention, the first hash value is returned to the host for identity authentication, including: the host concatenates the random number, the original key, and the chip ID to obtain a second message; hashes the second message through the SHA256 algorithm to obtain a second hash value; compares the first hash value with the second hash value, if the first hash value is equal to the second hash value, the identity authentication is successful; if the first hash value is not equal to the second hash value, the identity authentication fails.

[0053] Specifically, when the host performs an authentication function test on the chip, the host first concatenates a random number (RND), the chip's original key (KEY) and the chip ID to form a second message {RND, KEY, ID}. Then the SHA256 algorithm is used to hash the second message {RND, KEY, ID} to generate a second hash value Hashmsg for identity authentication. After the SHA256 calculation of the first message corresponding to the chip is completed, the first hash value Hashmsg' is obtained, and the first hash value Hashmsg' is returned to the host and compared with the second hash value Hashmsg. If the first hash value Hashmsg' is equal to the second hash value Hashmsg, the authentication is successful; if the first hash value Hashmsg' is not equal to the second hash value Hashmsg, the authentication fails.

[0054] The following is a specific example to illustrate the method for randomly extracting a key from a characteristic Latch PUF unit of the present invention.

[0055] Specifically, the present application integrates the proposed featureless latch PUF unit and SHA256 authentication scheme and uses the HJ standard 0.18μm CMOS process to implement chip tape-out and test. Specifically, Xilinx KintexUltraScale MKU040FA is used as the host and the chip as the slave to test the chip's authentication function.

[0056] First, the host concatenates the random number RND generated by TRNG, the original PUF key and the chip ID into a second message {RND, KEY, ID}. Then, SHA256 is calculated on the second message to obtain the second hash value Hash msgPerform identity authentication. The 256-bit random number RND (e678c69d6cb142d3b08e0eb20090a6e4aa671faf3d75a1826957c3adf21db464) received from the slave, the 32-bit key PUF_KEY (c55a6395) of the featureless latch PUF unit, and the 256-bit chip ID (4f3a6b37ef385129810f36ae0bbfc46b5c7367b26ad22d8eda042afee7302038) are connected to form the first message {RND, PUF_KEY, ID}. Then, the first message {RND, PUF_KEY, ID} is preprocessed and divided into multiple message blocks: Message Block_1, Message Block_2, and PUF_KEY is placed in the first message block Message Block_1. When the first message block Message Block_1 is divided into W0 to W 15 When KEY1 is placed in W8, the featureless Latch PUF unit will decide whether to output the key based on the lowest three bits of the random number RND[2:0]. If the current round number t is equal to RND[2:0], the featureless Latch PUF unit generates the key as the Latch PUF, and then updates it to W8 to participate in the calculation of the new W. When W8 is used up, the featureless Latch PUF unit switches to a latch to store each message block after 64 rounds of calculation. When the SHA256 calculation is completed, the slave will use the 256-bit first hash value Hash msg '(8030ae21aa0a8210bef23f72c61a798c60442aad23cdf59a5e9ea3ffedb93828) is returned to the host for authentication. The test results show that after applying the featureless latch PUF unit to the SHA256 security algorithm, the algorithm continues to operate normally and the hash msg 'With Hash msg Equal, successfully passed the identity authentication.

[0057] In order to evaluate the dependence of the output key on voltage and temperature (V&T), this application tests 1,600 featureless Latch PUF units from 50 chips (each chip contains 32 PUF featureless units). The voltage range of the power supply VDD is 0.9*1.8V~1.1*1.8V, and the operating temperature range is -40℃~125℃. Each test is repeated 100 times. Once the output of the PUF unit changes, the PUF unit is considered unstable. Figure 4(a) shows the bit error rate distribution of featureless Latch PUF, with an average bit error rate of 14.89%.

[0058] In addition, three statistical characterization indicators of the featureless latch PUF output response are tested. The bias performance is obtained from the test data of the PUF unit under normal working conditions (27℃, 100%*VDD). Figure 4 (b) It can be seen that 842 units of the security chip output “1” and the bias performance is 52.62%. The reliability of featureless Latch PUF is described by the intra-chip HD distribution, as shown in Figure 4 (c) For 50 chips, the average intra-chip HD of the featureless Latch PUF is 7.15%. Figure 4 (d) is the inter-chip HD distribution of the featureless Latch PUF output key, with an average inter-chip HD of 45.2% and a standard deviation of 0.0641.

[0059] In summary, according to the random key extraction method of the featureless latch PUF unit of the embodiment of the present invention, the random number sent by the host is first obtained, and then the random number, the PUF key, and the chip ID are spliced ​​to obtain a first message, and the first message is filled by the SHA256 algorithm, and the filled first message is divided into multiple message blocks, the PUF key is located in the first message block, and then the multiple message blocks are expanded by the SHA256 algorithm to obtain the message key W. t , where the PUF key is located in W8; during the time when W8 performs the shift operation, the PUF key is randomly extracted. Therefore, this method reuses the function of the featureless latch PUF and randomizes the timing of extracting the featureless latch PUF key, thereby greatly increasing the difficulty for attackers to predict and locate the PUF key generation time, preventing attackers from extracting the key through physical attacks such as detection and FIB, and improving the security of the chip.

[0060] Corresponding to the above embodiment, the present invention also proposes a key random extraction device of a featureless Latch PUF unit.

[0061] Figure 5 4 is a block diagram of a key random extraction device of a featureless Latch PUF unit according to an embodiment of the present invention.

[0062] like Figure 5As shown, the key random extraction device 100 of the featureless latch PUF unit according to the embodiment of the present invention may include: an acquisition module 110, a splicing and filling module 120, a segmentation module 130, an expansion processing module 140, and a random extraction module 150.

[0063] The acquisition module 110 is used to obtain the random number sent by the host. The splicing and filling module 120 is used to splice the random number, the PUF key, and the chip ID to obtain a first message, and fill the first message through the SHA256 algorithm. The segmentation module 130 is used to divide the filled first message into multiple message blocks, wherein the PUF key is located in the first message block. The expansion processing module 140 is used to expand the multiple message blocks through the SHA256 algorithm to obtain the message word W t , wherein the PUF key is located in W8. The random extraction module 150 is used to randomly extract the PUF key within the time when W8 performs the shift operation.

[0064] According to one embodiment of the present invention, the random extraction module 150 randomly extracts the PUF key within the time when W8 performs the shift operation, specifically for obtaining the current round number of the SHA256 algorithm; when the current round number is equal to the preset round number, the featureless Latch PUF unit acts as a Latch PUF to generate a PUF key.

[0065] According to an embodiment of the present invention, the random extraction module 150 is configured to use the featureless Latch PUF unit as a latch to store data when the current round number is not equal to the preset round number.

[0066] According to one embodiment of the present invention, after the featureless Latch PUF unit generates a PUF key as a Latch PUF, the apparatus 100 is further configured to update the generated PUF key to W8 to participate in the calculation of a new W.

[0067] According to one embodiment of the present invention, the device 100 is further used to determine whether W8 is used up; when W8 is not used up, the featureless Latch PUF unit continues to be used as a Latch PUF to generate a PUF key; when W8 is used up, the featureless Latch PUF unit is used as a latch to store data.

[0068] According to one embodiment of the present invention, the device 100 is further used to obtain a first hash value after completing SHA256 calculation on the first message; and return the first hash value to the host for identity authentication.

[0069] According to one embodiment of the present invention, the device 100 is also used to return the first hash value to the host for identity authentication, specifically, the host concatenates the random number, the original key, and the chip ID to obtain a second message; hashes the second message through the SHA256 algorithm to obtain a second hash value; compares the first hash value with the second hash value, if the first hash value is equal to the second hash value, the identity authentication is successful; if the first hash value is not equal to the second hash value, the identity authentication fails.

[0070] It should be noted that for details not disclosed in the device for randomly extracting a key from a featureless latch PUF unit in an embodiment of the present invention, please refer to the details disclosed in the method for randomly extracting a key from a featureless latch PUF unit in an embodiment of the present invention, and the details will not be repeated here.

[0071] According to the key random extraction device of the featureless latch PUF unit of the embodiment of the present invention, the acquisition module acquires the random number sent by the host; the splicing and filling module splices the random number, the PUF key, and the chip ID to obtain a first message, and fills the first message through the SHA256 algorithm; the segmentation module divides the filled first message into multiple message blocks, and the PUF key is located in the first message block; the expansion processing module expands the multiple message blocks through the SHA256 algorithm to obtain the message key W t , where the PUF key is located in W8; the random extraction module randomly extracts the PUF key during the time when W8 performs the shift operation. Therefore, the device reuses the function of the featureless latch PUF and randomizes the timing of extracting the featureless latch PUF key, thereby greatly increasing the difficulty for attackers to predict and locate the PUF key generation time, preventing attackers from extracting the key through physical attacks such as detection and FIB, and improving the security of the chip.

[0072] Corresponding to the above embodiment, the present invention also proposes a computer-readable storage medium.

[0073] The computer-readable storage medium of the embodiment of the present invention stores a random key extraction program for a featureless Latch PUF unit. When the random key extraction program for the featureless Latch PUF unit is executed by a processor, the random key extraction method for the featureless Latch PUF unit is implemented.

[0074] According to the computer-readable storage medium of the embodiment of the present invention, by executing the above-mentioned random key extraction method of the featureless Latch PUF unit, it is possible to greatly increase the difficulty for attackers to predict and locate the PUF key generation time, prevent attackers from extracting keys through physical attack methods such as detection and FIB, and improve the security of the chip.

[0075] Corresponding to the above embodiment, the present invention further provides an electronic device.

[0076] Figure 6 FIG. 4 is a block diagram of an electronic device according to an embodiment of the present invention.

[0077] like Figure 6 As shown, the electronic device 200 of the embodiment of the present invention includes: a memory 210 and a processor 220. The memory 210 stores a program that can be run on the processor 220. When the processor 220 executes the program, the above-mentioned random key extraction method of the featureless LatchPUF unit is implemented.

[0078] The electronic device according to the embodiment of the present invention can greatly increase the difficulty for attackers to predict and locate the PUF key generation time by executing the above-mentioned method for random key extraction of the featureless latch PUF unit, prevent attackers from extracting keys through physical attack methods such as detection and FIB, and improve the security of the chip.

[0079] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0080] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0081] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0082] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0083] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0084] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A method for randomly extracting a key from a featureless latch PUF unit, characterized in that: The method comprises: Get the random number sent by the host; Concatenate the random number, the PUF key, and the chip ID to obtain a first message, and fill the first message using a SHA256 algorithm; Dividing the padded first message into a plurality of message blocks, wherein the PUF key is located in the first message block; The message blocks are extended by the SHA256 algorithm to obtain the message word W. t , wherein the PUF key is located in W8; During the time when W8 performs the shift operation, the PUF key is randomly extracted.

2. The method for randomly extracting a key from a featureless latch PUF unit according to claim 1, characterized in that: During the time when W8 performs the shift operation, the PUF key is randomly extracted, including: Get the current round number of the SHA256 algorithm; When the current round number is equal to the preset round number, the featureless Latch PUF unit acts as a Latch PUF to generate the PUF key.

3. The method for randomly extracting a key from a featureless latch PUF unit according to claim 2, characterized in that: When the current round number is not equal to the preset round number, the featureless Latch PUF unit is used as a latch to store data.

4. The method for randomly extracting a key from a featureless latch PUF unit according to claim 2, wherein: After the featureless Latch PUF unit generates the PUF key as the Latch PUF, the method further includes: The generated PUF key is updated to W8 to participate in the calculation of the new W.

5. The method for randomly extracting a key from a featureless latch PUF unit according to claim 4, characterized in that: The method further comprises: Determine whether W8 has been used up; In the case where W8 is not used up, the featureless Latch PUF unit continues to generate the PUF key as a Latch PUF; When W8 is used up, the featureless Latch PUF unit acts as a latch to store data.

6. The method for randomly extracting a key from a featureless latch PUF unit according to claim 1, wherein: The method further comprises: After performing SHA256 calculation on the first message, a first hash value is obtained; The first hash value is returned to the host for identity authentication.

7. The method for randomly extracting a key from a featureless latch PUF unit according to claim 6, wherein: Returning the first hash value to the host for identity authentication includes: The host concatenates the random number, the original key, and the chip ID to obtain a second message; Hashing the second message using the SHA256 algorithm to obtain a second hash value; The first Hash value is compared with the second Hash value. If the first Hash value is equal to the second Hash value, the identity authentication is successful; if the first Hash value is not equal to the second Hash value, the identity authentication fails.

8. A key random extraction device for a featureless latch PUF unit, characterized in that: The device comprises: The acquisition module is used to obtain the random number sent by the host; A splicing and filling module, used to splice the random number, the PUF key, and the chip ID to obtain a first message, and fill the first message through a SHA256 algorithm; a segmentation module, configured to divide the padded first message into a plurality of message blocks, wherein the PUF key is located in the first message block; An expansion processing module is used to perform expansion processing on the plurality of message blocks through the SHA256 algorithm to obtain a message word W t , wherein the PUF key is located in W8; The random extraction module is used to randomly extract the PUF key within the time when W8 performs the shift operation.

9. A computer-readable storage medium, characterized in that: A key random extraction program of a featureless Latch PUF unit is stored thereon. When the key random extraction program of the featureless Latch PUF unit is executed by a processor, the key random extraction method of the featureless Latch PUF unit according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the memory stores a program that can be run on the processor, and when the processor executes the program, the method for randomly extracting a key of a featureless latch PUF unit according to any one of claims 1 to 7 is implemented.

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