N-type source electrode manufacturing method for improving robustness of Power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Abstract

The invention relates to a Power MOSFET manufacturing technology, and discloses an N-type source electrode manufacturing method for improving the robustness of a Power MOSFET, and the method comprises the steps: constructing a gate structure on a semiconductor substrate; injecting conductive impurities into the semiconductor substrate with the gate structure according to a predetermined dosage and energy by adopting accurate injection equipment to form a first main body; constructing a first conductive source area on the surface of the first main body through the control parameters; forming an interlayer insulating film on the semiconductor substrate on which the first conductive source region is formed by chemical vapor deposition; performing an etching operation on the interlayer insulating film and the semiconductor substrate through an etching process to form a first trench; implanting conductive impurities into the surface of the semiconductor substrate exposed by the first groove by adopting an implantation process so as to form a second main body with specific electrical properties; according to the doping method of multi-step injection into the main body, the doping contour of the main body is non-uniform, so that the threshold voltage of the MOSFET is not influenced, and the UIS characteristic can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of manufacturing a power metal oxide semiconductor field effect transistor (Power MOSFET), and in particular to a method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET. Background Art

[0002] Power MOSFET (Power Metal-Oxide-Semiconductor Field-Effect Transistor) is a multi-layer semiconductor device. Power MOSFET robustness refers to the ability of Power Metal-Oxide-Semiconductor Field-Effect Transistor (PowerMOSFET) to maintain its expected functions and performance under various complex working conditions, environmental factors, and internal and external interferences.

[0003] At the moment when MOSFET switches from the on state to the off state, a voltage higher than the rated voltage of the driving voltage is instantly applied to the MOSFET, and unwanted electron charge flows through the MOSFET. This is called overcurrent. If this transition current is not properly eliminated, the MOSFET will be destroyed.

[0004] Therefore, when the MOSFET is turned off, one of the methods to effectively extract the transient current that is instantly injected into the MOSFET is to reduce the bulk resistance of the semiconductor substrate.

[0005] However, by increasing the implant dose of the body formation to reduce the body resistance, the UIS (Unclamped Inductive Switching) characteristics can be improved, but by reducing the implant process of the body resistance, the threshold voltage of the MOSFET will increase, thereby increasing the switching speed and power consumption of the MOSFET element.

[0006] Therefore, there is an urgent need for a method for manufacturing an N-type source electrode that improves the robustness of a Power MOSFET and solves the technical problem.

[0007] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0008] The main purpose of the present application is to provide an N-type source manufacturing method for improving the robustness of Power MOSFET, aiming to solve the problem of improving UIS characteristics without changing the threshold voltage.

[0009] To achieve the above-mentioned purpose, the present application provides an N-type source manufacturing method for improving the robustness of Power MOSFET, including forming a gate in a semiconductor substrate, wherein a gate structure capable of controlling the current in the semiconductor is constructed on the semiconductor substrate by using processes such as photolithography and deposition; a conductive impurity is injected into the semiconductor substrate having the gate structure according to a predetermined dose and energy by using a precise injection device to form a first body; a first conductive source region for current entry and exit is constructed on the surface of the first body by controlling parameters such as doping concentration and position; an interlayer insulating film is formed on the semiconductor substrate forming the first conductive source region by using chemical vapor deposition; the interlayer insulating film and the semiconductor substrate are etched according to a predetermined pattern by an etching process to form a contact hole or a first trench; and a conductive impurity is implanted into the surface of the semiconductor substrate exposed by the contact hole or the first trench by using a precise implantation process to form a second body with specific electrical properties.

[0010] As a preferred solution of the present application, the step of constructing the gate structure includes: forming a first oxide film on a semiconductor substrate by a thermal oxidation method; performing a photolithography process on the first oxide film to form a photoresist pattern; using the photoresist pattern as an etching mask, etching the first oxide film to obtain a hard mask; removing the photoresist pattern by an ashing process; using the hard mask as an etching mask, performing a reactive ion etching process, etching the semiconductor substrate, and removing the hard mask after forming a second trench; A gate oxide film is constructed on the inner surface of the second trench by thermal oxidation; gate polysilicon is filled into the second trench where the gate oxide film is formed by chemical deposition, thereby completing the construction of the gate structure.

[0011] As a preferred solution of the present application, the interlayer insulating film is a stacked structure, and the interlayer insulating film includes at least one of a silicon dioxide film or a borophosphosilicate glass.

[0012] As a preferred solution of the present application, the step of forming the contact hole and the first groove specifically includes: forming a photolithography pattern on the interlayer insulating film, using the photoresist pattern as an etching mask, etching the interlayer insulating layer and the semiconductor substrate to form the contact hole or the first groove, and then removing the photoresist pattern through an ashing process.

[0013] As a preferred solution of the present application, it further includes a gasket, and the sidewall of the contact hole or the first groove is provided with the gasket.

[0014] As a preferred solution of the present application, the step of setting the gasket specifically includes: depositing an insulating film on the contact hole or the first groove, and forming the gasket on the side wall of the first contact hole or the first groove through an etch-back process.

[0015] As a preferred solution of the present application, the contact hole or the first trench penetrates the interlayer insulating film and the first conductive source region, and exposes the first body.

[0016] As a preferred solution of the present application, the concentration of the second main body is greater than the concentration of the first main body.

[0017] As a preferred solution of the present application, the depth of the region where the first body is formed on the semiconductor substrate is smaller than the depth of the region of the gate structure.

[0018] As a preferred solution of the present application, after constructing the contact hole or the first groove, the size of the gasket is also adjusted.

[0019] The present application provides a method for manufacturing an N-type source for improving the robustness of a Power MOSFET. In the early steps of forming a first main body, a first conductive source region, etc., the parameters such as doping concentration and position are precisely controlled, thereby laying a foundation for subsequently precisely controlling the length of the N source. An interlayer insulating film and a semiconductor substrate are etched according to a predetermined pattern through an etching process to form a contact hole or a first groove. In this process, the length of the N source can be precisely controlled. The etching accuracy determines the size of the contact hole or the first groove, which in turn affects the length of the N source formed subsequently. The length of the N source can be controlled within a suitable range through precise etching, thereby reducing unnecessary length and improving UIS capability. At the same time, the present application uses a doping method of multi-step injection into the first main body and the second main body to make the doping profiles of the first main body and the second main body uneven, thereby not affecting the threshold voltage of the MOSFET and improving the UIS characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a flowchart of the steps of a method for manufacturing an N-type source for improving the robustness of a Power MOSFET in one embodiment of the present application; Figure 2 A schematic diagram of a first structure of a Power MOSFET in a method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET in an embodiment of the present application; Figure 3 A second structural schematic diagram of a Power MOSFET in a method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET in an embodiment of the present application; Figure 4 A third structural schematic diagram of a Power MOSFET in a method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET in an embodiment of the present application; Figure 5It is a fourth structural schematic diagram of a Power MOSFET in a method for manufacturing an N-type source for improving the robustness of the Power MOSFET in an embodiment of the present application.

[0021] Description of reference numerals: 310, semiconductor substrate; 315, first main body; 320, gate structure; 325, first source conductive region; 330, first interlayer insulating film; 335, second interlayer insulating film; 340, gasket; 350, second main body. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0023] In addition, if the descriptions of "first", "second", etc. are involved in this application, they are only used for descriptive purposes (such as for distinguishing the same or similar elements), and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0024] Please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 In one embodiment, a method for manufacturing an N-type source for improving the robustness of a Power MOSFET comprises the following steps: S1, forming a gate in the semiconductor substrate 310, wherein a gate structure 320 capable of controlling current in the semiconductor is constructed on the semiconductor substrate 310 by using processes such as photolithography and deposition; S2, using precise implantation equipment to implant conductive impurities into the semiconductor substrate 310 having the gate structure 320 according to a predetermined dose and energy to form a first body 315; S3, by controlling parameters such as doping concentration and position, a first conductive source region 325 for current inflow and outflow is constructed on the surface of the first body 315; S4, forming an interlayer insulating film on the semiconductor substrate 310 where the first conductive source region 325 is formed by chemical vapor deposition; S5, etching the interlayer insulating film and the semiconductor substrate 310 according to a predetermined pattern through an etching process to form a contact hole or a first trench; S6. Using a precise implantation process, conductive impurities are implanted into the surface of the semiconductor substrate 310 exposed by the contact hole or the first trench to form a second body 350 with specific electrical properties.

[0025] Preferably, the gate structure 320 in the present embodiment is a trench-type gate, and the contact hole or the first trench penetrates the interlayer insulating film and the first conductive source region 325 , and exposes the first body 315 .

[0026] It can be understood that in the early steps of forming the first body 315 and the first conductive source region 325, by precisely controlling parameters such as doping concentration and position, a foundation is laid for the subsequent precise control of the length of the N source; the interlayer insulating film and the semiconductor substrate 310 are etched according to a predetermined pattern through an etching process to form a contact hole or a first groove. In this process, the length of the N source can be precisely controlled. The etching accuracy determines the size of the contact hole or the first groove, which in turn affects the length of the N source formed subsequently; the length of the N source can be controlled within a suitable range through precise etching, reducing unnecessary length, thereby improving the UIS capability. At the same time, the present application uses a doping method of multi-step injection into the first body 315 and the second body 350 to make the doping profiles of the first body 315 and the second body 350 uneven, thereby not affecting the threshold voltage of the MOSFET and improving the UIS characteristics; Furthermore, in the entire manufacturing method, each process step is relatively independent and precise; for example, when forming the gate structure 320, processes such as photolithography and deposition are used, and the photolithography process can accurately define the pattern of the gate; due to the use of precise processes, subsequent operations such as injection and construction of conductive source areas will not have unnecessary effects on the gate structure 320, thereby reducing the possibility of risks to the threshold of the photolithography equipment.

[0027] Specifically, based on the above embodiment, the steps of constructing the gate structure 320 include: forming a first oxide film on the semiconductor substrate 310 by a thermal oxidation method; performing a photolithography process on the first oxide film to form a photoresist pattern; using the photoresist pattern as an etching mask, etching the first oxide film to obtain a hard mask; removing the photoresist pattern by an ashing process; using the hard mask as an etching mask, performing a reactive ion etching process to etch the semiconductor substrate 310, and removing the hard mask after forming a second trench; constructing a gate oxide film on the inner surface of the second trench by a thermal oxidation method; and filling the gate polysilicon inside the second trench where the gate oxide film is formed by chemical deposition, thereby completing the construction of the gate structure 320.

[0028] It can be understood that the UIS characteristics mainly involve the performance of power devices during the switching process under inductive loads. Accurate pattern transfer and good interface control have a positive effect on improving UIS characteristics. Accurate groove shape and size help to form a more optimized channel structure, so that the flow of carriers can be more effectively controlled during the switching process. For example, in high-power applications, when the transistor is switching, the optimized channel structure can reduce the accumulation and scattering of carriers and reduce switching losses, which is an important aspect of improving UIS characteristics. High-quality gate oxide film and complete gate polysilicon filling can improve the gate's control over the channel. During the UIS process, the gate can more accurately adjust the conduction and cutoff of the channel and reduce overvoltage and overcurrent phenomena caused by carrier loss of control.

[0029] For details, please refer to Figure 4 , Figure 5 Based on the above embodiment, the interlayer insulating film is a stacked structure, and the interlayer insulating film includes at least one of a silicon dioxide film and borophosphosilicate glass (BPSG).

[0030] It can be understood that in this embodiment, the interlayer insulating film includes a first interlayer insulating film 330 and a second interlayer insulating film 330, and the interlayer insulating film is made of at least one of a silicon dioxide film or borophosphosilicate glass (BPSG), because silicon dioxide has excellent insulation properties; in Power MOSFET, the interlayer insulating film needs to prevent current leakage between different conductive layers to ensure the electrical independence of various functional areas; for example, between the source and the drain, or between the gate and other areas, the silicon dioxide film can effectively prevent unnecessary conduction of current, thereby reducing the leakage current of the device and improving the efficiency and reliability of the device.

[0031] The electrical properties of borophosphosilicate glass (BPSG), such as dielectric constant and resistivity, can be tuned to a certain extent by adjusting the content of boron (B) and phosphorus (P); this enables it to be customized according to specific circuit design and manufacturing requirements to meet different electrical performance needs, such as areas where specific capacitance values ​​or leakage requirements are required, which can be achieved by adjusting the composition of BPSG.

[0032] Specifically, based on the above-mentioned embodiment, the steps of forming the contact hole and the first groove specifically include: forming a photolithography pattern on the interlayer insulating film, using the photoresist pattern as an etching mask, etching the interlayer insulating layer and the semiconductor substrate 310 to form a contact hole or a first groove, and then removing the photoresist pattern through an ashing process.

[0033] It can be understood that the photolithography process can achieve nanometer-level pattern accuracy. This high-precision pattern can accurately define the position and shape of the contact hole or the first groove on the interlayer insulating film and the semiconductor substrate 310, providing an accurate template for the subsequent etching process; the photoresist pattern can ensure that the etching process only removes the interlayer insulating film and the semiconductor substrate 310 material at the predetermined position, thereby obtaining a contact hole or a first groove with precise size and regular shape. The precise contact hole and groove size helps to optimize the current conduction path and the electrical characteristics of the device. Compared with other methods for removing photoresist, the ashing process used in this embodiment produces less residue and will not cause pollution to the already formed contact hole or first groove and the surrounding materials, ensuring the smooth progress of subsequent processes (such as implanting conductive impurities, etc.).

[0034] For details, please refer to Figure 5 , based on the above embodiment, further comprising a gasket 340, the sidewall of the contact hole or the first trench is provided with the gasket 340; It can be understood that in a Power MOSFET (power metal-oxide-semiconductor field-effect transistor), the gasket 340 set on the sidewall of the contact hole or the first trench can play an isolation role; at the same time, the gasket 340 can affect the electric field distribution around the contact hole or the first trench, and due to its insulating properties, it can change the direction of the electric field lines; for example, under high voltage working conditions, a suitable gasket 340 can make the electric field more evenly distributed around the contact hole or the trench, avoiding breakdown caused by excessive local electric field, improving the voltage resistance of the device, and helping to improve the robustness of the Power MOSFET.

[0035] Specifically, based on the above embodiment, the step of setting the gasket 340 specifically includes: depositing an insulating film on the contact hole or the first trench, and forming the gasket 340 on the sidewall of the first contact hole or the first trench through an etch-back process.

[0036] It can be understood that an insulating film is deposited on the contact hole or the first groove. This deposition process has good controllability and can accurately control the thickness, uniformity and other parameters of the insulating film; for example, through chemical vapor deposition (CVD) technology, the deposition conditions such as gas flow, temperature, pressure, etc. can be adjusted as needed to obtain an insulating film that meets the requirements. This lays the foundation for the subsequent formation of high-quality gaskets 340, because the quality of gaskets 340 (such as thickness uniformity, etc.) directly affects its effects in reducing leakage, improving electric field distribution, etc.

[0037] Furthermore, a gasket 340 is formed on the side wall of the first contact hole or the first groove through an etch-back process, and the etch-back process can accurately remove unnecessary portions of the insulating film, leaving only the gasket 340 on the side wall; for example, the etch-back process can achieve precise control of the amount of insulating film removed by controlling parameters such as etching time, type and flow rate of etching gas; this precision ensures that the size and shape of the gasket 340 can meet the design requirements, for example, the thickness of the gasket 340 can be accurate to the nanometer level, so as to better play its electrical and mechanical roles.

[0038] Specifically, on the basis of the above embodiment, the concentration of the second body 350 is greater than the concentration of the first body 315 .

[0039] It can be understood that in a Power MOSFET (power metal-oxide-semiconductor field-effect transistor), the concentration of the second body 350 is greater than the concentration of the first body 315, which means that there are more carriers in a specific area (the area where the second body 350 is located). For N-type semiconductors, the carriers are mainly electrons. When the impurity concentration of the second body 350 is higher, the number of electrons available for conducting current in the area increases, thereby improving the conductivity of this area. This helps to reduce the on-resistance of the entire device; at the same time, since the concentration of the second body 350 is greater than the concentration of the first body 315, this concentration difference can be used to accurately control the threshold voltage of the Power MOSFET, that is, the threshold voltage.

[0040] For details, please refer to Figure 4 , Figure 5 On the basis of the above embodiment, the depth of the region where the first body 315 is formed on the semiconductor substrate 310 is smaller than the depth of the region where the gate structure 320 is formed.

[0041] It can be understood that when the depth of the region where the first body 315 is formed on the semiconductor substrate 310 is less than the depth of the region of the gate structure 320, a potential gradient will be formed in the vertical direction; for example, when the Power MOSFET (power metal-oxide-semiconductor field-effect transistor) is working, the gate structure 320 controls the movement of carriers in the semiconductor through the action of the electric field; since the depth of the first body 315 region is shallow, the gate electric field can more effectively affect the carriers in the first body 315. This is like in a shallow "carrier pool", the gate electric field is more likely to regulate the carriers, thereby more accurately controlling the conduction and cutoff of the current, and improving the switching performance of the device.

[0042] For details, please refer to Figure 5 Based on the above embodiment, after the contact hole or the first trench is constructed, the size of the gasket 340 is also adjusted.

[0043] It can be understood that when the spacer 340 is used after forming the contact hole or the first trench, the spacer 340 plays a role of physical isolation; before the second body 350 is formed to inject the conductive impurities, the size of the spacer 340 can control the area range of impurity diffusion; if the spacer 340 is large, it can limit the diffusion of impurities to a specific area, so that the impurity concentration in the A area is relatively low; on the contrary, if the spacer 340 is small, the restriction on impurity diffusion is small, and more impurities may enter the A area, resulting in an increase in the impurity concentration in the A area; By adjusting the size of the gasket 340 to adjust the impurity concentration in region A, the carrier distribution in region A is actually adjusted. Appropriate carrier distribution is crucial to optimizing UIS characteristics. For example, during the UIS process, appropriate carrier distribution can enable the MOSFET to better withstand voltage stress under the high induced voltage generated when the inductive load is turned off, reduce excessive charge accumulation and excessive concentration of the electric field, and thus improve the UIS capability. If the impurity concentration in region A is not appropriate, it may cause the local electric field to be too high or the current distribution to be uneven during the UIS process, thereby affecting the reliability and performance of the MOSFET.

[0044] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0045] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET, characterized in that: include: Forming a gate in a semiconductor substrate, wherein a gate structure capable of controlling current in the semiconductor is constructed on the semiconductor substrate by using processes such as photolithography and deposition; Using precise implantation equipment, implanting conductive impurities into the semiconductor substrate having the gate structure according to a predetermined dosage and energy to form a first body; By controlling parameters such as doping concentration and position, a first conductive source region for current inflow and outflow is constructed on the surface of the first body; forming an interlayer insulating film on the semiconductor substrate forming the first conductive source region by chemical vapor deposition; Performing etching operation on the interlayer insulating film and the semiconductor substrate according to a predetermined pattern through an etching process to form a contact hole or a first trench; Conductive impurities are implanted into the surface of the semiconductor substrate exposed by the contact hole or the first trench by a precise implantation process to form a second body with specific electrical properties.

2. The method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET according to claim 1, characterized in that: The step of constructing the gate structure comprises: forming a first oxide film on the semiconductor substrate by a thermal oxidation method; Performing a photolithography process on the first oxide film to form a photoresist pattern; Using the photoresist pattern as an etching mask, etching the first oxide film to obtain a hard mask; removing the photoresist pattern through an ashing process; Using the hard mask as an etching mask, performing a reactive ion etching process to etch the semiconductor substrate, and removing the hard mask after forming the second trench; constructing a gate oxide film on the inner surface of the second trench by thermal oxidation; The gate polysilicon is filled into the second trench where the gate oxide film is formed by chemical deposition, thereby completing the construction of the gate structure.

3. The method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET according to claim 1, characterized in that: The interlayer insulating film has a stacked structure, and the interlayer insulating film includes at least one of a silicon dioxide film and borophosphosilicate glass.

4. The method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET according to claim 1, characterized in that: The steps of forming the contact hole and the first trench specifically include: forming a photolithography pattern on the interlayer insulating film, using the photoresist pattern as an etching mask, etching the interlayer insulating layer and the semiconductor substrate to form the contact hole or the first trench, and then removing the photoresist pattern by an ashing process.

5. The method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET according to claim 1, characterized in that: A gasket is also included, and the sidewall of the contact hole or the first groove is provided with the gasket.

6. The method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET according to claim 5, characterized in that: The step of providing the gasket specifically includes: depositing an insulating film on the contact hole or the first trench, and forming the gasket on the sidewall of the first contact hole or the first trench through an etch-back process.

7. The method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET according to claim 1, characterized in that: The contact hole or the first trench penetrates the interlayer insulating film and the first conductive source region and exposes the first body.

8. The method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET according to claim 1, characterized in that: The concentration of the second host is greater than the concentration of the first host.

9. The method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET according to claim 1, characterized in that: The depth of a region where the first body is formed on the semiconductor substrate is smaller than the depth of a region where the gate structure is formed.

10. The method for manufacturing an N-type source electrode for improving the robustness of a Power MOSFET according to claim 6, characterized in that: After constructing the contact hole or the first groove, the size of the gasket is also adjusted.

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