Surface treatment method of oxide transistor

Abstract

The invention relates to a surface treatment method of an oxide transistor, and belongs to the field of integrated circuit micro-nano electronic devices. The method comprises the following specific steps: providing a substrate, and forming a bottom gate electrode on the substrate; sequentially forming a dielectric layer and an oxide active layer on the bottom gate electrode; respectively forming a source electrode and a drain electrode on two sides of the oxide active layer; a layer of oxidizable metal is evaporated on the oxide active layer between the source electrode and the drain electrode through electron beam evaporation, and then the metal is converted into metal oxide through natural oxidation, air annealing oxidation, oxygen annealing oxidation and the like. By forming the oxide layer, the interface state density of the transistor can be effectively reduced, the field effect mobility of the transistor is improved, the switching speed and the power consumption performance of the transistor are improved, in addition, the stability and the reliability of the transistor can be improved, and therefore the overall performance of an integrated circuit is improved.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit micro-nano electronic devices, and in particular relates to a surface treatment method for an oxide transistor. Background Art

[0002] In recent years, a series of new semiconductor materials, such as 2D transition metal dichalcogenides and oxide semiconductors, have received great attention, allowing integrated circuits to continue to shrink device size along Moore's Law. Oxide transistors have the advantages of high uniformity, small thermal displacement, low cost, and good back channel compatibility. In recent years, they have received extensive attention and application in the field of integrated circuits. So far, various new applications based on oxide transistors have been developed, such as neuromorphic computing, capacitor-free DRAM (2T0C DRAM) applications, and advanced sensors. In order to further achieve electrical performance and monolithic three-dimensional (M3D) integrated applications, it is very critical. Improvements in oxide transistor mobility, bias stress stability, and thermal stability are crucial for their use in integrated circuits.

[0003] To date, a variety of methods have been studied to maintain the trade-off between excellent device performance and high stability, such as controlling the elemental composition of the oxide film, improving the post-annealing process, and adjusting the transistor structure. However, there are still some problems with oxide transistors in terms of high frequency, low power consumption, and high reliability. It is necessary to provide a higher performance oxide transistor by improving the process. Summary of the invention

[0004] The present invention is intended to provide a surface treatment method for an oxide transistor to solve the deficiencies in the prior art. The technical problem to be solved by the present invention is achieved through the following technical solutions.

[0005] The present invention provides a surface treatment method for an oxide transistor, characterized in that the method comprises:

[0006] Providing a substrate (101) on which a bottom gate electrode (102) is formed;

[0007] forming a dielectric layer (103) and an oxide active layer (104) in sequence on the bottom gate electrode (102);

[0008] Forming source and drain electrodes (105) on both sides of the oxide active layer (104);

[0009] A layer of oxidizable metal is evaporated on the oxide active layer (104) between the source / drain electrodes (105) by electron beam evaporation, and then the oxidizable metal is converted into metal oxide by natural oxidation, air annealing oxidation or oxygen annealing oxidation.

[0010] Furthermore, the oxidizable metal is selected from aluminum, magnesium, tantalum, titanium, molybdenum or tungsten.

[0011] Furthermore, the thickness of the metal oxide is 2-10 nm.

[0012] Furthermore, the substrate is selected from a single crystal silicon substrate, a silicon oxide substrate, a glass substrate or a flexible substrate, and the flexible substrate includes PET or PI.

[0013] Furthermore, the bottom gate electrode is a combination of one or more of Al, Ti, Mo, Au or Pd, or a combination of one or more of transparent conductive films such as ITO, AZO and other conductive films.

[0014] Furthermore, the source / drain electrode is a combination of one or more of Al, Ti, Mo, Au or Pd, or a combination of one or more of transparent conductive films such as ITO, AZO and other conductive films.

[0015] Furthermore, the dielectric layer is Al2O3, HfO2 or TiO2.

[0016] Furthermore, the oxide active layer (104) is indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), a doped indium oxide film or a doped zinc oxide film.

[0017] Furthermore, the doping elements in the doped indium oxide film and the doped zinc oxide film are one or a combination of multiple of aluminum, tin, molybdenum, titanium, hafnium, zinc, gallium silicon, carbon, phosphorus, or lanthanum and erbium rare earth elements.

[0018] Furthermore, the content of doping elements in the doped indium oxide film and the doped zinc oxide film is 0.05%-50%.

[0019] The present invention has the following advantages:

[0020] The present invention is an effective surface treatment method for forming a metal oxide layer of about 5 nanometers thick by evaporating 2 nm of oxidizable metal on the surface of an oxide transistor by electron beam evaporation and forming a metal oxide layer of about 5 nanometers thick by natural oxidation. By forming an aluminum oxide layer, the interface state density of the transistor can be effectively reduced, the field effect mobility of the transistor can be increased, the switching speed and power consumption performance of the transistor can be improved, and the stability and reliability of the transistor can be improved, thereby improving the overall performance of the integrated circuit. In addition, the oxide transistor prepared by the present invention is prepared by magnetron sputtering, atomic layer deposition, photolithography and stripping processes, with simple steps and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a step diagram of a method for manufacturing an oxide transistor of the present invention;

[0022] Figure 2 is a schematic diagram of forming a bottom gate electrode according to the present invention;

[0023] Figure 3 is a schematic diagram of forming a dielectric layer according to the present invention;

[0024] Figure 4 is a schematic diagram of forming an active layer according to the present invention;

[0025] Figure 5 is a schematic diagram of forming a source and drain electrode of the present invention;

[0026] Figure 6 is a schematic diagram of forming a metal oxide according to the present invention;

[0027] Figure 7 is the current-voltage characteristic curve of the oxide transistor of the present invention. DETAILED DESCRIPTION

[0028] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] An embodiment of the present invention provides a surface treatment method for an oxide transistor, the specific process is as follows: Figure 1 As shown. First, a substrate 101 is provided. In this embodiment, the substrate is a glass substrate. In other embodiments, the substrate is a single crystal silicon substrate, a silicon oxide substrate, a glass substrate, a flexible substrate (PET and PI), etc. The glass substrate is placed in acetone, ethanol, and deionized water for ultrasonic cleaning in sequence. The cleaning time is 5 minutes. Then, a gate electrode pattern is formed by photolithography and stripping processes.

[0030] Then, a bottom gate electrode 102 is formed on the substrate 101. In this embodiment, the bottom gate electrode is a Ti film. In other embodiments, the bottom gate electrode is a combination of one or more metals such as Al, Ti, Mo, Au, Pd, or a combination of one or more conductive films such as indium tin oxide (ITO) and aluminum-doped zinc oxide (AZO). The thickness of the bottom gate electrode is 5-500 nanometers. In this embodiment, a metal Ti film is deposited on a glass substrate by a magnetron sputtering process, and the thickness of the Ti film is 100 nanometers; then a lift-off process is used to form the bottom gate electrode 102, such as Figure 2 shown.

[0031] Then, the dielectric layer and the oxide active layer are patterned by photolithography. The Al2O3 thin film is deposited on the bottom gate electrode 102 by atomic layer deposition as the dielectric layer 103. Figure 3The dielectric layer 103 has a thickness of 3-100 nanometers. In this embodiment, the dielectric layer has a thickness of 30 nanometers. In other embodiments, the dielectric layer can be selected from high-k dielectric materials such as HfO2, TiO2, or doped Al2O3, HfO2, and TiO2.

[0032] The oxide active layer 104 is deposited on the Al2O3 film by using magnetron sputtering process and atomic layer deposition process, such as Figure 4 The specific preparation steps are as follows: fix the substrate with the bottom gate electrode 102 and the dielectric layer 103 formed thereon to the tray of the magnetron sputtering equipment, and then pump the back bottom gas pressure of the magnetron sputtering equipment chamber to 5×10 -4 Pa; introduce oxygen and argon, adjust the air pressure control valve, set the cavity pressure to 1 Pa, turn on the tray rotation button, and set the speed to 15 rpm.

[0033] Turn on the RF power supply again and pre-sputter for 2 minutes. The sputtering target used in the magnetron sputtering process is indium oxide or doped indium oxide target. Turn the magnetron sputtering target baffle and officially sputter for 3 minutes. After the deposition of the indium aluminum tin oxide film is completed, turn off the RF power supply and the magnetron sputtering equipment.

[0034] The total thickness of the oxide active layer 104 is 2-200 nanometers, and can be indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), doped indium oxide film or doped zinc oxide film. For the doped indium oxide film or doped zinc oxide film, the doping element is one or more of metal elements such as aluminum, tin, molybdenum, titanium, hafnium, zinc, gallium, etc., inorganic non-metallic elements such as silicon, carbon, phosphorus, or rare earth elements such as lanthanum and erbium. The content of the doping element in the doped indium oxide film and the doped zinc oxide film is: 0.05%-50% of the doping element.

[0035] Then, a dielectric layer 103 and an oxide active layer 104 are formed by a lift-off process. Next, a source / drain electrode pattern is defined by a photolithography process, and source / drain electrodes 105 are formed on both sides of the oxide active layer 104, such as Figure 5 As shown. A metal Ti film is deposited on the oxide active layer 104 by magnetron sputtering as a source / drain electrode, and the thickness of the source / drain electrode is 5-500 nanometers. In this embodiment, the film thickness is 100 nanometers. Then a lift-off process is used to form a source / drain electrode structure. In other embodiments, the source / drain electrode is a combination of one or more metals such as Al, Mo, Au, and Pd, or a combination of one or more conductive films such as transparent conductive films such as ITO and AZO.

[0036] Then, a photolithography process is used to define the passivation layer pattern and form a metal oxide 106, such as Figure 6By electron beam evaporation process, a layer of oxidizable metal is evaporated on the oxide active layer (104) between the source / drain electrodes (105). In this embodiment, the oxidizable metal is aluminum. In other embodiments, the oxidizable metal can be magnesium, tantalum, titanium, molybdenum or tungsten.

[0037] Finally, a stripping process is used to form a passivation layer structure; then the device is placed in a natural environment to allow the oxidizable metal to oxidize naturally, or an oxygen or air atmosphere is used to perform an annealing treatment on the prepared oxide transistor at a temperature of 50-500°C for 10-120 minutes to oxidize the oxidizable metal. During the oxidation process, the oxidizable metal can obtain oxygen from the oxide active layer, increase oxygen vacancies, and improve mobility, thereby achieving surface modification of the transistor. In this embodiment, a natural oxidation method is adopted, and the thickness of the formed metal oxide is 3-10nm, preferably 5nm.

[0038] In another embodiment, a device with a conventional structure is manufactured by adopting the above manufacturing method but without forming an oxidizable metal layer, and an electrical performance test is performed. Figure 7 The current-voltage characteristic curves of the oxide transistor with an oxidizable metal layer prepared according to the above method and the oxide transistor without an oxidizable metal layer are compared. It can be seen that the oxide transistor with an oxidizable metal layer shows good transfer characteristics and the field effect mobility is improved.

[0039] It should be noted that the above detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present application belongs.

[0040] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0041] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0042] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0043] For ease of description, spatially relative terms, such as "above", "above", "on the upper surface of", "above", etc., may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein are interpreted accordingly.

[0044] In the above detailed description, reference is made to the accompanying drawings, which form a part of this document. In the accompanying drawings, similar symbols typically identify similar components unless the context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.

[0045] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A surface treatment method for an oxide transistor, characterized in that: The method comprises: Providing a substrate (101) on which a bottom gate electrode (102) is formed; forming a dielectric layer (103) and an oxide active layer (104) in sequence on the bottom gate electrode (102); Forming source / drain electrodes (105) on both sides of the oxide active layer (104); A layer of oxidizable metal is evaporated on the oxide active layer (104) between the source / drain electrodes (105) by electron beam evaporation, and then the oxidizable metal is converted into metal oxide (106) by natural oxidation, air annealing oxidation or oxygen annealing oxidation.

2. The surface treatment method of an oxide transistor according to claim 1, characterized in that: The oxidizable metal is selected from aluminum, magnesium, tantalum, titanium, molybdenum or tungsten.

3. The surface treatment method of an oxide transistor according to claim 1, characterized in that: The thickness of the metal oxide (106) is 3-10 nm.

4. The surface treatment method of an oxide transistor according to claim 1, wherein: The substrate is selected from a single crystal silicon substrate, a silicon oxide substrate, a glass substrate or a flexible substrate, and the flexible substrate includes PET or PI.

5. The surface treatment method of an oxide transistor according to claim 1, characterized in that: The bottom gate electrode is a combination of one or more of Al, Ti, Mo, Au or Pd, or a combination of one or more of transparent conductive film ITO and AZO conductive film.

6. The surface treatment method of an oxide transistor according to claim 1, wherein: The source / drain electrode is a combination of one or more of Al, Ti, Mo, Au or Pd, or a combination of one or more of transparent conductive film ITO and AZO conductive film.

7. The surface treatment method of an oxide transistor according to claim 1, characterized in that: The dielectric layer is Al2O3, HfO2 or TiO2.

8. The surface treatment method of an oxide transistor according to claim 1, characterized in that: The oxide active layer (104) is indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), a doped indium oxide film or a doped zinc oxide film.

9. The surface treatment method of an oxide transistor according to claim 8, characterized in that: The doping elements in the doped indium oxide film and the doped zinc oxide film are one or a combination of multiple rare earth elements such as aluminum, tin, molybdenum, titanium, hafnium, zinc, gallium silicon, carbon, phosphorus, or lanthanum and erbium.

10. The surface treatment method of an oxide transistor according to claim 8, characterized in that: The content of doping elements in the doped indium oxide film and the doped zinc oxide film is 0.05%-50%.

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