Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a barrier layer, a P-type gallium nitride layer, a cap layer, an etching groove, a source electrode and a drain electrode, the substrate, the barrier layer, the P-type gallium nitride layer, the cap layer and the etching groove are stacked in sequence, the source electrode and the drain electrode are arranged on the cap layer and far away from the two sides of the etching groove, and the etching groove penetrates through the cap layer and etches part of the P-type gallium nitride layer. A surface oxidation modified aluminum nitride deposition layer is arranged at the bottom of the etching groove, and a grid electrode is arranged on the surface oxidation modified aluminum nitride deposition layer. The semiconductor device provided by the invention not only can maintain relatively high conduction current, but also can enhance the threshold voltage performance of the device, and successfully improves the threshold voltage during zero bias on the premise of not sacrificing on-state current.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology and relates to a semiconductor device and a preparation method thereof. Background Art

[0002] Gallium nitride-based field-effect transistors are favored for their fast switching, low conduction loss, and high breakdown voltage. When designing complementary logic circuits, p-channel gallium nitride devices play a key role. In order to manufacture enhancement-mode p-channel devices, the upper p-GaN layer needs to be etched to a certain depth to form a depletion region so that the two-dimensional hole gas (2DHG) in the p-GaN / AlGaN channel is depleted. When the channel is turned on, a negative voltage needs to be applied to the gate to reach the threshold voltage. In the process of manufacturing p-channel gallium nitride devices, it is usually necessary to etch more p-GaN to achieve an enhancement-mode device, which reduces the saturation current when the channel is turned on. However, low threshold voltage or reduced saturation current are not good for the performance of complementary logic circuits.

[0003] In GaN device design, there is usually a trade-off between threshold voltage and on-state current. Under zero gate bias, a high threshold voltage can be achieved by etching more p-GaN to enhance channel depletion, but this will reduce the on-state current. Although etching less p-GaN can increase the on-state current, it will reduce the threshold voltage and even make it difficult to manufacture enhancement-mode devices.

[0004] CN116913962A discloses a GaN device and a preparation method thereof, wherein a first gate metal electrode and a second gate metal electrode with different work functions are formed, and the second gate metal electrode is located at the periphery of the first gate metal electrode with a larger work function, so that the GaN device can have different micro-area gate control capabilities, and constitute a GaN device with different local threshold voltages, so that the GaN device has different micro-area gate control capabilities. m -V GS The peak range in the characteristic curve is widened, improving the linearity of the GaN device.

[0005] CN103531476A discloses a method for manufacturing a semiconductor device, including: forming a gate stack structure on a substrate; depositing a dielectric material layer on the substrate and the gate stack structure; performing main etching to etch the dielectric material layer to form a side wall, and leaving a residue of the dielectric material layer on the substrate; performing over etching to remove the residue of the dielectric material layer.

[0006] The semiconductor device described in the above solution needs to sacrifice the on-state current to increase the threshold voltage. It is facing great challenges to realize both high threshold voltage and high saturation current of p-channel gallium nitride devices. Summary of the invention

[0007] The object of the present invention is to provide a semiconductor device and a method for preparing the same. The semiconductor device of the present invention can not only maintain a relatively high on-state current, but also enhance the threshold voltage performance of the device, and successfully improve the threshold voltage at zero bias without sacrificing the on-state current.

[0008] In order to achieve the purpose of the invention, the present invention adopts the following technical solutions:

[0009] In a first aspect, the present invention provides a semiconductor device, comprising a substrate, a barrier layer, a P-type gallium nitride layer, a cap layer, an etched groove, and a source and a drain arranged on the cap layer away from both sides of the etched groove, which are stacked in sequence. The etched groove penetrates the cap layer and etches a portion of the P-type gallium nitride layer. A surface oxidation-modified aluminum nitride deposition layer is arranged at the bottom of the etched groove, and a gate is arranged on the surface oxidation-modified aluminum nitride deposition layer.

[0010] In the semiconductor device described in the present invention, by introducing an aluminum nitride layer with surface oxidation modification under the gate, a high on-state current can be ensured and the threshold voltage of the p-channel gallium nitride device can be significantly improved. Most of the aluminum nitride in the upper layer of the surface oxidation modified aluminum nitride deposition layer is oxidized into aluminum nitride oxide, which has a very high dielectric constant and can withstand a larger gate voltage, thereby fully opening the channel; the lower unoxidized aluminum nitride layer introduces fixed positive charges at the interface to enhance the depletion of the channel. From the perspective of the energy band, the polarization characteristics of AlN cause the energy level at the interface to bend downward, so that the valence band at the channel is away from the Fermi level. For the conduction of the p-channel device, a negative voltage needs to be applied to raise the valence band at the channel above the Fermi level to generate a two-dimensional hole gas. In addition to the influence of the downward bending of the polarization energy band, a larger gate negative bias is required to make the valence band cross the Fermi level, thereby turning on the channel. This feature is crucial for achieving p-channel gallium nitride devices with high threshold voltage and high saturation current.

[0011] Preferably, the material of the substrate includes any one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium or silicon, or a combination of at least two of them. Typical but non-limiting combinations include a combination of gallium nitride and aluminum gallium nitride, a combination of germanium and silicon, or a combination of silicon carbide and silicon, etc.

[0012] Preferably, the thickness of the substrate is 1 mm to 1.5 mm, for example, 1 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm or 1.5 mm, etc., and is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0013] Preferably, the material of the barrier layer includes gallium nitride and / or gallium aluminum nitride.

[0014] Preferably, the thickness of the barrier layer is 20 nm to 25 nm, for example, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm or 25 nm, etc., and is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0015] Preferably, the thickness of the P-type gallium nitride layer is 65 nm to 70 nm, for example, 65 nm, 66 nm, 67 nm, 68 nm, 69 nm or 90 nm, etc., and is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0016] Preferably, the cap layer comprises P ++ type gallium nitride layer.

[0017] Preferably, the thickness of the cap layer is 10 nm to 15 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 15 nm, etc., and is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0018] Preferably, the materials of the source and drain independently include any one of nickel, titanium, aluminum, gold or titanium nitride, or a combination of at least two of them. Typical but non-limiting combinations include a combination of nickel and titanium, a combination of nickel and gold, or a combination of nickel, titanium aluminum and titanium nitride, etc.

[0019] Preferably, the material of the gate includes titanium and / or titanium nitride.

[0020] Preferably, the thickness of the partial P-type gallium nitride layer is 3 / 4 to 9 / 10 of the thickness of the P-type gallium nitride layer, for example: 3 / 4, 5 / 6, 6 / 7, 7 / 8, 8 / 9 or 9 / 10, etc., and is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0021] Preferably, the surface oxidation-modified aluminum nitride deposition layer comprises an aluminum nitride layer and an aluminum oxide nitride layer disposed on the surface of the aluminum nitride layer.

[0022] Preferably, the thickness of the surface oxidation-modified aluminum nitride deposition layer is 16 nm to 20 nm, for example, 16 nm, 17 nm, 18 nm, 19 nm or 20 nm, etc., and is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0023] Preferably, taking the thickness of the surface oxidation-modified aluminum nitride deposition layer as 100%, the thickness of the aluminum oxide nitride layer is 80% to 95%, for example: 80%, 82%, 85%, 88%, 90% or 95%, etc., not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0024] In a second aspect, the present invention provides a method for preparing the semiconductor device according to the first aspect, the method comprising the following steps:

[0025] (1) sequentially preparing a barrier layer, a first P-type gallium nitride layer, a second P-type gallium nitride layer and a cap layer on a substrate, etching the second P-type gallium nitride layer and the cap layer to form an etched groove, depositing a source electrode and a drain electrode on both sides of the cap layer away from the etched groove, and then annealing to obtain a semi-finished device;

[0026] (2) after preparing an aluminum nitride deposition layer on the surface of the semi-finished device, performing an oxidation modification treatment on the aluminum nitride deposition layer to obtain a surface oxidation-modified aluminum nitride deposition layer, and removing the surface oxidation-modified aluminum nitride deposition layer from other parts except the bottom of the etched groove;

[0027] (3) Depositing a gate on the surface oxidation-modified aluminum nitride deposition layer to obtain the semiconductor device.

[0028] In the preparation process of the aluminum nitride deposition layer described in the present invention, the aluminum nitride deposition layer can be deposited only in the groove, or the aluminum nitride deposition layer can be deposited on the entire surface of the semi-finished device. However, it is necessary to subsequently remove all aluminum nitride deposition layers except the aluminum nitride deposition layer at the bottom of the groove. In order to reduce the difficulty of operation, the present invention generally adopts the method of depositing the aluminum nitride deposition layer on the entire surface of the semi-finished device.

[0029] Preferably, the etching method in step (1) includes inductively coupled plasma etching.

[0030] Preferably, the etching gas used in the etching process in step (1) includes Cl2 and / or BCl3.

[0031] Preferably, the etching power of the etching treatment in step (1) is 190W to 230W, for example: 190W, 200W, 210W, 220W or 230W, etc., not limited to the listed values, other values ​​not listed within the numerical range are also applicable.

[0032] Preferably, the method of depositing the source and drain in step (1) comprises electron beam evaporation deposition.

[0033] Preferably, the temperature of the annealing treatment in step (1) is 500°C to 550°C, for example, 500°C, 510°C, 520°C, 530°C, 540°C or 550°C, etc., and is not limited to the listed values. Other values ​​not listed within the numerical range are also applicable.

[0034] Preferably, the annealing time in step (1) is 4 min to 7 min, for example, 4 min, 4.5 min, 5 min, 6 min or 7 min, etc., and is not limited to the listed values. Other values ​​not listed within the numerical range are also applicable.

[0035] Preferably, the method for preparing the aluminum nitride deposition layer in step (2) comprises plasma enhanced atomic layer deposition.

[0036] Preferably, the method for preparing the aluminum nitride deposition layer in step (2) comprises plasma enhanced atomic layer deposition.

[0037] Preferably, trimethylamine (TMA) and / or ammonia are used as precursors in the plasma enhanced atomic layer deposition process.

[0038] Preferably, the pulse time of the TMA is 40 ms to 50 ms, for example, 40 ms, 42 ms, 45 ms, 48 ​​ms or 50 ms, etc., and is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0039] Preferably, the pulse time of the ammonia gas is 8000 ms to 10000 ms, for example, 8000 ms, 8500 ms, 9000 ms, 9500 ms or 10000 ms, etc., and is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0040] Preferably, the oxidation modification treatment method in step (2) comprises oxygen plasma treatment.

[0041] Preferably, the oxygen plasma treatment time is 3s to 5s, for example, 3s, 3.5s, 4s, 4.5s or 5s, etc., and is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0042] Preferably, the method for removing excess surface oxidation-modified aluminum nitride deposition layer in step (2) comprises inductively coupled plasma etching.

[0043] Preferably, silicon nitride is used as a mask during the inductively coupled plasma etching process.

[0044] Preferably, the etching gas for removing the excess surface oxidation-modified aluminum nitride deposited layer in step (2) comprises Cl2 and / or BCl3.

[0045] Preferably, the method of depositing the gate in step (3) comprises electron beam evaporation deposition.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] The semiconductor device of the present invention can not only maintain a relatively high on-state current, but also enhance the threshold voltage performance of the device, and successfully improve the threshold voltage at zero bias without sacrificing the on-state current. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention, wherein 1 is a substrate, 2 is a barrier layer, 3 is a gallium nitride layer, 4 is a cap layer, 5 is a source electrode, 6 is a drain electrode, 7 is a surface oxidation-modified aluminum nitride deposition layer, and 8 is a gate electrode.

[0049] Figure 2 It is a schematic diagram of the preparation process of the semiconductor device provided by an embodiment of the present invention, wherein 1 is a substrate, 2 is a barrier layer, 3 is a gallium nitride layer, 4 is a cap layer, 5 is a source electrode, 6 is a drain electrode, 7 is a surface oxidation-modified aluminum nitride deposition layer, 8 is a gate electrode, 9 is a fully covered aluminum nitride deposition layer, and 10 is a fully covered surface oxidation-modified aluminum nitride deposition layer. DETAILED DESCRIPTION

[0050] The technical solution of the present invention is further described below by specific implementation methods. It should be understood by those skilled in the art that the embodiments are only to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0051] Example 1

[0052] This embodiment provides a semiconductor device. The structure diagram of the semiconductor device is as follows: Figure 1 As shown:

[0053] The semiconductor device comprises a substrate 1, a barrier layer 2, a P-type gallium nitride layer 3, a cap layer 4, an etched groove, and a source electrode 5 and a drain electrode 6 arranged at both ends of the cap layer 4, the etched groove penetrates the cap layer 4 and is etched to the 7 / 8 plane of the P-type gallium nitride layer, a surface oxidation-modified aluminum nitride deposition layer 7 is arranged at the bottom of the etched groove, and a gate electrode 8 is arranged on the surface oxidation-modified aluminum nitride deposition layer 7;

[0054] The substrate 1 is a silicon substrate with a thickness of 1 mm, the barrier layer 2 includes gallium nitride and aluminum gallium nitride, the thickness of the barrier layer 2 is 24 nm, the thickness of the P-type gallium nitride layer 3 is 65 nm, and the cap layer 4 is a P-type aluminum gallium nitride layer with a thickness of 15 nm. ++ type gallium nitride layer, the source 5 and the drain 6 are composite laminated electrodes of titanium / aluminum / nickel / titanium nitride, the gate 8 is a composite laminated electrode of titanium / titanium nitride, the thickness of the surface oxidation-modified aluminum nitride deposited layer is 20nm, wherein the thickness of the aluminum oxide nitride layer on the surface of the surface oxidation-modified aluminum nitride deposited layer is 17nm.

[0055] The schematic diagram of the preparation process of the semiconductor device is as follows Figure 2 As shown, the method for preparing the semiconductor device is as follows:

[0056] (1) A barrier layer 2, a P-type gallium nitride layer 3 and a cap layer 4 are sequentially prepared on a substrate 1, and Cl2 is used as an etching gas to etch the P-type gallium nitride layer 3 and the cap layer 4 by an inductively coupled plasma etching method to form an etching groove. The etching power is 210 W. After a source electrode 5 and a drain electrode 6 are deposited at both ends of the cap layer 4 by electron beam evaporation, an annealing treatment is performed at 520° C. for 6 min to obtain a semi-finished device;

[0057] (2) After preparing a fully covered aluminum nitride deposition layer 9 on the surface of the semi-finished device by plasma enhanced atomic layer deposition, the aluminum nitride deposition layer is subjected to oxidation modification treatment to obtain a fully covered surface oxidation-modified aluminum nitride deposition layer 10, and Cl2 is used as an etching gas to remove excess surface oxidation-modified aluminum nitride by an inductively coupled plasma etching method to obtain a surface oxidation-modified aluminum nitride deposition layer 7;

[0058] (3) A gate electrode 8 is deposited on the surface oxidation-modified aluminum nitride deposition layer 7 to obtain the semiconductor device.

[0059] Example 2

[0060] This embodiment provides a semiconductor device. The structure diagram of the semiconductor device is as follows: Figure 1 As shown:

[0061] The semiconductor device comprises a substrate 1, a barrier layer 2, a P-type gallium nitride layer 3, a cap layer 4, an etched groove, and a source electrode 5 and a drain electrode 6 arranged at both ends of the cap layer 4, the etched groove penetrates the cap layer 4 and is etched to the 7 / 8 plane of the P-type gallium nitride layer, a surface oxidation-modified aluminum nitride deposition layer 7 is arranged at the bottom of the etched groove, and a gate electrode 8 is arranged on the surface oxidation-modified aluminum nitride deposition layer 7;

[0062] The substrate 1 is a silicon carbide substrate with a thickness of 1 mm, the barrier layer 2 includes gallium nitride and aluminum gallium nitride, the thickness of the barrier layer 2 is 20 nm, the thickness of the P-type gallium nitride layer 3 is 65 nm, and the cap layer 4 is a P-type gallium nitride with a thickness of 10 nm. ++ type gallium nitride layer, the source 5 and the drain 6 are composite laminated electrodes of titanium / aluminum / nickel / titanium nitride, the gate 8 is a composite laminated electrode of titanium / titanium nitride, the thickness of the surface oxidation-modified aluminum nitride deposited layer is 20nm, wherein the thickness of the aluminum oxide nitride layer on the surface of the surface oxidation-modified aluminum nitride deposited layer is 19nm.

[0063] The schematic diagram of the preparation process of the semiconductor device is as follows Figure 2 As shown, the method for preparing the semiconductor device is as follows:

[0064] (1) A barrier layer 2, a P-type gallium nitride layer 3 and a cap layer 4 are sequentially prepared on a substrate 1, and Cl2 is used as an etching gas to etch the P-type gallium nitride layer 3 and the cap layer 4 by an inductively coupled plasma etching method to form an etching groove. The etching power is 190 W. After a source electrode 5 and a drain electrode 6 are deposited at both ends of the cap layer 4 by electron beam evaporation, an annealing treatment is performed at 500° C. for 4 min to obtain a semi-finished device;

[0065] (2) After preparing a fully covered aluminum nitride deposition layer 9 on the surface of the semi-finished device by plasma enhanced atomic layer deposition, the aluminum nitride deposition layer is subjected to oxidation modification treatment to obtain a fully covered surface oxidation-modified aluminum nitride deposition layer 10, and BCl3 is used as an etching gas to remove excess surface oxidation-modified aluminum nitride by an inductively coupled plasma etching method to obtain a surface oxidation-modified aluminum nitride deposition layer 7;

[0066] (3) A gate electrode 8 is deposited on the surface oxidation-modified aluminum nitride deposition layer 7 to obtain the semiconductor device.

[0067] Example 3

[0068] This embodiment provides a semiconductor device. The structure diagram of the semiconductor device is as follows: Figure 1 As shown:

[0069] The semiconductor device comprises a substrate 1, a barrier layer 2, a P-type gallium nitride layer 3, a cap layer 4, an etched groove, and a source electrode 5 and a drain electrode 6 arranged at both ends of the cap layer 4, the etched groove penetrates the cap layer 4 and is etched to the 7 / 8 plane of the P-type gallium nitride layer, a surface oxidation-modified aluminum nitride deposition layer 7 is arranged at the bottom of the etched groove, and a gate electrode 8 is arranged on the surface oxidation-modified aluminum nitride deposition layer 7;

[0070] The substrate 1 is a germanium substrate with a thickness of 1 mm, the barrier layer 2 includes gallium nitride and aluminum gallium nitride, the thickness of the barrier layer 2 is 25 nm, the thickness of the P-type gallium nitride layer 3 is 70 nm, and the cap layer 4 is a P-type gallium nitride layer with a thickness of 15 nm. ++ type gallium nitride layer, the materials of the source 5 and the drain 6 are gold, the gate 8 is a titanium / titanium nitride composite laminate electrode, the thickness of the surface oxidation-modified aluminum nitride deposited layer is 20nm, wherein the thickness of the aluminum oxide nitride layer on the surface of the surface oxidation-modified aluminum nitride deposited layer is 16nm.

[0071] The schematic diagram of the preparation process of the semiconductor device is as follows Figure 2 As shown, the method for preparing the semiconductor device is as follows:

[0072] (1) A barrier layer 2, a P-type gallium nitride layer 3 and a cap layer 4 are sequentially prepared on a substrate 1, and Cl2 is used as an etching gas to etch the P-type gallium nitride layer 3 and the cap layer 4 by an inductively coupled plasma etching method to form an etching groove. The etching power is 230 W. After a source electrode 5 and a drain electrode 6 are deposited at both ends of the cap layer 4 by electron beam evaporation, an annealing treatment is performed at 530° C. for 8 min to obtain a semi-finished device;

[0073] (2) After preparing a fully covered aluminum nitride deposition layer 9 on the surface of the semi-finished device by plasma enhanced atomic layer deposition, the aluminum nitride deposition layer is subjected to oxidation modification treatment to obtain a fully covered surface oxidation-modified aluminum nitride deposition layer 10, and SF6 is used as an etching gas to remove excess surface oxidation-modified aluminum nitride by an inductively coupled plasma etching method to obtain a surface oxidation-modified aluminum nitride deposition layer 7;

[0074] (3) A gate electrode 8 is deposited on the surface oxidation-modified aluminum nitride deposition layer 7 to obtain the semiconductor device.

[0075] Comparative Example 1

[0076] The only difference between this comparative example and Example 1 is that the surface oxidation-modified aluminum nitride deposition layer is not provided, and the other conditions and parameters are exactly the same as those in Example 1.

[0077] Comparative Example 2

[0078] The only difference between this comparative example and Example 1 is that the aluminum nitride deposited layer is not subjected to oxidation modification, and other conditions and parameters are exactly the same as those in Example 1.

[0079] By comparing Examples 1-3 and Comparative Examples 1-2, it can be seen that the present invention can ensure high on-state current and significantly improve the threshold voltage of the p-channel gallium nitride device by introducing an aluminum nitride layer after in-situ oxygen treatment under the gate. Most of the aluminum nitride in the upper layer is oxidized into aluminum nitride oxide, which can withstand a larger gate voltage, thereby fully opening the channel; the unoxidized aluminum nitride layer in the lower layer introduces fixed positive charges at the interface to enhance the depletion of the channel, which is crucial for achieving p-channel gallium nitride devices with high threshold voltage and high saturation current.

[0080] The applicant declares that the above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention shall fall within the protection scope and disclosure scope of the present invention.

Claims

1. A semiconductor device, characterized in that: The semiconductor device includes a substrate, a barrier layer, a P-type gallium nitride layer, a cap layer, an etched groove, and a source and a drain arranged on the cap layer away from both sides of the etched groove, which are stacked in sequence. The etched groove penetrates the cap layer and etches a portion of the P-type gallium nitride layer. A surface oxidation-modified aluminum nitride deposition layer is arranged at the bottom of the etched groove, and a gate is arranged on the surface oxidation-modified aluminum nitride deposition layer.

2. The semiconductor device according to claim 1, wherein The material of the substrate includes any one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium or silicon, or a combination of at least two thereof; Preferably, the thickness of the substrate is 1 mm to 1.5 mm; Preferably, the material of the barrier layer includes gallium nitride and / or gallium aluminum nitride; Preferably, the barrier layer has a thickness of 20 nm to 25 nm; Preferably, the thickness of the P-type gallium nitride layer is 65nm to 70nm; Preferably, the cap layer comprises P ++ Type gallium nitride layer; Preferably, the thickness of the cap layer is 10nm to 15nm; Preferably, the source and drain materials independently include any one of nickel, titanium, aluminum, gold or titanium nitride or a combination of at least two thereof; Preferably, the material of the gate includes titanium and / or titanium nitride; Preferably, the thickness of the partial P-type gallium nitride layer is 3 / 4 to 9 / 10 of the thickness of the P-type gallium nitride layer.

3. The semiconductor device according to claim 1 or 2, characterized in that The surface oxidation-modified aluminum nitride deposition layer comprises an aluminum nitride layer and an aluminum oxide nitride layer disposed on the surface of the aluminum nitride layer; Preferably, the thickness of the surface oxidation-modified aluminum nitride deposition layer is 16 nm to 20 nm; Preferably, based on the thickness of the surface oxidation-modified aluminum nitride deposition layer being 100%, the thickness of the aluminum oxide nitride layer is 80% to 95%.

4. A method for preparing a semiconductor device according to any one of claims 1 to 3, characterized in that: The preparation method comprises the following steps: (1) sequentially preparing a barrier layer, a first P-type gallium nitride layer, a second P-type gallium nitride layer and a cap layer on a substrate, etching the second P-type gallium nitride layer and the cap layer to form an etched groove, depositing a source electrode and a drain electrode on both sides of the cap layer away from the etched groove, and then annealing to obtain a semi-finished device; (2) after preparing an aluminum nitride deposition layer on the surface of the semi-finished device, performing an oxidation modification treatment on the aluminum nitride deposition layer to obtain a surface oxidation-modified aluminum nitride deposition layer, and removing the surface oxidation-modified aluminum nitride deposition layer from other parts except the bottom of the etched groove; (3) Depositing a gate on the surface oxidation-modified aluminum nitride deposition layer to obtain the semiconductor device.

5. The preparation method according to claim 4, characterized in that: The etching method in step (1) includes inductively coupled plasma etching; Preferably, the etching gas used in the etching process in step (1) includes Cl2 and / or BCl3; Preferably, the etching power of the etching process in step (1) is 190W to 230W.

6. The preparation method according to claim 4 or 5, characterized in that: The method of depositing the source and drain electrodes in step (1) comprises electron beam evaporation deposition; Preferably, the annealing temperature is 500°C to 550°C; Preferably, the annealing treatment time is 4 min to 7 min.

7. The preparation method according to any one of claims 4 to 6, characterized in that: The method for preparing the aluminum nitride deposition layer in step (2) includes plasma enhanced atomic layer deposition; Preferably, TMA and / or ammonia are used as precursors in the plasma enhanced atomic layer deposition process; Preferably, the pulse time of the TMA is 40ms to 50ms; Preferably, the pulse time of the ammonia gas is 8000 ms to 10000 ms.

8. The preparation method according to any one of claims 4 to 7, characterized in that: The oxidation modification treatment method in step (2) includes oxygen plasma treatment; Preferably, the oxygen plasma treatment time is 3s to 5s.

9. The preparation method according to any one of claims 4 to 8, characterized in that: The method for removing the excess surface oxidation-modified aluminum nitride deposition layer in step (2) comprises inductively coupled plasma etching; Preferably, silicon nitride is used as a mask during the inductively coupled plasma etching process; Preferably, the etching gas for removing excess surface oxidation-modified aluminum nitride deposition layer comprises Cl2 and / or BCl3.

10. The preparation method according to any one of claims 4 to 9, characterized in that: The method for depositing the gate in step (3) includes electron beam evaporation deposition.

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