Power semiconductor device including SiC semiconductor body

Abstract

A power semiconductor device including a SiC semiconductor body is disclosed. A power semiconductor device (100) is presented. A power semiconductor device (100) includes a silicon carbide (SiC) semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite the first surface (1031). The SiC semiconductor body (102) includes a transistor cell region (104), and the transistor cell region (104) includes transistor cells (1041). Each transistor cell (1041) includes a gate structure (106) including a gate dielectric structure (108) and a gate electrode structure (110) on the gate dielectric structure (108). The gate dielectric structure (108) includes a first gate dielectric layer (1081) adjacent to the SiC semiconductor body (102). The gate dielectric structure (108) further includes a second gate dielectric layer (1082). The gate dielectric structure (108) further includes a charge storage layer (1085) disposed between the first gate dielectric layer (1081) and the second gate dielectric layer (1082).

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device, and in particular to a power semiconductor device including a SiC semiconductor body. Background Art

[0002] The technical development of new generation SiC power semiconductor devices, such as insulated gate field effect transistors (IGFETs) such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) aims to improve electrical device characteristics such as short circuit current capability. In improving the short circuit current capability of SiC power semiconductor devices, various trade-offs and challenges must be met. For example, improving short circuit current capability (e.g., by reducing the saturation current through a lower overdrive voltage, and / or through a higher threshold voltage Vth, and / or through a lower gate voltage, and / or through a longer MOS channel) may have a negative impact on overall device performance or may increase circuit complexity.

[0003] There is a need for improving the short circuit current capability of SiC power semiconductor devices. Summary of the invention

[0004] An example of the present disclosure relates to a power semiconductor device. The power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell region, and the transistor cell region includes a transistor cell. Each transistor cell includes a gate structure, and the gate structure includes a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure includes: a first gate dielectric layer adjacent to the SiC semiconductor body; a second gate dielectric layer; and a charge storage layer arranged between the first gate dielectric layer and the second gate dielectric layer.

[0005] Another example of the present disclosure relates to a method for manufacturing a power semiconductor device. The method includes providing a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The method further includes forming a transistor cell region including a transistor cell in the SiC semiconductor body. Each transistor cell includes a gate structure, the gate structure including a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure includes: a first gate dielectric layer adjacent to the SiC semiconductor body; a second gate dielectric layer; and a charge storage layer arranged between the first gate dielectric layer and the second gate dielectric layer.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of SiC power semiconductor devices and together with the description serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims.

[0008] Figure 1A A partial cross-sectional view schematically and exemplarily shows a configuration example of a SiC power semiconductor device including a planar gate structure.

[0009] Figure 1B A partial cross-sectional view schematically and exemplarily shows a configuration example of a SiC power semiconductor device including a trench gate structure.

[0010] Figure 2 A partial cross-sectional view schematically and exemplarily shows a configuration example of a SiC power MOSFET including a trench gate structure.

[0011] FIG. 3A to FIG. 3C is a schematic view for illustrating an operation mode of a configuration example of a power MOSFET.

[0012] FIG. 4A to FIG. 7 is a schematic band diagram for illustrating an operation mode of a configuration example of a power MOSFET. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which specific examples in which semiconductor substrates can be processed are shown by way of illustration. It is to be understood that other examples can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example can be used on other examples or used in combination with other examples to produce yet another further example. The present disclosure is intended to include such modifications and variations. Examples are described using specific language that should not be interpreted as limiting the scope of the attached claims. The drawings are not to scale and are for illustrative purposes only. If not otherwise stated, corresponding elements are indicated by the same reference numerals in different drawings.

[0014] The terms "having", "comprising", "including", and "comprising" are open ended, and the terms indicate the presence of stated structures, elements, or features, but do not exclude the presence of additional elements or features. Unless the context clearly indicates otherwise, the quantifiers "a", "an", and the pronoun "the" are intended to include the plural as well as the singular.

[0015] The term "electrically connected" may describe a permanent low resistance connection between electrically connected elements, such as direct contact between the associated elements, or a low resistance connection via metal and / or heavily doped semiconductor materials. The term "electrically coupled" may include that one or more (multiple) intermediate elements adapted for signal and / or power transmission may be connected between electrically coupled elements, the electrically coupled elements being, for example, controllable to temporarily provide a low resistance connection in a first state and temporarily provide a high resistance electrical decoupling in a second state.

[0016] If "or" is used to combine two elements A and B, this can be understood as disclosing all possible combinations, i.e. only A, only B and A and B, unless otherwise explicitly or implicitly limited. Alternative expressions for the same combination may be "at least one of A and B" or "A and / or B". The same applies to combinations of more than two elements, mutatis mutandis.

[0017] Ranges given for physical dimensions may include boundary values. For example, a range from a to b for parameter y is read as a≤y≤b. The same applies to ranges with a boundary value, such as "at most" and "at least".

[0018] The main components of a layer or structure from a chemical composition or alloy may be elements whose atoms form the chemical composition or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0019] The term “on” should not be interpreted as meaning only “directly on.” On the contrary, if an element is positioned “on” another element (e.g., a layer is “on” another layer or is “on” a substrate), further components (e.g., further layers) may be positioned between the two elements (e.g., if a layer is “on” a substrate, the further layer may be positioned between the layer and the substrate).

[0020] An example of a power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body may include a transistor cell region, the transistor cell region including a transistor cell. Each transistor cell may include a gate structure, the gate structure including a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure may include a first gate dielectric layer adjacent to the SiC semiconductor body. The gate dielectric structure may further include a second gate dielectric layer. The gate dielectric structure may further include a charge storage layer arranged between the first gate dielectric layer and the second gate dielectric layer.

[0021] For example, the power semiconductor device may be part of an integrated circuit, or may be a discrete semiconductor device or a semiconductor module. For example, the power semiconductor device may be or may include an insulated gate field effect transistor (IGFET) or an insulated gate bipolar transistor (IGBT) such as a metal oxide semiconductor field effect transistor (MOSFET). The power semiconductor device may be a vertical power semiconductor device having a load current flowing between a first surface and a second surface opposite to the first surface. The vertical power semiconductor device may be configured to conduct a current greater than 1A, or greater than 10A, or greater than 30A, or greater than 50A, or greater than 75A, or even greater than 100A, and may be further configured to block a voltage in the range of several hundred volts to several thousand volts between load electrodes (e.g., between the collector and emitter on an IGBT or between the drain and source of a MOSFET), such as 400V, 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV, 10kV. For example, the blocking voltage may correspond to a voltage level specified in a data sheet of the power semiconductor device.

[0022] The power semiconductor device may be based on a semiconductor body from a crystalline SiC semiconductor material having a band gap greater than the band gap of silicon, i.e. greater than 1.12 eV. For example, the semiconductor material may be 2H-SiC (2H polytype SiC), 6H-SiC or 15R-SiC. According to an example, the semiconductor material is 4H polytype silicon carbide (4H-SiC). The semiconductor body may include or consist of a semiconductor substrate having no semiconductor layer, one semiconductor layer or more than one semiconductor layer on the semiconductor substrate, the semiconductor layer being, for example, an epitaxially grown layer.

[0023] For example, the first surface may be a front surface or top surface of the semiconductor body, and the second surface may be a back surface or rear surface of the semiconductor body. For example, the semiconductor body may be attached to a lead frame via the second surface. For example, above the first surface of the semiconductor body, a bonding pad may be arranged and a bonding wire may be bonded to the bonding pad.

[0024] In order to achieve the desired current carrying capacity, a SiC power semiconductor device can be designed by a plurality of transistor units connected in parallel. The transistor units connected in parallel can be, for example, transistor units formed in the shape of strips or strip segments. Of course, the transistor unit can also have any other shape, such as a circle, an ellipse, a polygon such as a hexagon or an octahedron. The transistor unit is arranged in a transistor unit region of a SiC semiconductor body. The transistor unit region can be an active region, in which the emitter region of an IGBT (or the source region of a MOSFET) and the collector region of an IGBT (or the drain region of a MOSFET) are arranged relative to each other in a vertical direction. In the active region, the load current can enter or leave the semiconductor body of the power semiconductor device, for example, via a contact plug on the first surface of the SiC semiconductor body. The power semiconductor device may further include an edge termination region, which may include a termination structure. In the blocking mode or reverse bias mode of the power semiconductor device, the blocking voltage between the transistor unit region and the field-free region drops laterally across the termination structure. The termination structure may have a voltage blocking capability that is higher or slightly lower than the transistor unit region. For example, the termination structure may include a junction termination extension (JTE) with or without lateral doping variation (VLD), one or more laterally separated guard rings, or any combination thereof.

[0025] For example, the gate structure may be a planar gate structure, or may be a trench gate structure. The gate structure may be strip-shaped. The gate electrode structure may also have another layout or geometry in a plan view, such as a hexagon, a square, a circle, an ellipse. For example, the gate electrode structure of the gate structure may be electrically connected to the gate pad via a gate interconnect structure. The gate interconnect structure or a portion thereof may be arranged outside the transistor cell region, and may be arranged laterally between the transistor cell region and the edge termination region. The interconnect electrode may include one or more (multiple) conductive materials, such as metals, metal alloys (e.g., Cu, Au, AlCu, Ag, or their alloys); metal compositions (e.g., TiN); highly doped semiconductor materials (such as highly doped polysilicon). For example, one or more conductive materials may form a layer stack. At least a portion of the interconnect electrode may be a so-called gate runner merged with the gate pad. The gate pad and, for example, the first load electrode pad (e.g., the source pad of a MOSFET or the emitter pad of an IGBT) may be part of the wiring region above the wide bandgap semiconductor body. The wiring area may include one or more than one (e.g., two, three, four or even more) wiring levels. Each wiring level may be formed by a single conductive layer or a stack of conductive layers (e.g., (multiple) metal layers). For example, the wiring levels may be lithographically patterned. An interlayer dielectric structure may be arranged between the stacked wiring levels. (Multiple) contact plugs and / or (multiple) contact lines may be formed in the openings of the interlayer dielectric structure to electrically connect the parts of the different wiring levels (e.g., metal lines or contact areas) to each other.

[0026] By providing a charge storage layer in the gate dielectric structure, an intermediate insulating layer can be integrated into the gate dielectric structure, that is, between the first gate dielectric layer and the second gate dielectric layer. The charge storage layer (e.g., an intermediate layer) can be configured to capture charge depending on the operating state of the power semiconductor device. For example, in the normal operating state or mode of the power semiconductor device, the intermediate layer may be uncharged. In the case of a short-circuit current event, charges (e.g., electrons) can be injected into the intermediate layer from the channel region of the power semiconductor device and form a charge QOX on the intermediate layer. The charging process may be caused, for example, by a temperature increase within the power semiconductor device. For example, the temperature increase may be due to a short-circuit current event. In the case of an n-channel power semiconductor device, this may increase the negative electron charge on the intermediate layer and thus increase the threshold voltage of the power semiconductor device. Therefore, this may lead to a reduction in the so-called overdrive voltage. The saturation current and therefore the heat load in the case of a short circuit can be similarly reduced. When the power semiconductor device is properly designed, a complete shutdown of the power semiconductor device can be achieved. The technical effects and benefits associated with the configuration examples of the power semiconductor device disclosed herein include, among others, one or more of the following:

[0027] - Self-triggered shutdown or turn-off of the short circuit can allow significant thermal loading of the power semiconductor device to be avoided without affecting the device parameters. This can also allow the use of gate materials that are sensitive to elevated temperatures (e.g. high-k dielectric materials);

[0028] - The optimization of the short-circuit strength or short-circuit current capability of a power semiconductor device can be performed independently of the optimization of other important electrical characteristics (e.g. channel density, JFET, dual gate);

[0029] - No further circuitry may be required to monitor, detect and disconnect short circuits. This can reduce the complexity of the overall system and primarily shift the added value of these functions to the power semiconductor devices;

[0030] After the power semiconductor device has shut itself down by self-triggering and the cause of the short circuit in the overall system has been eliminated, the threshold voltage can be restored to or close to its initial state, for example by selectively applying a negative gate voltage.

[0031] For example, the conduction band offset at the first interface between the SiC semiconductor body and the first dielectric layer may have a value in the range of from 1.0 eV to 2.0 eV or from 1.5 eV to 2.0 eV. This may be achieved by using an appropriate material for the first dielectric layer. The conduction band offset in the range of from 1.0 eV to 2.0 eV or from 1.5 eV to 2.0 eV may allow charge to be accumulated in the charge storage layer based on thermal electron emission described by Richardson's law, which allows the power semiconductor device to be turned off within an appropriate time period based on a deviation in the threshold voltage due to the charging process.

[0032] For example, the gate dielectric structure may further include a third gate dielectric layer arranged between the second gate dielectric layer and the gate electrode. The third gate dielectric layer may be adjacent to the gate electrode. The provision of the third gate dielectric layer may allow the second gate dielectric layer to be optimized with respect to charge trapping in the charge storage layer by, for example, appropriately setting the band offset between the charge storage layer and the second dielectric layer on the one hand, and optimizing the third gate dielectric layer with respect to contact with the termination of the gate dielectric structure towards the gate electrode structure on the other hand.

[0033] For example, the third gate dielectric layer may be a high-k dielectric layer. For example, the high-k dielectric material in the third gate dielectric layer or any other high-k dielectric layer of the gate dielectric structure may include at least one of: Al2O3, ZrO2, HfO2, AlN, aluminosilicate AlSiOx, silicon-doped HfO2, lanthanum-doped HfO2, TiO2, Y2O3 or Si3N4, ONO (oxide-nitride-oxide), or any stacked combination thereof.

[0034] For example, the second gate dielectric layer may be adjacent to the gate electrode.This may allow providing a gate dielectric structure comprising a charge storage layer for self-triggered turn-off, which can be easily manufactured by comprising a minimum of dielectric sub-layers.

[0035] For example, the charge storage layer may include a potential well for electrons. The conduction band offset at the second interface between the charge storage layer and the first gate dielectric layer may be smaller than the conduction band offset at the third interface between the charge storage layer and the second gate dielectric layer. This may allow for avoiding the transfer of trapped charges (e.g., electrons) from the charge storage layer to the gate electrode structure.

[0036] For example, the difference between the conduction band offset at the third interface and the conduction band offset at the second interface may have a value in the range from 0.5 eV to 3 eV.

[0037] For example, the conduction band offset at the second interface may have a value in the range from 0.5 eV to 1.5 eV.

[0038] For example, the charge storage layer may be a Hf2O3 layer. The first gate dielectric layer may be an Al2O3 layer. The second gate dielectric layer may be a SiO2 layer. Thus, a potential well for electrons may be achieved, which has a larger band offset towards the gate electrode structure than towards the SiC semiconductor body. This may allow avoiding the transfer of trapped charges (e.g., electrons) from the charge storage layer to the gate electrode structure.

[0039] For example, the charge storage layer may be an interface layer including interface trapping states at an interface between the first gate dielectric layer and the second gate dielectric layer. For example, a surface treatment of the first gate dielectric layer before forming (e.g., depositing) the second gate dielectric layer on the treated surface may allow for setting an interface trapping density. A surface treatment of the first gate dielectric layer before forming (e.g., depositing) the second gate dielectric layer on the treated surface may allow for reducing the trapping density at an interface between the first gate dielectric layer and the SiC semiconductor. After the first gate dielectric layer is annealed, the second dielectric layer is deposited. For example, the materials of the first gate dielectric layer and the second gate dielectric layer may correspond to each other.

[0040] For example, the charge storage layer may be a transition gate dielectric layer having a material composition that changes from a material composition of a first gate dielectric layer to a material composition of a second gate dielectric layer along the thickness direction of the gate dielectric structure. According to a configuration example, the transition gate dielectric layer may transition from a material composition of Al2O3 (the first gate dielectric layer) to a material composition of SiO2 (the second gate dielectric layer). According to another configuration example, the transition gate dielectric layer may transition from a material composition of Al2O3 (the first gate dielectric layer) to a material composition of SiO2 (the second gate dielectric layer). x SiO y The material composition of the transition gate dielectric layer may be changed from AlN (the first gate dielectric layer) to Al2O3 (the second gate dielectric layer). According to another configuration example, the transition gate dielectric layer may be changed from HfO2 (the first gate dielectric layer) to SiO2 (the second gate dielectric layer). According to another configuration example, the transition gate dielectric layer may be changed from AlN (the first gate dielectric layer) to Al2O3 (the second gate dielectric layer). According to another configuration example, the transition gate dielectric layer may be changed from HfO2 (the first gate dielectric layer) to SiO2 (the second gate dielectric layer).

[0041] For example, the thickness of the transition gate dielectric layer may have a value in the range from 0.1 nm to 3 nm.

[0042] For example, the transition gate dielectric layer may include a 11 cm -3 to 10 13 cm -3 For example, the impurity may be configured as an acceptor-like state within the dielectric bandgap.

[0043] For example, the thickness of the first gate dielectric has a value in the range from 3 nm to 20 nm. When the thickness of the first gate dielectric is reduced below the lower limit, undesired direct tunneling of electrons from the channel into the charge electrode layer becomes more likely. When the thickness of the first gate dielectric is increased above the upper limit, the effect on deviating the threshold voltage Vth may be too low.

[0044] For example, the power semiconductor device may be an n-channel vertical power MOSFET (or IGBT) including a gate trench including a gate structure.

[0045] For example, a vertical power MOSFET may include a p-doped diode region adjacent to one of the first and second sidewalls of the gate trench. The p-doped diode region may also be adjacent to the bottom side of the gate trench. For example, the p-doped diode region may be configured to shield the gate dielectric structure at the bottom side of the gate trench from high electric field strength. A sidewall adjacent to the p-doped diode region may define a non-channel region of the vertical power MOSFET. The other sidewall of the gate trench may define a channel region formed by a portion of the p-doped body region adjacent to the gate structure at the other sidewall of the gate trench. For example, the conductivity of the channel region may be controlled by a potential applied to the gate electrode structure, such as by a field effect. For example, a positive voltage applied to the gate electrode structure in an n-channel MOSFET may, for example, induce an n inversion channel in a portion of the p-doped body region adjacent to the first gate dielectric layer. The body region may be electrically connected via a first surface, such as by a contact plug and / or a groove contact on the top surface of the body region, and the groove contact may extend into the SiC semiconductor body and may be electrically connected to the body region via the sidewall of the groove contact. For example, the channel region portion of the body region may include partial compensation with a dopant of a second conductivity type (e.g., an n-type dopant in the case of a p-doped body region) for adjusting the threshold voltage. For example, partial compensation can be achieved by oblique ion implantation through the sidewalls of the trench. For example, the sidewalls of the gate trench may be non-tapered or slightly tapered. In the case of slightly tapered sidewalls of the gate trench, the channel length may be slightly greater than the vertical extension of the channel region. The taper angle of the trench gate structure may be caused by the processing technology (e.g., the aspect ratio of the trench etching process) and may also be used to maximize the charge carrier mobility in the channel region, depending on the direction along which the channel current flows. Another example for a tapered trench gate structure is a V-shaped gate trench.

[0046] An example of a method for operating a power semiconductor device of any configuration example described herein includes resetting a charge storage layer of the power semiconductor device at least in part by applying a negative gate-to-source voltage pulse.

[0047] Details of the structure or function or technical benefits of the features described above with respect to power semiconductor devices such as FETs or IGBTs are equally applicable to the exemplary methods described herein. Processing a SiC semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned with respect to the proposed concept or one or more examples described above or below.

[0048] The description and drawings illustrate only the principles of the present disclosure. Furthermore, all examples described herein are primarily and explicitly intended to be used for illustrative purposes only, to help the reader understand the principles of the present disclosure and the concepts contributed by the inventors to advance the art. All statements describing the principles, aspects and examples of the present disclosure and specific examples thereof are intended to encompass their equivalents.

[0049] It is to be understood that the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims may not be interpreted as being in a specific order, unless otherwise explicitly or implicitly stated, such as for technical reasons and for example explained by a statement such as "after". Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a specific order, unless such actions or functions are not interchangeable for technical reasons. Further, in some examples, a single action, function, process, operation or step may include or may be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations or sub-steps, respectively. Unless explicitly excluded, such sub-actions may be included and be part of the disclosure of the single action.

[0050] The method for manufacturing a power semiconductor device includes providing a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The method further includes forming a transistor cell region including a transistor cell in the SiC semiconductor body. Each transistor cell includes a gate structure, the gate structure including a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure may include a first gate dielectric layer adjacent to the SiC semiconductor body. The gate dielectric structure may further include a second gate dielectric layer. The gate dielectric structure may further include a charge storage layer arranged between the first gate dielectric layer and the second gate dielectric layer.

[0051] The examples and features described above and below may be combined.

[0052] Some of the examples above and below are described in relation to silicon carbide substrates. Alternatively, a wide bandgap semiconductor substrate, such as a wide bandgap wafer, may be processed, which, for example, includes a wide bandgap semiconductor material different from silicon carbide. The wide bandgap semiconductor wafer may have a bandgap larger than the bandgap of silicon (1.12 eV). For example, the wide bandgap semiconductor wafer may be a silicon carbide (SiC) wafer, or a gallium arsenide (GaAs) wafer, or a gallium nitride (GaN) wafer.

[0053] Further details and aspects are mentioned in relation to the examples described above or below.Processing a SiC semiconductor wafer may include one or more optional additional features corresponding to one or more aspects mentioned in relation to the proposed concept or one or more examples described above or below.

[0054] The description and drawings illustrate only the principles of the present disclosure. In addition, all examples described herein are primarily intended to be used only for illustration, to help the reader understand the principles of the present disclosure and the conception of the contributions made by the inventors to advance the art. All statements of the principles, aspects and examples of the present disclosure described herein, and specific examples thereof, are intended to encompass their equivalents.

[0055] In the following, further examples of field effect transistors FET are explained in relation to the accompanying drawings. The functional and structural details described with respect to the above examples will also apply to the exemplary embodiments further described below and illustrated in the figures. In the illustrated examples, n-channel FETs are illustrated. However, the examples described herein can also be applied to p-channel devices, such as p-channel MOSFETs or p-channel IGBTs.

[0056] Details regarding the structure or functionality or technical benefits of the features described above are equally applicable to the following examples and vice versa.

[0057] Figure 1A A partial cross-sectional view of a power semiconductor device 100 configured as a planar gate SiC power MOSFET is schematically and exemplarily shown.

[0058] Figure 1A 1 illustrates a portion of a transistor cell 1041 in a SiC semiconductor body 102 having a first surface 1031 and a second surface 1032 opposite to the first surface 1031. The SiC power MOSFET includes a gate structure 106 configured as a planar gate structure. The gate structure 106 includes a gate dielectric structure 108. A gate electrode structure 110 of the gate structure 106 is arranged on the gate dielectric structure 108. A first gate dielectric layer 1081 of the gate dielectric structure 108 adjoins the SiC semiconductor body 102 at a first interface 1221. A charge storage layer 1085 is arranged on and adjoins the first gate dielectric layer 1081. A second gate dielectric layer 1082 is arranged on and adjoins the charge storage layer 1085.

[0059] Figure 1B A partial cross-sectional view of a power semiconductor device 100 configured as a trench gate SiC power MOSFET is schematically and exemplarily shown.

[0060] Figure 1BThe partial cross-sectional view of FIG. 1 illustrates a portion of a transistor cell 1041 in a SiC semiconductor body 102. The SiC power MOSFET includes a gate structure 106 configured as a trench gate structure in a gate trench 124. The gate structure 106 is as described above with reference to FIG. Figure 1A Configure as described.

[0061] Figure 2 Schematically and exemplarily, a partial cross-sectional view of a configuration example of a power semiconductor device 100 configured as a trench gate SiC power MOSFET is shown. The SiC power MOSFET is a vertical power semiconductor device, which further includes an edge termination region ( Figure 2 (not shown in the figure).

[0062] The gate structure 106 is as described above with reference to Figure 1B The first gate dielectric layer 1081 is configured as described above. The first gate dielectric layer 1081 is adjacent to the channel region 112. The channel region 112 is defined by a portion of the p-doped body region 114 that is adjacent to the first gate dielectric layer 1081 at the first sidewall 1241 of the gate structure 106. For example, the conductivity of the channel region 112 can be controlled by a potential applied to the gate electrode structure 110, such as by a field effect. For example, a positive voltage applied to the gate electrode structure 110 can, for example, induce an n-type inversion channel in the channel region 112 adjacent to the first gate dielectric layer 1081. The p-doped body region 114 can be electrically connected to the first load electrode L1 via the first surface 1031, such as by a contact plug and / or a recessed contact on the top surface of the body region 114, and the recessed contact can extend into the SiC semiconductor body 102 and can be electrically connected to the body region 114 ( Figure 2 For example, the channel region 112 as a part of the body region 114 may include partial compensation with n-type dopants for adjusting the threshold voltage. For example, partial compensation may be achieved by: oblique ion implantation through the sidewalls of the trench. The first gate dielectric layer 1081 of the gate dielectric structure 108 is also connected to an n-type dopant arranged between the p-doped body region 114 and the first surface 1031. + The first gate dielectric layer 1081 of the gate dielectric structure 108 further adjoins an n-doped current diffusion region 118 arranged between the p-doped body region 114 and the n-doped drift region 120. The n-doped drift region 120 has a lower doping concentration than the current diffusion region 118. The n-doped drift region 120 is electrically coupled to the second load electrode L2 via the second surface 1032 of the SiC semiconductor body 102.

[0063] At the second sidewall 1242 of the gate structure 106, the first dielectric layer 1081 is adjacent to the p-doped diode region 123. The p-doped diode region 123 includes a first sub-region 1231 and a second sub-region 1232. The doping concentration profiles of the first sub-region 1231 and the second sub-region 1232 overlap each other along the vertical direction y. The number of sub-regions may also be different from the illustrated example of two sub-regions, for example, one, three or four, or five, or even more. The interlayer dielectric 126 electrically isolates the gate electrode structure 110 from the first load electrode L1.

[0064] FIG. 3A to FIG. 3C The schematic diagram of FIG. 1 is used to illustrate the operating principle of a power semiconductor device configured as an n-channel power MOSFET as described in the examples herein.

[0065] Reference Figure 3A , the power MOSFET includes a charge storage layer 1085 integrated in the gate structure 106. Figure 3B In the normal operation mode illustrated in FIG, electron channel current flows as indicated by the circles. The electrons do not reach the charge storage layer 1085. Figure 3C In the short circuit mode of the power MOSFET illustrated in , some of the electrons flowing through the channel region reach the charge storage layer 1085 and contribute to the self-triggered turn-off or shutdown of the short circuit.

[0066] Figure 4A and Figure 4B 1 is an exemplary conduction band diagram for illustrating the gate dielectric structure 108. The charge storage layer 1085 defines a potential well for electrons and is disposed between the first gate dielectric layer 1081 and the second gate dielectric layer 1082. The gate dielectric structure 108 further includes a third gate dielectric layer 1083 disposed between the second gate dielectric layer 1082 and the gate electrode structure 110. There is a conduction band offset Φ at the first interface 1221 between the SiC semiconductor body 102 and the first gate dielectric layer 1081. B,1 . Figure 4A and Figure 4B The schematic conduction band diagrams of Figure 4B Compared with Figure 4A The conduction band offset at the second interface 1222 between the charge storage layer 1085 and the first gate dielectric layer 1081 is smaller. This results in a greater asymmetry in the conduction band offset of the potential well. Figure 4B Compared with Figure 4A The asymmetry in thickness of the barrier defined by the first gate dielectric layer 1081 and the second gate dielectric layer 1082 is smaller. Figure 4A , Figure 4BIn the normal operation mode illustrated in , electrons in the conduction band Ec of the SiC semiconductor body 102 do not reach the charge storage layer 1085 at low temperature and positive gate-to-source voltage.

[0067] Figure 5A and Figure 5B Based on Figure 4A and Figure 4B , but for higher temperatures (e.g., caused by a short circuit event). At higher temperatures, some of the electrons flowing through the channel region tunnel by thermally assisted tunneling (see Figure 5B ) or by thermal electron emission (see Figure 5A ) reaches the charge storage layer 1085 and contributes to the self-triggered turn-off or shutdown of the short circuit.

[0068] Fig. 6A and Figure 6B Based on Figure 4A and Figure 4B 108 and illustrates the transfer of electrons from the charge storage layer 1085 back into the SiC semiconductor body 102 (including the Fowler-Nordheim tunneling process ( Fig. 6A ) and direct tunneling processing ( Figure 6B )) is used to reset the negative gate-to-source voltage pulse of the charge storage layer 1085 of the power MOSFET.

[0069] Figure 7 1 is an exemplary conduction band diagram for illustrating a gate dielectric structure having a charge storage layer 1085 including a varying material composition. The varying material composition is a transition gate dielectric layer having a material composition that changes from a material composition of a first gate dielectric layer 1081 to a material composition of a second gate dielectric layer 1082 over an extension d along a thickness direction x1 of the gate dielectric structure 108. The transition gate dielectric layer includes impurities configured as acceptor-like states within the dielectric band gap. The acceptor-like states are illustrated by reference numerals Ea1, Ea2 and are energetically greater than the conduction band edge E of the SiC semiconductor body. C When the extension d is contracted to zero, the acceptor-like state becomes an interface trap state at the interface between the first gate dielectric layer 1081 and the second gate dielectric layer 1082 .

[0070] Aspects and features mentioned and described in conjunction with one or more of the previously described examples and figures may also be combined with one or more other examples in order to replace similar features of the other examples or in order to additionally introduce features into the other examples.

[0071] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. The present application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A power semiconductor device (100), comprising: A silicon carbide (SiC) semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite to the first surface (1031), the SiC semiconductor body (102) comprising a transistor cell region (104), the transistor cell region (104) comprising transistor cells (1041), each transistor cell (1041) comprising: A gate structure (106) comprising a gate dielectric structure (108) and a gate electrode structure (110) on the gate dielectric structure (108), wherein the gate dielectric structure (108) comprises a first gate dielectric layer (1081) adjacent to a SiC semiconductor body (102), a second gate dielectric layer (1082), and a charge storage layer (1085) arranged between the first gate dielectric layer (1081) and the second gate dielectric layer (1082).

2. The power semiconductor device (100) according to the preceding claim, wherein the conduction band offset (Φ) at the first interface (1221) between the SiC semiconductor body (102) and the first dielectric layer (1081) is B,1 ) has a value in the range from 1.0 eV to 2 eV.

3. A power semiconductor device (100) according to any one of the preceding claims, wherein the gate dielectric structure (108) further comprises a third gate dielectric layer (1083) arranged between the second gate dielectric layer (1082) and the gate electrode (108), the third gate dielectric layer (1083) being adjacent to the gate electrode (106).

4. The power semiconductor device (100) according to the preceding claim, wherein the third gate dielectric layer (1083) is a high-k dielectric layer.

5. The power semiconductor device (100) according to claim 1 or 2, wherein the second gate dielectric layer (1082) adjoins the gate electrode (106).

6. A power semiconductor device (100) according to any one of the preceding claims, wherein the charge storage layer (1085) comprises a potential well for electrons, and a conduction band offset at a second interface (1222) between the charge storage layer (1085) and the first gate dielectric layer (1081) is smaller than a conduction band offset at a third interface (1223) between the charge storage layer (1085) and the second gate dielectric layer (1082).

7. The power semiconductor device (100) according to the preceding claim, wherein the difference between the conduction band offset at the third interface (1223) and the conduction band offset at the second interface (1222) has a value in the range from 0.5 eV to 3 eV.

8. The power semiconductor device (100) according to the preceding claim, wherein the conduction band offset at the second interface (1222) has a value in the range from 0.5 eV to 1.5 eV.

9. A power semiconductor device (100) according to any one of the preceding claims, wherein the charge storage layer (1085) is a Hf2O3 layer, the first gate dielectric layer (1081) is an Al2O3 layer, and the second gate dielectric layer (1082) is a SiO2 layer.

10. The power semiconductor device (100) according to any one of claims 1 to 5, wherein the charge storage layer (1085) is an interface layer comprising interface trapping states at an interface between the first gate dielectric layer (1081) and the second gate dielectric layer (1082).

11. A power semiconductor device (100) according to any one of claims 1 to 5, wherein the charge storage layer (1085) is a transition gate dielectric layer having a material composition that changes from a material composition of a first gate dielectric layer (1081) to a material composition of a second gate dielectric layer (1082) along a thickness direction of the gate dielectric structure.

12. The power semiconductor device (100) according to the preceding claim, wherein the thickness of the transition gate dielectric layer has a value in the range from 0.1 nm to 3 nm.

13. The power semiconductor device (100) according to any one of the two preceding claims, wherein the transition gate dielectric layer comprises a transition gate dielectric layer having a thickness from 10 11 cm -3 to 10 13 cm -3 The impurity concentration is within the range of values.

14. The power semiconductor device (100) according to any of the preceding claims, wherein the thickness of the first gate dielectric layer (1081) has a value in the range from 3 nm to 20 nm.

15. The power semiconductor device (100) according to any one of the preceding claims, wherein the power semiconductor device (100) is an n-channel vertical power MOSFET comprising a gate trench (124), the gate trench (124) comprising a gate structure (106).

16. A power semiconductor device (100) according to the preceding claim, wherein the vertical power MOSFET comprises a p-doped diode region adjacent to one of the first and second opposite side walls of the gate trench (124), and wherein the p-doped diode region is adjacent to a bottom side of the gate trench (124).

17. A method for operating a power semiconductor device (100) according to any one of the preceding claims, comprising: A charge storage layer (1085) of a power semiconductor device (100) is reset at least in part by applying a negative gate-to-source voltage pulse.

18. A method for manufacturing a power semiconductor device (100), the method comprising: Providing a silicon carbide (SiC) semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite to the first surface (1031); and A transistor cell region (104) comprising transistor cells (1041) is formed in a SiC semiconductor body (102), wherein each transistor cell (1041) comprises a gate structure (106), the gate structure (106) comprising a gate dielectric structure (108) and a gate electrode structure (110) on the gate dielectric structure (108), wherein the gate dielectric structure (108) comprises a first gate dielectric layer (1081) adjacent to the SiC semiconductor body (102), a second gate dielectric layer (1082), and a charge storage layer (1085) arranged between the first gate dielectric layer (1081) and the second gate dielectric layer (1082).

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