A SiCVD MOSFET structure for suppressing drain-source voltage overshoot and a method for preparing the same

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a SiCVDMOSFET structure for suppressing drain-source voltage overshoot, comprising a metal drain, a semiconductor epitaxial layer, a metal source, a gate, and a gate oxide layer covering the surface of the gate, wherein the semiconductor epitaxial layer comprises an N substrate layer, a diffusion layer, a P well layer, a doped P layer, and an N well layer; the cross-sectional profile of the gate is in an inverted 'U' shape, and a polysilicon doped layer is provided below the gate; the cross-sectional profile of the P well layer is in an 'L' shape, and the cross-sectional height of the P well layer is higher than the cross-sectional height of the polysilicon doped layer; a doped N layer is provided below the polysilicon doped layer, wherein the doped N layer blocks the direct contact between the polysilicon doped layer and the diffusion layer. The present invention forms a polysilicon doped layer by deposition inside the semiconductor epitaxial layer, and the polysilicon doped layer can reduce the influence of drain-source voltage overshoot, and effectively suppress the concentration of high electric field, and avoid breakdown under high voltage.

Description

Technical Field

[0001] The invention relates to the technical field of MOS semiconductors, and in particular to a SiCVD MOSFET structure capable of suppressing drain-source voltage overshoot and a preparation method thereof. Background Art

[0002] The preparation method of SiC VDMOSFET (Silicon Carbon Vertical Bipolar Metal Oxide Semiconductor Field Effect Transistor) structure is mainly focused on optimizing the design and material properties of the device to improve its performance and reduce the overshoot phenomenon.

[0003] The existing patent discloses a SiC VDMOSFET device with a laterally variable doped body diode (publication number CN115632069A), including: a drain, an N+ substrate and an N-drift region arranged in sequence from bottom to top; P-well regions are respectively provided on both sides of the N-drift region; an N+ active region is provided inside the P-well region; a first P+ contact region is formed on the side surface of the P-well region facing outward; a P-contact region is formed on the side of the first P+ contact region facing away from the N+ active region; and a second P+ contact region is formed on the side of the P-contact region facing away from the first P+ contact region. In the technology disclosed in the patent, when the device is used for a long switching time, not only the switching loss is increased, but also the drain-source voltage is prone to overshoot, which makes it impossible for the voltage stabilization performance, parasitic capacitance, etc. of the device to directly form the best match with the electric adjustment equipment, which seriously limits the full performance of the SiCMOSFET device. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a SiCVD MOSFET structure for suppressing drain-source voltage overshoot and a preparation method thereof, thereby solving the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a SiCVDMOSFET structure for suppressing drain-source voltage overshoot includes a metal drain, a semiconductor epitaxial layer, a metal source, a gate, and a gate oxide layer covering the surface of the gate, wherein the semiconductor epitaxial layer includes an N substrate layer, a diffusion layer, a P well layer, a doped P layer, and an N well layer;

[0006] The cross-sectional profile of the gate is in an inverted 'U' shape, and a polysilicon doping layer is provided below the gate.

[0007] Furthermore, the cross-sectional profile of the P-well layer is in an 'L' shape, and the cross-sectional height of the P-well layer is higher than the cross-sectional height of the polysilicon doped layer.

[0008] Furthermore, a doped N layer is provided below the polysilicon doped layer, wherein the doped N layer blocks direct contact between the polysilicon doped layer and the diffusion layer.

[0009] A method for preparing a SiCVD MOSFET structure for suppressing drain-source voltage overshoot, specifically comprising the following steps:

[0010] S1, growing a gate oxide layer on the surface of the semiconductor epitaxial layer;

[0011] S2, doping N-type or P-type dopants on the semiconductor epitaxial layer substrate to form a P-well layer, a doped P layer and an N-well layer;

[0012] S3. Forming a polysilicon doped layer by deposition inside the semiconductor epitaxial layer. The polysilicon doped layer can reduce the influence of drain-source voltage overshoot and effectively suppress the concentration of high electric field to avoid breakdown under high voltage;

[0013] S4, adding N-type dopants between the metal drain and the metal source to form a diffusion layer, which can form a reverse electric field;

[0014] S5, passivating the surface of the SiCVDMOSFET structure;

[0015] S6. Conduct detailed performance testing on the SiCVD MOSFET structure, especially the voltage and current characteristics during switching.

[0016] Furthermore, in step S2, the source-drain resistance is controlled by adjusting the doping concentration and depth of the source and drain regions through an ion implantation process. Appropriate optimization of the doping concentration of the source and drain can effectively reduce the concentration of the electric field during the switching process.

[0017] Furthermore, in step S5, a passivation treatment is performed by depositing silicon nitride or aluminum oxide on the surface of the semiconductor epitaxial layer using a deposition technique, so as to reduce surface defects, prevent an increase in leakage current, and improve the switching characteristics of the device.

[0018] Furthermore, in step S6, whether the electrical performance of the SiCVDMOSFET structure is qualified is determined according to the current gain of the SiCVDMOSFET structure per unit time, the increment of the threshold voltage with temperature, and the increment of the switching time with temperature, which are:

[0019]

[0020] In the formula, The qualified index coefficient that represents the electrical performance of the SiCVDMOSFET structure, represents the increment of threshold voltage changing with temperature, represents the increment of switching time as the temperature changes, Represents the current gain per unit time.

[0021] Furthermore, when When , it means that the electrical performance of the tested MOSFET structure is excellent;

[0022] when When , it means that the electrical performance of the tested MOSFET structure is qualified;

[0023] when When , it means that the electrical performance of the tested MOSFET structure is unqualified.

[0024] Beneficial effects:

[0025] 1. The present invention forms a polysilicon doping layer by deposition inside the semiconductor epitaxial layer. The polysilicon doping layer can reduce the influence of drain-source voltage overshoot and effectively suppress the concentration of high electric field to avoid breakdown under high voltage.

[0026] 2. The present invention can effectively reduce the concentration of the electric field during the switching process by providing a doped N layer below the polysilicon doped layer, reduce the influence of drain-source voltage overshoot, and thus avoid breakdown under high voltage.

[0027] 3. The present invention determines whether the electrical performance of the device is qualified by the device's current gain per unit time, the increment of the threshold voltage changing with temperature, and the increment of the switching time changing with temperature. This design, which uses the least indicators to maximize the judgment of whether the electrical performance of the device containing the polysilicon doped layer is qualified, can effectively improve the efficiency of device quality inspection. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention;

[0029] Figure 2 It is a structural schematic diagram of Embodiment 2 of the present invention;

[0030] Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention.

[0031] In the figure: 1. Metal drain; 2. N substrate layer; 3. Diffusion layer; 4. P well layer; 5. Doped P layer; 6. N well layer; 7. Polysilicon doped layer; 8. Gate; 9. Gate oxide layer; 10. Metal source; 11. Doped N layer. DETAILED DESCRIPTION

[0032] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] A method for preparing a SiCVD MOSFET structure for suppressing drain-source voltage overshoot, specifically comprising the following steps:

[0034] Step 1: growing a gate oxide layer on the surface of the semiconductor epitaxial layer.

[0035] Step 2: N-type or P-type dopants are doped into the semiconductor epitaxial layer substrate to form a P-well layer 4, a doped P layer 5 and an N-well layer 6; through the ion implantation process, the doping concentration and depth of the source and drain regions are adjusted to control the source-drain resistance. Appropriate optimization of the doping concentration of the source and drain can effectively reduce the concentration of the electric field during the switching process.

[0036] Step 3: forming a polysilicon doped layer 7 by deposition inside the semiconductor epitaxial layer. The polysilicon doped layer 7 can reduce the influence of drain-source voltage overshoot and effectively suppress the concentration of high electric field to avoid breakdown under high voltage.

[0037] Step 4: N-type dopants are doped between the metal drain 1 and the metal source 10 to form a diffusion layer 3, which can form a reverse electric field.

[0038] Step 5: Passivate the surface of the SiCVDMOSFET structure; the passivation treatment uses silicon nitride or aluminum oxide deposition technology to deposit on the surface of the semiconductor epitaxial layer to reduce surface defects, prevent the increase of leakage current, and improve the switching characteristics of the device.

[0039] Step 6: Conduct detailed performance testing on the SiCVD MOSFET structure, especially the voltage and current characteristics during the switching process.

[0040] According to the current gain of SiCVDMOSFET structure per unit time, the increment of threshold voltage with temperature change, and the increment of switching time with temperature change, the electrical performance of SiCVDMOSFET structure is determined to be qualified. There are:

[0041]

[0042] In the formula, The qualified index coefficient that represents the electrical performance of the SiCVDMOSFET structure, represents the increment of threshold voltage changing with temperature, represents the increment of switching time as the temperature changes, Represents the current gain per unit time.

[0043] when When , it means that the electrical performance of the tested MOSFET structure is excellent;

[0044] when When , it means that the electrical performance of the tested MOSFET structure is qualified;

[0045] when When , it means that the electrical performance of the tested MOSFET structure is unqualified.

[0046] Among them, the qualified index coefficient of the electrical performance of the SiCVDMOSFET structure is calculated. The increment of the threshold voltage with temperature is taken as (The increment of threshold voltage change with temperature = threshold voltage 0.7V at 25℃ - threshold voltage 0.55V at 100℃).

[0047] The switching time increments with temperature are (Unit: nanoseconds, the increment of switching time with temperature change = 35 nanoseconds at 100°C - 20 nanoseconds at 25°C). And the current gain per unit time is , then we have:

[0048]

[0049] From the above calculation, we can know that the qualified index coefficient of the electrical performance of the SiCVDMOSFET structure is . Then the electrical performance of the tested MOSFET structure is qualified.

[0050] Example 1

[0051] like Figure 1 As shown, according to one aspect of the present invention, a SiCVDMOSFET structure for suppressing drain-source voltage overshoot is provided, comprising a metal drain 1, a semiconductor epitaxial layer, a metal source 10, a gate 8, and a gate oxide layer 9 covering the surface of the gate 8, characterized in that: the semiconductor epitaxial layer comprises an N substrate layer 2, a diffusion layer 3, a P well layer 4, a doped P layer 5 and an N well layer 6; the cross-sectional profile of the gate 8 is in an inverted "U" shape, and a polysilicon doping layer 7 is provided under the gate 8. The polysilicon doping layer 7 can reduce the influence of the drain-source voltage overshoot, and effectively suppress the concentration of high electric fields, and avoid breakdown under high voltage.

[0052] Example 2

[0053] like Figure 2 In the SiCVD MOSFET structure for suppressing drain-source voltage overshoot shown, the cross-sectional profile of the P-well layer 4 is in an 'L' shape, and the cross-sectional height of the P-well layer 4 is higher than the cross-sectional height of the polysilicon doped layer 7. The P-well layer 4 can suppress the charge from gathering at the two convex parts of the gate 8 (because the linear distance between the two convex parts of the gate 8 and the metal drain 1 is shorter, it is easier to form charge accumulation).

[0054] Example 3

[0055] like Figure 3In the SiCVD MOSFET structure for suppressing drain-source voltage overshoot shown, a doped N layer 11 is provided below the polysilicon doped layer 7, wherein the doped N layer 11 blocks direct contact between the polysilicon doped layer 7 and the diffusion layer 3. Providing the doped N layer 11 below the polysilicon doped layer 7 can effectively reduce the concentration of the electric field during the switching process, reduce the influence of the drain-source voltage overshoot, and thus avoid breakdown under high voltage.

[0056] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A SiCVD MOSFET structure for suppressing drain-source voltage overshoot, comprising a metal drain (1), a semiconductor epitaxial layer, a metal source (10), a gate (8), and a gate oxide layer (9) covering the surface of the gate (8), characterized in that: The semiconductor epitaxial layer comprises an N substrate layer (2), a diffusion layer (3), a P well layer (4), a doped P layer (5) and an N well layer (6); The cross-sectional profile of the gate (8) is in the shape of an inverted "U", and a polysilicon doping layer (7) is provided below the gate (8); A doped N layer (11) is provided below the polysilicon doped layer (7), wherein the doped N layer (11) blocks direct contact between the polysilicon doped layer (7) and the diffusion layer (3).

2. The SiCVD MOSFET structure for suppressing drain-source voltage overshoot according to claim 1, characterized in that: The cross-sectional profile of the P-well layer (4) is in an 'L' shape, and the cross-sectional height of the P-well layer (4) is higher than the cross-sectional height of the polysilicon doped layer (7).

3. A method for preparing a SiCVD MOSFET structure for suppressing drain-source voltage overshoot, characterized in that: The SiCVD MOSFET structure for suppressing drain-source voltage overshoot according to any one of claims 1 to 2, wherein the method for preparing the SiCVD MOSFET structure for suppressing drain-source voltage overshoot specifically comprises the following steps: S1, growing a gate oxide layer on the surface of the semiconductor epitaxial layer; S2, doping N-type or P-type dopants on the semiconductor epitaxial layer substrate to form a P well layer (4), a doped P layer (5) and an N well layer (6); S3, forming a polysilicon doped layer (7) inside the semiconductor epitaxial layer by deposition; S4, doping an N-type dopant between the metal drain (1) and the metal source (10) to form a diffusion layer (3), wherein the diffusion layer (3) is capable of forming a reverse electric field; S5, passivating the surface of the SiCVDMOSFET structure; S6. Conduct detailed performance testing on the SiCVD MOSFET structure, especially the voltage and current characteristics during switching.

4. The method for preparing a SiCVD MOSFET structure for suppressing drain-source voltage overshoot according to claim 3, characterized in that: In step S2, the source-drain resistance is controlled by adjusting the doping concentration and depth of the source-drain region through an ion implantation process.

5. The method for preparing a SiCVD MOSFET structure for suppressing drain-source voltage overshoot according to claim 3, characterized in that: In the step S5, a passivation treatment is performed by depositing silicon nitride or aluminum oxide on the surface of the semiconductor epitaxial layer using a deposition technique.

6. The method for preparing a SiCVD MOSFET structure for suppressing drain-source voltage overshoot according to claim 3, characterized in that: In step S6, whether the electrical performance of the SiCVDMOSFET structure is qualified is determined according to the current gain of the SiCVDMOSFET structure per unit time, the increment of the threshold voltage with temperature, and the increment of the switching time with temperature. In the formula, The qualified index coefficient representing the electrical performance of SiCVDMOSFET structure; Indicates the increment of threshold voltage changing with temperature, in units of ; Indicates the increment of switching time as the temperature changes, in units of ; Represents the current gain per unit time, in units of .

7. The method for preparing a SiCVD MOSFET structure for suppressing drain-source voltage overshoot according to claim 6, characterized in that: when When , it indicates that the electrical performance of the SiCVDMOSFET structure tested is excellent; when When , it means that the electrical performance of the tested SiCVDMOSFET structure is qualified; when When , it means that the electrical performance of the SiCVDMOSFET structure tested is unqualified.

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