Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a first source / drain region connected by a first channel structure controlled by a first gate structure; and a second source / drain region over the first source / drain regions, respectively, connected by a second channel structure controlled by a second gate structure, where the first channel structure and the second channel structure comprise different materials.

Description

Technical Field

[0001] Devices and methods consistent with the present disclosure relate to three-dimensional stacked (3D stacked) or multi-stacked semiconductor devices, wherein the channel structure, source / drain region and gate structure of transistors of a first level are different in size and material from the channel structure, source / drain region and gate structure of transistors of a second level. Background Art

[0002] In response to the growing demand for integrated circuits with high device density and high performance, a 3D stacked semiconductor device including a first level of transistors and a second level of transistors above the first level is introduced. Each of the two transistors can be a fin field effect transistor (FinFET), a nanosheet transistor, or any other type of transistor. FinFET has one or more horizontally arranged vertical fin structures as a channel structure, at least three surfaces of which are surrounded by a gate structure, and the nanosheet transistor is characterized by one or more nanosheet channel layers as a channel structure stacked vertically on a substrate and a gate structure surrounding all four surfaces of each nanosheet channel layer. Nanosheet transistors are called all-around gate (GAA) transistors or multi-bridge channel field effect transistors (MBCFETs).

[0003] In addition to 3D stacked semiconductor devices, a backside power distribution network (BSPDN) for semiconductor devices has been introduced to address the busy traffic of signal lines and power rails at the front side of the semiconductor device. The BSPDN can help reduce the contact resistance between circuit elements formed on the front side of the semiconductor device. Here, the front side refers to the side where the transistor is formed relative to the top surface of the substrate, and the back side refers to the side opposite to the front side. The BSPDN is formed on the back side of the semiconductor device and may include a backside metal line (such as a buried power rail) and a backside source / drain contact structure formed on the bottom surface of the source / drain region of a field effect transistor (such as a nanosheet transistor or a FinFET), respectively. The backside metal line can connect the backside contact structure to a voltage source or another circuit element for signal routing.

[0004] A 3D stacked semiconductor device with a BSPDN structure is used to form CMOS devices, such as inverter circuits, NAND gates, NOR gates, and AND gates, etc., in which different polarities (p-type and n-type) of transistors are formed at the first level and the second level, respectively. In this 3D stacked semiconductor device, when the two transistors have different polarities or different types, the work function metal layer of the gate structure of the transistor of the first level may be different from the work function metal layer of the transistor of the second level. The work function metal layer of the gate structure can control the threshold voltage of the transistor formed by the gate structure. However, it is challenging to control process variations when manufacturing a 3D stacked semiconductor device in which the gate structures of the two transistors should have different work function metal layers of nanoscale size and also have a BSPDN structure.

[0005] The information disclosed in this background technology section is known to the inventor or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information acquired in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0006] The present disclosure provides a semiconductor device comprising a first transistor and a second transistor stacked thereon, wherein the gate structures of the two transistors can be vertically isolated from each other by one or more semiconductor layers, and the one or more semiconductor layers have sufficient thickness to improve the isolation between the gate structures of the two transistors.

[0007] According to one or more embodiments, a semiconductor device is provided, which may include: a first source / drain region, connected by a first channel structure controlled by a first gate structure; and a second source / drain region, respectively above the first source / drain region, connected by a second channel structure controlled by a second gate structure, wherein the first channel structure and the second channel structure are formed of different materials.

[0008] According to one or more embodiments, the first channel structure may be formed of silicon germanium (SiGe), and the second channel structure may be formed of silicon (Si).

[0009] According to one or more embodiments, a semiconductor device is provided, which may include: a first source / drain region, connected through a first channel structure controlled by a first gate structure; and a second source / drain region, respectively above the first source / drain region, connected through a second channel structure controlled by a second gate structure, wherein in a first direction in which the first source / drain region is connected and the second source / drain region is connected, a length of the first channel structure is different from a length of the second channel structure.

[0010] According to one or more embodiments, a semiconductor device is provided, which may include: a first source / drain region, connected through a first channel structure controlled by a first gate structure; and a second source / drain region, respectively above the first source / drain region, connected through a second channel structure controlled by a second gate structure, wherein in a first direction where the first source / drain region is connected and where the second source / drain region is connected, a length of the first gate structure is different from a length of the second gate structure.

[0011] According to one or more embodiments, a semiconductor device is provided, which may include: a first source / drain region, connected through a first channel structure controlled by a first gate structure; and a second source / drain region, respectively above the first source / drain region, connected through a second channel structure controlled by a second gate structure, wherein in a first direction in which the first source / drain region is connected and the second source / drain region is connected, a length of the first source / drain region is different from a length of the second source / drain region.

[0012] According to one or more embodiments, a method for manufacturing a semiconductor device is provided. The method may include: forming a first channel stack at a first level above a substrate, and forming a second channel stack at a second level above the first level, wherein the first channel stack and the second channel stack respectively include different material compositions; forming a first dummy gate structure and a second dummy gate structure to respectively surround the first channel stack and the second channel stack, wherein the first dummy gate structure and the second dummy gate structure respectively include different materials; based on the first channel stack, forming a first source / drain region at the first level; based on the second channel stack, forming a second source / drain region at the second level; replacing the second dummy gate structure with a second gate structure; replacing the substrate with a backside isolation structure; and replacing the first dummy gate structure with the first gate structure, wherein the first channel stack is formed by alternately stacking a first sacrificial layer of silicon germanium (SiGe) and a first channel layer of silicon (Si), and wherein the second channel stack is formed by alternately stacking a second channel layer of SiGe and a second sacrificial layer of Si. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figures 1A to 1F A 3D stacked semiconductor device 10 is shown according to one or more embodiments, wherein a channel structure, source / drain regions, and gate structure of a first transistor 10L at a first level are different in size and material from a channel structure, source / drain regions, and gate structure of a second transistor 10U at a second level.

[0015] Figure 2A-2EA semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a first channel stack 110 ′, a sacrificial stack 140 ′, and a second channel stack 120 ′ are formed on a substrate 101 and surrounded by a first dummy gate structure 115 ′.

[0016] Figures 3A-3E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein the first dummy gate structure 115 ′ is partially removed to surround only the first channel stack 110 ′.

[0017] Figures 4A-4E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a second dummy gate structure 125 ′ is formed on the first dummy gate structure 115 ′ to surround the second channel stack 120 ′.

[0018] Figures 5A-5E A semiconductor device structure 10 ′ is shown in accordance with one or more embodiments, wherein a second dummy gate structure 125 ′ is patterned to form a first semiconductor stack 10A, a second semiconductor stack 10B, and a third semiconductor stack 10C.

[0019] Figures 6A-6E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a second channel stack 120 ′ is patterned to provide a space for forming a second source / drain region therein between the first semiconductor stack 10A, the second semiconductor stack 10B, and the third semiconductor stack 10C.

[0020] Figures 7A-7E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein each second sacrificial layer 121 in the second channel structure 120 is partially etched at a side surface thereof to form a sacrificial spacer 126 ′ on the etched side surface.

[0021] Figures 8A-8E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a first channel stack 110 ′ and a substrate 101 thereunder are patterned to provide space for forming first source / drain regions and placeholder structures between first to third semiconductor stacks 10A, 10B, and 10C.

[0022] Figures 9A-9E A semiconductor device structure 10' according to one or more embodiments is shown, wherein each of the first sacrificial layer 111 in the first channel structure 110 and the second channel layer 122 in the second channel structure 120 is partially etched at a side surface thereof to form a first inner spacer 116 on the etched side surface, and further, a placeholder structure 109' is formed in each of the recesses R1 and R2 formed in the substrate 101.

[0023] Figures 10A-10E A semiconductor device structure 10 ′ is shown in accordance with one or more embodiments, wherein a first source / drain region 135 is formed from a first channel layer 112 in a first channel structure 110 .

[0024] Figures 11A-11E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a front side isolation structure 141 is formed on the first source / drain region 135 , and sacrificial spacers 126 ′ and first inner spacers 116 on side surfaces of the second channel structure 120 are removed.

[0025] Figures 12A-12E A semiconductor device structure 10 ′ according to one or more embodiments is shown, in which each second sacrificial layer 121 is partially etched again at a side surface thereof to form a second inner spacer 126 on the etched side surface.

[0026] Figures 13A-13E A semiconductor device structure 10 ′ is shown in which a second source / drain region 145 is formed from a second channel layer 122 according to one or more embodiments.

[0027] Figures 14A-14E A semiconductor device structure 10 ′ is shown in accordance with one or more embodiments, wherein a front side isolation structure 141 is extendedly formed on the second source / drain region 145 .

[0028] Figures 15A-15E A semiconductor device structure 10 ′ is shown in accordance with one or more embodiments, wherein the second dummy gate structure 125 ′ and the second sacrificial layer 121 are removed.

[0029] Figures 16A-16E A semiconductor device structure 10 ′ according to one or more embodiments is shown, in which a second gate structure 125 is formed in a space provided by removing the second dummy gate structure 125 ′ and the second sacrificial layer 121 .

[0030] Figures 17A-17E A semiconductor device structure 10 ′ is shown in which a front side contact structure 119 and a BEOL layer 160 are formed according to one or more embodiments.

[0031] Figures 18A-18E A semiconductor device structure 10 ′ is shown with the substrate 101 removed therefrom in accordance with one or more embodiments.

[0032] Figures 19A-19EA semiconductor device structure 10 ′ is shown in accordance with one or more implementations, wherein contact spacers 107 are formed on side surfaces of placeholder structures 109 ′, and an initial backside isolation structure 142 ′ is formed around the placeholder structure 109 ′ having the contact spacers 107 thereon.

[0033] Figures 20A-20E A semiconductor device structure 10 ′ is shown in accordance with one or more embodiments, wherein the initial backside isolation structure 142 ′, the first dummy gate structure 115 ′, and the first sacrificial layer 111 are removed.

[0034] Figures 21A-21E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a first gate structure 115 may be formed to surround a first channel layer 112 .

[0035] Figures 22A-22E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein the first gate structure 115 formed in the previous step is partially etched back, and a backside isolation structure 142 may be formed on the backside of the semiconductor device structure 10 ′.

[0036] Figures 23A-23E A semiconductor device structure 10 ′ is shown with the semiconductor device 10 ′ removed therefrom according to one or more embodiments. Figures 22A-22E The placeholder structure 109 ′ shown in FIG.

[0037] Figures 24A-24E 1 ' shows a semiconductor device structure 10' according to one or more embodiments, wherein the backside contact structures 109 are formed by removing Figures 22A-23E In the space provided by the placeholder structure 109 ′ shown in FIG.

[0038] Figures 25A-25C A flow chart of manufacturing a 3D stacked semiconductor device according to one or more embodiments is shown, wherein reference is made to Figure 2A-2E to Figures 24A-24E , the channel structure, source / drain region and gate structure of the transistors of the first level are different in size and material from the channel structure, source / drain region and gate structure of the transistors of the second level.

[0039] Fig.26 FIG. 1 is a diagram showing a 3D stacked semiconductor device 10 according to one or more embodiments, including the 3D stacked semiconductor device 10 shown in FIG. 1 or as described above with reference to FIG. Figure 2A-2E to Figures 25A-25C Schematic block diagram of an electronic device of the fabricated 3D stacked semiconductor device. DETAILED DESCRIPTION

[0040] The embodiments of the present disclosure described here are example embodiments, and therefore, the present disclosure is not limited thereto and can be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided here or not provided here but consistent with the present disclosure. For example, even if the content described in a specific example or embodiment is not described in an example or embodiment different from it, these contents can also be understood as being related to or combined with different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure. For example, the channel layer, sacrificial layer and isolation layer described here can take different types or forms, as long as the present invention can be applied to it.

[0041] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on" another element of the semiconductor device, "over" another element of the semiconductor device, "on" another element of the semiconductor device, "under" another element of the semiconductor device, "under" another element of the semiconductor device, "connected to" or "coupled to" another element of the semiconductor device, it may be directly on, directly over, directly on, directly under, directly under, directly under, directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element of a semiconductor device is referred to as being "directly on", "directly over", "directly on", "directly under", "directly under", "directly under", "directly connected to" or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Like reference numerals refer to like elements throughout this disclosure.

[0042] For ease of description, spatial relationship terms such as "above", "above", "on", "below", "below", "below", "under", "under", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc. may be used here to describe the relationship of one element to another element as shown in the figure. It will be understood that the spatial relationship terms are intended to cover different orientations of the semiconductor device in use or operation other than the orientation depicted in the figure. For example, if the semiconductor device in the figure is turned over, the element described as "below" or "below" another element will be oriented as "above" another element. Therefore, the term "below" can cover both the above and below orientations. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used here are interpreted accordingly. As another example, when the device or structure including these elements is oriented differently, the elements referred to as "left" elements and "right" elements can be "right" elements and "left" elements. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, with the necessary description to distinguish the two elements.

[0043] It will be understood that although the terms "1st", "2nd", "3rd", "4th", "5th", "6th", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0044] As used herein, expressions such as "at least one of..." when preceding a list of elements modify the entire list of elements rather than the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all a, b, and c. Here, when the term "same" is used to compare the size of two or more elements, the term can cover "substantially the same" sizes.

[0045] It will also be understood that even if a step or operation of manufacturing a device or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

[0046] Many embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments (and intermediate structures). As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions shown here, but will include shape deviations, for example, caused by manufacturing. The various regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of the layers and regions may be exaggerated for clarity.

[0047] For the sake of brevity, conventional elements, structures or layers of semiconductor devices including nanosheet transistors and the materials forming them may or may not be described in detail here. For example, when a certain isolation layer or structure of a semiconductor device is not related to the novel features of an embodiment, the layer or structure and the materials forming it may be omitted here. In addition, when the materials forming the well-known structural elements of the semiconductor device are not related to the novel features of the embodiment, the description of those materials may be omitted here. Here, the term "isolation" refers to the electrical insulation or separation between structures, layers, components or regions in the corresponding device or structure.

[0048] Figures 1A-1F A 3D stacked semiconductor device 10 is shown according to one or more embodiments, wherein a channel structure, source / drain regions, and gate structure of a first transistor 10L at a first level are different in size and material from a channel structure, source / drain regions, and gate structure of a second transistor 10U at a second level.

[0049] Figures 1A-1D It is taken along lines I-I', II-II', III-III' and IV-IV' Figure 1E FIG. 1 is a cross-sectional view of a 3D stacked semiconductor device 10 shown in FIG. Figure 1E is a plan view of a 3D stacked semiconductor device 10. It will be understood that Figure 1E To show the positional relationship between the channel structure, source / drain region and gate structure, therefore, Figure 1E Some structural elements are not shown, such as Figures 1A-1D The isolation layer, contact structure and back-end-of-line (BEOL) layers shown in FIG. Figure 1F Shows Figure 1A An enlarged portion A is shown in FIG.

[0050] like Figure 1E As shown, D1 direction is the channel length direction in which current flows between two source / drain regions connected to each other through the channel structure, D2 direction is the channel width direction intersecting with D1 direction, and D3 direction is the channel thickness direction intersecting with D1 and D2 directions.

[0051] Reference Figures 1A-1F The 3D stacked semiconductor device 10 may include a first semiconductor stack 10A, a second semiconductor stack 10B, and a third semiconductor stack 10C on a backside isolation structure 142 .

[0052] Each of the semiconductor stacks 10A-10C may include a first channel structure 110 surrounded by a first gate structure 115 at a first level and a second channel structure 120 surrounded by a second gate structure 125 at a second level, and the second level may be provided above the first level in the D3 direction. The first channel structure 110 may include a plurality of first channel layers 112, and the second channel structure 120 may include a plurality of second channel layers 122. These channel layers 112 and 122 may each be a thin nanosheet, nanowire, or nanobelt, and therefore, the transistor formed by these channel layers may be referred to as a nanosheet transistor.

[0053] The first channel layer 112 may connect the first source / drain regions 135 to each other to allow current to flow therebetween under the control of the first gate structure 115. The second channel layer 122 may connect the second source / drain regions 145 to each other to allow current to flow therebetween under the control of the second gate structure 125. Therefore, the first channel structure 110 (including the first channel layer 112), the first gate structure 115, and the first source / drain regions 135 may form a first transistor 10L at a first level, and the second channel structure 120 (including the second channel layer 122), the second gate structure 125, and the second source / drain regions 145 may form a second transistor 10U at a second level.

[0054] The first channel layers 112 may each be formed of silicon (Si), and the first source / drain region 135 epitaxially grown from the first channel layers 112 may also be formed of silicon (Si). In contrast, the second channel layers 122 may each be formed of silicon germanium (SiGe), and the second source / drain region 145 epitaxially grown from the second channel layers 122 may also be formed of silicon germanium (SiGe). The first source / drain region 135 may be doped with n-type impurities such as phosphorus (P), arsenic (As), antimony (Sb), etc. to form the first transistor 10L as an n-type transistor. The second source / drain region 145 may be formed of SiGe doped with p-type impurities such as boron (B), gallium (Ga), indium (In), etc. to form the second transistor 10U as a p-type transistor.

[0055] Forming the second channel layer 122 with silicon germanium (SiGe) instead of silicon (Si) may achieve higher hole mobility for current flow between the p-type second source / drain regions. Thus, improved device performance of the 3D stacked semiconductor device 10 may be achieved.

[0056] However, when the second channel layer 122 is formed of silicon germanium (SiGe) to serve as the channel of the second transistor 10U, and the first channel layer 112 is formed of silicon (Si) to serve as the channel of the first transistor 10L, in the direction D1, the second length L21 of the second channel layer 122 may be formed to be smaller than the first length L11 of the first channel layer 112, as shown in FIG. Figure 1A and Figure 1F Therefore, in the same direction D1, the fourth length L22 of the second source / drain region 145 epitaxially grown from the second channel layer 122 may become greater than the third length L12 of the first source / drain region 135 epitaxially grown from the first channel layer 112, as shown in FIG. Figure 1A and Figure 1F As shown. Figure 2A-2E to Figures 24A-24E Describe how this length difference in the channel layer and source / drain regions occurs, Figure 2A-2E to Figures 24A-24E A method of manufacturing a 3D stacked semiconductor device is shown.

[0057] At the same time, the first channel layer 112 and the second channel layer 122 included in each of the first semiconductor stack 10A and the third semiconductor stack 10C can be used to form the first source / drain region 135 and the second source / drain region 145 as will be described later, but in some cases may not act as the corresponding channels for the current flow of the first transistor 10L and the second transistor 10U. Therefore, the first semiconductor stack 10A and the third semiconductor stack 10C can each be a dummy transistor structure and can be removed in its complete form in the 3D stacked semiconductor device 10. In other examples (not shown for simplicity), the first semiconductor stack 10A and the third semiconductor stack 10C can be configured as active regions of additional transistors, thereby connecting even more source / drain regions.

[0058] In addition, if Figure 1C and Figure 1DAs shown, in the D2 direction, the second channel layer 122 may have a smaller width than the first channel layer 112. Therefore, in the same D2 direction, the second source / drain region 145 grown from the second channel layer 122 may have a smaller width than the first source / drain region 135. Due to this width difference between the second source / drain region 145 and the first source / drain region 135, a contact structure (if any) connecting the first source / drain region 135 to the BEOL layer 160 may be formed on the top surface of the first source / drain region 135 through a space to the right of the second source / drain region 145 and above the top surface of the first source / drain region 135 without contacting the second source / drain region 145 and the front side contact structure 119 thereon. The BEOL layer 160 may include one or more metal lines connecting the first source / drain region 135 and / or the second source / drain region 145 to one or more voltage sources or other circuit elements for internal wiring purposes.

[0059] Instead of the front side contact structure that may be formed on the top surface of the first source / drain regions 135, a back side contact structure 109 may be formed on the bottom surface of at least one of the first source / drain regions 135 to avoid circuit congestion at the front side of the 3D stacked semiconductor device 10. Thus, at least one first source / drain region 135 may be connected to one or more voltage sources or other circuit elements through the back side contact structure 109. As will be described later, the back side contact structure 109 may be formed by a self-aligned process using contact spacers 107 formed on side surfaces thereof.

[0060] However, the second source / drain region 145 can still be connected to one or more voltage sources or other circuit elements through the corresponding front side contact structure 119 connected to the BEOL layer 160. The back side contact structure 109 and the front side contact structure 119 can be formed of metals such as copper (Cu), tungsten (W), aluminum (Al), ruthenium (Ru), molybdenum (Mo), cobalt (Co), etc. and various compounds or alloys thereof. The contact spacer 107 can be formed of silicon nitride (e.g., SiN, SiBCN, SiCN, SiOCN, etc.), but is not limited thereto.

[0061] Meanwhile, the second gate structure 125 may have a sixth length L23 that is smaller than the fifth length L13 of the first gate structure 115. The gate length difference may also be caused by a material difference between the second channel layer 122 of silicon germanium (SiGe) and the first channel layer 112 of silicon (Si), which may cause a length difference between the second channel layer 122 and the first channel layer 112 and between the second source / drain region 145 and the first source / drain region 135, as described above.

[0062] The first gate structure 115 and the second gate structure 125 may each include a gate dielectric layer, a work function metal layer, and a gate electrode. The gate dielectric layer may include an oxide material such as silicon oxide (SiO), silicon dioxide (SiO 2 The gate dielectric layer may further include an interfacial layer formed of, but not limited to, silicon oxide nitride (SiON) and / or silicon oxide nitride (SiON). The gate dielectric layer may further include a high-k dielectric layer formed of a high-k material such as Hf, Al, Zr, La, Mg, Ba, Ti, Pb and / or a combination thereof, but not limited to this.

[0063] The work function metal layer may be formed of a metal such as titanium (Ti), tantalum (Ta), Al, W, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, and / or a combination thereof, but is not limited thereto. However, the work function metal layers of the first gate structure 115 and the second gate structure 125 having opposite polarities may be different from each other so that they may have different threshold voltages for the first transistor 10L and the second transistor 10U. Therefore, when the first transistor 10L and the second transistor 10U are n-type and p-type, respectively, the first gate structure 115 of the first transistor 10L may include a work function metal layer formed of Al or TiC, and the second gate structure 125 of the second transistor 10U may include a work function metal layer formed of TiN. The gate electrode may be formed of Cu, W, Al, Ru, Mo, Co and / or a combination thereof, but is not limited thereto.

[0064] As will be described later, the second gate structure 125 is formed in a front-side process of manufacturing the 3D stacked semiconductor device 10, and the first gate structure 115 is formed in a back-side process of manufacturing the 3D stacked semiconductor device 10. Therefore, when manufacturing the 3D stacked semiconductor device 10, process variations in forming gate structures having metal layers with different work functions can be more easily controlled.

[0065] The first gate structure 115 may be isolated from the first source / drain region 135 by a first inner spacer 116 formed between the first gate structure 115 and the first source / drain region 135. The second gate structure 125 may be isolated from the second source / drain region 145 by a second inner spacer 126 formed between the second gate structure 125 and the second source / drain region 145. The gate structures 115 and 125 in each of the first semiconductor stack 10A, the second semiconductor stack 10B, and the third semiconductor stack 10C may be protected by a gate spacer 151, which prevents the first gate structure 115 and the second gate structure 125 (and the dummy gate structure replaced by the first gate structure 115 and the second gate structure 125) from being oxidized during the process of manufacturing the 3D stacked semiconductor device 10. The first inner spacer 116 and the second inner spacer 126 may be formed of silicon nitride (e.g., SiN, SiBCN, SiCN, SiOCN, etc.), but are not limited thereto. The gate spacer 151 may be made of silicon oxide or silicon nitride (eg, SiO 2 , SiN, SiBCN, SiCN, SiOC, SiOCN, etc.), but not limited thereto, and may be different from the material forming the first inner spacer 116 and the second inner spacer 126 in at least aspect of etching selectivity.

[0066] A front side isolation structure 141 may be formed to isolate the first source / drain region 135 and the second source / drain region 145 from each other or to isolate the first source / drain region 135 from other circuit elements. On the back side of the 3D stacked semiconductor device 10, a back side isolation structure 142 may be formed to isolate the back side contact structures 109 from each other or to isolate the back side contact structure 109 from another circuit element. The back side isolation structure 142 may replace the substrate of the 3D stacked semiconductor device 10 during the manufacture of the 3D stacked semiconductor device 10. Both the front side isolation structure 141 and the back side isolation structure 142 may be made of silicon oxide (e.g., SiO or SiO 2 ) is formed, but is not limited to this.

[0067] An intermediate isolation structure 140 may be formed between the first gate structure 115 and the second gate structure 125 to separate the first gate structure 115 from the second gate structure 125. Figure 1A The intermediate isolation structure 140 may be formed of a dielectric material such as silicon nitride (eg, SiBCN, SiCN, SiOCN, SiN, etc.), but is not limited thereto.

[0068] In the above embodiments, the first transistor 10L and the second transistor 10U have both a length difference and a width difference in the channel layer and the source / drain region, and a length difference in the gate structure. However, the present disclosure is not limited thereto, and according to one or more embodiments, the first transistor 10L and the second transistor 10U may be formed to have only a length difference in the channel layer, the source / drain region, and the gate structure without a width difference.

[0069] exist Figures 1A-1E , the second channel structure 120 of the second transistor 10U has three first channel layers 122, and the first channel structure 110 of the first transistor 10L has two second channel layers 112. However, the present disclosure is not limited thereto, and according to an embodiment, more or less than two first channel layers 112 may form the first channel structure 110, and more or less than three second channel layers 122 may form the second channel structure 120. In addition, in Figures 1A-1E In the embodiment, the backside contact structure 109 is formed on the bottom surface of each of the two first source / drain regions 135. However, the present disclosure is not limited thereto, and according to another embodiment, the backside contact structure 109 may be formed on the bottom surface of only one of the two first source / drain regions 135.

[0070] In addition, in an embodiment, each of the first channel structure 110 and the second channel structure 120 is formed of a plurality of channel layers as nanosheet layers to form each of the first transistor 10L and the second transistor 10U as a nanosheet transistor. However, the present disclosure is not limited thereto, and according to one or more embodiments, each of the first channel structure 110 and the second channel structure 120 may include a plurality of channel layers to form a nanosheet transistor or a fork sheet transistor, or include one or more fin structures to form a FinFET.

[0071] Provided below is a method for manufacturing a 3D stacked semiconductor device 10 according to one or more embodiments, wherein a first-level transistor (first transistor 10L) and a second-level transistor (second transistor 10U) have channel structures and source / drain regions that are different in size and material.

[0072] Figure 2A-2E to Figures 15A-15E A semiconductor device structure is shown after corresponding steps of manufacturing a 3D stacked semiconductor device according to one or more embodiments, wherein the channel structure, source / drain region, and gate structure of transistors of a first level are different from the channel structure, source / drain region, and gate structure of transistors of a second level in terms of size and material.

[0073] It should be noted here that Figures 2A-2D to Figures 15A-15DIt is taken along lines I-I', II-II', III-III' and IV-IV' Figures 2E to 15E 1 is a corresponding cross-sectional view of a semiconductor device structure 10 ′ shown in FIG. Figures 2E to 15E is a corresponding plan view of the semiconductor device structure 10'. However, it will be understood here that Figures 2E to 15E Only selected structures are shown to help understand the Figures 2A-2D to Figures 15A-15D Therefore, the Figures 2A-2D to Figures 15A-15D Structural elements on or above the selected structure shown in the Figures 2E to 15E Shown in.

[0074] Due to the Figure 2A-2E to Figures 15A-15E The 3D stacked semiconductor device manufactured by the various steps shown in Figures 1A-1E The 3D stacked semiconductor device 10 shown in FIG. 1 is the same as or may correspond thereto, so a repeated description thereof may be omitted and the same reference numerals may be used in the following description.

[0075] Figure 2A-2E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a first channel stack 110 ′, a sacrificial stack 140 ′, and a second channel stack 120 ′ are formed on a substrate 101 and surrounded by a first dummy gate structure 115 ′.

[0076] Reference Figure 2A-2E , a semiconductor device structure 10' may be formed by epitaxially growing a plurality of semiconductor layers one by one from a substrate 101 to sequentially form a first channel stack 110', a sacrificial stack 140', and a second channel stack 120' on the substrate 101. In addition, a first dummy gate structure 115' may be formed to surround the first channel stack 110', the sacrificial stack 140', and the second channel stack 120' with an additional gate (EG) layer 117 therebetween.

[0077] The substrate 101 may be a silicon (Si) substrate. Additionally or alternatively, it may include other materials, such as silicon germanium (SiGe), silicon carbide (SiC), but is not limited thereto. The first channel stack 110' may include a first sacrificial layer 111 and a first channel layer 112 vertically stacked on the substrate 101 in an alternating manner. In the first channel stack 110', the first channel layer 112 may be inserted between two adjacent first sacrificial layers 111. A sacrificial stack 140' may be formed on the first channel stack 110'. A second channel stack 120' may be formed on the sacrificial stack 140', which may include a second sacrificial layer 121 and a second channel layer 122 vertically stacked on the sacrificial stack 140' in an alternating manner. In the second channel stack 120', in addition to the uppermost second channel layer 122 being inserted between the uppermost second sacrificial layer 121 and the additional gate (EG) layer 117, the second channel layer 122 may be inserted between two adjacent second sacrificial layers 121. The sacrificial stack 140 ′ may be interposed between the uppermost first sacrificial layer 111 and the lowermost second sacrificial layer 121 .

[0078] In the first channel stack 110', the first sacrificial layer 111 may be formed of silicon germanium (SiGe), and the first channel layer 112 may be formed of silicon (Si). In contrast, in the second channel stack 120', the second sacrificial layer 121 may be formed of Si, and the second channel layer 122 may be formed of SiGe. The sacrificial stack 140' may also be formed of SiGe. However, for the purpose of etching selectivity, the concentration of germanium (Ge) in the sacrificial stack 140' may be higher than the concentration of germanium (Ge) in the first sacrificial layer 111 and the second channel layer 122, as will be described later. For example, the sacrificial stack 140' may have a Ge concentration of 50-60%, while the first sacrificial layer 111 and the second channel layer 122 may have a Ge concentration of 20-30%. However, the present disclosure is not limited to these specific percentages, as long as the sacrificial stack 140' has a higher Ge concentration than the first sacrificial layer 111 and the second channel layer 122 to allow sufficient etching selectivity for the first sacrificial layer 111 and the second channel layer 122.

[0079] Here, the sacrificial stack 140 ′, the first sacrificial layer 111 , and the second sacrificial layer 121 are named as such because these structural elements will be removed and replaced by other layers or structures in subsequent steps of manufacturing the 3D stacked semiconductor device.

[0080] After forming the second channel stack 120' above the sacrificial stack 140', a portion of the second channel stack 120' may be etched back from the top so that the second channel stack 120' may have a smaller width than the first channel stack 110' in the D1 direction, as shown in FIG. Figure 1C and Figure 1DAs shown. Such partial removal of the second channel stack 120' can be performed by, for example, photolithography, masking, and dry etching, but is not limited thereto. As will be described later, such partial removal of the second channel stack 120' can be performed to have a smaller width, thereby controlling the width of the first source / drain region to be grown from the first channel layer 112 in the first channel stack 110' to be smaller than the width of the second source / drain region to be grown from the second channel layer 122 in the second channel stack 120', as described above with reference to Figure 1C and Figure 1D described.

[0081] The EG layer 117 may be formed to surround the first channel stack 110', the sacrificial stack 140', and the partially removed second channel stack 120' on the substrate 101 to protect the surrounding structures at least during various processes including partially removing the first dummy gate structure 115' in the next step. The EG layer 117 may be formed by, for example, silicon oxide (e.g., SiO or SiO 2 ) is formed by atomic layer deposition, but is not limited to this.

[0082] The first dummy gate structure 115' may be formed to surround the first channel stack 110', the sacrificial stack 140', and the partially removed second channel stack 120', with the EG layer 117 therebetween. The purpose of forming the first dummy gate structure 115' is to protect the channel stacks 110' and 120' from various processes such as deposition and etching performed in subsequent processes for manufacturing a 3D stacked semiconductor device to form surrounding structures. The first dummy gate structure 115' may also be used to define the size of the channel layers 112 and 122 of the 3D stacked semiconductor device. The formation of the first dummy gate structure 115' may be performed by depositing a material such as silicon nitride (e.g., SiN, SiBCN, SiCN, SiOCN, etc.) by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or a combination thereof, followed by planarization such as chemical mechanical polishing (CMP), but is not limited thereto.

[0083] Prior to the epitaxial growth of the channel stacks 110' and 120', the substrate 101 may be patterned to form shallow trench isolation (STI) structures 108 at its upper left and upper right corners with STI pads 106 therebetween to isolate the semiconductor device structure 10' or a 3D stacked semiconductor device to be fabricated from the semiconductor device structure 10' from one or more adjacent semiconductor devices or circuit elements. The STI structures 108 may include silicon oxide (e.g., SiO or SiO 2 ), but not limited thereto, the STI liner 106 may include silicon nitride (eg, SiN or Si 3 N 4), but are not limited to them.

[0084] Figures 3A-3E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein the first dummy gate structure 115 ′ is partially removed to surround only the first channel stack 110 ′.

[0085] Reference Figures 3A-3E , the first dummy gate structure 115' may be partially etched back so that its top surface is placed at a level between the top surface and the bottom surface of the sacrificial stack 140'. This partial etching operation may be performed on the semiconductor device structure 10' to expose a portion of the EG layer 117 surrounding the second channel stack 120' and the upper portion of the sacrificial stack 140', while the lower portions of the first channel stack 110' and the sacrificial stack 140' are surrounded on the side by the first dummy gate structure 115'.

[0086] The partial removal of the first dummy gate structure 115 ′ in this step may be performed by, for example, dry etching, but is not limited thereto.

[0087] Figures 4A-4E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a second dummy gate structure 125 ′ is formed on the first dummy gate structure 115 ′ to surround the second channel stack 120 ′.

[0088] Reference Figures 4A-4E , a second dummy gate structure 125 ′ may be formed to surround the second channel stack 120 ′ and the upper portion of the sacrificial stack 140 ′ having the EG layer 117 thereon, which is exposed by partially etching the first dummy gate structure 115 ′ in the previous step.

[0089] The formation of the second dummy gate structure 125 ′ may be performed by depositing a material such as amorphous silicon (a-Si) or polysilicon (p-Si) by, for example, PVD, CVD, PECVD, or a combination thereof and then planarizing by, for example, CMP, but is not limited thereto.

[0090] As will be described later, the first dummy gate structure 115' and the second dummy gate structure 125' can be formed to surround the first channel stack 110' and the second channel stack 120', respectively, to at least form corresponding gate structures that replace the two dummy gate structures in different steps (i.e., front side process and back side process).

[0091] Figures 5A-5E A semiconductor device structure 10 ′ is shown in accordance with one or more embodiments, wherein a second dummy gate structure 125 ′ is patterned to form a first semiconductor stack 10A, a second semiconductor stack 10B, and a third semiconductor stack 10C.

[0092] Reference Figures 5A-5E , the second dummy gate structure 125' having the EG layer 117 thereon can be patterned by, for example, directional dry etching (such as reactive ion etching (RIE)) based on the hard mask pattern 161 and the mask protection pattern 171 respectively formed thereon as mask structures. Through this etching operation, the second dummy gate structure 125' can be divided into three second dummy gate structures 125' with the first opening O1 and the second opening O2 therebetween. Therefore, the uppermost second channel layer 122 of the second channel stack 120' can be exposed through the first opening O1 and the second opening O2.

[0093] In addition, the sacrificial stack 140' may be removed by, for example, selective etching (such as dry etching or wet etching using hydrofluoric acid (HF)), which selectively etches the sacrificial stack 140' formed of silicon germanium (SiGe) with a high germanium (Ge) concentration of 50-60% relative to the first sacrificial layer 111 formed of SiGe with a low Ge concentration of 20-30% and the first channel layer 112 formed of silicon (Si), the second sacrificial layer 121 also formed of silicon (Si), and the second channel layer 112 formed of SiGe with a low Ge concentration of 20-30%. Subsequently, in the space provided by removing the sacrificial stack 140', a dielectric material (not limited thereto) such as silicon nitride (e.g., SiBCN, SiCN, SiOCN, SiN, etc.) may be filled to form the intermediate isolation structure 140.

[0094] In addition, silicon oxide or silicon nitride (e.g., SiO) may be deposited by, for example, ALD, plasma enhanced ALD (PEALD), PVD, CVD, PECVD, or a combination thereof. 2 , SiN, SiBCN, SiCN, SiOC, SiOCN, etc.) and then dry etching is performed to form a gate spacer 151 on the side surface of each divided second dummy gate structure 125', but is not limited thereto. The gate spacer 151 can be formed to isolate or protect the first dummy gate structure 115' and the second dummy gate structure 125' (and the first gate structure and the second gate structure that will replace the first dummy gate structure 115' and the second dummy gate structure 125' in a later step) from oxidation in a subsequent process of manufacturing a 3D stacked semiconductor device.

[0095] The hard mask pattern 161 may include a dielectric material such as silicon nitride (SiN), titanium nitride (TiN), or silicon oxynitride (SiON), but is not limited thereto. The mask protection pattern 171 may be made of silicon oxide (eg, SiO or SiO 2When the gate spacer 151 is formed on the side surfaces of the first dummy gate structure 115 ′ and the second dummy gate structure 125 ′, the mask protection pattern 171 may protect the hard mask pattern 161 .

[0096] Figures 6A-6E A semiconductor device structure 10 ′ is shown according to one or more embodiments, wherein Figure 5A , Figure 5B and Figure 5D The second channel stack 120 ′ shown in FIG. 1 is patterned to provide a space for forming a second source / drain region therein between the first semiconductor stack 10A, the second semiconductor stack 10B, and the third semiconductor stack 10C.

[0097] Reference Figures 6A-6E , the first to third semiconductor stacks 10A, 10B, and 10C obtained in the previous step may be used as a mask structure to etch downward through the first opening O1 and the second opening O2 Figure 5A , Figure 5B and Figure 5D The second channel stack 120 ′ shown in FIG. 1 is formed by a semiconductor stack 120 ′ to obtain three second channel structures 120 respectively included in the first semiconductor stack 10A, the second semiconductor stack 10B and the third semiconductor stack 10C.

[0098] Through this etching operation, the top surface of the intermediate isolation structure 140 and the side surface of each second channel structure 120 can be exposed through the first opening O1 and the second opening O2. For example, two opposite side surfaces of each second sacrificial layer 121 and two opposite side surfaces of each second channel layer 122 in the second channel structure 120 of the second semiconductor stack 10B can be exposed through the first opening O1 and the second opening O2, respectively. In addition, the right side surface of each second sacrificial layer 121 and the right side surface of each second channel layer 122 in the second channel structure 120 of the first semiconductor stack 10A can be exposed through the first opening O1, and the left side surface of each second sacrificial layer 121 and the left side surface of each second channel layer 122 in the second channel structure 120 of the third semiconductor stack 10C can be exposed through the second opening O2.

[0099] In addition, the etching operation in this step may be performed by, for example, dry etching such as reactive ion etching (RIE), but is not limited thereto, so that in each of the first opening O1 and the second opening O2, side surfaces of the second sacrificial layer 121 and the second channel layer 122 are vertically aligned or coplanar with each other and with the side surface of the gate spacer 151. As will be described later, a second source / drain region may be formed based on the second channel layer 122 of the first semiconductor stack 10A, the second semiconductor stack 10B, and the third semiconductor stack 10C exposed through the first opening O1 and the second opening O2.

[0100] Figures 7A-7E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein each second sacrificial layer 121 is partially etched at a side surface thereof to form a sacrificial spacer 126 ′ on the etched side surface.

[0101] Reference Figures 7A-7E A selective etching operation can be performed on the side surface of the second sacrificial layer 121 formed of silicon (Si) to make the side surface of each second sacrificial layer 121 recessed relative to the side surface of the second channel layer 122 formed of silicon germanium (SiGe) and the intermediate isolation structure 140 formed of silicon nitride (e.g., SiBCN, SiCN, SiOCN, SiN, etc.), and a sacrificial spacer 126' can be formed in the space where the second sacrificial layer 121 is partially removed.

[0102] For the selective etching operation in this step, dry etching or wet etching may be performed using an etchant (e.g., sulfur hexafluoride (SF), tetramethylammonium hydroxide (TMAH), or potassium hydroxide (KOH), but not limited thereto), which may etch the second sacrificial layer 121 of Si relative to the second channel layer 122 of SiGe and the intermediate isolation structure 140 of silicon nitride (e.g., SiBCN, SiCN, SiOCN, SiN, etc.). In order to form the sacrificial spacer 126', a material such as silicon nitride (e.g., SiN, SiBCN, SiCN, SiOCN, etc.) which may be different from the material of the intermediate isolation structure 140 may be deposited by, for example, ALD, PVD, PEALD, CVD, PECVD, or a combination thereof (not limited thereto), so that the side surfaces of the gate spacer 151, the second channel layer 122, and the sacrificial spacer 126' may be vertically aligned or coplanar with each other in the openings O1 and O2.

[0103] Forming a sacrificial spacer 126' of silicon nitride on the side surface of the etched Si second sacrificial layer 121 may be performed to prevent Si from epitaxially growing from the second sacrificial layer 121 when forming the first source / drain region from the Si first channel layer 112 in a later step ( Figures 10A-10E ).

[0104] Figures 8A-8E A semiconductor device structure 10 ′ is shown according to one or more embodiments, wherein Figures 7A-7D The first channel stack 110 ′ and the substrate 101 thereunder shown in FIG. 1 are patterned to provide spaces for forming first source / drain regions and placeholder structures therein between the first semiconductor stack 10A, the second semiconductor stack 10B, and the third semiconductor stack 10C.

[0105] Reference Figures 8A-8E , the first semiconductor stack 10A, the second semiconductor stack 10B, and the third semiconductor stack 10C may be used as a mask structure to etch downward through the first opening O1 and the second opening O2 Figures 7A-7D The intermediate isolation structure 140 on the substrate 101 and the first channel stack 110' thereunder are formed to obtain three intermediate isolation structures 140 and three first channel structures 110 respectively included in the first semiconductor stack 10A, the second semiconductor stack 10B and the third semiconductor stack 10C. In addition, the top surface thereof can be etched downward by etching Figures 7A-7D The first channel stack 110 ′ is shown to expose the substrate 101 to form a first groove R1 and a second groove R2 in the substrate 101. Figures 7A-7D The first channel stack 110 ′ and Figure 5A , Figure 5B and Figure 5D The first opening O1 and the second opening O2 formed by the second channel stack 120 ′ shown in FIG. 1 may be connected to the first recess R1 and the second recess R2 , respectively.

[0106] The etching operation in this step can be performed by, for example, dry etching (such as reactive ion etching (RIE)), but not limited thereto, so that in each of the extended first opening O1 and the extended second opening O2, the side surfaces of the first sacrificial layer 111, the first channel layer 112 and the intermediate isolation structure 140 can be vertically aligned or coplanar with the side surfaces of the second channel layer 122, the sacrificial spacer 126' and the gate spacer 151.

[0107] As will be described later, Figures 7A-7D The first channel stack 110' shown in FIG. 1 may be patterned in this step to provide a space for forming a first source / drain region based on the first channel layer 112 exposed through the first opening O1 and the second opening O2. In addition, the substrate 101 may be etched to form a first recess R1 and a second recess R2, in which a placeholder structure for a backside contact structure of the first source / drain region will be formed in the next step.

[0108] Figures 9A-9EA semiconductor device structure 10' according to one or more embodiments is shown, wherein each of the first sacrificial layer 111 and the second channel layer 122 is partially etched at side surfaces thereof to form a first inner spacer 116 on the etched side surfaces, and further, a placeholder structure 109' is formed in each of the first recess R1 and the second recess R2 obtained in the previous step.

[0109] Reference Figures 9A-9E , a selective etching operation may be performed on the side surfaces of the first sacrificial layer 111 and the second channel layer 122 formed of SiGe so that the side surface of each of these layers is recessed. In addition, the first inner spacer 116 may be formed in the space where the first sacrificial layer 111 and the second channel layer 122 are respectively removed. Through this selective etching operation, the length of the second channel layer 122 becomes smaller than the length of the first channel layer 112. For example, as Figure 1F As shown, the second channel layer 122 may have a second length L21 that is smaller than the first length L11 of the first channel layer 112 .

[0110] When the 3D stacked semiconductor device is completed, the first inner spacer 116 formed on the side surface of the first sacrificial layer 111 can isolate the first gate structure used to replace the first sacrificial layer 111 from the first source / drain region to be formed from the first channel layer 112, and the sacrificial spacer 126' formed on the side surface of the second sacrificial layer 121 will be removed together with the first inner spacer 116 for additional front-side processing in a later step.

[0111] For the selective etching operation in this step, dry etching or wet etching can be applied using an etchant such as chlorine / oxygen (Cl 2 / O 2 ), hydrofluoric acid (HF) and ammonium fluoride (NH 4 F), but not limited thereto, which can etch the first sacrificial layer 111 and the second channel layer 122 of SiGe relative to the first channel layer 112 of Si, the sacrificial spacer 126' of silicon nitride, and the intermediate isolation structure 140 of silicon nitride. In order to form the first inner spacer 116, a material (such as silicon nitride) that can form the sacrificial spacer 126' can be deposited by, for example, ALD, PVD, PEALD, CVD, PECVD or a combination thereof, but not limited thereto, so that the side surface of the first inner spacer 116 can be vertically aligned or coplanar with the side surfaces of the first channel layer 112, the intermediate isolation structure 140, the sacrificial spacer 126' and the gate spacer 151 in each of the first opening O1 and the second opening O2.

[0112] After forming the first inner spacer 116 as described above, a placeholder structure 109' may be formed in the first recess R1 and the second recess R2 to reserve space for forming a corresponding backside contact structure in a later step. In the later step, the backside contact structure may be respectively connected to the bottom surface of the first source / drain region to be formed thereover. The formation of the placeholder structure 109' may be performed by, for example, ALD, PVD, PEALD, CVD, PECVD, or a combination thereof and then planarizing, so that the top surface of each placeholder structure 109' may be at a level below the bottom surface of the lowermost first channel layer 112. The material forming the placeholder structure 109' may be, for example, silicon germanium (SiGe), but is not limited thereto.

[0113] Figures 10A-10E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a first source / drain region 135 is formed from a first channel layer 112 in a first opening O1 and a second opening O2 .

[0114] Reference Figures 10A-10E The first source / drain region 135 may be epitaxially grown from the first channel layer 112 of silicon (Si) exposed in the first opening O1 and the second opening O2 while the first sacrificial layer 111, the second sacrificial layer 121, and the second channel layer 122 are respectively covered by the first inner spacer 116 and the sacrificial spacer 126'.

[0115] The first source / drain region 135 may also be formed of silicon (Si) and may be doped with impurities such as phosphorus (P), arsenic (As), antimony (Sb), etc. Therefore, the first transistor formed based on the first channel layer 112 and the first source / drain region 135 will be an n-type transistor.

[0116] Figures 11A-11E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a front side isolation structure 141 is formed on the first source / drain region 135 , and sacrificial spacers 126 ′ and first inner spacers 116 on side surfaces of the second channel structure 120 are removed.

[0117] Reference Figures 11A-11E , the first front side isolation structure 141 can be formed to isolate the first source / drain region 135 from other circuit elements including a second source / drain region to be formed at a second level in a later step. The first front side isolation structure 141 can be formed by, for example, depositing silicon oxide (e.g., SiO or SiO 2), but not limited thereto, and then planarization (eg, CMP) is performed so that a top surface thereof is at a level below a bottom surface of the lowermost second channel layer 122 in each of the first opening O1 and the second opening O2.

[0118] In addition, the sacrificial spacers 126′ on the side surface of the second sacrificial layer 121 and the first inner spacers 116 on the side surface of the second channel layer 122 can be etched by using an etchant (eg, chlorotrifluoromethane / oxygen (CHF 3 / O 2 ) or hot phosphoric acid (H 3 PO 4 ), but not limited to this), is removed by dry etching or wet etching of the etchant that can etch silicon nitride relative to silicon oxide. Through this operation, the second sacrificial layer 121 and the second channel layer 122 can be exposed through the first opening O1 and the second opening O2. Here, when the sacrificial spacer 126' and the first inner spacer 116 are removed at the second level of the semiconductor device structure 10', each of the first opening O1 and the second opening O2 can become wider at the second level than at the first level. Therefore, when the second source / drain region is epitaxially grown from the second channel layer 122 in a later step, the length of the second source / drain region can become greater than the length of the first source / drain region 135 grown from the first channel layer 112 at the first level.

[0119] Figures 12A-12E A semiconductor device structure 10 ′ according to one or more embodiments is shown, in which each second sacrificial layer 121 is partially etched again at a side surface thereof to form a second inner spacer 126 on the etched side surface.

[0120] Reference Fig. 12A and Fig.12D , a selective etching operation may be performed on the side surfaces of the second sacrificial layers 121 formed of Si to recess the side surfaces of each second sacrificial layer 121 relative to the side surfaces of the second channel layer 122 formed of SiGe and the front side isolation structure 141 of silicon oxide. Subsequently, a second inner spacer 126 may be formed in the space where the portion of the second sacrificial layer 121 is removed.

[0121] For the selective etching operation in this step, dry etching or wet etching may be performed using an etchant (e.g., sulfur hexafluoride (SF), tetramethylammonium hydroxide (TMAH), or potassium hydroxide (KOH), but not limited thereto), which may etch the second sacrificial layer 121 of Si relative to the second channel layer 122 of SiGe and the front side isolation structure 141 of silicon oxide. In order to form the second inner spacer 126, a material such as silicon nitride (e.g., SiN, SiBCN, SiCN, SiOCN, etc.) which may be different from the material of the gate spacer 151 may be deposited by, for example, ALD, PVD, PEALD, CVD, PECVD, or a combination thereof (not limited thereto), so that the side surfaces of the second channel layer 122 and the second inner spacer 126 may be vertically aligned or coplanar with each other in each of the first opening O1 and the second opening O2.

[0122] The second inner spacer 126 may be formed on the side surface of the etched second sacrificial layer 121 to isolate the second gate structure replacing the second sacrificial layer 121 in a later step from the second source / drain region also formed from the second channel layer 122 in a later step. Figures 7A-7E In addition to the previously described etching operation, the second sacrificial layers 121 are shortened again by the etching operation in this step, so the length of each second sacrificial layer 121 becomes smaller than the length of each first sacrificial layer 111. Therefore, in the following steps, the length of the second gate structure for replacing the second sacrificial layer 121 will be smaller than the length of the first gate structure for replacing the first sacrificial layer 111.

[0123] Figures 13A-13E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein the second source / drain region 145 is formed from the second channel layer 122 in the first opening O1 and the second opening O2 .

[0124] Reference Figures 13A-13E , the second source / drain region 145 may be epitaxially grown from the second channel layer 122 of SiGe exposed in the first opening O1 and the second opening O2 on the front isolation structure 141, while the second sacrificial layer 121 of Si is covered by the second inner spacer 126. At this time, the second source / drain region 145 may also be formed of SiGe, and may be doped with impurities such as boron (b), gallium (Ga), indium (In), etc., and therefore, the second transistor formed based on the second channel layer 122 and the second source / drain region 145 at the second level will be a p-type transistor.

[0125] Here, each second source / drain region 145 may be at a wider portion in the D1 direction (that is, at a second level based on the second channel layer 122 having a smaller length, as shown in FIG. Figures 9A-9E and Figures 11A-11E The second source / drain region 145 may be formed in each of the openings O1 and O2. Therefore, the length of the second source / drain region 145 may become greater than the first source / drain region 135 at the first level therebelow. Figure 1F As shown in , the second source / drain region 145 may have a fourth length L22 greater than the third length L12 of the first source / drain region 135 .

[0126] However, when the second channel layer 122 has a width smaller than the first channel layer 112, each second source / drain region 145 may have a width smaller than the first source / drain region 135, as shown in FIG. Figures 1A-1E described.

[0127] Figures 14A-14E 1 shows a semiconductor device structure 10 ′ according to one or more embodiments, wherein a front side isolation structure 141 is extendedly formed on the second source / drain region 145, and Figures 13A-13C The hard mask pattern 161 and the mask protection pattern 171 shown in FIG. 1 may be removed.

[0128] Reference Figures 14A-14E , the front side isolation structure 141 may be additionally formed to surround the second source / drain region 145 to isolate the second source / drain region 145 from the first source / drain region 135 and other circuit elements. In addition, each of the first semiconductor stack 10A, the second semiconductor stack 10B, and the third semiconductor stack 10C may be removed. Figures 13A-13C The hard mask pattern 161 and the mask protection pattern 171 shown in FIG. 1 are formed to expose the top surface of the second dummy gate structure 125 ′ through the gate spacer 151 surrounding the second dummy gate structure 125 ′.

[0129] The additional formation of the front side isolation structure 141 can be performed by, for example, depositing silicon oxide (e.g., SiO or SiO 2 ) to execute, but is not limited to this. Figures 13A-13C The removal of the hard mask pattern 161 and the mask protection pattern 171 shown in can be performed by, for example, stripping, ashing, dry etching, or wet etching, but is not limited thereto, so that the top surfaces of the gate spacer 151, the second dummy gate structure 125', and the front side isolation structure 141 are horizontally aligned or coplanar with each other.

[0130] Figures 15A-15E A semiconductor device structure 10 ′ is shown in accordance with one or more embodiments, wherein the second dummy gate structure 125 ′, an upper portion of the EG layer 117 , and the second sacrificial layer 121 are removed.

[0131] Reference Figures 15A-15E, an etchant (e.g., nitric acid (HNO 3 ) and a mixture of hydrofluoric acid (HF), but not limited thereto) by, for example, dry etching, wet etching, or a combination thereof (but not limited thereto) to remove Figures 14A-14E The second dummy gate structure 125', the upper portion of the EG layer 117 surrounding the second channel structure 120, and the second sacrificial layer 121 shown in the figure are exposed in the previous step to release the second channel layer 122 of the second channel structure 120 forming the semiconductor device structure 10'.

[0132] Therefore, in the semiconductor device structure 10', Figures 14A-14E The second dummy gate structure 125 ′ and the second channel layer 122 of SiGe surrounded by the second sacrificial layer 121 shown in FIG. 1 may be released to an open space where a second gate structure will be formed at a second level of the semiconductor device structure 10 ′ in a next step.

[0133] Figures 16A-16E A semiconductor device structure 10 ′ is shown according to one or more embodiments, wherein the second gate structure 125 is formed by removing Figures 14A-14E The second dummy gate structure 125 ′, the upper portion of the EG layer 117 and the second sacrificial layer 121 are provided in the space shown in FIG.

[0134] Reference Figures 16A-16E The second gate structure 125 surrounding the second channel layer 122 may be formed by, for example, PVD, CVD, PECVD, ALD, PEALD, or a combination thereof (but not limited thereto) after removing the second gate structure 125. Figures 14A-14E The second dummy gate structure 125 ′, the upper portion of the EG layer 117 and the second sacrificial layer 121 are formed in a space obtained by the above-mentioned steps.

[0135] To form the second gate structure 125, a gate dielectric layer including an interfacial layer and a high-k dielectric layer may first be layered to surround the second channel layer 122. The interfacial layer may be provided to protect the second channel layer 122 and promote growth of the high-k dielectric layer thereon, and the high-k dielectric layer may be formed to allow for increased gate capacitance without associated current leakage at the second gate structure 125. For these purposes, the interfacial layer may be made of a material such as silicon oxide (SiO or SiO 2 ) and / or silicon oxynitride (SiON), but not limited thereto, and the high-k dielectric layer can be formed of a high-k material such as Hf, Al, Zr, La, Mg, Ba, Ti, Pb and / or a combination thereof, but not limited thereto.

[0136] A work function metal layer and a gate electrode may be formed on the gate dielectric layer. The work function metal layer may control the threshold voltage of the second transistor formed by the second gate structure 125. For these purposes, the work function metal layer may include a metal such as Ti, Ta, Al, W, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, and / or a combination thereof, but is not limited thereto. When the second gate structure 125 is formed as a gate structure for a p-type transistor, it may include TiN, and when the second gate structure 125 is formed as a gate structure for an n-type transistor, it may include Al or TiC. The gate electrode may be formed of Cu, W, Al, Ru, Mo, Co and / or a combination thereof, but is not limited thereto.

[0137] Figures 17A-17E A semiconductor device structure 10 ′ is shown in which a front side contact structure 119 and a BEOL layer 160 are formed according to one or more embodiments.

[0138] Reference Figures 17A-17E , the front side contact structure 119 may be formed by, for example, performing dry etching or wet etching on the front side isolation structure 141 to form a hole therein exposing the top surface of the second source / drain region 145, and forming the front side contact structure 119 in the hole by, for example, CVD, PVD, PECVD, or a combination thereof, so that the top surfaces of the second source / drain regions 145 may be respectively connected to the front side contact structure 119. In addition, a BEOL layer 160 including one or more metal lines may be formed on the top surface of the semiconductor device structure 10' obtained in the previous step, so that the front side contact structure 119 is connected to the metal line of the BEOL layer 160. The formation of the BEOL layer 160 may be performed by, for example, a damascene process, but is not limited thereto.

[0139] The second source / drain region 145 may be connected to one or more voltage sources or other circuit elements for internal wiring purposes in view of the front side contact structure 119 and the BEOL layer 160. The metal lines included in the front side contact structure 119 and the BEOL layer 160 may be formed of metals such as Cu, W, Al, Ru, Mo, Co, etc., and various compounds or alloys thereof.

[0140] Figures 18A-18E A semiconductor device structure 10 ′ is shown with the semiconductor device 10 ′ removed therefrom according to one or more embodiments. Figures 17A-17E The substrate 101 is shown in FIG.

[0141] Reference Figures 18A-18E , you can remove Figures 17A-17E101 is removed from the substrate 101 shown in the figure to expose the placeholder structures 109' formed on the bottom surfaces of the first source / drain regions 135, respectively. The removal of the substrate 101 can be performed by, for example, wet etching using an etchant (e.g., sulfur hexafluoride (SF), tetramethylammonium hydroxide (TMAH), or potassium hydroxide (KOH), but not limited thereto), which can be etched with respect to the placeholder structures 109' of SiGe and silicon nitride (e.g., SiN or Si 3 N 4 )'s STI liner 106 is selectively etched to form the Si substrate 101.

[0142] Although not shown in the drawings, the substrate removal process in this step and subsequent steps to be described below may be performed after inverting the semiconductor device structure 10 ′ obtained in the previous step.

[0143] Figures 19A-19E A semiconductor device structure 10 ′ is shown in accordance with one or more implementations, wherein contact spacers 107 are formed on side surfaces of placeholder structures 109 ′, and an initial backside isolation structure 142 ′ is formed around the placeholder structure 109 ′ having the contact spacers 107 thereon.

[0144] Reference Figures 19A-19E , Figures 18A-18E The STI structure 108 and the STI liner 106 shown in the figure can be removed by, for example, dry etching or wet etching, and a contact spacer 107 including silicon nitride (such as SiN, SiBCN, SiCN, SiOCN, etc.) (but not limited thereto) can be formed on the side surface of each placeholder structure 109' by, for example, ALD, PEALD, PVD, CVD, PECVD or a combination thereof. In addition, a contact spacer 107 including silicon oxide (SiO, SiO 2 An initial backside isolation structure 142' of the structure shown in FIG. 1 may be formed to surround each placeholder structure 109' having the contact spacer 107 thereon. In addition, the bottom surface of each placeholder structure 109' may be covered by the same material from which the contact spacer 107 is formed, so that the contact spacer 107 may completely surround the bottom surface and side surfaces of each placeholder structure 109'.

[0145] As will be described later, contact spacers 107 may be formed to facilitate self-aligned deposition of metal or metal compounds to form backside contact structures replacing placeholder structures 109'. Capping of placeholder structures 109' may be performed to protect placeholder structures 109' from subsequent processes that form gate structures at the first level of semiconductor device structure 10'.

[0146] Figures 20A-20E A semiconductor device structure 10 ′ is shown according to one or more embodiments, wherein Figures 19A-19EThe initial backside isolation structure 142 ′, the remaining EG layer 117 , the first dummy gate structure 115 ′, and the first sacrificial layer 111 shown in FIG. 1 are removed.

[0147] Reference Figures 20A-20E , Figures 19A-19E The initial backside isolation structure 142′ shown in FIG. 1 can be removed by using an etchant (e.g., carbon tetrafluoride (CF 4 ) or hydrofluoric acid (HF) and ammonium fluoride (NH 4 F) is removed by wet etching or dry etching of a mixture of, but not limited to, a mixture of, the etchant can selectively remove the silicon oxide (e.g., SiO, SiO2) forming the initial backside isolation structure 142' relative to the silicon nitride (e.g., SiN, SiBCN, SiCN, SiOCN, etc.) forming the contact spacer 107. 2 wait).

[0148] also, Figures 19A-19E The first dummy gate structure 115′ of silicon nitride (eg, SiN, SiBCN, SiCN, SiOCN, etc.) shown in FIG. 1 can be etched by using an etchant (eg, chlorotrifluoromethane / oxygen (CHF 3 / O 2 ) or hot phosphoric acid (H 3 PO 4 ), the first sacrificial layer 111 of SiGe and the first channel layer 112 of Si are selectively removed by dry etching or wet etching of (not limited to) . Subsequently, Figures 19A-19E The silicon oxide (eg, SiO, SiO 2 The remaining EG layer 117 of Si (eg, Si) can be selectively removed relative to the first channel layer 112 by, for example, dry etching or wet etching to release the first channel layer 112.

[0149] Figures 21A-21E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein a first gate structure 115 may be formed to surround a first channel layer 112 .

[0150] Reference Figures 21A-21E , the first gate structure 115 may be formed by removing the Figures 19A-19E The initial backside isolation structure 142', the remaining EG layer 117, the first dummy gate structure 115' and the first sacrificial layer 111 are formed in a space provided by the initial backside isolation structure 142' shown in FIG. The formation of the first gate structure 115 may be performed by, for example, PVD, CVD, PECVD, ALD, PEALD or a combination thereof, but is not limited thereto.

[0151] Similar to the second gate structure 125, the first gate structure 115 may further include a gate dielectric layer, a work function metal layer, and a gate electrode, which are formed of the same or similar materials as those included in the second gate structure 125. Therefore, repeated description thereof is omitted here. However, when the first gate structure 115 is to form an n-type transistor and the second gate structure 125 is to form a p-type transistor, the work function metal layer of the first gate structure 115 may be formed of, for example, TiN, and the work function metal layer of the second gate structure 125 may be formed of, for example, Al or TiC, but is not limited thereto.

[0152] Meanwhile, although the second gate structure 125 may be Figures 16A-16E By replacing as shown in reference Figures 7A-7E and Figures 12A-12E The second sacrificial layer 121 of Si etched twice at its side surface is formed, but the first gate structure 115 can be replaced as shown in reference Figures 9A-9E The first gate structure 115 is formed by etching the first sacrificial layer of SiGe at its side surface. Therefore, the first gate structure 115 may have a greater length than the second gate structure 125 in the D1 direction. Figure 1F As shown in , the first gate structure 115 may have a fifth length L13 that is greater than a sixth length L23 of the second gate structure 125 .

[0153] Figures 22A-22E A semiconductor device structure 10 ′ according to one or more embodiments is shown, wherein the first gate structure 115 formed in the previous step is partially etched back, and a backside isolation structure 142 may be formed on the backside of the semiconductor device structure 10 ′.

[0154] Reference Figures 22A-22E The first gate structure 115 formed as a second layer structure surrounding the semiconductor device structure 10' (including the placeholder structure 109' having the contact spacer 107 thereon) can be removed from the bottom to the level of the bottom surface of the first source / drain region 135 or the lowest first inner spacer 116 by, for example, dry etching or wet etching, but is not limited thereto.

[0155] Therefore, although the second gate structure 125 can be Figures 16A-16E Although the first gate structure 115 is formed in the front side process described above, the first gate structure 115 may be formed in the back side process. Therefore, the process deviation occurring during the formation of different gate structures at the first level and the second level of the 3D stacked semiconductor device may be easily controlled.

[0156] After the first gate structure 115 is formed as described above, a backside isolation structure 142 may be formed on the back side of the semiconductor device structure 10′ to surround the placeholder structure 109′ having the contact spacer 107 thereon, such that the bottom surface of the backside isolation structure 142 is horizontally aligned or coplanar with the bottom surface of the contact spacer 107. The backside isolation structure 142 may be formed by, for example, depositing the same material (e.g., SiO, SiO2) as the material forming the frontside isolation structure 141 by PVD, CVD, PECVD, ALD, PEALD, or a combination thereof (but not limited thereto). 2 etc.) and then planarization (e.g. CMP) is performed.

[0157] Figures 23A-23E A semiconductor device structure 10 ′ is shown according to one or more embodiments, wherein the semiconductor device structure 10 ′ is removed from the semiconductor device structure 10 ′. Figures 22A-22E The placeholder structure 109 ′ shown in FIG.

[0158] Reference Figures 23A-23E The bottom cover portion of each contact spacer 107 can be selectively removed relative to the backside isolation structure 142 to expose the Figures 22A-22E The placeholder structure 109 ′ is shown, and the placeholder structure 109 ′ may be removed selectively to the contact spacers 107 and the first source / drain regions 135 formed on the placeholder structure 109 ′.

[0159] The selective removal of the bottom capping portion of the contact spacer 107 and the placeholder structure 109' can be performed by dry etching or wet etching using an etchant such as chlorotrifluoromethane / oxygen (CHF 3 / O 2 ), hot phosphoric acid (H 3 PO 4 ), nitric acid (HNO 3 ) and a mixture of hydrofluoric acid (HF), chlorine / oxygen (Cl 2 / O 2 ), hydrofluoric acid (HF) and ammonium fluoride (NH 4 F) mixtures, but not limited thereto.

[0160] Figures 24A-24E 1 ' shows a semiconductor device structure 10' according to one or more embodiments, wherein the backside contact structures 109 are formed by removing Figures 22A-23E In the space provided by the placeholder structure 109 ′ shown in FIG.

[0161] Reference Figures 24A-24E , the backside contact structure 109 can be formed in a self-aligned manner by removing the contact spacer 107 Figures 22A-23EIn the space provided by each placeholder structure 109' shown in . For example, a metal or a metal compound such as Cu, W, Al, Ru, Mo, Co and / or a combination thereof may be deposited along the inner surface of the contact spacer 107 to fill the space left by the placeholder structure 109' and contact the bottom surface of the first source / drain region 135 thereon. Therefore, possible misalignment between the backside contact structure 109 and the first source / drain region 135 may be avoided.

[0162] The backside contact structure 109 may connect the first source / drain region 135 to a voltage source or another circuit element through one or more metal lines formed below the backside contact structure 109. Thus, the backside contact structure 109 and these metal lines form a BSPDN structure of the 3D stacked semiconductor device.

[0163] Therefore, the semiconductor device structure 10' obtained in this step can be used in the same Figures 1A-1E . For example, in the semiconductor device structure 10', the first channel layer 112 of the p-type transistor can be formed of Si, and the second channel layer 122 of the n-type transistor can be formed of SiGe to utilize the higher hole mobility of the current flow in the p-type transistor. Therefore, the first channel layer 112 can have a greater length in the D1 direction than the second channel layer 122 of SiGe, and the first source / drain region 135 can have a smaller length than the second source / drain region 145 in the same D1 direction. In addition, the first gate structure 115 can have a greater length than the second gate structure 125, and the first gate structure 115 and the second gate structure 125 can be formed by different work function metal layers.

[0164] In addition, when the first gate structure 115 and the second gate structure 125 are formed in the backside process and the frontside process, respectively, the risk of process variation can be reduced. In addition, the formation of the contact spacer 107 can realize the self-aligned formation of the backside contact structure 109, which can respectively reduce the misalignment between the backside contact structure 109 and the bottom surface of the first source / drain region 135 at the first level.

[0165] Figures 25A-25C A flow chart of manufacturing a 3D stacked semiconductor device according to one or more embodiments is shown, wherein reference is made to Figure 2A-2E to Figures 24A-24E , the channel structure, source / drain region and gate structure of the transistors of the first level are different from the channel structure, source / drain region and gate structure of the transistors of the second level in terms of size and material.

[0166] In step S10( Figure 2A-2E), a semiconductor device structure 10' including a first channel stack 110' at a first level and a second channel stack 120' at a second level can be provided on a substrate 101, wherein the first channel stack 110' includes a first sacrificial layer 111 of silicon germanium (SiGe) and a first channel layer 112 of silicon (Si) alternately stacked on the substrate 101, and the second channel stack 120' includes a second channel layer 122 of SiGe (non-Si) and a second sacrificial layer 121 of Si (non-SiGe) alternately stacked on the first channel stack 110'.

[0167] The first sacrificial layer 111 and the first channel layer 112 of the first channel stack 110 ′ and the second sacrificial layer 121 and the second channel layer 122 of the second channel stack 120 ′ may be epitaxially grown one after another from the substrate 101 in an alternating manner until a desired number of layers is obtained.

[0168] In step S20( Figures 3A-3E and Figures 4A-4E ), a first dummy gate structure 115' of silicon nitride may be formed around the first channel stack 110', and a second dummy gate structure 125' of amorphous silicon (a-Si) or polycrystalline (p-Si) may be formed around the second channel stack 120'.

[0169] In step S30 ( Figures 5A-5E and Figures 6A-6E ), the semiconductor device structure 10' having the first dummy gate structure 115' and the second dummy gate structure 125' thereon can be divided into three semiconductor stacks 10A, 10B and 10C at the second level, with two vertical openings therebetween, wherein the side surfaces of the second channel layer 122 and the second sacrificial layer 121 are exposed.

[0170] In step S40( Figures 7A-7E and Figures 8A-8E ), the second sacrificial layer 121 of Si can be partially etched at the side surface, and a sacrificial spacer 126' of silicon nitride can be formed on the etched side surface of the second sacrificial layer 121', and the two openings O1 and O2 can be vertically extended downward to form two corresponding grooves R1 and R2 in the substrate 101, and the side surfaces of the first sacrificial layer 111 and the first channel layer 112 are exposed in the two openings O1 and O2.

[0171] Here, when the second sacrificial layer 121 of Si is partially etched at the side surface thereof, the second sacrificial layer 121 may have a smaller length in the channel length direction than the first sacrificial layer 111 of SiGe which is not partially etched at the side surface thereof at this time.

[0172] In step S50( Figures 9A-9E), a placeholder structure 109' can be formed in each of the grooves R1 and R2 in the substrate 101, and the side surfaces of the first sacrificial layer 111 of SiGe and the second channel layer 122 of SiGe can be partially etched, and a first inner spacer 116 of silicon nitride can be formed on the etched side surfaces of the first sacrificial layer 111 and the second channel layer 122.

[0173] A placeholder structure 109' may be formed in the substrate 101 to reserve space for a backside contact structure 109 to be formed in a later step. The backside contact structure 109 may connect a first source / drain region formed on the backside contact structure in a next step to one or more voltage sources or another circuit element.

[0174] In step S60( Figures 10A-10E ), a first source / drain region 135 of a first transistor may be formed on the placeholder structure 109 ′ based on the first channel layer 112 .

[0175] The first source / drain region 135 may be epitaxially grown from the first channel layer 112 of Si, while the first inner spacer 116 covers the first sacrificial layer 111 of SiGe and the second channel layer 122 of SiGe, and the sacrificial spacer 126' covers the second sacrificial layer 121 of Si. At this time, the first source / drain region 135 of Si may be doped with impurities such as phosphorus (P), arsenic (As), antimony (Sb), etc., so that the first transistor formed at the first level based on the first channel layer 112 and the first source / drain region 135 will be n-type.

[0176] In step S70( Figures 11A-11E and Figures 12A-12E ), the sacrificial spacer 126' on the side surface of the second sacrificial layer 121 and the first inner spacer 116 on the side surface of the second channel layer 122 can be removed together to widen the openings O1 and O2 at the second level and expose the second sacrificial layer 121 and the second channel layer 122 through the widened openings O1 and O2, and the side surface of the second sacrificial layer 121 can be partially etched again, and then a second inner spacer 126 of silicon nitride is formed thereon.

[0177] Here, the second sacrificial layer 121 is partially etched again in addition to the partial etching in step S40 , and thus the second sacrificial layer 121 may have a smaller length in the channel length direction than the first sacrificial layer 111 partially etched once at its side surface in step S50 .

[0178] In step S80( Figures 13A-13E ), a second source / drain region 145 for a second transistor can be formed in the widened openings O1 and O2 based on the second channel layer 121.

[0179] The second source / drain region 145 may be epitaxially grown from the second channel layer 122 of SiGe, while the second sacrificial layer 121 of Si is covered by the second inner spacer 126. At this time, the second source / drain region 145 may also be doped with impurities such as boron (B), gallium (Ga), indium (In), etc., so that the second transistor to be formed at the second level based on the second channel layer 122 and the second source / drain region 145 will be of p-type.

[0180] When the second source / drain regions 145 are formed in the widened openings O1 and O2 , the second source / drain regions 145 may have a greater length than the first source / drain regions 135 , respectively.

[0181] In step S90( Figures 14A-14E to Figures 17A-17E ), the second dummy gate structure 125′ and the second sacrificial layer 121 may be replaced by the second gate structure 125, and thus, the second channel layer 122 may now be surrounded by the second gate structure 125 instead of the second dummy gate structure 125′.

[0182] In step S100( Figures 18A-18E and Figures 19A-19E ), the substrate 101 may be removed, contact spacers 107 may be formed on side surfaces of the placeholder structures 109', respectively, and an initial backside isolation structure 142' may be formed to surround the placeholder structures 109' having the contact spacers 107 thereon.

[0183] In step S110 ( Figures 20A-20E to Figures 22A-22E ), the initial backside isolation structure 142' may be removed, and the first dummy gate structure 115' and the first sacrificial layer 111 may be replaced with the first gate structure 115, and then the backside isolation structure 142 may be formed to surround the placeholder structure 109' having the contact spacer 107 thereon.

[0184] Thus, the first channel layer 112 may now be surrounded by the first gate structure 115. Here, the first gate structure 115 may have a greater length than the second gate structure 125 because the second gate structure 125 replaces the second sacrificial layer 121 that is partially etched twice, while the first sacrificial layer 111 is partially etched once, as described above with reference to step S70.

[0185] In step S120 ( Figures 23A-23E and Figures 24A-24E), the placeholder structure 109′ may be removed, leaving the contact spacer 107 in the backside isolation structure 142, and the backside contact structure 109 may fill the space provided by removing the placeholder structure 109′ in a self-aligned manner based on the contact spacer 107.

[0186] Through the above steps, a 3D stacked semiconductor device 10 can be manufactured so that the channel structure 110 and 120, source / drain regions 135 and 145, and gate structures 115 and 125 of the first transistor 10L at the first level are different in material and size from the channel structure 110 and 120, source / drain regions 135 and 145, and gate structures 115 and 125 of the second transistor 10U at the second level.

[0187] Fig.26 FIG. 1 is a diagram showing a 3D stacked semiconductor device 10 according to one or more embodiments, including the 3D stacked semiconductor device 10 shown in FIG. 1 or as described above with reference to FIG. Figure 2A-2E to Fig.25A -25E is a schematic block diagram of an electronic device of the 3D stacked semiconductor device fabricated as described above.

[0188] Reference Fig.26 , the electronic device 1000 may include at least one processor 1100, a communication module 1200, an input / output (I / O) module 1300, a memory 1400, and a buffer random access memory (RAM) module 1500. According to an embodiment, the electronic device 1000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

[0189] The processor 1100 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or any other processor that controls the operation of the electronic device 1000. The communication module 1200 may be implemented to perform wireless or wired communication with an external device. The input / output module 1300 may include at least one of a touch sensor, a touch panel, a keyboard, a mouse, a proximity sensor, a microphone, etc. for receiving an input, and at least one of a display, a speaker, etc. for generating an output signal processed by the processor 1100. The memory 1400 may be implemented to store user data, output signals, etc. input by the input / output module 1300. The memory 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc.

[0190] The buffer RAM module 1500 may temporarily store data for processing operations of the electronic device 1000. For example, the buffer RAM 1500 may include a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0191] although Fig.26 Although not shown in the figure, the electronic device 1000 may further include at least one sensor, such as an image sensor.

[0192] According to one or more embodiments, at least one component in the electronic device 1000 may be based on the 3D stacked semiconductor device 10 shown in FIG. 1 or as described above with reference to FIG. Figure 2A-2E to Fig.25A -25E is used to form a 3D stacked semiconductor device manufactured as described above.

[0193] The foregoing is a description of exemplary embodiments and should not be construed as limiting the present disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications in the above embodiments are possible without materially departing from the present disclosure.

Claims

1. A semiconductor device, comprising: a first source / drain region connected via a first channel structure controlled by a first gate structure; as well as second source / drain regions, respectively above the first source / drain regions, connected via a second channel structure controlled by a second gate structure, The first channel structure and the second channel structure include different materials.

2. The semiconductor device according to claim 1, wherein The first channel structure includes silicon germanium (SiGe), and the second channel structure includes silicon (Si).

3. The semiconductor device according to claim 1, wherein In a first direction in which the first source / drain regions are connected and the second source / drain regions are connected, a length of the first channel structure is different from a length of the second channel structure.

4. The semiconductor device according to claim 3, wherein: The length of the first channel structure is greater than the length of the second channel structure.

5. The semiconductor device according to claim 3, wherein: The length of the first source / drain region is smaller than the length of the second source / drain region. 6 . The semiconductor device according to claim 3 , the length of the first gate structure is greater than the length of the second gate structure.

7. A semiconductor device comprising: a first source / drain region connected via a first channel structure controlled by a first gate structure; as well as second source / drain regions, respectively above the first source / drain regions, connected via a second channel structure controlled by a second gate structure, Wherein, in a first direction in which the first source / drain regions are connected and the second source / drain regions are connected, a length of the first channel structure is different from a length of the second channel structure.

8. The semiconductor device according to claim 7, wherein: The length of the first channel structure is greater than the length of the second channel structure.

9. The semiconductor device according to claim 7, wherein: The length of the first source / drain region is smaller than the length of the second source / drain region.

10. The semiconductor device according to claim 7, wherein: The length of the first gate structure is greater than the length of the second gate structure.

11. The semiconductor device according to claim 7, wherein: The width of the first channel structure is greater than the width of the second channel structure.

12. A semiconductor device comprising: a first source / drain region connected via a first channel structure controlled by a first gate structure; as well as second source / drain regions, respectively above the first source / drain regions, connected via a second channel structure controlled by a second gate structure, wherein, in a first direction in which the first source / drain regions are connected and the second source / drain regions are connected, a length of the first gate structure is different from a length of the second gate structure, and Wherein, the length of the first gate structure is greater than the length of the second gate structure.

13. A semiconductor device comprising: a first source / drain region connected via a first channel structure controlled by a first gate structure; as well as second source / drain regions, respectively above the first source / drain regions, connected via a second channel structure controlled by a second gate structure, Wherein, in a first direction in which the first source / drain regions are connected and the second source / drain regions are connected, a length of the first source / drain region is different from a length of the second source / drain region.

14. The semiconductor device according to claim 13, wherein: The length of the first source / drain region is smaller than the length of the second source / drain region.

15. The semiconductor device according to claim 14, wherein: In a second direction crossing the first direction, a width of the first source / drain region is greater than a width of the second source / drain region.

16. A method for manufacturing a semiconductor device, the method comprising: forming a first channel stack at a first level above a substrate and forming a second channel stack at a second level above the first level, wherein the first channel stack and the second channel stack respectively include different material compositions; forming a first dummy gate structure and a second dummy gate structure to surround the first channel stack and the second channel stack, respectively, wherein the first dummy gate structure and the second dummy gate structure include different materials, respectively; Based on the first channel stack, forming a first source / drain region at the first level; forming a second source / drain region at the second level based on the second channel stack; replacing the second dummy gate structure with a second gate structure; replacing the substrate with a backside isolation structure; and The first dummy gate structure is replaced with a first gate structure.

17. The method according to claim 16, in, The first channel stack is formed by alternately stacking a first sacrificial layer of silicon germanium (SiGe) and a first channel layer of silicon (Si), and The second channel stack is formed by alternately stacking a second channel layer of SiGe and a second sacrificial layer of Si.

18. The method according to claim 17, wherein: The forming of the first source / drain region and the forming of the second source / drain region include: forming a sacrificial spacer at a side surface of the second sacrificial layer; forming a first inner spacer at side surfaces of the first sacrificial layer and the second channel layer; epitaxially growing the first source / drain region from the first channel layer; removing the sacrificial spacer on the side surface of the second sacrificial layer, and removing the first inner spacer on the side surface of the second channel layer; forming a second inner spacer on a side surface of the second sacrificial layer from which the sacrificial spacer is removed; and The second source / drain region is epitaxially grown from the second channel layer.

19. The method according to claim 16, wherein: Replacing the first dummy gate structure with the first gate structure is performed after replacing the substrate with the backside isolation structure.

20. The method of claim 16, further comprising: Before forming the first source / drain region, forming a placeholder structure in the substrate; In the process of replacing the substrate with the backside isolation structure, forming contact spacers on side surfaces of the placeholder structure; as well as The placeholder structure is replaced with a backside contact structure in a self-aligned manner using the contact spacers.

Images