Image sensing device including source follower transistor

Abstract

An image sensing device including a source follower transistor is disclosed. The image sensing device includes a first photoelectric conversion element and a second photoelectric conversion element spaced apart from each other in a semiconductor substrate, pixel isolation structures spaced apart from each other between the first photoelectric conversion element and the second photoelectric conversion element, and a source follower transistor, a gate of the source follower transistor is disposed on the semiconductor substrate within a space between the pixel isolation structures spaced apart from each other.

Description

Technical Field

[0001] The techniques and implementations disclosed in this patent document generally relate to image sensing devices, and more particularly, to an image sensing device including a source follower transistor. Background Art

[0002] An image sensing device is a device that captures at least one image using the semiconductor property of reacting to light incident thereon to generate an image. In recent years, with the continuous development of the information technology (IT) industry and related technologies, the demand for high-quality and high-performance image sensing devices is rapidly increasing in various electronic devices such as smart phones, digital cameras, etc.

[0003] Image sensing devices can be roughly classified into CCD (Charge Coupled Device) based image sensing devices and CMOS (Complementary Metal Oxide Semiconductor) based image sensing devices. Unlike in the past, CMOS image sensing devices have been intensively studied and are rapidly being widely used. Summary of the invention

[0004] Various embodiments of the disclosed technology are directed to an image sensing device having a structure that allows a larger area to be secured for a gate region of a source follower transistor to reduce the amount of noise.

[0005] According to an embodiment of the disclosed technology, an image sensing device may include: a semiconductor substrate, which is configured to include a first surface onto which light from a scene is incident and a second surface facing the first surface or opposite to the first surface; a first photoelectric conversion element and a second photoelectric conversion element, which are arranged to be spaced apart from each other within the semiconductor substrate, each of which generates photocharge by sensing incident light; a first pixel isolation structure, which is recessed from the second surface and is configured to surround the first photoelectric conversion element and the second photoelectric conversion element; a second pixel isolation structure and a third pixel isolation structure, which are arranged to be spaced apart from each other between the first photoelectric conversion element and the second photoelectric conversion element; and a gate of a source follower transistor, which is arranged on the second surface in at least a portion of a gap area between the second pixel isolation structure and the third pixel isolation structure.

[0006] In some implementations, a gate of the source follower transistor may be formed to overlap at least one of the first photoelectric conversion element and the second photoelectric conversion element.

[0007] In some implementations, each of the second pixel isolation structure and the third pixel isolation structure can contact the first pixel isolation structure.

[0008] In some implementations, the image sensing device may further include a fourth pixel isolation structure disposed in the gap region.

[0009] In some implementations, the image sensing device may also include: a first floating diffusion region configured to store photocharges generated by the first photoelectric conversion element in response to incident light; and a second floating diffusion region configured to store photocharges generated by the second photoelectric conversion element in response to incident light.

[0010] In some implementations, the image sensing device may also include: a first transfer transistor, one terminal of which is electrically connected to the first photoelectric conversion element and another terminal of which is electrically connected to the first floating diffusion region; and a second transfer transistor, one terminal of which is electrically connected to the second photoelectric conversion element and another terminal of which is electrically connected to the second floating diffusion region.

[0011] In some implementations, the gate of the first transfer transistor may overlap with the first photoelectric conversion element and may be separated from the gate of the source follower transistor on the second surface of the semiconductor substrate; and the gate of the second transfer transistor may overlap with the second photoelectric conversion element and may be separated from the gate of the source follower transistor on the second surface of the semiconductor substrate.

[0012] In some implementations, the gate of the first transfer transistor may include a structure that is recessed from the second surface of the semiconductor substrate toward the interior of the semiconductor substrate, and may be spaced apart from the first floating diffusion region within the semiconductor substrate; and the gate of the second transfer transistor may include a structure that is recessed from the second surface of the semiconductor substrate toward the interior of the semiconductor substrate, and may be spaced apart from the second floating diffusion region within the semiconductor substrate.

[0013] In some implementations, the image sensing device may further include a reset transistor, a gate of the reset transistor overlapping the first photoelectric conversion element and spaced apart from the gate of the source follower transistor on the second surface of the semiconductor substrate, wherein the reset transistor is configured to drain photocharges stored in the first floating diffusion region and the second floating diffusion region.

[0014] In some embodiments, the image sensing device may also include a selection transistor, a gate of the selection transistor overlapping with the second photoelectric conversion element and separated from the gate of the source follower transistor on the second surface of the semiconductor substrate, wherein the selection transistor outputs an electrical signal having a voltage level corresponding to the photocharge generated by the first photoelectric conversion element or the second photoelectric conversion element.

[0015] In some implementations, the image sensing device may further include a drain transistor, a gate of the drain transistor overlapping the first photoelectric conversion element and spaced apart from the gate of the source follower transistor on the second surface of the semiconductor substrate, wherein the photocharge generated by the first photoelectric conversion element or the second photoelectric conversion element is reset by the drain transistor.

[0016] In some embodiments, the image sensing device may also include a dual conversion gain (DCG) transistor, the gate of the DCG transistor overlapping the first photoelectric conversion element and being separated from the gate of the source follower transistor on the second surface of the semiconductor substrate, wherein the DCG transistor changes the capacitance of at least one of the first transistor and the second transistor.

[0017] According to another embodiment of the disclosed technology, an image sensing device may include: a semiconductor substrate, which is configured to include a first surface onto which light is incident and a second surface facing the first surface or opposite to the first surface; a first photoelectric conversion element, which is disposed in the semiconductor substrate and is configured to generate photocharges in response to the incident light; a second photoelectric conversion element, which is spaced apart from the first photoelectric conversion element in the semiconductor substrate and is configured to generate photocharges in response to the incident light; and a gate of a source follower transistor, which is disposed on the second surface of the semiconductor substrate corresponding to a gap area between the first photoelectric conversion element and the second photoelectric conversion element, wherein the gate of the source follower transistor overlaps with at least a portion of each of the first photoelectric conversion element and the second photoelectric conversion element arranged in a first direction perpendicular to the second surface.

[0018] In some embodiments, the image sensing device may also include: a first transfer transistor, a gate of the first transfer transistor overlapping with the first photoelectric conversion element in the first direction and spaced apart from the gate of the source follower transistor on the second surface of the semiconductor substrate; and a second transfer transistor, a gate of the second transfer transistor overlapping with the second photoelectric conversion element in the first direction and spaced apart from both the gate of the source follower transistor and the gate of the first transfer transistor on the second surface of the semiconductor substrate.

[0019] In some implementations, the image sensing device may further include a floating diffusion region disposed in the semiconductor substrate in a space between a gate of the first transfer transistor and a gate of the second transfer transistor and arranged adjacent to the second surface of the semiconductor substrate.

[0020] In some implementations, the image sensing device may further include: a first floating diffusion region, which is spaced apart from the gate of the first transfer transistor, disposed in the semiconductor substrate, and adjacent to the second surface; and a second floating diffusion region, which is spaced apart from the gate of the second transfer transistor, disposed in the semiconductor substrate, and adjacent to the second surface.

[0021] In some implementations, the image sensing device may include a first floating diffusion region and a second floating diffusion region. The first floating diffusion region may be spaced apart from a gate of the first transfer transistor, may be disposed in a semiconductor substrate, and may be adjacent to a second surface. The second floating diffusion region may be spaced apart from a gate of the second transfer transistor, may be disposed in a semiconductor substrate, and may be adjacent to the second surface.

[0022] In some implementations, the image sensing device may further include a metal interconnect layer configured to contact each of the first floating diffusion region and the second floating diffusion region while being located outside the semiconductor substrate, wherein the metal interconnect layer electrically connects the first floating diffusion region and the second floating diffusion region to each other.

[0023] In some implementations, the image sensing device may further include a pixel isolation structure recessed from the first surface of the semiconductor substrate corresponding to the gap region toward the interior of the semiconductor substrate.

[0024] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0026] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0027] Figure 2 Some implementations based on the disclosed technology are shown in Figure 1 A plan view of an example of a portion of a pixel array is shown.

[0028] Figure 3 Some implementations based on the disclosed technology are shown in Figure 2 A circuit diagram of an example of a unit pixel is shown.

[0029] Figure 4 Some implementations based on the disclosed technology are shown in Figure 2 FIG. 1 is a plan view of an example of a first embodiment of a unit pixel shown in FIG.

[0030] Figure 5 Some implementations based on the disclosed technology are shown in Figure 2 FIG. 2 is a plan view of an example of a second embodiment of a unit pixel shown in FIG.

[0031] Figure 6 Some implementations based on the disclosed technology are shown in Figure 2 FIG. 2 is a plan view of an example of a third embodiment of a unit pixel shown in FIG.

[0032] Figure 7 Some implementations based on the disclosed technology are shown in Figure 2 FIG. 2 is a plan view of an example of a fourth embodiment of a unit pixel shown in FIG.

[0033] Figure 8 is a diagram showing some implementations based on the disclosed technology. Figures 4 to 6 A cross-sectional view of an example of a unit pixel taken along line AA′.

[0034] Fig. 9 is a diagram showing some implementations based on the disclosed technology. Figure 7 A cross-sectional view of an example of a unit pixel taken along line BB′.

[0035] Fig.10 is a diagram showing some implementations based on the disclosed technology. Figure 4 A cross-sectional view of an example of a unit pixel taken along line CC'.

[0036] Fig.11 is a diagram showing some implementations based on the disclosed technology. Figures 4 to 7 A cross-sectional view of an example of a unit pixel taken along line DD'.

[0037] Fig.12 is a diagram showing some implementations based on the disclosed technology. Figures 4 to 7 A cross-sectional view of an example of a unit pixel taken along line EE'. DETAILED DESCRIPTION

[0038] This patent document provides implementations and examples of image sensing devices including source follower transistors that can be used in a configuration that substantially solves one or more technical or engineering problems and alleviates limitations or disadvantages encountered in some image sensing devices in the art. Some implementations of the disclosed technology relate to an image sensing device including a structure that can ensure a larger gate area for the source follower transistor to reduce the amount of noise. Recognizing the above problems, the image sensing device can reduce the amount of noise generated in the electrical signal output from the pixel by ensuring a large gate area for the source follower transistor.

[0039] Reference will now be made in detail to some embodiments of the disclosed technology, examples of which are shown in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the accompanying drawings to represent the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0040] Figure 1 is a block diagram illustrating an example of an image sensing device 100 based on some implementations of the disclosed technology.

[0041] Reference Figure 1 , an image sensing device 100 based on some implementations of the disclosed technology may include a timing controller 110, a row driver 120, a pixel array 20, a correlated double sampler (CDS) 130, an analog-to-digital converter (ADC) 140, an output buffer 150, and a column driver 160. Figure 1 The components of the image sensing device shown are discussed as examples only, and this patent document encompasses numerous other variations, permutations, changes, alterations, and modifications. In this patent document, the word "pixel" may be used to indicate an image sensing pixel that is configured to detect incident light to generate an electrical signal that carries an image in the incident light.

[0042] The timing controller 110 may provide a timing signal and a control signal to at least one of the row driver 120 , a correlated double sampler (CDS) 130 , the ADC 140 , the output buffer 150 , and the column driver 160 .

[0043] The row driver 120 may enable the pixel array 20 to perform a specific operation on pixels included in a corresponding row based on a timing signal and a control signal received from the timing controller 110 .

[0044] In some implementations, the row driver 120 may select at least one pixel arranged in at least one row of the pixel array 20, and may provide a control signal for performing a specific operation to the selected pixel. The row driver 120 may generate a row selection signal to select at least one row from among the plurality of rows. When the row driver 120 selects a specific row from among the plurality of rows to perform a specific operation, the row driver 120 may not perform the specific operation on rows adjacent to the selected specific row.

[0045] The pixels of the row selected by the row driver 120 may sequentially transmit an analog reference signal and an image signal to a correlated double sampler (CDS) 130. The reference signal may be an electrical signal provided to the CDS 130 when the floating diffusion region of each pixel is reset to the power supply voltage VDD. The image signal may be an electrical signal provided to the CDS 130 when photocharges generated by each pixel are accumulated in the floating diffusion region (FD) region.

[0046] The reference signal may be a signal indicating unique pixel noise of each pixel, and the reference signal and the image signal may be collectively referred to as a pixel signal as needed.

[0047] The pixel array 20 may include a plurality of pixels arranged in a plurality of rows and columns and supported by a substrate. The plurality of pixels may be connected to a row driver 120 via a plurality of row lines extending in a row direction. The plurality of pixels may be connected to a CDS 130 via a plurality of column lines extending in a column direction. The pixel array 20 may include at least one pixel 200 arranged in a row direction and a column direction. For example, the pixel array 20 may be arranged in a two-dimensional (2D) pixel array in which a plurality of unit pixels include rows and columns.

[0048] A plurality of unit pixels 200 included in the pixel array 20 may convert an optical signal into an electrical signal and may be connected to a specific internal pixel circuit.

[0049] The pixel array 20 may receive pixel control signals including a row selection signal, a pixel reset signal, a row transfer signal, etc. from the row driver 120. At least one pixel included in a row selected by the row driver 120 according to the pixel control signal may perform a specific operation in response to the row selection signal, the pixel reset signal, and the row transfer signal.

[0050] The CDS 130 may receive a reference signal and an image signal each corresponding to a column of the pixel array 20, and may sample the levels of the reference signal and the image signal. In an image sensing device designed to use CMOS, the CDS 130 may sample the pixel signal twice to remove the difference between the two samples, and may perform correlated double sampling to remove an undesired offset value (e.g., fixed noise) of the pixel. For example, the CDS 130 may compare the pixel output voltage obtained before and after the photocharge generated by the incident light is accumulated in the floating diffusion region to remove the undesired offset value, so that the pixel output voltage based on the incident light can be measured.

[0051] The CDS 130 may transmit the reference signal and the image signal generated by column based on the timing signal and the control signal of the timing controller 110 to the ADC 140 as a CDS signal.

[0052] The ADC 140 may convert an analog CDS signal received from the CDS 130 into a digital signal and may output the resulting digital signal.

[0053] The output buffer 150 may temporarily hold and output the digital signal provided from the ADC 140 .

[0054] The column driver 160 may select a column from the output buffer 150 based on a timing signal and a control signal of the timing controller 110 , and may control the temporarily held digital signal to be output according to the selection order.

[0055] Figure 2 Some implementations based on the disclosed technology are shown in Figure 1 A plan view of an example of a portion of a pixel array is shown.

[0056] Reference Figure 2 , the pixel array 20A may correspond to Figure 1 A portion of the pixel array 20 shown. The pixel array 20A may include a plurality of unit pixels arranged adjacent to each other. For example, the plurality of unit pixels included in the pixel array 20A may be arranged in an (M×N) matrix structure. Here, “m” may represent the number of lines in the row direction D2, and may be an integer equal to or greater than 2. In addition, “n” may represent the number of lines in the column direction D1, and may be an integer equal to or greater than 2. Figure 2 is a diagram showing an example structure in which first to sixteenth unit pixels (200-1 to 200-16) are arranged in a (4×4) matrix structure including four row lines (m=4) and four column lines (n=4).

[0057] Each of the first to sixteenth unit pixels (200-1 to 200-16) may include an active region (AR) and a pixel isolation structure 210. Adjacent active regions (AR) may be isolated from each other by the pixel isolation structure 210.

[0058] A plurality of active regions (AR) may be supported by or included in a semiconductor substrate, and the semiconductor substrate may include, for example, silicon (Si). For example, the active region (AR) may include a photoelectric conversion element that generates photocharges in response to incident light when external light is incident on the semiconductor substrate including the active region (AR).

[0059] The pixel isolation structure 210 may isolate the active area (AR) of each of the first to sixteenth unit pixels (200-1 to 200-16) from each other. The pixel isolation structure 210 may include, for example, a grid structure. The pixel isolation structure 210 may optically isolate the active areas (AR) of adjacent unit pixels (e.g., the first unit pixel 200-1 and the second unit pixel 200-2) from each other, and the pixel isolation structure 210 may include an insulating material (e.g., polysilicon, etc.). The pixel isolation structure 210 may be disposed above the semiconductor substrate while being formed as a recessed structure recessed from a first surface of the semiconductor substrate or a second surface facing the first surface or opposite to the first surface. In a semiconductor substrate, the first surface may refer to a rear surface onto which light is incident from the outside, and the second surface may refer to a front surface. In some implementations, the pixel isolation structure 210 may have a structure recessed from the front surface of the semiconductor substrate toward the inside of the semiconductor substrate.

[0060] Figure 3 Some implementations based on the disclosed technology are shown in Figure 2 A circuit diagram of an example of a unit pixel is shown.

[0061] Reference Figure 3 , the equivalent circuit 30C of the unit pixel may include a first photoelectric conversion element (PD1), a second photoelectric conversion element (PD2), a first transfer transistor (TX1), a second transfer transistor (TX2), a first floating diffusion region (FD1), a second floating diffusion region (FD2), a reset transistor (RST), a source follower transistor (SF) and a selection transistor (SEL).

[0062] The first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) can generate and accumulate photoelectric charges corresponding to the intensity of the incident light by photoelectric conversion of the incident light. For example, each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. Figure 3 is a circuit diagram showing an example circuit in which the first photoelectric conversion element ( PD1 ) and the second photoelectric conversion element ( PD2 ) are implemented as photodiodes.

[0063] The first floating diffusion region (FD1) and the second floating diffusion region (FD2) may respectively receive the photocharges accumulated in the first photoelectric conversion element (PD1) and the photocharges accumulated in the second photoelectric conversion element (PD2), and may respectively store the received photocharges. Figure 3In the example shown, the first floating diffusion region (FD1) and the second floating diffusion region (FD2) can be modeled as capacitors that can be configured to have corresponding capacitances. The first floating diffusion region (FD1) and the second floating diffusion region (FD2) can be electrically connected in parallel to each other. The first floating diffusion region (FD1) and the second floating diffusion region (FD2) connected in parallel to each other can be included in one floating diffusion region (FD).

[0064] The first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may share one floating diffusion region (FD), and one floating diffusion region (FD) may provide a capacitance equal to the sum of the capacitance of the first floating diffusion region (FD1) and the capacitance of the second floating diffusion region (FD2).

[0065] The first transfer transistor (TX1) may be a transistor having one terminal connected to the first photoelectric conversion element (PD1) and the other terminal connected to the floating diffusion region (FD). A first transfer signal (TS1) may be sent to the first transfer transistor (TX1). A voltage corresponding to a signal level of the first transfer signal (TS1) may be applied to a gate of the first transfer transistor (TX1), and when a voltage equal to or greater than a threshold voltage is applied to the gate of the first transfer transistor (TX1), photocharges accumulated in the first photoelectric conversion element (PD1) may be transferred to the floating diffusion region (FD).

[0066] The second transfer transistor (TX2) may be a transistor having one terminal connected to the second photoelectric conversion element (PD2) and the other terminal connected to the floating diffusion region (FD). A second transfer signal (TS2) may be sent to the second transfer transistor (TX2). A voltage corresponding to a signal level of the second transfer signal (TS2) may be applied to a gate of the second transfer transistor (TX2), and when a voltage equal to or greater than a threshold voltage is applied to the gate of the second transfer transistor (TX2), photocharges accumulated in the second photoelectric conversion element (PD2) may be transferred to the floating diffusion region (FD).

[0067] The reset transistor (RST) may be a transistor having one terminal connected to the floating diffusion region (FD) and the other terminal connected to the power supply voltage (VDD). A reset signal (RS) may be sent to the reset transistor (RST). A voltage corresponding to the signal level of the reset signal (RS) may be applied to the gate of the reset transistor (RST), and when a voltage equal to or greater than a threshold voltage is applied to the gate of the reset transistor (RST), the photocharge stored in the floating diffusion region (FD) may be removed from the floating diffusion region (FD).

[0068] The reset transistor (RST) and each of the first transfer transistor and the second transfer transistor (TX1, TX2) may be in an on state or an off state. The on state may refer to a case where a voltage equal to or greater than a threshold voltage is applied to the reset transistor (RST) and a corresponding one of the first transfer transistor and the second transfer transistor (TX1, TX2). The off state may refer to a case where a voltage less than a threshold voltage is applied to the reset transistor (RST) and a corresponding one of the first transfer transistor and the second transfer transistor (TX1, TX2). When the reset transistor (RST) and each of the first transfer transistor or the second transfer transistor (TX1 or TX2) are in an on state, the photoelectric conversion element or the second photoelectric conversion element (PD1 or PD2) accumulated photoelectric charges may be removed, and the photoelectric charges stored in the floating diffusion region (FD) may also be removed.

[0069] One terminal of the source follower transistor (SF) may be connected to a power supply voltage (VDD), and the other terminal of the source follower transistor (SF) may be connected to a selection transistor (SEL). A voltage generated by photocharges stored in a floating diffusion region (FD) may be applied to a gate of the source follower transistor (SF). The source follower transistor (SF) may output an electrical signal in response to the voltage generated by photocharges stored in a floating diffusion region (FD).

[0070] One terminal of the selection transistor (SEL) may be connected to the source follower transistor (SF), and the other terminal of the selection transistor (SEL) may be connected to the output terminal. A selection signal (SS) may be transmitted to the selection transistor (SEL). A voltage corresponding to the signal level of the selection signal (SS) may be applied to the gate of the selection transistor SEL, and when a voltage equal to or greater than the threshold voltage is applied to the gate of the selection transistor (SEL) (i.e., the selection transistor (SEL) is turned into a conductive state), the electrical signal amplified by the source follower transistor (SF) may be output to the output terminal. The output terminal may transmit the electrical signal output to the output terminal to the Figure 1 A correlated double sampler (CDS) 130 is provided.

[0071] Figure 4 Some implementations based on the disclosed technology are shown in Figure 2 FIG. 1 is a plan view of an example of a first embodiment of a unit pixel shown in FIG.

[0072] Reference Figures 2 to 4 , Figure 4 The unit pixel 30 may be Figure 2The first to sixteenth unit pixels (200-1 to 200-16) of the present invention are shown in FIG. 3. The unit pixel 30 may include a first pixel isolation structure 310, a first photoelectric conversion element (PD1), a second photoelectric conversion element (PD2), a first floating diffusion region (FD1), a second floating diffusion region (FD2), a gate (TXG1) of a first transfer transistor (TX1), a gate (TXG2) of a second transfer transistor (TX2), a gate (RSTG) of a reset transistor (RST), a gate (SFG) of a source follower transistor (SF), and a gate (SELG) of a select transistor (SEL). The unit pixel 30 may also include a second pixel isolation structure 320 and a third pixel isolation structure 330.

[0073] The first pixel isolation structure 310 may be disposed outside the unit pixel 30. The first pixel isolation structure 310 may be provided and supported by a semiconductor substrate (e.g., disposed inside the semiconductor substrate). The semiconductor substrate may include a first surface on which light is incident and a second surface facing or opposite to the first surface. The first pixel isolation structure 310 may include a structure recessed from the second surface. The first pixel isolation structure 310 may include at least one of polysilicon or silicon oxide. For example, the first pixel isolation structure 310 may include polysilicon or silicon oxide. For example, the first pixel isolation structure 310 may include both polysilicon and silicon oxide. The first pixel isolation structure 310 may be disposed between the unit pixel 30 and at least one adjacent unit pixel (not shown) arranged adjacent to the unit pixel 30, and is configured to optically isolate the unit pixel 30 and at least one adjacent unit pixel from each other. For example, the first pixel isolation structure 310 may prevent crosstalk between the unit pixel 30 and the adjacent unit pixels, so that light incident on the unit pixel 30 may be prevented from being incident on the adjacent unit pixels.

[0074] The second pixel isolation structure 320 may be arranged to extend in the second direction D2 within the first gap region 41 indicating the space between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2). The second pixel isolation structure 320 may be disposed to contact the first pixel isolation structure 310. The second pixel isolation structure 320 may include a structure recessed from the second surface of the semiconductor substrate. The second pixel isolation structure 320 may include substantially the same material as the first pixel isolation structure 310.

[0075] The third pixel isolation structure 330 may be arranged to extend in the second direction D2 within the first gap region 41. The third pixel isolation structure 330 may be arranged to be spaced apart from the second pixel isolation structure 320. The third pixel isolation structure 330 may be arranged to contact the first pixel isolation structure 310 at an opposite side of the region where the second pixel isolation structure 320 contacts the first pixel isolation structure 310. The third pixel isolation structure 330 may include a structure recessed from the second surface of the semiconductor substrate. The third pixel isolation structure 330 may include substantially the same material as the first pixel isolation structure 310.

[0076] The second pixel isolation structure 320 and the third pixel isolation structure 330 may prevent crosstalk of incident light between the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 .

[0077] Each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may generate and accumulate photocharges corresponding to the intensity of incident light. The first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may be spaced apart from each other in the first direction D1. Each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may be arranged to occupy as large an area as possible to increase a fill factor indicating light receiving efficiency. For example, each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0078] When the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) are implemented as photodiodes, each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may be a region where ions are implanted into a semiconductor substrate. In some implementations, the photodiode may include a structure in which a plurality of doped regions are stacked.

[0079] The first gap region 41 may be a space disposed between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) or may include a space disposed between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2). More specifically, the first gap region 41 may refer to a space where both ends of the first gap region 41 disposed in the first direction D1 in the semiconductor substrate contact the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2), respectively, and both ends of the first gap region 41 disposed in the second direction D2 in the semiconductor substrate contact the first pixel isolation structure 310. The figure shows that the width of the first gap region 41 in the first direction D1 is less than the separation distance between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) and the width of the first gap region 41 in the second direction D2 is greater than the separation distance between the two ends of the first pixel isolation structure 310. Figure 4 The structure shown may only be constructed to prevent Figure 4 The width of the first gap region 41 in the first direction D1 may be equal to the separation distance between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2), and the width of the first gap region 41 in the second direction D2 may be equal to the separation distance between both ends of the first pixel isolation structure 310.

[0080] The second gap region 42 may be a space located inside the semiconductor substrate or may include a space located inside the semiconductor substrate, which is surrounded by the first photoelectric conversion element (PD1), the second photoelectric conversion element (PD2), the second pixel isolation structure 320 and the third pixel isolation structure 330. Figure 4 The second gap region 42 shown is configured such that the width of the second gap region 42 in the first direction D1 is smaller than the separation distance between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) and the width of the second gap region 42 in the second direction D2 is smaller than the separation distance between the second pixel isolation structure 320 and the third pixel isolation structure 330. Figure 4 The width of the second gap region 42 in the first direction D1 may be equal to the separation distance between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2), and the width of the second gap region 42 in the second direction D2 may be equal to the separation distance between the second pixel isolation structure 320 and the third pixel isolation structure 330.

[0081] In some implementations, the gate (SFG) of the source follower transistor (SF) may be disposed on the second surface of the semiconductor substrate including the second gap region 42. The gate of the source follower transistor SF may be disposed to overlap the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2). As the width of the region where the gate of the source follower transistor (SF) overlaps the first photoelectric conversion element and the second photoelectric conversion element (PD1, PD2) increases, the noise of the electrical signal output from the source follower transistor (SF) may be reduced.

[0082] The gate (SFG) of the source follower transistor (SF) may overlap with the second gap region 42 and may extend in the first direction D1. For example, the gate (SFG) of the source follower transistor (SF) may be formed in a rectangular shape, the vertical length of which extends to the maximum extent in the first direction D1 within a range that does not contact the first pixel isolation structure 310, and the horizontal length of which is equal to the width of the second gap region 42 in the second direction D2. In another example, in the region where the gate (SFG) of the source follower transistor (SF) overlaps with the first photoelectric conversion element PD1 or the second photoelectric conversion element PD2, the width of the gate (SFG) of the source follower transistor (SF) in the second direction D2 may be greater than the second gap region 42 arranged in the second direction D2. The scope of the disclosed technology is not limited to the above two embodiments, and other implementations are also possible. For example, an image sensing device based on some implementations of the disclosed technology may be configured such that the gate (SFG) structure of the source follower transistor (SF) extends in the first direction D1 while being disposed above the second surface of the semiconductor substrate corresponding to the second gap region 42, regardless of the width of the gate (SFG) of the source follower transistor (SF). For example, in some implementations, the width of the gate (SFG) of the source follower transistor (SF) may vary.

[0083] If the size of the area of ​​the gate (SFG) of the source follower transistor (SF) increases, the noise of the unit pixel 30 can be reduced. More specifically, the source follower transistor (SF) can amplify the potential of the first floating diffusion region (FD1) storing the photocharge generated by the first photoelectric conversion element (PD1) and the potential of the second floating diffusion region (FD2) storing the photocharge generated by the second photoelectric conversion element (PD2). As the size of the gate (SFG) of the source follower transistor (SF) increases, the noise of each pixel can be reduced. Hereinafter, a detailed description thereof will be given with reference to the following formula 1.

[0084] [Formula 1]

[0085]

[0086] In Formula 1, “Svg ” represents the noise voltage power, “N T ” represents the density of trap states, “C ox " represents the capacitance of the oxide layer, "W" represents the width of the gate of the transistor, "L" represents the length of the gate of the transistor, and "WL" corresponding to "W×L" corresponds to the area (region) of the gate of the transistor. Since the noise power (S vg ) and the area of ​​the gate region (WL) of the transistor are inversely proportional to each other, so as the size of the gate region of the transistor increases, the noise can be reduced. The above formula 1 can also be applied to the source follower transistor (SF). As the size of the area of ​​the gate (SFG) of the source follower transistor (SF) increases, the noise of the electrical signal output by the selection transistor (SEL) can be reduced. An image sensing device based on some implementations of the disclosed technology can ensure a larger area of ​​the gate (SFG) of the source follower transistor (SF) within a unit pixel with a limited size by not allocating a source follower transistor (SF) to each of the first photoelectric conversion element and the second photoelectric conversion element (PD1, PD2) and the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) only share a specific structure of a source follower transistor (SF).

[0087] For example, the first floating diffusion region (FD1) may be arranged to overlap with the first photoelectric conversion element (PD1) in the third direction D3. In another example, when viewed in the third direction D3, the first floating diffusion region (FD1) may be arranged not to overlap with the first photoelectric conversion element (PD1). As the size of the light receiving area of ​​the first photoelectric conversion element (PD1) increases, the photoelectric conversion efficiency of the first photoelectric conversion element (PD1) may be improved. An embodiment in which the first floating diffusion region (FD1) and the first photoelectric conversion element (PD1) overlap each other in the third direction D3 will be described below with reference to the accompanying drawings.

[0088] For example, the second floating diffusion region (FD2) may be arranged to overlap with the second photoelectric conversion element (PD2) in the third direction D3. In another example, when viewed in the third direction D3, the second floating diffusion region (FD2) may be spaced apart from the second photoelectric conversion element (PD2). An embodiment in which the second floating diffusion region (FD2) and the second photoelectric conversion element (PD2) overlap with each other in the third direction D3 will be described below with reference to the accompanying drawings.

[0089] When Figure 4 When viewed in a plan view of FIG. 1 , the second floating diffusion region (FD2) may be arranged to be spaced apart from the first floating diffusion region (FD1), but may be electrically connected to the first floating diffusion region (FD1) through a predetermined metal interconnection layer. The predetermined metal interconnection layer will be referred to later. Fig.11 describe.

[0090] Figure 4 The floating diffusion region (FD) is arranged so that the first floating diffusion region (FD1) and the second floating diffusion region (FD2) are isolated from each other and the first floating diffusion region (FD1) and the second floating diffusion region (FD2) are electrically connected to each other through a predetermined metal interconnection layer. Figure 4 In the implementation shown, other implementations are also possible. For example, in some implementations, only one floating diffusion region may be provided without using a predetermined metal interconnect layer. For example, the one floating diffusion region may be provided between the gate (TXG1) of the first transfer transistor (TX1) and the gate (TXG2) of the second transfer transistor (TX2).

[0091] Each of the gate (TXG1) of the first transfer transistor (TX1) and the gate (TXG2) of the second transfer transistor (TX2) may be spaced apart from the gate (SFG) of the source follower transistor SF, so that the gate (TXG1) of the first transfer transistor (TX1) and the gate (TXG2) of the second transfer transistor (TX2) spaced apart from each other may be disposed on the second surface of the semiconductor substrate. The gate (TXG1) of the first transfer transistor (TX1) may overlap with the first photoelectric conversion element (PD1) in a third direction D3, and the gate (TXG2) of the second transfer transistor (TX2) may overlap with the second photoelectric conversion element (PD2) in the third direction D3. The gate (TXG1) of the first transfer transistor (TX1) may overlap or be spaced apart from the first floating diffusion region (FD1) in the third direction D3, and the gate (TXG2) of the second transfer transistor (TX2) may overlap or be spaced apart from the second floating diffusion region (FD2) in the third direction D3. Figure 4 It can be seen that the gate (TXG1) of the first transfer transistor (TX1) and the first floating diffusion region (FD1) may be arranged to be spaced apart from each other, and the gate (TXG2) of the second transfer transistor (TX2) and the second floating diffusion region (FD2) may be arranged to be spaced apart from each other.

[0092] The gate (RSTG) of the reset transistor (RST) may be disposed on the second surface of the semiconductor substrate while being spaced apart from the gate (SFG) of the source follower transistor (SF). The gate (RSTG) of the reset transistor (RST) may be disposed to overlap with the first photoelectric conversion element (PD1). The gate (RSTG) of the reset transistor (RST) may correspond to a region where a voltage is applied to the reset transistor (RST).

[0093] The gate (SELG) of the selection transistor (SEL) may be spaced apart from the gate (SFG) of the source follower transistor (SF) and may be disposed on the second surface of the semiconductor substrate. The gate (SELG) of the selection transistor SEL may be disposed to overlap the second photoelectric conversion element (PD2). The gate (SELG) of the selection transistor (SEL) may correspond to a region where a voltage is applied to the selection transistor (SEL).

[0094] Figure 5 Some implementations based on the disclosed technology are shown in Figure 2 FIG. 2 is a plan view of an example of a second embodiment of a unit pixel shown in FIG.

[0095] In the following, we will mainly describe Figure 4 The characteristics of unit pixels are different Figure 5 Characteristics of unit pixels.

[0096] Reference Figure 5 , the gate (G1) of the first transistor may be disposed on the second surface of the semiconductor substrate while being spaced apart from the gate (SFG) of the source follower transistor in the unit pixel 30. The gate (G1) of the first transistor may be disposed to overlap with the first photoelectric conversion element (PD1). Figure 5 An embodiment in which the gate (G1) of the first transistor overlaps the first photoelectric conversion element (PD1) is shown, but other implementations are possible. For example, in some implementations, the gate (G1) of the first transistor may also overlap the second photoelectric conversion element (PD2). The gate (G1) of the first transistor may correspond to the region where the voltage is applied to the first transistor. For example, the first transistor may be a drain transistor or a dual conversion gain (DCG) transistor.

[0097] When the first transistor is a drain transistor, one terminal of the drain transistor may be connected to the first photoelectric conversion element (PD1) or the second photoelectric conversion element (PD2), and the other terminal of the drain transistor may be connected to a power supply voltage (VDD). When a voltage equal to or greater than a threshold voltage is applied to the gate of the drain transistor, photocharges generated and accumulated in the first photoelectric conversion element (PD1) or the second photoelectric conversion element (PD2) may be removed.

[0098] When the first transistor is a DCG transistor, when a voltage equal to or greater than a threshold voltage is applied to the gate of the DCG transistor, the capacitance of the first floating diffusion region (FD1) or the second floating diffusion region (FD2) may increase. The amount of photocharge accumulated in the first floating diffusion region (FD1) and the second floating diffusion region (FD2) may be proportional to the capacitance and the voltage. As the capacitance increases, the voltage to be applied to the source follower transistor may decrease. As the capacitance decreases, the voltage to be applied to the source follower transistor may increase. Therefore, when a voltage equal to or greater than the threshold voltage is applied to the gate of the DCG transistor, the voltage to be applied to the source follower transistor may decrease so that the source follower transistor may have a low conversion gain. Then, when a voltage less than the threshold voltage is applied to the gate of the DCG transistor, a relatively high voltage may be applied to the source follower transistor, and the source follower transistor may have a high conversion gain.

[0099] Figure 6 Some implementations based on the disclosed technology are shown in Figure 2 FIG. 2 is a plan view of an example of a third embodiment of a unit pixel shown in FIG.

[0100] In the following, we will mainly describe Figure 4 The characteristics of unit pixels are different Figure 6 Characteristics of unit pixels.

[0101] Reference Figure 6 The gate (G2) of the second transistor may be spaced apart from the gate (SFG) of the source follower transistor (SF) in the unit pixel 30 and may be disposed on the second surface of the semiconductor substrate. The second transistor may be a drain transistor or a DCG transistor.

[0102] The gate (G3) of the third transistor may be disposed on the second surface of the semiconductor substrate at a position where the gate (G3) of the third transistor is spaced apart from each of the gate (SFG) of the source follower transistor (SF) and the gate (G2) of the second transistor within the unit pixel 30. The third transistor may be a DCG transistor.

[0103] In one embodiment where the second transistor is a drain transistor and the third transistor is a DCG transistor, the process of resetting the photocharge of the first photoelectric conversion element (PD1) or the second photoelectric conversion element (PD2) can be performed by the drain transistor. Figure 5 It can be seen that when the magnitude of the voltage that can be applied to the gate of the DCG transistor is adjusted according to the on-off state of the DCG transistor, a double gain conversion of the source follower transistor can be achieved.

[0104] One embodiment in which the second transistor is a first DCG transistor and the third transistor is a second DCG transistor can be implemented so that three gain conversions of the source follower transistor can be performed according to the on-off state of each of the first DCG transistor and the second DCG transistor. For example, when both the first DCG transistor and the second DCG transistor are turned on (when a voltage equal to or greater than the threshold voltage is applied to each of the first DCG transistor and the second DCG transistor), a first gain conversion can be performed. Then, when either one of the first DCG transistor and the second DCG transistor is turned on or the other is turned off, a second gain conversion can be performed, and when both the first DCG transistor and the second DCG transistor are turned off, a third gain conversion can be performed.

[0105] At the same time, one embodiment of the disclosed technology can provide an image sensing device, which can maximize the area of ​​the gate (SFG) of the source follower transistor within the range where the gate (SFG) of the source follower transistor is spaced apart from the gate (G2) of the second transistor and the gate (G3) of the third transistor, thereby reducing the amount of noise of the electrical signal that can be output from the source follower transistor.

[0106] Figure 7 Some implementations based on the disclosed technology are shown in Figure 2 FIG. 2 is a plan view of an example of a fourth embodiment of a unit pixel shown in FIG.

[0107] In the following, we will mainly describe Figure 4 The characteristics of unit pixels are different Figure 7 Characteristics of unit pixels.

[0108] In the following, except Figure 4 In addition to the constituent elements of the unit pixel 30, Figure 7 The unit pixel 30 may further include a fourth pixel isolation structure 340 .

[0109] The fourth pixel isolation structure 340 may be disposed in the second gap region 42. The fourth pixel isolation structure 340 may include a recessed structure on the first surface of the semiconductor substrate. The fourth pixel isolation structure 340 may include at least one of polysilicon and silicon oxide. The fourth pixel isolation structure 340 may be configured to optically isolate the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) from each other, thereby preventing crosstalk between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2).

[0110] Figure 8 is a diagram showing some implementations based on the disclosed technology. Figures 4 to 6 A cross-sectional view of an example of a unit pixel taken along line AA′.

[0111] Reference Figure 4 and Figure 8 , along Figure 4 The first cross section 800 of the unit pixel 30 taken along the line AA′ may be an example of a cross section of the unit pixel 30 taken along the line AA′. Figure 4 The cross section is taken along the line AA', but the cross section of another portion taken along the line AA' (i.e., the portion taken along the line intersecting the unit pixel 30 in the second direction D2 between the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2) may also have a structure substantially the same as the first cross section 800.

[0112] A first cross section 800 of the unit pixel 30 may include a semiconductor substrate 850 , an epitaxial region 830 , a first pixel isolation structure 310 , a second pixel isolation structure 320 , a third pixel isolation structure 330 , a pixel insulation structure 350 , and a gate (SFG) of a source follower transistor.

[0113] The semiconductor substrate 850 may include a first surface 810 and a second surface 820 facing or opposite to the first surface 810. The semiconductor substrate 850 may include a silicon material. The first surface 810 may be a rear surface onto which light is incident. The second surface 820 may be a front surface. One or more filters (not shown) for transmitting light of a specific color may be disposed on the first surface 810.

[0114] In some implementations, the first pixel isolation structure 310 may be disposed in a recessed structure recessed in the third direction D3 from the second surface 820. The first pixel isolation structure 310 may be disposed at both ends of the unit pixels 30 arranged in the second direction D2.

[0115] In some implementations, the second pixel isolation structure 320 may be disposed in a recessed structure recessed from the second surface 820 in the third direction D3. The second pixel isolation structure 320 may be disposed on one side of the unit pixel 30 (eg, at Figure 8 The left side of the pixel contacts the first pixel isolation structure 310.

[0116] In some implementations, the third pixel isolation structure 330 may be disposed in a recessed structure recessed from the second surface 820 in the third direction D3. The third pixel isolation structure 330 may be disposed on the other side of the unit pixel 30 (eg, at Figure 8 The right side of the pixel contacts the first pixel isolation structure 310.

[0117] The pixel insulation structure 350 may be disposed in a recessed structure recessed in the third direction D3 from the second surface 820. The pixel insulation structure 350 may have a recessed depth less than each of the first to third pixel isolation structures (310, 320, 330). The pixel insulation structure 350 may be disposed adjacent to each of the second pixel isolation structure 320 and the third pixel isolation structure 330. When a voltage is applied to the gate (SFG) of the source follower transistor, the pixel insulation structure 350 may prevent carriers in a carrier movement channel that may be formed under the gate (SFG) of the source follower transistor from moving toward the second direction D2 and leaking to the outside.

[0118] The gate (SFG) of the source follower transistor may be disposed on the second surface 820 of the semiconductor substrate 850. The gate (SFG) of the source follower transistor may be disposed in a region between the pixel insulation structures 350 located on both sides of the gate (SFG) of the source follower transistor. Each of the source and the drain of the source follower transistor may be arranged in a first direction D1 relative to the gate (SFG) of the source follower transistor.

[0119] The gate (SFG) of the source follower transistor may include metal. The gate (SFG) of the source follower transistor may also include an insulating material. For example, the gate (SFG) of the source follower transistor may include a structure in which a gate insulating layer including an insulating material is disposed on the second surface 820 and a gate metal layer is disposed on the gate insulating layer.

[0120] The epitaxial region 830 may be a region not doped with impurities. The epitaxial region 830 may refer to a region where the first pixel isolation structure 310 , the second pixel isolation structure 320 , the third pixel isolation structure 330 , and the pixel insulation structure 350 are not arranged in the semiconductor substrate 850 .

[0121] Fig. 9 is a diagram showing some implementations based on the disclosed technology. Figure 7 A cross-sectional view of an example of a unit pixel taken along line BB′.

[0122] Reference Figure 7 and Fig. 9 , along Figure 7 The second cross section 900 of the unit pixel 30 taken along the line BB' may be an example of a cross section of the unit pixel 30 taken along the line BB'. Figure 7 The cross section is taken along the line BB', but the cross section of another portion taken along the line BB' (i.e., the portion taken along the line intersecting the unit pixel 30 in the second direction D2 between the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2) may also have a structure substantially the same as the second cross section 900.

[0123] In the following, we mainly discuss Figure 8 The structure and Fig. 9 to avoid redundant descriptions of the differences between the structures.

[0124] The second cross section 900 may include a semiconductor substrate 950, an epitaxial region 930, a first pixel isolation structure 310, a second pixel isolation structure 320, a third pixel isolation structure 330, a fourth pixel isolation structure 340, a pixel insulation structure 350, and a gate (SFG) of a source follower transistor.

[0125] The fourth pixel isolation structure 340 may be disposed in a structure facing the second surface 920 of the semiconductor substrate 950 and recessed in the third direction D3 from the first surface 910 onto which light is incident. The fourth pixel isolation structure 340 may be disposed between the second pixel isolation structure 320 and the third pixel isolation structure 330.

[0126] The epitaxial region 930 may be a region not doped with impurities. The epitaxial region 930 may refer to a region where the first pixel isolation structure 310 , the second pixel isolation structure 320 , the third pixel isolation structure 330 , the fourth pixel isolation structure 340 and the pixel insulation structure 350 are not arranged in the semiconductor substrate 950 .

[0127] Can be respectively Fig. 9 The components corresponding to Figure 8 The description of the components can also be applied to Fig. 9 The components of Figure 8 The description provided does not match Fig. 9 The descriptions of the constituent components conflict.

[0128] Fig.10 is a diagram showing some implementations based on the disclosed technology. Figure 4 A cross-sectional view of an example of a unit pixel taken along line CC'.

[0129] Reference Figure 4 and Fig.10 , along Figure 4 The third cross section 1000 of the unit pixel 30 taken along the line CC' may be an example of a cross section of the unit pixel 30 taken along the line CC'. Figure 4 The cross section is taken along the line CC', but the cross section of another portion taken along the line CC' (i.e., the portion taken along the line intersecting the gate (SFG) of the source follower transistor in the first direction D1) may also have a structure substantially the same as the third cross section 1000.

[0130] The third cross section 1000 may include a semiconductor substrate 1050, an epitaxial region 1030, a first pixel isolation structure 310, a first photoelectric conversion element (PD1), a second photoelectric conversion element (PD2), a pixel insulation structure 350, a gate (SFG) of a source follower transistor, and a source and a drain (91S, 92S) of the source follower transistor.

[0131] The semiconductor substrate 1050 may include a first surface 1010 and a second surface 1020 facing or opposite to the first surface 1010. The semiconductor substrate 1050 may include a silicon material. The first surface 1010 may be a rear surface onto which light is incident. The second surface 1020 may be a front surface.

[0132] The first pixel isolation structure 310 may be disposed in a recessed structure recessed from the second surface 1020 at both ends of the unit pixel 30 .

[0133] The first photoelectric conversion element (PD1) may be disposed in the semiconductor substrate 1050 while being spaced apart from the first surface 1010 on which light is incident. The first photoelectric conversion element (PD1) may be a region doped with impurities.

[0134] The second photoelectric conversion element (PD2) may be disposed in the semiconductor substrate 1050 while being spaced apart from the first surface 1010 on which light is incident. The second photoelectric conversion element (PD2) may be disposed in the semiconductor substrate 1050 while being spaced apart from the first photoelectric conversion element (PD1). The space between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may be Figure 4 The second gap region 42 is shown. The second photoelectric conversion element (PD2) may be a region doped with impurities.

[0135] The pixel insulating structure 350 may be disposed in a recessed structure recessed in the third direction D3 from the second surface 1020. The pixel insulating structure 350 may have a recessed depth less than that of the first pixel isolation structure 310. The pixel insulating structure 350 may be disposed adjacent to the first pixel isolation structure 310.

[0136] The gate (SFG) of the source follower transistor may be disposed on the second surface 1020 of the semiconductor substrate 1050. The gate (SFG) of the source follower transistor may be arranged to extend in the first direction D1. When the gate (SFG) of the source follower transistor increases in size by extending in the first direction D1, the noise of the image sensing device may be reduced. When viewed in the third direction D3, the gate (SFG) of the source follower transistor may overlap with the first photoelectric conversion element (PD1). When viewed in the third direction D3, the gate (SFG) of the source follower transistor may overlap with the second photoelectric conversion element (PD2).

[0137] The gate (SFG) of the source follower transistor may include a gate insulating layer disposed on the second surface 1020 and configured to include an insulating material, and a gate electrode layer disposed on the gate insulating layer and configured to include a metal material.

[0138] The source and drain ( 91S, 92S) of the source follower transistor may be respectively disposed at both ends of the gate (SFG) of the source follower transistor arranged in the first direction D1 .

[0139] The source 91S of the source follower transistor may be electrically connected to Figure 4 One terminal of the gate (SELG) of the selection transistor shown (e.g., the drain region of the selection transistor). The source 91S of the source follower transistor and the drain region of the selection transistor (not shown) can be electrically connected to each other through a first metal interconnect layer 91M that can be disposed on the semiconductor substrate 1050 and the second surface 1020.

[0140] The drain 92S of the source follower transistor may be connected to a supply voltage (eg, Figure 3 The power supply voltage (for example, Figure 3 VDD) can be applied to the drain 92S of the source follower transistor through the second metal interconnect layer 92M.

[0141] The epitaxial region 1030 may be a region that is not doped with impurities or may include a region that is not doped with impurities. The epitaxial region 1030 may refer to a region where the first photoelectric conversion element PD1, the second photoelectric conversion element PD2, the source 91S of the source follower transistor, the drain 92S of the source follower transistor, the first pixel isolation structure 310, and the pixel insulation structure 350 are not arranged in the semiconductor substrate 1050.

[0142] Can be respectively Fig.10 The components corresponding to Figure 7 The description of the components can also be applied to Fig.10 The components of Figure 7 The description provided does not match Fig.10 The descriptions of the constituent components conflict.

[0143] Fig.11 is a diagram showing some implementations based on the disclosed technology. Figures 4 to 7 A cross-sectional view of an example of a unit pixel taken along line DD'.

[0144] Reference Figure 4 and Fig.11 , along Figure 4The fourth cross section 1100 of the unit pixel 30 taken along the line DD' may be an example of a cross section of the unit pixel 30 taken along the line DD'. Figure 4 The cross section is not a cross section taken along the line D-D', but the cross section of another portion taken along the line D-D' (i.e., the portion taken along the line that intersects both the gate (TXG1) of the first transfer transistor and the gate (TXG2) of the second transfer transistor) may also have a structure substantially the same as the fourth cross section 1100.

[0145] The fourth cross section 1100 may include a semiconductor substrate 1150, an epitaxial region 1130, a first pixel isolation structure 310, a third pixel isolation structure 330, a pixel insulation structure 350, a first photoelectric conversion element (PD1), a second photoelectric conversion element (PD2), a gate of a first transfer transistor (TXG1), a gate of a second transfer transistor (TXG2), a first floating diffusion region (FD1), a second floating diffusion region (FD2) and a third metal interconnection layer 50.

[0146] The semiconductor substrate 1150 may include a first surface 1110 onto which light is incident and a second surface 1120 facing or opposite to the first surface 1110 .

[0147] The first pixel isolation structure 310 may be disposed at both ends of the unit pixel 30 , and may include a structure recessed from the second surface 1120 toward the inside of the semiconductor substrate 1150 .

[0148] The first photoelectric conversion element (PD1) may generate and accumulate photocharges in response to light incident on the first surface 1110. The first photoelectric conversion element (PD1) may be disposed in the semiconductor substrate 1150 while being spaced apart from the first surface 1110 on which light is incident.

[0149] The second photoelectric conversion element (PD2) may be disposed in the semiconductor substrate 1150 while being spaced apart from the first surface 1110 on which light is incident. The second photoelectric conversion element (PD2) may be disposed in the semiconductor substrate 1150 while being spaced apart from the first photoelectric conversion element (PD1). The space between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may refer to Figure 4 The first gap region 41 is shown. The first gap region 41 may refer to a portion of the first gap region 41 that does not overlap with the second gap region 42.

[0150] The third pixel isolation structure 330 may be disposed in the semiconductor substrate 1150 within the first gap region 41 of the unit pixel 30 .

[0151] The pixel insulating structure 350 may be disposed adjacent to the first pixel isolation structure 310 and the third pixel isolation structure 330. When a voltage is applied to the gate (TXG1) of the first transfer transistor or the gate (TXG2) of the second transfer transistor, when photocharges generated by the first photoelectric conversion element (PD1) in response to incident light move to the first floating diffusion region (FD1) and photocharges generated by the second photoelectric conversion element (PD2) in response to incident light move to the second floating diffusion region (FD2), the pixel insulating structure 350 may prevent these photocharges from leaking.

[0152] The gate (TXG1) of the first transfer transistor may include a first gate plane portion (TXG1a) and a first gate buried portion (TXG1b). The first gate plane portion (TXG1a) may refer to a region corresponding to an upper portion of the gate (TXG1) of the first transfer transistor above the second surface 1020. The first gate buried portion (TXG1b) may refer to a region corresponding to a lower portion of the gate (TXG1) of the first transfer transistor below the second surface 1120. Therefore, the first gate buried portion (TXG1b) may refer to a region corresponding to a portion recessed into the semiconductor substrate 1150. The gate (TXG1) of the first transfer transistor may include a gate insulating layer including an insulating material, and may include a gate metal layer disposed on the gate insulating layer.

[0153] The gate (TXG2) of the second transfer transistor may include a second gate plane portion (TXG2a) and a second gate buried portion (TXG2b). The second gate plane portion (TXG2a) may refer to a region corresponding to an upper portion of the second surface 1120 among the gate (TXG2) of the second transfer transistor. The second gate buried portion (TXG2b) may refer to a region corresponding to a lower portion of the second surface 1120 among the gate (TXG2) of the second transfer transistor. That is, the second gate buried portion (TXG2b) may be a region corresponding to a portion recessed into the semiconductor substrate 1150. The gate (TXG2) of the second transfer transistor may include a gate insulating layer including an insulating material, and may include a gate metal layer disposed on the gate insulating layer.

[0154] The first floating diffusion region (FD1) may be disposed adjacent to the second surface 1120 and may be disposed in the semiconductor substrate 1150. When viewed in the third direction D3, the first floating diffusion region (FD1) may overlap with the first photoelectric conversion element (PD1). In some implementations, when viewed in the third direction D3, the first floating diffusion region (FD1) may overlap with the first gate plane portion (TXG1a). In some other implementations, when viewed in the third direction D3, the first floating diffusion region (FD1) may be spaced apart from the first gate plane portion (TXG1a).

[0155] The second floating diffusion region (FD2) may be disposed adjacent to the second surface 1120 and may be disposed in the semiconductor substrate 1150. When viewed in the third direction D3, the second floating diffusion region (FD2) may overlap with the second photoelectric conversion element (PD2). In some implementations, when viewed in the third direction D3, the second floating diffusion region (FD2) may overlap with the second gate plane portion (TXG2a). In some other implementations, when viewed in the third direction D3, the second floating diffusion region (FD2) may be spaced apart from the second gate plane portion (TXG2a).

[0156] The third metal interconnection layer 50 may electrically connect the first floating diffusion region (FD1) and the second floating diffusion region (FD2) to each other. Figures 4 to 7 The first floating diffusion region (FD1) and the second floating diffusion region (FD2) are shown as separate floating diffusion regions when viewed in a plan view of FIG. 1 , but other implementations are possible, and it should be noted that the first floating diffusion region (FD1) and the second floating diffusion region (FD2) may be included in one floating diffusion region substantially shared by the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) through the third metal interconnect layer 50. The third metal interconnect layer 50 may include a metal material.

[0157] The epitaxial region 1130 may be a region that is not doped with impurities. The epitaxial region 1130 may refer to a region in the semiconductor substrate 1150 where the first pixel isolation structure 310, the third pixel isolation structure 330, the pixel insulation structure 350, the first floating diffusion region (FD1), the second floating diffusion region (FD2), the buried portion (TXG1b) of the gate (TXG1) of the first transfer transistor, and the gate (TXG2) of the second transfer transistor are not disposed.

[0158] Can be respectively Fig.11 The components corresponding to Figure 8 The description of the components can also be applied to Fig.11 The components of Figure 8 The description provided does not match Fig.11 The descriptions of the constituent components conflict.

[0159] Fig.12 is a diagram showing some implementations based on the disclosed technology. Figures 4 to 7 A cross-sectional view of an example of a unit pixel taken along line EE'.

[0160] Reference Figure 4 and Fig.12 , along Figure 4The fifth cross-section 1200 of the unit pixel 30 taken along the line EE′ may be an example of a cross-section of the unit pixel 30 taken along the line EE′.

[0161] Although the fifth cross section 1200 is along Figure 4 The cross-section is not a cross-section taken along the line EE', but the cross-section of another portion taken along the line EE' (i.e., the portion taken along the line intersecting the gate (RSTG) of the reset transistor, the gate (SFG) of the source follower transistor, and the gate (TXG1) of the first transfer transistor) may also have a structure substantially the same as the fifth cross-section 1200.

[0162] The fifth cross section 1200 may include a semiconductor substrate 1250, an epitaxial region 1230, a first pixel isolation structure 310, a pixel insulation structure 350, a first photoelectric conversion element (PD1), a gate of a source follower transistor (SFG), a gate of a first transfer transistor (TXG1), and a gate of a reset transistor (RSTG).

[0163] The semiconductor substrate 1250 may include a first surface 1210 onto which light is incident and a second surface 1220 facing or opposite to the first surface 1210 .

[0164] The first pixel isolation structure 310 may be recessed from the second surface 1220 toward the inside of the semiconductor substrate 1250 , and may be disposed at each of both ends of the unit pixel 30 .

[0165] The pixel insulation structure 350 may be disposed adjacent to the first pixel isolation structure 310. The pixel insulation structure 350 may be further disposed between the gate (RSTG) of the reset transistor and the gate (SFG) of the source follower transistor adjacent to the gate (RSTG) of the reset transistor, and may be further disposed between the gate (SFG) of the source follower transistor and the gate (TXG1) of the first transfer transistor. When a voltage equal to or greater than the threshold voltage is applied to the gate of the transistor, a channel through which carriers may move may be created under the gate of the transistor, and the pixel insulation structure 350 may guide the carriers to move in the channel to prevent leakage of these carriers.

[0166] The first photoelectric conversion element ( PD1 ) may be disposed between first pixel isolation structures 310 disposed at both ends of the unit pixel 30 in the semiconductor substrate 1250 .

[0167] The gate (SFG) of the source follower transistor may be disposed on the second surface 1220. When viewed in the third direction D3, the gate (SFG) of the source follower transistor may overlap with the first photoelectric conversion element (PD1).

[0168] The gate (TXG1) of the first transfer transistor may be disposed on the second surface 1220. When viewed in the third direction D3, the gate (TXG1) of the first transfer transistor may overlap with the first photoelectric conversion element (PD1). The gate (TXG1) of the first transfer transistor may be disposed to be spaced apart from the gate (SFG) of the source follower transistor in the second direction D2.

[0169] The gate (RSTG) of the reset transistor may be disposed on the second surface 1220. When viewed in the third direction D3, the gate (RSTG) of the reset transistor may overlap with the first photoelectric conversion element (PD1). The gate (RSTG) of the reset transistor may be arranged to be spaced apart from the gate (SFG) of the source follower transistor in the second direction D2. One terminal of the reset transistor may be electrically connected to the first floating diffusion region (FD1) and the second floating diffusion region (FD2), and the other terminal of the reset transistor may be a region to which a power supply voltage may be applied. One terminal may correspond to the drain of the reset transistor, the other terminal may correspond to the source of the reset transistor, and each of the source and drain of the reset transistor may be disposed in the first direction (D1) relative to the gate (RSTG) of the reset transistor.

[0170] The epitaxial region 1230 may be a region not doped with impurities. The epitaxial region 1230 may be a region where the first pixel isolation structure 310, the pixel insulation structure 350, the buried portion (TXG1b) of the gate (TXG1) of the first transfer transistor, and the first photoelectric conversion element (PD1) are not disposed in the semiconductor substrate 1250.

[0171] Can be respectively Fig.12 The components corresponding to Figure 8 The description of the components can also be applied to Fig.12 The components of Figure 8 The description provided does not match Fig.12 The descriptions of the constituent components conflict.

[0172] As apparent from the above description, an image sensing device based on some implementations of the disclosed technology can reduce the amount of noise generated in an electrical signal output from a pixel by ensuring a large gate area of ​​a source follower transistor.

[0173] The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0174] Although a number of exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments are contemplated based on what is described and / or illustrated in this patent document.

[0175] CROSS-REFERENCE TO RELATED APPLICATIONS

[0176] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0122368, filed on September 14, 2023, the disclosure of which is incorporated herein by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a semiconductor substrate including a first surface onto which light from a scene is incident and a second surface facing or opposite to the first surface; a first photoelectric conversion element and a second photoelectric conversion element, the first photoelectric conversion element and the second photoelectric conversion element being supported by the semiconductor substrate and spaced apart from each other, each photoelectric conversion element receiving incident light and generating photocharges by sensing the received incident light; a first pixel isolation structure, which is recessed from the second surface and surrounds the first photoelectric conversion element and the second photoelectric conversion element; a second pixel isolation structure and a third pixel isolation structure, the second pixel isolation structure and the third pixel isolation structure being disposed between the first photoelectric conversion element and the second photoelectric conversion element and spaced apart from each other; as well as A source follower transistor is supported by the semiconductor substrate and includes a gate, the gate of the source follower transistor being disposed on the second surface in at least a portion of a gap region between the second pixel isolation structure and the third pixel isolation structure.

2. The image sensing device according to claim 1, wherein: The gate of the source follower transistor is disposed to overlap with at least one of the first photoelectric conversion element and the second photoelectric conversion element.

3. The image sensing device according to claim 1, wherein: Each of the second pixel isolation structure and the third pixel isolation structure is in contact with the first pixel isolation structure.

4. The image sensing device according to claim 1, further comprising: A fourth pixel isolation structure is disposed in the gap region.

5. The image sensing device according to claim 1, further comprising: a first floating diffusion region storing photocharges generated by the first photoelectric conversion element in response to the incident light; as well as A second floating diffusion region stores photocharges generated by the second photoelectric conversion element in response to the incident light.

6. The image sensing device according to claim 5, further comprising: a first transfer transistor having a first terminal electrically connected to the first photoelectric conversion element and a second terminal electrically connected to the first floating diffusion region; as well as A second transfer transistor has a first terminal electrically connected to the second photoelectric conversion element and a second terminal electrically connected to the second floating diffusion region.

7. The image sensing device according to claim 6, wherein: The gate of the first transfer transistor overlaps with the first photoelectric conversion element and is disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor; and A gate of the second transfer transistor overlaps with the second photoelectric conversion element, and is disposed on the second surface of the semiconductor substrate to be spaced apart from a gate of the source follower transistor.

8. The image sensing device according to claim 6, wherein: The gate of the first transfer transistor includes a structure recessed from the second surface toward the inside of the semiconductor substrate, and is disposed in the semiconductor substrate to be spaced apart from the first floating diffusion region; and The gate of the second transfer transistor includes a structure recessed from the second surface toward the inside of the semiconductor substrate, and is disposed within the semiconductor substrate to be spaced apart from the second floating diffusion region.

9. The image sensing device according to claim 5, further comprising: a reset transistor supported by the semiconductor substrate and including a gate, the gate of the reset transistor overlapping the first photoelectric conversion element and being disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor, The reset transistor drains the photocharges stored in the first floating diffusion region and the second floating diffusion region.

10. The image sensing device according to claim 1, further comprising: a selection transistor supported by the semiconductor substrate and including a gate, the gate of the selection transistor overlapping the second photoelectric conversion element and disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor, The selection transistor outputs an electrical signal having a voltage level corresponding to the photocharge generated by the first photoelectric conversion element or the second photoelectric conversion element.

11. The image sensing device according to claim 1, further comprising: a draining transistor supported by the semiconductor substrate and including a gate, the gate of the draining transistor overlapping the first photoelectric conversion element and disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor, The photocharge generated by the first photoelectric conversion element or the second photoelectric conversion element is reset by the drain transistor.

12. The image sensing device according to claim 6, further comprising: a dual conversion gain DCG transistor supported by the semiconductor substrate and including a gate, the gate of the DCG transistor overlapping the first photoelectric conversion element and disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor, The DCG transistor changes the capacitance of at least one of the first floating diffusion region and the second floating diffusion region.

13. The image sensing device according to claim 5, further comprising: a metal interconnection layer that contacts each of the first floating diffusion region and the second floating diffusion region while being located outside the semiconductor substrate, The metal interconnection layer electrically connects the first floating diffusion region and the second floating diffusion region to each other.

14. An image sensing device, comprising: a semiconductor substrate including a first surface onto which light is incident and a second surface facing or opposite to the first surface; a first photoelectric conversion element supported by the semiconductor substrate and generating photocharges in response to incident light; a second photoelectric conversion element supported by the semiconductor substrate and spaced apart from the first photoelectric conversion element and generating photocharges in response to the incident light; as well as a source follower transistor supported by the semiconductor substrate and including a gate disposed in a gap region between the first photoelectric conversion element and the second photoelectric conversion element, wherein a gate of the source follower transistor overlaps at least a portion of each of the first photoelectric conversion element and the second photoelectric conversion element arranged in a first direction perpendicular to the second surface.

15. The image sensing device according to claim 14, further comprising: a first transfer transistor supported by the semiconductor substrate and including a gate, the gate of the first transfer transistor overlapping the first photoelectric conversion element in the first direction and disposed on the second surface of the semiconductor substrate to be spaced apart from the gate of the source follower transistor; as well as A second transfer transistor, which is supported by the semiconductor substrate and includes a gate, the gate of the second transfer transistor overlapping the second photoelectric conversion element in the first direction and arranged on the second surface of the semiconductor substrate to be spaced apart from both the gate of the source follower transistor and the gate of the first transfer transistor.

16. The image sensing device according to claim 15, further comprising: A floating diffusion region is supported by the semiconductor substrate in a space between the gate of the first transfer transistor and the gate of the second transfer transistor and is arranged adjacent to the second surface of the semiconductor substrate.

17. The image sensing device according to claim 15, further comprising: a first floating diffusion region, the first floating diffusion region being spaced apart from the gate of the first transfer transistor, the first floating diffusion region being disposed in the semiconductor substrate and adjacent to the second surface; as well as A second floating diffusion region is spaced apart from the gate of the second transfer transistor, the second floating diffusion region is disposed in the semiconductor substrate and adjacent to the second surface.

18. The image sensing device according to claim 17, further comprising: a metal interconnection layer that contacts each of the first floating diffusion region and the second floating diffusion region while being located outside the semiconductor substrate, The metal interconnection layer electrically connects the first floating diffusion region and the second floating diffusion region to each other.

19. The image sensing device according to claim 14, further comprising: A pixel isolation structure is recessed from the first surface of the semiconductor substrate corresponding to the gap area toward the inside of the semiconductor substrate.

20. The image sensing device according to claim 16, wherein: The first photoelectric conversion element and the second photoelectric conversion element share the floating diffusion region.

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