Back contact solar cell and method of manufacturing the same

Abstract

The application provides a back contact solar cell and a preparation method thereof. By adopting a technical means of "coating sol-annealing solidification", a patterned sacrificial layer with a preset roughness is conveniently prepared, and by matching the relative thicknesses of related film layers, at least the tip of the patterned sacrificial layer is not completely covered by the film layer formed later. Based on this, the subsequent etching step is continued, so as to facilitate the etching removal of the patterned sacrificial layer through the exposed tip, and the target film layer covering the patterned sacrificial layer can be peeled off. In this way, by adopting the preparation method provided by the application, the photolithography process or the laser ablation process which are expensive and complicated in the related art can be omitted, and the p region (for example, a first carrier collection layer) and the n region (for example, a second carrier collection layer) arranged in an interdigital manner are conveniently and low-costly prepared, and the process difficulty and the preparation cost are effectively reduced.

Description

Technical Field

[0001] This invention relates to a back-contact solar cell and its fabrication method, belonging to the field of semiconductor materials. Background Technology

[0002] Back-contact solar cells move the emitter (p-region) from the front side of the traditional heterojunction solar cell structure to the back side, forming an interdigitated back contact with the back field (n-region). This not only effectively improves the cell's response to short-wavelengths and avoids light loss due to shading by the front metal electrode, significantly increasing the short-circuit current, but also greatly increases the open-circuit voltage. Therefore, this cell structure combines high open-circuit voltage and high short-circuit current, further enhancing conversion efficiency and becoming a research hotspot for major research institutions and companies.

[0003] In related technologies, p-regions and n-regions are fabricated on the back side of back-contact solar cells using photolithography or laser ablation processes. However, these methods suffer from complex processes and high production costs, hindering large-scale manufacturing. Therefore, developing a simple and low-cost method for producing back-contact solar cells has become a current research direction. Summary of the Invention

[0004] This invention provides a method for fabricating a back-contact solar cell, which is characterized by simple process and low cost.

[0005] The present invention also provides a back-contact solar cell, which has the advantages of low production difficulty and low production cost.

[0006] On one hand, the present invention provides a method for fabricating a back-contact solar cell, comprising: providing a substrate (10), the substrate (10) comprising a first surface and a second surface disposed opposite to each other; wherein, the method further comprises:

[0007] An initial second passivation layer (50a) is formed on the second surface of the substrate (10);

[0008] An initial first carrier collection layer (60a) of a first conductivity type is formed on the side of the initial second passivation layer (50a) opposite to the substrate (10);

[0009] A patterned sacrificial layer (70) with an interdigitated opening pattern is formed on the side of the initial first carrier collection layer (60a) opposite to the substrate (10); the surface of the patterned sacrificial layer (70) is formed to include a plurality of tips.

[0010] Using the patterned sacrificial layer (70) as a mask, the initial first carrier collection layer (60a) and the initial second passivation layer (50a) exposed by the interdigitated opening pattern are removed by a first type of etching process to form the first carrier collection layer (60) and the second passivation layer (50) respectively, and to expose part of the second surface of the substrate (10).

[0011] A stacked third passivation layer (80) and a second carrier collection layer (90) of the second conductivity type are sequentially formed on the second surface exposed by the patterned sacrificial layer (70) and the substrate (10); wherein at least a portion of the tip of the patterned sacrificial layer (70) is not completely covered by the third passivation layer (80) and the second carrier collection layer (90);

[0012] The patterned sacrificial layer (70) is removed by etching the exposed tip using a second type of etching process, and a portion of the third passivation layer (80) and a portion of the second carrier collection layer (90) covering the patterned sacrificial layer (70) are also stripped; the remaining second carrier collection layer (90) is arranged in an intersecting pattern with the first carrier collection layer (60).

[0013] The method for fabricating a back-contact solar cell as described above, wherein the step of forming a patterned sacrificial layer (70) with an interdigitated opening pattern on the side of the initial first carrier collection layer (60a) facing away from the substrate (10) includes:

[0014] A silica sol layer with an interdigitated pattern is formed by coating the initial first carrier collection layer (60a) on the side opposite to the substrate (10) with silica sol.

[0015] The silica sol layer is subjected to annealing and curing treatment to form a silica layer with a preset roughness; the silica layer serves as the patterned sacrificial layer (70).

[0016] In the method for preparing a back-contact solar cell as described above, the silica sol contains 29-31 wt% silica, has a pH of 9.0-10.5, and a viscosity of ≤6.5 mm. 2 / s.

[0017] In the preparation method of the back contact solar cell as described above, the annealing and curing treatment is carried out at a temperature of 150℃-220℃ for a duration of 15min-60min.

[0018] In the method for fabricating a back-contact solar cell as described above, the thickness of the patterned sacrificial layer (70) is 5 μm-50 μm;

[0019] The roughness of the patterned sacrificial layer (70) is 1μm-50μm.

[0020] In the method for fabricating a back-contact solar cell as described above, the thickness of the first passivation layer (20) and / or the second passivation layer (50) is 3 nm-10 nm; and / or,

[0021] The thickness of the first carrier collection layer (60) and / or the second carrier collection layer (90) is 10nm-30nm.

[0022] The fabrication method of the back contact solar cell as described above, wherein the first type of etching process includes: alkaline etching process; the duration of the first type of etching process is 5 min-10 min;

[0023] The second type of etching process includes: acid etching; the duration of the second type of etching process is 1 min to 20 min.

[0024] In the method for fabricating a back-contact solar cell as described above, the ratio of the thickness of the patterned sacrificial layer (70) to the sum of the thicknesses of the third passivation layer (80) and the second carrier collection layer (90) is in the range of 200 to 10000.

[0025] The method for fabricating a back-contact solar cell as described above, wherein the method further includes:

[0026] A transparent conductive layer (100) is formed on the side of the first carrier collection layer (60) and the second carrier collection layer (90) away from the substrate (10); the transparent conductive layer (100) has a plurality of isolation trenches for isolating the portion of the transparent conductive layer (100) covering the first carrier collection layer (60) from the portion of the transparent conductive layer (100) covering the second carrier collection layer (90);

[0027] A gate electrode (MO) is formed on the side of the transparent conductive layer opposite to the substrate.

[0028] The method for fabricating a back-contact solar cell as described above, wherein the method further includes:

[0029] A first passivation layer (20), a first conductivity type doped layer (30), and an antireflection layer (40) are formed on the first surface of the substrate (10) in a direction opposite to the substrate (10) in sequence.

[0030] The present invention also provides a back contact solar cell, wherein the back contact solar cell includes a substrate (10), a first passivation layer (20), a doped layer (30), an antireflection layer (40), a second passivation layer (50), a first carrier collection layer (60), a third passivation layer (80), a second carrier collection layer (90), a transparent conductive layer (100), and a grid electrode (M0).

[0031] The substrate (10) has two surfaces;

[0032] A first passivation layer (20), a first conductivity type doped layer (30), and an antireflection layer (40) are sequentially stacked on one surface of the substrate (10) in a direction away from the substrate (10);

[0033] The other surface of the substrate (10) is provided with a second passivation layer (50) and a third passivation layer (80) that are in contact with each other;

[0034] The second passivation layer (50) has a first carrier collection layer (60) disposed on its surface in a direction away from the substrate (10). The first carrier collection layer (60) and the third passivation layer (80) are separated by the third passivation layer (80) and are arranged in a cross pattern.

[0035] The first carrier collection layer (60) and the second carrier collection layer (90) have a transparent conductive layer (100) on the side opposite to the substrate (10); the transparent conductive layer (100) has a plurality of isolation grooves;

[0036] The transparent conductive layer has a gate electrode (M0) on the side opposite to the substrate (10).

[0037] The back-contact solar cell fabrication method provided by this invention utilizes a "sol-coating-annealing and curing" technique to conveniently prepare a patterned sacrificial layer with a preset roughness. By matching the relative thicknesses of the relevant film layers, it ensures that the tip of the patterned sacrificial layer is not completely covered by the subsequently formed film layers (e.g., the third passivation layer and the second carrier collection layer). Based on this, subsequent etching steps are performed to facilitate the removal of the patterned sacrificial layer through etching the exposed tip, and the target film layer covering the patterned sacrificial layer can also be peeled off. Thus, using the fabrication method provided by this invention, the expensive and complex photolithography or laser ablation processes of related technologies can be eliminated, and the interdigitated p-regions (e.g., the first carrier collection layer) and n-regions (e.g., the second carrier collection layer) can be prepared relatively conveniently and at low cost, effectively reducing the process difficulty and fabrication cost. Attached Figure Description

[0038] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0039] Figure 1 This is a flowchart illustrating the fabrication process of the back-contact solar cell provided in Embodiment 1 of the present invention.

[0040] Figures 2 to 15 This is a structural diagram illustrating the fabrication process of the back-contact solar cell provided in Embodiment 1 of the present invention.

[0041] Explanation of reference numerals in the attached figures:

[0042] 10-Substrate; 20-First passivation layer; 30-Doped layer; 40-Antireflection layer; 50a-Initial second passivation layer; 50-Second passivation layer; 60a-Initial first carrier collection layer; 60-First carrier collection layer; 70-Patterned sacrificial layer; 80-Third passivation layer; 90-Second carrier collection layer; 100-Transparent conductive layer; M0-Gate electrode. Detailed Implementation

[0043] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0046] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] The first aspect of this invention provides a method for preparing a back-contact solar cell.

[0048] In the method for fabricating a back-contact solar cell provided by this invention, each layer structure can be generated using methods commonly used in the art, such as PECVD, unless otherwise specified.

[0049] The first conductivity type is selected from either p-type or n-type; the second conductivity type is selected from either p-type or n-type.

[0050] Figure 1 This is a flowchart illustrating the fabrication process of the back-contact solar cell provided in Embodiment 1 of the present invention, with reference to... Figure 1 The process includes:

[0051] Step S10: Provide a substrate 10, the substrate 10 including a first surface and a second surface disposed opposite to each other;

[0052] Step S20: A first passivation layer 20, a first conductivity type doped layer 30, and an antireflection layer 40 are formed on the first surface of the substrate in a direction away from the substrate.

[0053] Step S30: Form an initial second passivation layer 50a on the second surface of the substrate;

[0054] Step S40: Form an initial first carrier collection layer 60a of the first conductivity type on the side of the initial second passivation layer away from the substrate;

[0055] Step S50: A patterned sacrificial layer 70 with an interdigitated opening pattern is formed on the side of the initial first carrier collection layer 60a away from the substrate; the surface of the patterned sacrificial layer 70 is formed to include a morphology with multiple tips;

[0056] Step S60: Using the patterned sacrificial layer 70 as a mask, the initial first carrier collection layer 60a and the initial second passivation layer 50a exposed by the interdigitated opening pattern are removed by the first type of etching process, so as to form the first carrier collection layer 60 and the second passivation layer 50 respectively, and expose part of the second surface of the substrate 10.

[0057] Step S70: A stacked third passivation layer 80 and a second carrier collection layer 90 of the second conductivity type are sequentially formed on one of the exposed surfaces of the patterned sacrificial layer 70 and the substrate 10; wherein at least a portion of the tips of the patterned sacrificial layer 70 are not completely covered by the third passivation layer 80 and the second carrier collection layer 90.

[0058] Step S80: The patterned sacrificial layer 70 is removed by etching the exposed tip using a second type of etching process, and a portion of the third passivation layer 80 and a portion of the second carrier collection layer 90 covering the patterned sacrificial layer 70 are also stripped off; the remaining second carrier collection layer 90 is arranged in an intersecting pattern with the first carrier collection layer 60.

[0059] Step S90: A transparent conductive layer 100 is formed on the side of the first carrier collection layer 60 and the second carrier collection layer 90 away from the substrate 10; the transparent conductive layer 100 has a plurality of isolation trenches to isolate the portion of the transparent conductive layer 100 covering the first carrier collection layer 60 from the portion of the transparent conductive layer 100 covering the second carrier collection layer 90.

[0060] Step S100: A gate electrode M0 is formed on the side of the transparent conductive layer away from the substrate.

[0061] The first surface can be, for example, the light-incident surface of the battery, and the second surface can be, for example, the backlight surface of the battery. When the first surface is "another surface", the second surface is "one of the surfaces".

[0062] This invention does not limit the specific conductivity types of the first conductivity type and the second conductivity type; the first conductivity type and the second conductivity type are different. When the first conductivity type is n-type, the second conductivity type is p-type; when the first conductivity type is p-type, the second conductivity type is n-type.

[0063] The back-contact solar cell fabrication method provided by this invention can use relatively mature and low-cost processes (such as screen printing and PECVD processes) to produce back-contact solar cells without the need for photolithography or laser processes, and has the characteristics of low production difficulty and low production cost.

[0064] Figures 2 to 15 This is a structural diagram illustrating the fabrication process of a back-contact solar cell according to the first embodiment of the present invention. The upper surface of the substrate 10 is the first surface, and the lower surface of the substrate 10 is the second surface.

[0065] refer to Figure 3 and Figure 4 An initial second passivation layer 50a is formed on the second surface of the substrate; an initial first carrier collection layer 60a of a first conductivity type is formed on the side of the initial second passivation layer 50a facing away from the substrate. Figure 3 This is a sectional view. Figure 4 To and Figure 3 The corresponding bottom view.

[0066] The initial second passivation layer 50a and the first passivation layer 20 can be made of the same material.

[0067] The initial first carrier collection layer 60a of the first conductivity type is composed of phosphorus-doped amorphous silicon or microcrystalline silicon, and its main function is to collect photogenerated electrons.

[0068] refer to Figure 5 and Figure 6 A patterned sacrificial layer 70 with an interdigitated opening pattern is formed on the side of the initial first carrier collection layer 60a facing away from the substrate; the surface of the patterned sacrificial layer 70 is formed with a morphology including multiple tips. Figure 5 This is a sectional view. Figure 6 To and Figure 5 The corresponding bottom view.

[0069] The patterned sacrificial layer 70 is a temporary mask layer used to form a specific pattern in a designated area to mask parts that do not need to be processed. It is then etched away in subsequent processes, leaving behind the specific structure and pattern. This invention does not limit the specific material of the patterned sacrificial layer 70; commonly used materials in the art, such as silicon dioxide, can be used.

[0070] The morphology of the tip can be referenced. Figure 11 .Depend on Figure 11 Thus, the patterned sacrificial layer 70 has six triangular structures protruding from the third passivation layer 80 and the second carrier collection layer 90, which are the tips. The present invention does not limit the specific shape of the tips, and other patterns may also be used.

[0071] also, Figure 6 Using a forked opening pattern as an illustration, where a forked opening pattern is... Figure 6 The patterned sacrificial layer 70 forms a structure consisting of two protrusions and one concave portion. The accompanying drawings illustrate only one interdigitated opening pattern, but the invention does not limit the number of interdigitated opening patterns. Specifically, the patterned sacrificial layer 70 may contain multiple interdigitated opening patterns composed of concave and convex portions, and the specific number of interdigitated opening patterns can be matched and set according to actual needs.

[0072] refer to Figure 7 and Figure 8 Using the patterned sacrificial layer 70 as a mask, a first-type etching process is employed to remove the initial first carrier collection layer 60a and the initial second passivation layer 50a exposed by the interdigitated opening pattern, thereby forming the first carrier collection layer 60 and the second passivation layer 50, and exposing a portion of the second surface of the substrate 10. Figure 7 This is a sectional view. Figure 8 To and Figure 7 The corresponding bottom view.

[0073] During the etching process of the first type of etching process, the structure covered by the patterned sacrificial layer 70 with the interdigitated opening pattern cannot be removed, while the uncovered structure is removed in the process.

[0074] Specifically, in the above process, the initial first carrier collection layer 60a and the initial second passivation layer 50a, which are not covered by the patterned sacrificial layer 70 with the interdigitated opening pattern, are removed by the first type of etching process. The initial first carrier collection layer 60a covered by the patterned sacrificial layer 70 that is not removed forms the first carrier collection layer 60, and the initial second passivation layer 50a covered by the patterned sacrificial layer 70 that is not removed forms the second passivation layer 50.

[0075] This invention does not limit the specific process used in the first type of etching process, as long as it meets the requirement of removing the initial first carrier collection layer 60a and the initial second passivation layer 50a. For example, an alkaline etching process can be used. Furthermore, by adjusting process parameters such as etching duration, the substrate 10 can be used as an etching stop layer to ensure that the portion of the initial first carrier collection layer 60a and the initial second passivation layer 50a exposed by the opening pattern is completely removed. That is, the first type of etching can "over-etch" away a portion of the substrate 10 material.

[0076] refer to Figures 9 to 11 A third passivation layer 80 and a second carrier collection layer 90 of the second conductivity type are sequentially formed on the patterned sacrificial layer 70 and the second surface exposed by the substrate 10; wherein at least a portion of the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90.

[0077] Figure 9 This is a sectional view. Figure 10 To and Figure 9 The corresponding bottom view, Figure 11 for Figure 9 Top view of section A.

[0078] exist Figure 7 and Figure 8In the fabrication process shown, after removing part of the initial first carrier collection layer 60a and the initial second passivation layer 50a using a first-type etching process, the patterned sacrificial layer 70 and the substrate 10 not covered by the patterned sacrificial layer 70 are exposed. At this time, a stacked third passivation layer 80 and a second carrier collection layer 90 of the second conductivity type can be sequentially formed on the patterned sacrificial layer 70 and the second surface exposed on the substrate 10.

[0079] In this design, at least a portion of the tips of the patterned sacrificial layer 70 are not completely covered by the third passivation layer 80 and the second carrier collection layer 90. This facilitates the removal of the patterned sacrificial layer 70 by etching with the exposed tips in subsequent steps, and allows for the successful stripping of the associated film structures covering the patterned sacrificial layer 70.

[0080] like Figure 11 As shown, at least a portion of the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90; that is, at least a portion of the patterned sacrificial layer 70 can contact the outside environment. It is worth noting that... Figure 11 This invention is not limited to the specific shape of the tip of the patterned sacrificial layer 70, but only one possible configuration shape for the tip of the patterned sacrificial layer 70. Other shapes are possible as long as the requirement that at least part of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90 is met.

[0081] The material of the third passivation layer 80 is the same as that of the first passivation layer 20.

[0082] The second carrier collection layer 90 of the second conductivity type has a different conductivity type than the first carrier collection layer 60 of the first conductivity type.

[0083] refer to Figures 12 to 13 The second type of etching process is used to remove the patterned sacrificial layer 70 by etching the exposed tip, and also peels off a portion of the third passivation layer 80 and a portion of the second carrier collection layer 90 covering the patterned sacrificial layer 70; the remaining second carrier collection layer 90 is arranged in an interdigital pattern with the first carrier collection layer 60. Figure 12 This is a sectional view. Figure 13 To and Figure 12 The corresponding bottom view.

[0084] Specifically, at least the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90, and is therefore etched during the etching process using the second type of etching process due to contact with the etchant. The etchant enters the voids created by the etched patterned sacrificial layer 70 and continues to erode the patterned sacrificial layer 70 covered by the third passivation layer 80 and the second carrier collection layer 90. Eventually, the patterned sacrificial layer 70 is completely removed, and consequently, a portion of the third passivation layer 80 and a portion of the second carrier collection layer 90 covering the patterned sacrificial layer 70 are also peeled off along with the patterned sacrificial layer 70 due to the loss of their adhesion base.

[0085] like Figure 13 As shown, after the etching process using the second type of etching process is completed, the retained second carrier collection layer 90 and the first carrier collection layer 60 are arranged in a cross pattern and isolated by the third passivation layer 80. Specifically, the cross pattern means that the second carrier collection layer 90 has one protrusion and multiple recesses, and the first carrier collection layer 60 has one recess and multiple protrusions. The protrusion of the second carrier collection layer 90 is positioned opposite the recess of the first carrier collection layer 60, spaced apart from the third passivation layer 80, and the recess of the second carrier collection layer 90 is positioned opposite the protrusion of the first carrier collection layer 60, spaced apart from the third passivation layer 80.

[0086] The accompanying drawings of this application only illustrate one cross arrangement, but this application does not limit the number of cross arrangements. Specifically, both the first carrier collection layer 60 and the second carrier collection layer 90 may include multiple cross arrangements composed of concave and convex portions. The specific number of cross arrangements can be matched and set according to actual needs to achieve cross arrangements between the first carrier collection layer 60 and the second carrier collection layer 90.

[0087] This invention does not limit the specific process used in the second type of etching process, as long as it meets the requirement of removing the patterned sacrificial layer 70. For example, an acid etching process can be used.

[0088] refer to Figures 14 to 15 A transparent conductive layer 100 is formed on the side of the first carrier collection layer 60 and the second carrier collection layer 90 away from the substrate 10. The transparent conductive layer 100 has a plurality of isolation trenches to isolate the portion of the transparent conductive layer 100 covering the first carrier collection layer 60 from the portion of the transparent conductive layer 100 covering the second carrier collection layer 90.

[0089] A gate electrode M0 is formed on the side of the transparent conductive layer away from the substrate.

[0090] The transparent conductive layer 100 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO) to ensure good conductivity and light transmittance. This invention does not limit the method of forming the transparent conductive layer 100; methods commonly used in the art, such as physical vapor deposition, sputtering, or electron beam evaporation, may be employed.

[0091] In addition, patterning techniques such as photolithography, laser etching, or inkjet printing can be used to form multiple isolation trenches in the transparent conductive layer 100 to isolate the transparent conductive layer portion covering the first carrier collection layer 60 from the transparent conductive layer portion covering the second carrier collection layer 90. In one embodiment, photoresist can be coated on the surface of the transparent conductive layer 100, and the pattern of the isolation trenches can be formed using photolithography with a mask; the material in the patterned areas of the transparent conductive layer 100 can be removed using dry etching such as plasma etching or wet etching such as acid etchant to form the isolation trenches. The width and depth of the isolation trenches are appropriately controlled to ensure complete isolation of the transparent conductive layer.

[0092] On the side of the transparent conductive layer 100 facing away from the substrate 10, a gate electrode M0 is formed for collecting and conducting current. The gate electrode M0 is typically made of silver or copper and is prepared using screen printing, inkjet printing, laser transfer, or electroplating techniques. In one embodiment, screen printing can be used to coat the surface of the transparent conductive layer with silver or copper paste to form a gate pattern, and the gate electrode can be cured by drying and sintering. Alternatively, a photolithography electroplating method can be used to form the gate pattern on the surface of the transparent conductive layer.

[0093] In one specific embodiment, the step of forming a patterned sacrificial layer 70 with an interdigitated opening pattern on the side of the initial first carrier collection layer 60a facing away from the substrate 10 includes:

[0094] A silica sol layer with an interdigitated pattern is formed by coating the initial first carrier collection layer 60a on the side opposite to the substrate 10 with silica sol.

[0095] The silica sol layer is subjected to annealing and curing treatment to form a silica layer with a preset roughness; the silica layer serves as a patterning sacrificial layer 70.

[0096] Silica sol is a mixture comprising silica and a solvent. Annealing and curing involves heating the silica sol to evaporate the solvent, transforming it into a patterned sacrificial layer 70 composed of silica. This invention does not limit the specific processing temperature and time of the annealing and curing process, as long as it meets the requirement of allowing the solvent in the silica sol to evaporate. A gap exists at the contact interface between the silica layer with a preset roughness and the initial first carrier collection layer 60a. During the etching process using the second type of etching process, the etchant can enter this gap, thereby dissolving the silica layer. This invention does not limit the roughness of the silica layer; a suitable roughness can be preset. For example, in one embodiment, the roughness is 1 μm-50 μm.

[0097] In another specific embodiment, the step of forming a patterned sacrificial layer 70 with an interdigitated opening pattern on the side of the second passivation layer 50 facing away from the substrate 10 includes:

[0098] A silica sol layer with an interdigitated pattern is formed by coating the second passivation layer 50 on the side opposite to the substrate 10 with silica sol.

[0099] The silica sol layer is subjected to annealing and curing treatment to form a silica layer with a preset roughness; the silica layer serves as a patterning sacrificial layer 70.

[0100] Silica sol is a mixture comprising silica and a solvent. Annealing and curing involves heating the silica sol to evaporate the solvent, transforming it into a patterned sacrificial layer 70 composed of silica. This invention does not limit the specific processing temperature and time of the annealing and curing process, as long as the solvent in the silica sol can evaporate. A gap exists at the interface between the silica layer with a preset roughness and the second passivation layer 50. During the etching process using the second type of etching process, the etchant can enter this gap, thereby dissolving the silica layer. This invention does not limit the roughness of the silica layer; a suitable roughness can be preset. For example, in one embodiment, the roughness is 1 μm-50 μm.

[0101] Furthermore, to further facilitate the formation of a silica layer with a predetermined roughness, in one embodiment, the silica sol contains a silica mass fraction of 29wt%-31wt%, a pH value of 9.0-10.5, and a viscosity of less than or equal to 6.5 mm. 2 / s.

[0102] Silica sol, also known as silica sol mSiO2·nH2O, is a dispersion of nano-sized silica particles in water. During the annealing and curing process, the water in the silica sol evaporates, forming a silica layer that serves as the patterned sacrificial layer 70. This invention does not limit the specific preparation method of the silica sol; common preparation methods in the art can be used. For example, water glass can be used as a raw material, and sodium ions can be removed through ion exchange resin treatment and sulfuric acid neutralization to obtain the silica sol. Alternatively, it can be prepared by hydrolysis of silicate esters.

[0103] In one embodiment, the annealing and curing treatment is carried out at a temperature of 150°C to 220°C for a duration of 15 min to 60 min. Suitable annealing and curing conditions facilitate the evaporation of solvents in the silica sol, thereby forming a silica layer with a predetermined roughness.

[0104] In a more specific embodiment, the patterned sacrificial layer 70 has a thickness of 5 μm-50 μm and a roughness of 1 μm-50 μm. The patterned sacrificial layer 70 with a suitable thickness ensures that at least a portion of its tips are not completely covered by the third passivation layer 80 or the initial first carrier collection layer 60a; the suitable roughness prevents structures (e.g., tips) deposited on the surface of the patterned sacrificial layer 70 from completely covering the silicon dioxide, creating appropriately sized gaps. During etching using the second-type etching process, the etchant can smoothly complete the etching of the silicon dioxide layer and the smooth removal of the structures covering its surface, thereby making the preparation method provided by this invention more efficient.

[0105] More specifically, the thickness of the first passivation layer 20 and / or the second passivation layer 50 can be controlled to be 3nm-10nm; the thickness of the first carrier collection layer 60 and / or the second carrier collection layer 90 can be controlled to be 10nm-30nm. Appropriate passivation layer and carrier collection layer thicknesses can enable the fabricated back-contact solar cell to have better electrical performance.

[0106] In one embodiment, the first type of etching process includes: alkaline etching; the duration of the first type of etching process includes 5-10 minutes. The alkaline etching process involves using an alkaline substance to etch the initial first carrier collection layer 60a and the initial second passivation layer 50a, wherein the alkaline substance can be an alkaline solution. This invention does not limit the specific selection of the alkaline solution; at least one of a 1-5 wt% sodium hydroxide aqueous solution, potassium hydroxide aqueous solution, or organic base aqueous solution can be selected as needed. Tetramethylammonium hydroxide (TMAH) can be used as the organic base. This invention also does not limit the time and temperature of the alkaline etching process; they can be selected according to actual needs. A suitable first type of etching process duration can achieve the etching requirements without causing excessive corrosion to the substrate 10, thereby resulting in a back-contact solar cell with better electrical performance.

[0107] In one embodiment, the ratio of the thickness of the patterned sacrificial layer 70 to the sum of the thicknesses of the third passivation layer 80 and the second carrier collection layer 90 can be controlled within a range of 200 to 10000. This range allows at least a portion of the tip of the patterned sacrificial layer 70 to be partially not completely covered by the third passivation layer 80 and the second carrier collection layer 90.

[0108] The second type of etching process includes acid etching; the duration of the second type of etching process ranges from 1 min to 20 min. Acid etching involves using an acidic substance to etch the patterned sacrificial layer 70, wherein the acidic substance can be an acidic solution. In one embodiment, the acidic solution is hydrofluoric acid with a concentration of 0.5-2% v / v, that is, in the hydrofluoric acid used for etching, the volume fraction of a 20% hydrofluoric acid solution is 0.5-2%. A suitable second type of etching process time can etch the patterned sacrificial layer 70 without damaging other components.

[0109] In one embodiment, the method for fabricating a back-contact solar cell provided by the present invention further includes the following process: forming a first passivation layer 20, a doped layer 30 of a first conductivity type, and an antireflection layer 40 sequentially stacked along a direction away from the substrate 10 on another surface of the substrate 10.

[0110] refer to Figure 2 On the other surface of the substrate 10, namely the surface where the initial second passivation layer 50a is not formed, a first passivation layer 20, a first conductivity type doped layer 30, and an antireflection layer 40 are formed in sequence along the direction away from the substrate.

[0111] The substrate 10 is made of high-purity single-crystal silicon, such as n-type single-crystal silicon; the first passivation layer 20 is made of intrinsic amorphous silicon, which helps to reduce the recombination of electrons and holes and improve battery efficiency; the anti-reflection layer 40 is made of silicon nitride, which allows sunlight to pass through and reduces light reflection, while also helping to protect the structure beneath the layer.

[0112] A second aspect of the present invention provides a back-contact solar cell. For example... Figure 14 and Figure 15 As shown, the back contact solar cell includes a substrate 10, a first passivation layer 20, a doped layer 30, an antireflection layer 40, a second passivation layer 50, a first carrier collection layer 60, a third passivation layer 80, a second carrier collection layer 90, a transparent conductive layer 100, and a grid electrode M0.

[0113] Substrate 10 has two surfaces;

[0114] A first passivation layer 20, a first conductivity type doped layer 30, and an antireflection layer 40 are sequentially stacked on one surface of the substrate 10 along the direction away from the substrate 10.

[0115] A second passivation layer 50 and a third passivation layer 80 that are in contact with each other are disposed on another surface of the substrate 10;

[0116] The second passivation layer 50 has a first carrier collection layer 60 disposed on its surface in the direction away from the substrate 10. The first carrier collection layer 60 and the third passivation layer 80 are separated by the third passivation layer 80 and are arranged in a cross pattern.

[0117] The first carrier collection layer 60 and the second carrier collection layer 90 have a transparent conductive layer 100 on the side away from the substrate 10; the transparent conductive layer 100 has a plurality of isolation grooves;

[0118] A gate electrode M0 is provided on the side of the transparent conductive layer away from the substrate 10.

[0119] In one embodiment, the battery can be prepared using the back-contact solar cell preparation method provided in the first aspect of the present invention.

[0120] The method for fabricating a back-contact solar cell provided by this invention is characterized by its simple process and low cost. The back-contact solar cell provided by the second aspect of this invention is characterized by its low production difficulty and low production cost.

[0121] The following detailed description of the back-contact solar cell, its preparation method, and its application provided by the present invention is illustrated through specific embodiments.

[0122] Example 1

[0123] This embodiment uses the following method to prepare a back-contact solar cell:

[0124] Step S10: Provide a substrate 10, the substrate 10 including a first surface and a second surface disposed opposite to each other;

[0125] Step S20: A first passivation layer 20, a first conductivity type doped layer 30, and an antireflection layer 40 are formed on the first surface of the substrate in a direction away from the substrate.

[0126] Step S30: Form an initial second passivation layer 50a on the second surface of the substrate;

[0127] Step S40: Form an initial first carrier collection layer 60a of the first conductivity type on the side of the initial second passivation layer away from the substrate;

[0128] Step S50: A patterned sacrificial layer 70 with an interdigitated opening pattern is formed on the side of the initial first carrier collection layer 60a away from the substrate; the surface of the patterned sacrificial layer 70 is formed to include a morphology with multiple tips;

[0129] Step S60: Using the patterned sacrificial layer 70 as a mask, the initial first carrier collection layer 60a and the initial second passivation layer 50a exposed by the interdigitated opening pattern are removed by the first type of etching process, so as to form the first carrier collection layer 60 and the second passivation layer 50 respectively, and expose part of the second surface of the substrate 10.

[0130] Step S70: A stacked third passivation layer 80 and a second carrier collection layer 90 of the second conductivity type are sequentially formed on the patterned sacrificial layer 70 and the second surface exposed by the substrate 10; wherein the ratio of the thickness of the patterned sacrificial layer 70 to the sum of the thicknesses of the third passivation layer 80 and the second carrier collection layer 90 is in the range of 200 to 10000, so that at least a portion of the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90;

[0131] Step S80: The patterned sacrificial layer 70 is removed by etching the exposed tip using a second type of etching process, and a portion of the third passivation layer 80 and a portion of the second carrier collection layer 90 covering the patterned sacrificial layer 70 are also stripped off; the remaining second carrier collection layer 90 is arranged in an intersecting pattern with the first carrier collection layer 60.

[0132] Step S90: A transparent conductive layer 100 is formed on the side of the first carrier collection layer 60 and the second carrier collection layer 90 away from the substrate 10; the transparent conductive layer 100 has a plurality of isolation trenches to isolate the portion of the transparent conductive layer 100 covering the first carrier collection layer 60 from the portion of the transparent conductive layer 100 covering the second carrier collection layer 90.

[0133] Step S100: A gate electrode M0 is formed on the side of the transparent conductive layer away from the substrate.

[0134] A back-contact solar cell A1 was fabricated.

[0135] In the above process:

[0136] The annealing and curing treatment temperature is 190℃, and the treatment time is 25 minutes.

[0137] The first type of etching process uses a 2% sodium hydroxide solution for alkaline etching, and the processing time is 5 minutes.

[0138] The second type of etching process uses a 1% hydrofluoric acid solution for acid etching, and the processing time is 5 minutes.

[0139] The thickness data of each layer of the back contact solar cell A1 are as follows:

[0140] Substrate 10: 150 μm;

[0141] First passivation layer: 20: 6nm;

[0142] The first conductivity type of doped layer is 30: 10 nm;

[0143] Antireflection layer 40: 80nm;

[0144] Second passivation layer 50: 6nm;

[0145] First carrier collection layer 60: 20nm

[0146] Third passivation layer: 80: 6nm;

[0147] Second carrier collection layer: 90: 20nm;

[0148] The patterned sacrificial layer 70 has a thickness of 50 μm and a roughness of 30 μm.

[0149] Comparative Example 1

[0150] This comparative example refers to the process flow of the background technology in Chinese Patent CN117577709B, and uses the following conventional process to fabricate a back-contact solar cell:

[0151] S11, double-sided polishing of silicon wafers;

[0152] S12. A first mask layer is deposited on the back of the silicon wafer for protection; the thickness of the first mask layer is 200nm;

[0153] S13. Silicon wafer texturing and cleaning: A pyramid textured surface is formed opposite to the first mask layer. Then, the first mask layer is removed to form a silicon wafer with a single-sided texturing and single-sided polishing structure.

[0154] S14. A first semiconductor layer and a second mask layer are sequentially deposited on the back of the silicon wafer. The first semiconductor layer includes an intrinsic amorphous or microcrystalline silicon layer and an n-type doped amorphous or microcrystalline silicon layer. The second mask layer is generally silicon nitride. The thickness of the first semiconductor layer is 25nm and the thickness of the second mask layer is 200nm.

[0155] S15. Laser or etch an opening on the back of the silicon wafer to remove the second mask layer and part of the first semiconductor layer, forming a second semiconductor opening region; the width of the second semiconductor opening region is 700μm.

[0156] S16. Silicon wafer cleaning to remove the first semiconductor layer in the second semiconductor opening region;

[0157] S17. An amorphous layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer, and a second semiconductor layer is formed on the back side. The second semiconductor layer includes an intrinsic amorphous or microcrystalline silicon layer and a p-type doped amorphous or microcrystalline silicon layer. The thickness of the amorphous layer is 10nm, the thickness of the anti-reflection layer is 85nm, and the thickness of the second semiconductor layer is 25nm.

[0158] S18. Laser or etched openings on the back of the silicon wafer to form a first semiconductor opening region that alternates with the second semiconductor opening region; the width of the first semiconductor opening region is 300μm.

[0159] S19. Silicon wafer cleaning to remove the second mask layer in the first semiconductor opening area;

[0160] S20, A conductive film layer is deposited on the back of the silicon wafer; the thickness of the conductive film layer is 100nm;

[0161] S21. An isolation trench is formed between the first semiconductor opening region and the second semiconductor opening region by means of laser or etching.

[0162] S22. Metal electrodes are formed on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer.

[0163] Back-contact solar cell B1 was fabricated.

[0164] Test case

[0165] The following tests were conducted using batteries A1 and B1: Under standard measurement conditions, the test temperature was 25℃ and the light intensity was 1000W / m². 2 AM1.5 spectral analysis was performed. The test results are shown in Table 1.

[0166] Table 1 Test results of electrical parameters of each battery

[0167]

[0168] As shown in Table 1, battery A1 has similar electrical performance to battery B1, which is made using common processes in the field. This indicates that the back-contact solar cell preparation method provided by the present invention uses relatively mature and low-cost processes (such as screen printing and PECVD processes) to prepare back-contact solar cells without the need for photolithography or laser ablation processes, and has the characteristics of low production difficulty and low production cost.

Claims

1. A method for fabricating a back-contact solar cell, comprising: A substrate (10) is provided, the substrate (10) including a first surface and a second surface disposed opposite to each other; characterized in that it further includes: An initial second passivation layer (50a) is formed on the second surface of the substrate (10); An initial first carrier collection layer (60a) of a first conductivity type is formed on the side of the initial second passivation layer (50a) opposite to the substrate (10). A patterned sacrificial layer (70) with an interdigitated opening pattern is formed on the side of the initial first carrier collection layer (60a) opposite to the substrate (10); the surface of the patterned sacrificial layer (70) is formed to include a plurality of tips. Using the patterned sacrificial layer (70) as a mask, the initial first carrier collection layer (60a) and the initial second passivation layer (50a) exposed by the interdigitated opening pattern are removed by a first type of etching process to form the first carrier collection layer (60) and the second passivation layer (50) respectively, and to expose part of the second surface of the substrate (10). A stacked third passivation layer (80) and a second carrier collection layer (90) of the second conductivity type are sequentially formed on the second surface exposed by the patterned sacrificial layer (70) and the substrate (10); wherein at least a portion of the tip of the patterned sacrificial layer (70) is not completely covered by the third passivation layer (80) and the second carrier collection layer (90); The patterned sacrificial layer (70) is removed by etching the exposed tip using a second type of etching process, and a portion of the third passivation layer (80) and a portion of the second carrier collection layer (90) covering the patterned sacrificial layer (70) are also stripped; the remaining second carrier collection layer (90) is arranged in an intersecting pattern with the first carrier collection layer (60); The step of forming a patterned sacrificial layer (70) with an interdigitated opening pattern on the side of the initial first carrier collection layer (60a) opposite to the substrate (10) includes: A silica sol layer with an interdigitated pattern is formed by coating the initial first carrier collection layer (60a) on the side opposite to the substrate (10) with silica sol. The silica sol layer is subjected to annealing and curing treatment to form a silica layer with a preset roughness; the silica layer serves as the patterned sacrificial layer (70).

2. The method for preparing a back-contact solar cell according to claim 1, characterized in that, The silica sol contains 29wt%-31wt% silica by mass, has a pH of 9.0-10.5, and a viscosity of ≤6.5 mm. 2 / s.

3. The method for preparing a back-contact solar cell according to claim 2, characterized in that, The annealing and curing treatment is performed at a temperature of 150℃-220℃ for a duration of 15min-60min; and / or, The thickness of the patterned sacrificial layer (70) is 5μm-50μm; The roughness of the patterned sacrificial layer (70) is 1μm-50μm.

4. The method for preparing a back-contact solar cell according to claim 3, characterized in that, The thickness of the second passivation layer (50) is 3nm-10nm; The thickness of the first carrier collection layer (60) and / or the second carrier collection layer (90) is 10nm-30nm.

5. The method for fabricating a back-contact solar cell according to claim 4, characterized in that, The first type of etching process includes: alkaline etching; the duration of the first type of etching process is 5 min-10 min; The second type of etching process includes: acid etching; the duration of the second type of etching process is 1 min to 20 min.

6. The method for fabricating a back-contact solar cell according to claim 5, characterized in that, The ratio of the thickness of the patterned sacrificial layer (70) to the sum of the thicknesses of the third passivation layer (80) and the second carrier collection layer (90) is in the range of 200 to 10000.

7. The method for fabricating a back-contact solar cell according to claim 5, characterized in that, The method further includes: A transparent conductive layer (100) is formed on the side of the first carrier collection layer (60) and the second carrier collection layer (90) away from the substrate (10); the transparent conductive layer (100) has a plurality of isolation trenches for isolating the portion of the transparent conductive layer (100) covering the first carrier collection layer (60) from the portion of the transparent conductive layer (100) covering the second carrier collection layer (90); A gate electrode (M0) is formed on the side of the transparent conductive layer opposite to the substrate.

8. The method for preparing a back-contact solar cell according to any one of claims 1-7, characterized in that, The method further includes: A first passivation layer (20), a first conductivity type doped layer (30), and an antireflection layer (40) are formed on the first surface of the substrate (10) in a direction opposite to the substrate (10). The thickness of the first passivation layer (20) is 3nm-10nm.

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