Chalcogenide-based memory material, and memory device and electronic device including same

Abstract

Disclosed are a chalcogenide-based memory material, and a memory device and an electronic device including the same. The chalcogenide-based memory material may include a ternary semiconductor compound having a composition represented by XaY 'bSec, where the chalcogenide-based memory material may have bidirectional threshold switching (OTS) characteristics, and a threshold voltage of the chalcogenide-based memory material may vary according to polarity and intensity of an applied voltage. In XaY 'bSec, X is not equal to Y, a + b + c = 1, egt, 0.12, bgt, 0.18, c > = 0.4, and X and Y' may independently be different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P. The memory device may include the chalcogenide-based memory material, and the electronic device may include the memory device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0124090 filed on September 18, 2023, and Korean Patent Application No. 10-2024-0100542 filed on July 29, 2024, in the Korean Intellectual Property Office, the disclosures of each of which are incorporated herein in their entirety by reference. Technical Field

[0003] The present disclosure relates to chalcogenide-based storage (memory) materials, and storage devices and / or electronic devices (equipment) including the same. Background Art

[0004] According to the trend towards lighter, thinner and smaller electronic appliances, the demand for high integration of memory devices has increased. A memory device with a cross-point structure may have a structure in which word lines and bit lines cross each other vertically and memory cells are arranged at respective locations of the cross-point regions. The above structure may have a memory cell that is small in a plane. In general, a memory cell in a memory device with a cross-point structure includes a two-terminal selector and a memory device connected in series to limit and / or prevent the flow of sneak current between adjacent memory cells. In this way, the aspect ratio (depth-to-width ratio) of a unit memory cell increases, and therefore, the process for manufacturing the memory cell may be complicated, and there may be limitations in increasing the storage capacity of the memory device. Summary of the invention

[0005] Embodiments provide a chalcogenide-based memory material, and a memory device and / or an electronic apparatus including the same.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to an embodiment of the present disclosure, a chalcogenide-based storage material may include a a Y' b Se c A ternary semiconductor compound of a composition represented by X, wherein the chalcogenide-based storage material may have an unidirectional threshold switching (OTS) characteristic, and the threshold voltage of the chalcogenide-based storage material may be changed according to the polarity and intensity of the applied voltage. a Y' b Se cIn the invention, X≠Y, a+b+c=1, a>0.12, b>0.18, c≥0.4, and X and Y′ independently can be different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P.

[0008] In some embodiments, a concentration of X in the ternary semiconductor compound may be greater than 12 atomic % and less than or equal to 40 atomic %.

[0009] In some embodiments, the concentration of Y′ in the ternary semiconductor compound may be greater than 18 atomic % and less than or equal to 40 atomic %.

[0010] In some embodiments, a concentration of Se in the ternary semiconductor compound may be greater than or equal to 40 atomic % and less than 75 atomic % (or 70 atomic %).

[0011] According to an embodiment, a memory device may include a plurality of memory cells. Each of the plurality of memory cells may include a first electrode and a second electrode spaced apart from and facing each other, and a memory layer between the first electrode and the second electrode. The memory layer may have an OTS characteristic. A threshold voltage of the memory layer may change according to the polarity and intensity of an applied voltage. The memory layer may include a first electrode having an X a Y' b Se c The composition of the ternary semiconductor compound. a Y' b Se c , X≠Y′, a+b+c=1, a>0.12, b>0.18, c≥0.4, and X and Y′ independently may be different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P.

[0012] In some embodiments, the width of the space charge region in the storage layer caused by the reset operation of the storage unit may be greater than or equal to 2nm, for example, in the range of 2nm to 3.1nm, 2.1nm to 2.9nm, 2.2nm to 2.7nm, or 2.3nm to 2.5nm.

[0013] In some embodiments, a concentration of X in the ternary semiconductor compound may be greater than 12 atomic % and less than or equal to 40 atomic %.

[0014] In some embodiments, the concentration of Y′ in the ternary semiconductor compound may be greater than 18 atomic % and less than or equal to 40 atomic %.

[0015] In some embodiments, a concentration of Se in the ternary semiconductor compound may be greater than or equal to 40 atomic % and less than 70 atomic %.

[0016] In some embodiments, the first state of the memory layer may have a first threshold voltage, and the second state of the memory layer may have a second threshold voltage. The second threshold voltage is greater than the first threshold voltage.

[0017] In some embodiments, when the memory layer is in the first state, in response to applying a negative bias voltage to the memory layer so that current flows from the first electrode to the second electrode, the memory layer can be transformed from the first state to the second state.

[0018] In some embodiments, when the storage layer is in the second state, in response to applying a positive bias voltage greater than or equal to the second threshold voltage to the storage layer so that current flows from the second electrode to the first electrode, the storage layer can be transformed from the second state to the first state.

[0019] In some embodiments, a read voltage between the first threshold voltage and the second threshold voltage may be applied to the memory layer in a read operation.

[0020] In some embodiments, the memory device may have a three-dimensional cross-point structure.

[0021] In some embodiments, the memory device may include a plurality of bit lines extending in a first direction and a plurality of word lines extending in a second direction, the second direction intersecting the first direction, and the plurality of memory cells may be disposed at points where the plurality of bit lines and the plurality of word lines intersect each other.

[0022] In some embodiments, the memory device may have a VNAND structure.

[0023] In some embodiments, the plurality of storage units may be arranged in a third direction, and the third direction may be perpendicular to a plane including the first direction and the second direction.

[0024] In some embodiments, the memory device may include: a plurality of word planes extending along a plane including the first direction and the second direction, the plurality of word planes being spaced apart from each other in the third direction; a vertical bit line passing through the plurality of word planes and extending in the third direction; and a memory cell string extending in the third direction while surrounding the vertical bit line. A memory cell may be defined as follows: a corresponding one of the plurality of word planes surrounds a portion of the memory cell string, and a portion of the memory cell string surrounds a portion of the vertical bit line.

[0025] According to an embodiment, an electronic device may include the above-mentioned memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features, and advantages of some embodiments of the present disclosure will become more apparent from the following description considered in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a cross-sectional view schematically showing a memory device according to an embodiment;

[0028] Figure 2 is a diagram showing an example of voltage-current characteristics of a storage layer in a storage device according to an embodiment;

[0029] Figure 3A is a diagram showing an example of bias voltages used for a set operation and a read operation in a memory device according to an embodiment;

[0030] Figure 3B is a diagram showing an example of bias voltages used for a reset operation and a read operation in a memory device according to an embodiment;

[0031] Figure 4A is a conceptual diagram showing an example of a trap state in a memory layer in a pristine state of the memory layer in a memory device according to an embodiment, and Figure 4B A diagram schematically showing an energy band diagram of a storage layer in a pristine state;

[0032] Figure 5A is a conceptual diagram showing an example of a trap state in a memory layer after a positive bias voltage is applied to the memory layer in an original state for a first firing, Figure 5B A diagram schematically showing an energy band diagram of a storage layer around a first electrode after a first firing, and Figure 5C A diagram schematically showing an energy band diagram of a storage layer around a second electrode after first firing;

[0033] Fig. 6A is a conceptual diagram showing an example of a trap state in a memory layer after a negative bias voltage is applied to the memory layer fired for the first time, Figure 6B is a diagram schematically showing an energy band diagram of a storage layer region around a first electrode after a negative bias voltage is applied, and Figure 6C A diagram schematically showing an energy band diagram of a storage layer region around a second electrode after a negative bias voltage is applied;

[0034] Figure 7 is a diagram schematically showing an energy band diagram of a space charge region formed by a reset operation in a memory device according to an embodiment;

[0035] Figure 8 To show the Figure 7Graph of results of simulation regarding an IV curve obtained by modeling the results shown in FIG. 5 , which indicates generation of a memory window in a memory device according to an embodiment.

[0036] Fig. 9 A diagram showing results obtained by simulation of about 500 Se-based ternary semiconductor compounds, indicating a trend of a memory window according to a set threshold voltage;

[0037] Fig.10 A diagram showing results obtained by simulation of about 500 Se-based ternary semiconductor compounds, indicating the trend of the memory window according to the width of the space charge region;

[0038] Fig.11 A diagram showing the results of measuring the memory window through actual experiments conducted on a Se-based ternary semiconductor compound not including arsenic (As) (Ge-Sb-Se-based compound) and a ternary semiconductor compound including As (Ge-As-Se-based compound);

[0039] Fig.12 is a perspective view schematically showing a storage device according to an embodiment;

[0040] Fig.13 To display Fig.12 FIG. 1 is a diagram of an enlarged view of a memory cell in a memory device;

[0041] Fig.14 To display in Fig.12 A plan view of an example of an operation for selecting a certain memory cell in a memory device;

[0042] Fig.15 is a perspective view schematically showing a storage device according to an embodiment;

[0043] Fig.16 To schematically show Fig.15 A vertical cross section of a structure of a memory cell in a memory device;

[0044] Fig.17 To schematically show Fig.15 A horizontal cross section of a structure of a memory cell in a memory device;

[0045] Fig.18 A conceptual diagram schematically showing an example of a device architecture that can be applied to an electronic device;

[0046] Fig.19 is a block diagram of a storage system according to an embodiment; and

[0047] Fig. 20FIG. 1 is a block diagram showing a neuromorphic device and an external device connected to the neuromorphic device according to an embodiment. DETAILED DESCRIPTION

[0048] Embodiment will now be described in detail, and its example is shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiment is described below with reference to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the related enumerated items. Statements such as "at least one (kind) of", when before or after the list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one (kind) of A, B and C" and similar language (for example, "selected from at least one (kind) of A, B, and C") can be interpreted as only A, only B, only C, or any combination of two (kinds) or more (kinds) of A, B, and C, such as ABC, AB, BC, and AC.

[0049] When the terms "about" or "substantially" are used in this specification with respect to a numerical value, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "substantially" and "substantially" are used with respect to a geometric shape, it is intended that the accuracy of the geometric shape is not required, but that the tolerance for the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value or shape. When a range is specifically stated, the range includes all values ​​therebetween, for example in increments of 0.1%.

[0050] Hereinafter, one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same components, and for ease of explanation, the sizes of the components in the accompanying drawings may be exaggerated. The embodiments of the present disclosure can be modified in various ways and can be embodied in many different forms.

[0051] When a layer, film, region, or panel is referred to as being "on" another element, it may be directly on / below / to the left / to the right of the other layer or substrate, or an intermediate layer may also be present. Expressions used in the singular include the plural expression unless it has an obviously different meaning in the context. It will be further understood that when a part is referred to as "comprising" another component, the part may not exclude the other component, but may further include the other component, unless the context states otherwise.

[0052] The use of the term "above" and similar referential terms may correspond to both the singular and the plural. Moreover, the steps of all methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.

[0053] Also, the terms "... unit", "... module" used herein designate a unit for performing at least one function or operation, and this may be implemented by hardware or software, or a combination of hardware and software.

[0054] In addition, the connecting lines or connectors shown in the drawings are intended to represent example functional relationships and / or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in a practical device (equipment).

[0055] The use of any and all examples, or example language, provided herein is intended merely to better illuminate the present disclosure and does not pose a limitation on the scope of the present disclosure unless otherwise claimed.

[0056] Figure 1 FIG. 1 is a cross-sectional view schematically showing a memory device 10 according to an embodiment.

[0057] Reference Figure 1 , the memory device 10 may include a first electrode 11 , a second electrode 12 spaced apart from the first electrode 11 to face the first electrode 11 , and a memory layer 13 disposed between the first electrode 11 and the second electrode 12 .

[0058] The first electrode 11 and the second electrode 12 may apply a voltage to the storage layer 13. To do this, the first electrode 11 and the second electrode 12 may each include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the first electrode 11 and the second electrode 12 may each include at least one of the following: titanium nitride (titanium nitride) (TiN), titanium silicon nitride (titanium silicon nitride) (TiSiN), titanium carbon nitride (TiCN), titanium carbon silicon nitride (titanium carbon silicon nitride) (TiCSiN), tantalum (Ta), tantalum nitride (tantalum nitride) (TaN), tantalum silicon nitride (tantalum silicon nitride) (TaSiN), tantalum aluminum nitride (tantalum aluminum nitride) (TaAlN), tungsten silicide (tungsten silicide) (WSi), titanium tungsten (TiW), molybdenum nitride (molybdenum nitride) (MoN), niobium nitride (niobium nitride) (NbN), titanium boron nitride (titanium boron nitride) (TiBN), zirconium silicon nitride (zirconium silicon nitride) ( The present invention relates to a novel nanostructured carbon ore having a nanostructured carbon ore and a nanostructured carbon ore. The nanostructured carbon ore has the following properties: ZrSiN), tungsten silicon nitride (tungsten silicon nitride) (WSiN), tungsten boron nitride (tungsten boron nitride) (WBN), zirconium aluminum nitride (zirconium aluminum nitride) (ZrAlN), molybdenum aluminum nitride (molybdenum aluminum nitride) (MoAlN), titanium aluminum (TiAl), titanium oxynitride (titanium oxynitride) (TiON), titanium aluminum oxynitride (titanium aluminum oxynitride) (TiAlON), tungsten oxynitride (tungsten oxynitride) (WON), tantalum oxynitride (tantalum oxynitride) (TaON), silicon carbide (SiC), silicon carbonitride (SiCN), carbonitride (carbon nitride) (CN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (tungsten nitride) (WN), carbon (C), or a combination thereof.

[0059] The memory layer 13 may have a bidirectional threshold switch (OTS) characteristic in which it has a high resistance state when a voltage less than a threshold voltage is applied, and in which it has a low resistance state when a voltage greater than a threshold voltage is applied. In addition, the memory layer 13 may have a memory characteristic in which the threshold voltage shifts according to the polarity and strength of a bias voltage applied thereto. Therefore, the memory layer 13 may have a self-selection memory characteristic by which both a memory function and a selector function can be performed with only a single material. To this end, the memory layer 13 may include a chalcogenide-based material, in particular, a Se-based ternary semiconductor compound, as described later.

[0060] Figure 2 is a diagram showing an example of voltage-current characteristics of the memory layer 13 in the memory device 10 according to the embodiment.

[0061] Reference Figure 2, the memory layer 13 may have one of a first state (LVS; low Vth state) in which the threshold voltage is relatively low and a second state (HVS; high Vth state) in which the threshold voltage is relatively high. For example, in the first state, the threshold voltage of the memory layer 13 may be a first voltage V1, and in the second state, the threshold voltage of the memory layer 13 may be a second voltage V2 greater than the first voltage V1.

[0062] When the storage layer 13 is in the first state, when a voltage smaller than the first voltage V1 is applied to the storage layer 13, current rarely flows between both ends of the storage layer 13, and when a voltage larger than the first voltage V1 is applied to the storage layer 13, the storage layer 13 is turned on and current flows through the storage layer 13. Also, when the storage layer 13 is in the second state, when a voltage smaller than the second voltage V2 is applied to the storage layer 13, current rarely flows between both ends of the storage layer 13, and when a voltage larger than the second voltage V2 is applied to the storage layer 13, the storage layer 13 is turned on and current flows through the storage layer 13.

[0063] Therefore, a voltage between the first voltage V1 and the second voltage V2 may be selected as the read voltage VR. When the storage layer 13 is in the first state and the read voltage VR is applied to the storage layer 13, current flows through the storage layer 13, and at this time, the value of the data stored in the storage layer 13 may be defined as "1". When the storage layer 13 is in the second state and the read voltage VR is applied to the storage layer 13, current rarely flows through the storage layer 13, and at this time, the value of the data stored in the storage layer 13 may be defined as "0". In other words, when measuring the current flowing through the storage layer 13 while the read voltage VR is applied to the storage layer 13, the value of the data stored in the storage layer 13 may be read.

[0064] In addition, when the storage layer 13 is in the first state and a negative bias voltage is applied to the storage layer 13, the threshold voltage of the storage layer 13 increases and the storage layer 13 may be transformed into the second state. For example, when a negative third voltage V3 is applied to the storage layer 13, the storage layer 13 may be transformed into the second state. The above operation may be referred to as a reset operation. Moreover, when the storage layer 13 is in the second state and a positive (+) bias voltage greater than the second voltage V2 is applied to the storage layer 13, the threshold voltage of the storage layer 13 decreases and the storage layer 13 may be transformed into the first state. The above operation may be referred to as a set operation. The difference between the second voltage V2 (ie, the reset threshold voltage) and the first voltage V1 (ie, the set threshold voltage) corresponds to the storage window.

[0065] Figure 3A is a diagram showing an example of bias voltages used for a set operation and a read operation in the memory device 10 according to the embodiment. Figure 3A, a positive bias voltage greater than or equal to the second voltage V2 may be applied to the memory layer 13 in a set operation. Then, the threshold voltage of the memory layer 13 may be shifted to the first voltage V1. After that, in a read operation, a positive read voltage VR between the first voltage V1 and the second voltage V2 may be applied to the memory layer 13. When the read voltage VR is applied, the memory layer 13 may be turned on.

[0066] Figure 3B is a diagram showing an example of bias voltages used for a reset operation and a read operation in the memory device 10 according to the embodiment. Figure 3B , in a reset operation, a negative bias voltage, i.e., a third voltage V3, may be applied to the storage layer 13. The absolute value of the third voltage V3 may be equal to the second voltage V2, or may be slightly less than or greater than the second voltage V2. Then, the threshold voltage of the storage layer 13 may be shifted to the second voltage V2, which is greater than the first voltage V1. After that, in a read operation, a positive read voltage VR between the first voltage V1 and the second voltage V2 may be applied to the storage layer 13. When the read voltage VR is applied, the storage layer 13 may be turned off.

[0067] As described above, the memory layer 13 of the memory device 10 according to the embodiment may have an OTS characteristic and, at the same time, have a memory characteristic of changing a threshold voltage. In particular, the threshold voltage of the memory layer 13 may be shifted according to the polarity of the bias voltage applied to the memory layer 13. From this point of view, the memory device 10 according to the embodiment may be a self-selection memory device having a threshold voltage shift characteristic with polarity dependence.

[0068] The polarity-dependent threshold voltage shift behavior can be described by the change of trap states in the storage layer 13 . Figures 4A to 6B is a diagram for conceptually describing changes in the trap state in the memory layer 13 .

[0069] Figure 4A is a conceptual diagram showing an example of a trap state in the memory layer 13 in the original state of the memory layer 13 in the memory device 10 according to the embodiment, and Figure 4B 2 is a diagram schematically showing an energy band diagram of the memory layer 13 in an original state.

[0070] Figure 5A 2 is a conceptual diagram showing an example of a trap state in the memory layer 13 after a positive bias voltage is applied to the memory layer 13 in an original state for the first firing. Figure 5B A diagram schematically showing an energy band diagram of the storage layer 13 around the first electrode 11 after the first firing, and Figure 5C FIG. 1 is a diagram schematically showing an energy band diagram of the storage layer 13 around the second electrode 12 after the first firing.

[0071] Fig. 6A 2 is a conceptual diagram showing an example of a trap state in the memory layer 13 after a negative bias voltage is applied to the memory layer 13 fired for the first time. Figure 6B is a diagram schematically showing an energy band diagram regarding a region in the storage layer 13 around the first electrode 11 after application of a negative bias voltage, and Figure 6C 2 is a diagram schematically showing an energy band diagram regarding a region in the storage layer 13 around the second electrode 12 after application of a negative bias voltage.

[0072] Reference Figure 4A In the original state immediately after manufacturing, the storage layer 13 mainly contains deactivated traps. For the convenience of description, the deactivated traps are Figure 4A The passivation traps may be mainly formed by covalent bonds (Se—Se) between adjacent selenium (Se) elements in the storage layer 13 .

[0073] Moreover, in Figure 4B In the figure, CB represents the conduction band, VB represents the valence band, and the horizontal axis represents the state density. Figure 4B , the energy bands formed by the passivated traps are shown as thin dashed lines. Figure 4B In FIG. 1 , the energy band indicated by the solid line is formed by other components in the storage layer 13. The energy band formed by the passivated traps may be distributed around the Fermi level Ef.

[0074] For the first firing of the memory layer 13 in the original state, a positive (+) bias voltage may be applied. For example, a bias voltage may be applied to the memory layer 13 so that current flows from the second electrode 12 to the first electrode 11. Figure 5A , some of the passivated traps may be activated (activated) by the first firing to form activated traps. The activated traps may be mainly composed of selenium ions (Se 2- Due to the activated traps, a percolation path may be formed in the memory layer 13, and when the percolation path is formed, the threshold voltage of the memory layer 13 may be lowered.

[0075] exist Figure 5A In the example, activated traps are represented by circles with slashes and circles with a net pattern. Figure 5AAs shown in , the amount of activated traps in the memory layer 13 may increase from the first electrode 11 toward the second electrode 12. In particular, in a region in the memory layer 13 close to the second electrode 12, a large number of activated traps may be generated. Therefore, after the first firing, the memory layer 13 may have a first region 13a in which the density of activated traps is relatively low and a second region 13b in which the density of activated traps is relatively high. The thickness of the second region 13b may be less than that of the first region 13a.

[0076] The first region 13a is adjacent to the first electrode 11. The activated traps in the first region 13a are represented as circles with a diagonal pattern. In the first region 13a, the density of the activated traps may gradually increase toward the boundary with the second region 13b, but the increase may be relatively small. The second region 13b is adjacent to the second electrode 12. Moreover, the second region 13b may be in direct contact with the first region 13a, and may be disposed between the first region 13a and the second electrode 12. The activated traps in the second region 13b are represented as circles with a mesh pattern. In the second region 13b, the density of the activated traps may be greater (greatly increased) as it is closer to the boundary with the second electrode 12. Therefore, the density of the activated traps in the second region 13b may be greater than the density of the activated traps in the first region 13a. In this case, the memory layer 13 may be in a first state in which its threshold voltage is relatively low. In other words, when the memory layer 13 is in the first state, the density of the activated traps in the second region 13b is greater than the density of the activated traps in the first region 13a.

[0077] Reference Figure 5B , the energy band formed by the activated traps in the first region 13a is indicated by a dotted line. The energy band formed by the activated traps may be located at an energy level slightly lower than the Fermi level Ef. Figure 5C , the energy band formed by the activated traps in the second region 13b is indicated by a thick dashed line. Figure 5B and Figure 5C When the energy band formed by the activated traps in the second region 13b has an energy distribution slightly wider than that of the energy band formed by the activated traps in the first region 13a. Moreover, the state density of the activated traps in the second region 13b is greater than the state density of the activated traps in the first region 13a. Therefore, the amount of activated traps in the second region 13b is greater than the amount of activated traps in the first region 13a.

[0078] After the first firing, the high density of activated traps around the second electrode 12 may greatly affect the offset movement of the threshold voltage in the memory layer 13. For example, the density of activated traps in the second region 13b may be easily changed according to the polarity of the bias voltage, and thus, the threshold voltage of the memory layer 13 may be easily offset.

[0079] Reference Fig. 6A When a negative (-) bias voltage is applied to the first fired storage layer 13, that is, when a bias voltage is applied to the storage layer 13 in the reverse direction so that current flows from the first electrode 11 to the second electrode 12, some of the activated traps in the second region 13b adjacent to the second electrode 12 are annihilated and become passive traps. This can be described as the adjacent Se ions (Se 2- ) are combined again and form a covalent bond. As a result, the density of activated traps in the storage layer 13 is reduced.

[0080] When compared Figure 5A and Fig. 6A When the negative bias voltage is applied to the storage layer 13, the density of the activated traps in both the first region 13a and the second region 13b may be reduced. In particular, the density of the activated traps in the second region 13b may be further reduced. On the contrary, the change in the density of the activated traps in the first region 13a may be less than the change in the density of the activated traps in the second region 13b. Therefore, after the negative bias voltage is applied to the storage layer 13, the density of the activated traps in the second region 13b may be less than the density of the activated traps in the first region 13a. In this way, an interface tunneling barrier (ITB) may be formed around the boundary between the first region 13a and the second region 13b.

[0081] In addition, when comparing Figure 5B and Figure 6B When the negative bias voltage is applied to the storage layer 13, the state density of the activated traps in the first region 13a may be slightly reduced. Figure 5C and Figure 6C When a negative bias voltage is applied to the storage layer 13, the state density of the activated traps in the second region 13b can be greatly reduced. Figure 6B and Figure 6C When a negative bias voltage is applied to the storage layer 13, the state density of the activated traps in the second region is less than the state density of the activated traps in the first region 13a.

[0082] In the storage layer 13, when the amount of activated traps, particularly activated traps in the second region 13b adjacent to the second electrode 12, is small, a larger bias voltage is necessary to form an electrical conduction path, and thus, the threshold voltage of the storage layer 13 may be increased. Here, the storage layer 13 is in a second state having a relatively large threshold voltage. In other words, when the storage layer 13 is in the second state, the density of activated traps in the second region 13b may be smaller than the density of activated traps in the first region 13a. In addition, when the storage layer 13 is in the second state, the density of activated traps in the first region 13a and the density of activated traps in the second region 13b may be respectively smaller than the density of activated traps in the first region 13a and the density of activated traps in the second region 13b when the storage layer 13 is in the first state.

[0083] After that, when a positive bias voltage greater than or equal to the threshold voltage is applied to the memory layer 13, in the memory layer 13, particularly in the second region 13b, the amount of activated traps increases, and the threshold voltage of the memory layer 13 may be lowered again. Thus, the memory layer 13 may be in the first state.

[0084] As described above, in the memory device 10 according to the embodiment, the threshold voltage shift movement can be achieved by the change of the state of the activated traps in the memory layer 13, in particular, by the large change of the state of the activated traps in the second region 13b adjacent to the second electrode 12. In addition, the density of the activated traps in the original state is lower than the density of the activated traps when the negative bias voltage is applied after the first firing, and therefore, the positive bias voltage required for the first firing can be greater than the positive bias voltage for lowering the threshold voltage of the memory layer 13 after the negative bias voltage.

[0085] In the memory device 10 according to the embodiment, the memory layer 13 may include a chalcogenide-based material, for example, a Se-based ternary semiconductor compound. In detail, the memory layer may include a chalcogenide-based material, for example, a Se-based ternary semiconductor compound. a Y' b Se c A ternary semiconductor compound having a composition of (a+b+c=1, a>0.12, b>0.18, c≥0.4). Here, X and Y' represent different elements. X and Y' can each be one of In, Sb, Ga, Sn, Al, Ge, Si, and P.

[0086] The concentration of X may be greater than about 12 atomic %. For example, the concentration of X may be greater than 12 atomic % and may be less than or equal to 40 atomic %. The concentration of Y' may be greater than about 18 atomic %. For example, the concentration of Y' may be greater than 18 atomic % and may be less than or equal to 40 atomic %. The concentration of Se may be greater than or equal to 40 atomic %. For example, the concentration of Se may be greater than or equal to 40 atomic % and may be less than 70 atomic %.

[0087] In the memory device 10 according to the embodiment, the memory layer 13 includes a Se-based ternary semiconductor compound, wherein as described later, a space charge region is formed to have a large width greater than or equal to about 2 nm, and therefore, the memory window of the memory device can be increased. Moreover, the memory layer includes a ternary semiconductor compound excluding arsenic (As), and therefore, environmental pollution caused by As can be reduced.

[0088] Figure 7 Schematically showing an energy band diagram of a space charge region formed by a reset operation in the memory device 10 according to the embodiment. Figure 7 , charged defects with different polarities accumulate around the interface of the storage layer including the Se-based ternary semiconductor compound during the reset operation, and a space charge region is formed due to the band bending. The space charge region acts as an electric barrier to block electron injection during the read operation. Figure 7 In this example, Ls represents the width of the space charge region, and V bi Represents a potential barrier.

[0089] Figure 8 To show the Figure 7 FIG. 1 is a diagram showing the results of a simulation of an IV curve obtained by modeling the results shown in FIG. 1 , which shows that a memory window is generated in the memory device 10 according to the embodiment. Figure 8 , the threshold voltage RESET V in the reset operation th Increase to a value greater than the threshold voltage SET V in the set operation th , thus generating a storage window.

[0090] Hereinafter, the results of a simulation in which 500 Se-based ternary semiconductor compounds are used as storage materials are described. Here, the Se-based ternary semiconductor compounds may have X a Y' b Se c The composition of (X≠Y′, a+b+c=1), and the elements X and Y′ may each be one of In, Sb, Ga, Sn, Al, Ge, Si, and P.

[0091] Fig. 9To show the relationship between the set threshold voltage SET V th The simulation is performed on a computer with Fig.13 A memory cell of the same structure as shown in FIG. 1 is performed, wherein the material used for the lower electrode 101 is carbon, the material used for the upper electrode 102 is carbon, and the thicknesses of the lower electrode 101, the memory layer 103, and the upper electrode 102 are 10, 16, and 10 nm, respectively. Fig. 9 ,As the set threshold voltage increases, the storage window tends to increase.

[0092] Fig.10 The following is a graph showing the results obtained by simulation of about 500 Se-based ternary semiconductor compounds showing the trend of the storage window according to the width Ls of the space charge region. The simulation is for a ternary semiconductor compound having Fig.13 A memory cell of the same structure as shown in FIG. 1 is performed, wherein the material used for the lower electrode 101 is carbon, the material used for the upper electrode 102 is carbon, and the thicknesses of the lower electrode 101, the memory layer 103, and the upper electrode 102 are 10, 16, and 10 nm, respectively. Fig.10 , as the width of the space charge region increases, the storage window tends to increase.

[0093] Table 1 below is a simulation result showing an example of a material having a relatively large memory window among 500 Se-based ternary semiconductor compounds. The simulation is for a material having a relatively large memory window. Fig.13 The same structure as shown in the memory cell is carried out, wherein the material for the lower electrode 101 is carbon, the material for the upper electrode 102 is carbon, and the thicknesses of the lower electrode 101, the memory layer 103 and the upper electrode 102 are 10, 16 and 10 nm respectively. In the following Table 1, Es represents the energy band gap, and ΔVth represents the memory window. In addition, Ls represents the width of the space charge region, and I off Indicates the off (cut-off) current.

[0094] [Table 1]

[0095]

[0096] Referring to Table 1 above, when the concentration of Se is about 40 atomic % or more, the concentration of X is about 12 atomic % or more, and the concentration of Y' exceeds about 18 atomic %, in the Se-based ternary semiconductor compound, a relatively large memory window is obtained. In particular, the concentration of Se may be greater than or equal to 40 atomic % and less than 70 atomic %, the concentration of X may be greater than or equal to 12 atomic % and less than or equal to 40 atomic %, and the concentration of Y' may be greater than or equal to 18 atomic % and less than or equal to 40 atomic %. In addition, when the width Ls of the space charge region formed by the reset operation is about 2 nm or more, a relatively large memory window may be achieved.

[0097] Table 2 below shows a comparison of the ternary semiconductor compounds (Ge 0.17 As 0.31 Se 0.52 ,Ge 0.21 As 0.25 Te 0.54 ) measured for a Se-based ternary semiconductor compound (Ge 0.22 Sb 0.20 Se 0.58 ) measured the actual experimental results of the storage window △Vth. In the actual experiment, a Fig.12 The memory device has the same structure as shown in FIG. Fig.13 Regarding the memory cell, the material for the lower electrode 101 is carbon, the material for the upper electrode 102 is carbon, and the thicknesses of the lower electrode 101, the memory layer 103, and the upper electrode 102 are 10, 16, and 10 nm, respectively.

[0098] [Table 2]

[0099] composition △Vth(V) SET Vth(V) <![CDATA[Ge 0.22 Sat 0.20 With 0.58 ]]> 2.4 2.75 <![CDATA[Ge 0.17 Ace 0.31 To 0.52 ]]> 1.2 3.2 <![CDATA[Ge 0.21 Ace 0.25 yourself 0.54 ]]> 0.83 1.85

[0100] Referring to Table 2 above, the ternary semiconductor compound (Ge 0.17 As 0.31 Se 0.52 ,Ge 0.21 As 0.25 Te 0.54 ) compared to the Se-based ternary semiconductor compound (Ge 0.22 Sb 0.20 Se 0.58 ) has a larger storage window.

[0101] Table 3 below shows the results of measuring the storage window ΔVth through actual experiments conducted on an exemplary Se-based ternary semiconductor compound (Ge-Sb-Se-based compound) that does not include arsenic (As). Fig.12 The memory device has the same structure as shown in FIG. Fig.13 . With respect to the memory cell, the material for the lower electrode 101 is carbon, the material for the upper electrode 102 is carbon, and the thicknesses of the lower electrode 101, the memory layer 103, and the upper electrode 102 are 10, 16, and 10 nm, respectively. Table 3 below shows the experimental results of the memory window measured according to the concentration of the element Sb in the Ge-Sb-Se based compound. In Table 3 below, "Vth drift" indicates the degree of change of the threshold voltage over time.

[0102] [Table 3]

[0103]

[0104]

[0105] Referring to Table 3 above, it can be determined that Ge-Sb-Se based compounds having element Sb at a concentration of greater than about 18 atomic % mostly have a larger memory window than Ge-Sb-Se based compounds having element Sb at a concentration of 15.1 atomic % or less.

[0106] Table 4 below shows the results of measuring the memory window ΔVth through actual experiments on an exemplary Se-based ternary semiconductor compound (Ge-As-Se-based compound) including As. Fig.12 The memory device has the same structure as shown in FIG. Fig.13 . With respect to the memory cell, the material for the lower electrode 101 is carbon, the material for the upper electrode 102 is carbon, and the thicknesses of the lower electrode 101, the memory layer 103, and the upper electrode 102 are 10, 16, and 10 nm, respectively. Table 4 below shows actual experimental results of the memory window measured according to the concentration of the element As in the Ge-As-Se based compound.

[0107] [Table 4]

[0108]

[0109] Referring to the above Table 4, it can be determined that the Ge-As-Se based compounds including As mostly have a memory window similar to that of the Ge-Sb-Se based compounds having element Sb at a concentration of 15.1 atomic % or less as described above.

[0110] Fig.11 Results of measuring the memory window through actual experiments on a Se-based ternary semiconductor compound not including As (Ge-Sb-Se based compound) and a Se-based ternary semiconductor compound including As (Ge-As-Se based compound) are shown.

[0111] exist Fig.11 In the above table, "A" represents the memory window for the Ge-Sb-Se based compounds in which the concentration of the element Sb is greater than about 18 atomic % as shown in Table 3 above, and "B" represents the memory window for the Ge-Sb-Se based compounds in which the concentration of the element Sb is 15.1 atomic % or less as shown in Table 3 above. "C" represents the memory window for 28 exemplary Ge-As-Se based compounds including As.

[0112] Reference Fig.11 , it is determined that Ge-Sb-Se-based compounds in which the concentration of element Sb is greater than about 18 atomic % generally have a larger memory window than Ge-Sb-Se-based compounds and Ge-As-Se-based compounds in which the concentration of element Sb is 15.1 atomic % or less. As described above, the memory device 10 according to the embodiment can perform a memory function and a selector function with a single material by using a phenomenon in which the density of activated traps changes according to the polarity and intensity of a bias voltage. Therefore, a unit memory cell can be realized by using only one memory device 10 without using an additional selector. In the memory device 10 according to the embodiment, both the memory function and the selector function can be performed by one memory layer 13, and therefore, the aspect ratio of the memory device 10 can be reduced, and the memory device 10 can be manufactured by a relatively simple process. Moreover, in the memory device 10 according to the embodiment, the memory layer 13 includes a layer having X a Y' b Se c A ternary semiconductor compound of composition (a+b+c=1, a>0.12, b>0.18, c≥0.4, X≠Y, X and Y are each one of In, Sb, Ga, Sn, Al, Ge, Si, and P), and therefore, the memory window can be increased.

[0113] Fig.12 is a perspective view schematically showing a memory device 100 according to some embodiments. Fig.13 To display Fig.12FIG. 1 is an enlarged view of a memory cell MC in a memory device.

[0114] Reference Fig.12 and Fig.13 , the memory device 100 may have a three-dimensional (3D) cross-point structure. For example, the memory device 100 may include a plurality of bit lines BL extending in a first direction (i.e., an x-axis direction), a plurality of word lines WL extending in a second direction (i.e., a y-axis direction) crossing the first direction, and a plurality of memory cells MC provided at points where the plurality of bit lines BL and the plurality of word lines WL cross each other.

[0115] Each of the plurality of memory cells MC may have a rod (bar) shape and may correspond to Figure 1 The memory device 10 shown in FIG. The lower electrode 101 and the upper electrode 102 may correspond to Figure 1 The first electrode 11 and the second electrode 12 of the memory device 10 shown in FIG. In addition, the memory layer 103 may correspond to Figure 1 The memory layer 13 of the memory device 10 shown in FIG. 10 and the memory layer 103 may have Figure 1 The characteristics of the storage layer 13 in the storage device 10 are the same as the characteristics of the storage layer 13 in the storage device 10.

[0116] In this structure, the memory cell MC can be driven by the potential difference between the word line WL and the bit line BL connected to both ends of each memory cell MC. For example, when the memory layer 103 is in the first state with a relatively low first threshold voltage and the potential difference between the word line WL and the bit line BL is less than or equal to, for example, -4V, the memory layer 103 can be switched to the second state with a relatively high second threshold voltage. Moreover, when the memory layer 103 is in the second state with a relatively high second threshold voltage and the potential difference between the word line WL and the bit line BL is greater than or equal to the second threshold voltage, for example, +4V, the memory layer 103 can be switched to the first state with a relatively low first threshold voltage. When reading data recorded on the memory layer 103, the potential difference between the word line WL and the bit line BL may be between the first threshold voltage and the second threshold voltage, for example, about +3V to about +3.5V.

[0117] Fig.14 To display in Fig.12 FIG. 1 is a plan view showing an example of an operation for selecting a certain memory cell in the memory device 100. Fig.14, the memory device 100 may further include a row decoder 110 that selectively supplies a voltage to a plurality of word lines WL and a column decoder 120 that selectively supplies a voltage to a plurality of bit lines BL. When a voltage V is to be applied to a selected memory cell sMC among a plurality of memory cells MC, the row decoder 110 may supply the voltage V to the word line WL connected to the selected memory cell sMC, and supply the voltage V / 2 to the other word lines WL. Here, the column decoder 120 may supply a voltage of 0V to the bit line BL connected to the selected memory sMC, and supply the voltage V / 2 to the other bit lines BL.

[0118] Thus, the potential difference between the word line WL and the bit line BL of the selected memory cell sMC is V. On the other hand, the potential difference between the word line WL supplied with the voltage V / 2 and the bit line BL supplied with the voltage V / 2 is 0V. Therefore, the voltage is not applied to the unselected memory cell uMC arranged between the word line WL and the bit line BL not connected to the selected memory cell sMC. In addition, the voltage V / 2 may be applied to both ends of the half-selected memory cell hMC connected to the same word line WL as the word line WL of the selected memory cell sMC or the same bit line BL as the bit line BL of the selected memory cell sMC. Each of the plurality of memory cells MC is a self-selecting memory device having a threshold voltage as described above, and therefore, the half-selected memory cell hMC adjacent to the selected memory cell sMC does not turn on even when the voltage V / 2 is applied, and therefore, sneak current rarely occurs.

[0119] Fig.15 FIG. 2 is a perspective view schematically showing a storage device 200 according to another embodiment.

[0120] Reference Fig.15 , the memory device 200 may include: a plurality of word planes WP extending along a plane including the first direction and the second direction and spaced apart from each other along a third direction (i.e., the z-axis direction) intersecting the first and second directions, a plurality of vertical bit lines VBL extending in the third direction and arranged two-dimensionally along the first direction and the second direction, and a plurality of memory cell strings MCS extending in the third direction while surrounding surfaces of the plurality of vertical bit lines VBL. The plurality of memory cell strings MCS may also be arranged two-dimensionally in the first and second directions like the plurality of vertical bit lines VBL. Each of the plurality of memory cell strings MCS and each of the plurality of vertical bit lines VBL may be arranged to pass through the plurality of word planes WP in the third direction. Because each of the plurality of memory cell strings MCS extends in a vertical direction, Fig.14The memory device 200 shown in FIG. 2 may be referred to as a vertical type memory device (ie, a VNAND memory device) and may have improved storage capacity. Each of the plurality of memory cell strings MCS may include Figure 1 The material of the storage layer 13 in the storage device 10 is the same material.

[0121] Fig.16 To schematically show Fig.15 FIG. 2 is a vertical cross-section of the structure of one memory cell in the memory device 200 shown in FIG. Fig.17 To schematically show Fig.15 FIG. 4 is a horizontal cross-section of the structure of one memory cell in the memory device 200 shown in FIG.

[0122] Reference Fig.16 and Fig.17 Each word plane WP and the memory cell string MCS surrounded by the word plane WP and the vertical bit line VBL can form a memory cell MC. Here, the memory cell may correspond to Figure 1 The memory device 10 shown in FIG. The word plane WP and the vertical bit line VBL may correspond to Figure 1 1 and 12 of the memory device 10 shown in FIG. In addition, the memory cell string MCS may correspond to Figure 1 The memory layer 13 of the memory device 10 shown in FIG. 1 and the memory cell string MCS may have Figure 1 The characteristics of the storage layer 13 in the storage device 10 are the same as the characteristics of the storage layer 13 in the storage device 10.

[0123] The memory device 100 or 200 according to the embodiments described above may be used to store data in various electronic devices, such as a mobile phone, a tablet computer, an electronic watch, a laptop computer, a desktop computer, a notebook computer, or a television, but example embodiments are not limited thereto. Fig.18 FIG. 1 is a conceptual diagram schematically showing a device architecture applied to an electronic apparatus according to an embodiment.

[0124] Reference Fig.18 , the cache memory 1510, the ALU 1520, and the control unit 1530 may configure the central processing unit (CPU) 1500, and the cache memory 1510 may include a static random access memory (SRAM). The main memory 1600 and the auxiliary memory 1700 may be provided separately from the central processing unit 1500. The main memory 1600 may include a DRAM device, and the auxiliary memory 1700 may include the above-mentioned memory device 100 or 200.

[0125] In some embodiments, an input / output device 2500 (eg, a keyboard, and / or a touch screen display) may also be provided. In some cases, the device architecture may be implemented in a form where the computing unit device and the memory unit device are adjacent to each other in one chip without distinguishing subunits.

[0126] The memory devices 100 and 200 according to the embodiments may be implemented as a chip-type memory block (memory block) to be used as a neuromorphic computing platform or to construct a neural network.

[0127] Fig.19 is a block diagram of a storage system 2600 according to an embodiment.

[0128] Reference Fig.19 , the memory system 2600 may include a memory controller 1601 and a memory device 1602. The memory controller 1601 controls the memory device 1602. For example, the memory controller 1601 may provide a command CMD to the memory device 1602 for programming (or recording), reading and / or erasing the address ADD and the memory device 1602. Moreover, data for programming operations and read data may be transmitted between the memory controller 1601 and the memory device 1602.

[0129] The memory device 1602 may include a memory cell array 1610 and a voltage generator 1620. The memory cell array 1610 may include a plurality of memory cells, and may include the memory device 100 or 200 according to an embodiment.

[0130] The storage controller 1601 may include a processing circuit system such as hardware including a logic circuit, a combination of hardware / software (such as software implemented by a processor), or a combination thereof. For example, the processing circuit system may particularly include a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc., but is not limited thereto. The storage controller 1601 may operate in response to a request from a host (not shown) and may access the storage device 1602 to control the control operation (such as recording / reading operation) as described above, and therefore, the storage controller 1601 may be transformed into a dedicated controller. The storage controller 1601 may generate an address ADD and a command CMD for performing programming / reading / erasing operations on the storage cell array 1610. Moreover, in response to a command from the storage controller 1601, the voltage generator 1620 (such as a power supply circuit) may generate a voltage control signal for controlling the voltage level of a word line to perform data programming or data reading on the storage cell array 1610.

[0131] Furthermore, the memory controller 1601 may perform a determination operation on the data read from the memory device 1602. For example, the number of on cells and / or the number of off cells may be determined by the data read from the memory cells. The memory device 1602 may provide a pass / fail signal (P / F) to the memory controller 1601 according to the determination result on the read data. The memory controller 1601 may control the write / read operation of the memory cell array 1610 with reference to the pass / fail signal (P / F).

[0132] Fig. 20 FIG. 1 is a block diagram showing a neuromorphic device 1700 and external devices connected to the neuromorphic device according to an embodiment.

[0133] Reference Fig. 20 , the neuromorphic device 1700 may include a processing circuit system 1710 and / or an on-chip memory 1720. The neuromorphic device 1700 may include the memory device 100 or 200 according to an embodiment.

[0134] In some embodiments, the processing circuit system 1710 may be configured to control functions for driving the neuromorphic device 1700. For example, the processing circuit system 1710 may be configured to control the neuromorphic device 1700 by executing a program stored in the on-chip memory 1720. In some embodiments, the processing circuit system 1710 may include hardware such as a logic circuit, a hardware / software combination such as a processor that executes software, or a combination thereof. For example, the processor may include, but is not limited to, a CPU, a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1700, an ALU, a digital signal processor, a microcomputer, an FPGA, a SoC, a programmable logic unit, a microprocessor, an ASIC, etc. In some embodiments, the processing circuit system 1710 may be configured to read / record various data about the external device 1730 and / or implement the neuromorphic device 1700 by using the read / recorded data. In some embodiments, the external device 1730 may include an external memory and / or a sensor array having an image sensor (e.g., a CMOS image sensor circuit).

[0135] In some embodiments, Fig. 20 The neuromorphic device 1700 can be applied to a machine learning system. The machine learning system can use various artificial neural network organizations and processing models, such as convolutional neural networks (CNNs), deconvolutional neural networks, repetitive neural networks (RNNs) that selectively include long short-term memory (LSTM) units and / or gated recurrent (recurrent) units (GRUs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0136] Alternatively or additionally, such a machine learning system may include other types of machine learning models, such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, expert systems, and / or random forests; or combinations thereof. The machine learning models may be used to provide various services and / or applications. For example, image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance system (ADAS) services, voice assistance services, automatic speech recognition (ASR) services, etc. may be implemented by electronic devices.

[0137] The memory device 10, 100, or 200 according to the embodiment can perform a memory function and a selector function with a single material by utilizing a phenomenon in which the density of activated traps changes according to the polarity and intensity of a bias voltage. Therefore, a unit memory cell can be implemented by using only one memory device without using an additional selector. In the memory device 10, 100, or 200 according to the embodiment, both the memory function and the selector function can be performed by one storage layer, and therefore, the aspect ratio of the memory device can be reduced, and the memory device can be manufactured by a relatively simple process. Moreover, in the memory device 10, 100, or 200 according to the embodiment, the storage layer includes a plurality of layers having X a Y' b Se c A ternary semiconductor compound of composition (a+b+c=1, a>0.12, b>0.18, c≥0.4, X≠Y, X and Y' are each one of In, Sb, Ga, Sn, Al, Ge, Si, and P), and therefore, the memory window can be increased.

[0138] While the memory device 10, 100, or 200 has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.

[0139] One or more of the elements disclosed above may include or be implemented with a processing circuit system, such as hardware including logic circuits; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processing circuit system may more particularly include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0140] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should typically be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. Chalcogenide-based storage materials, including: With X a Y' b Se c represents a ternary semiconductor compound of composition, where The chalcogenide-based storage material has bidirectional threshold switching characteristics. The threshold voltage of the chalcogenide-based memory material changes according to the polarity and magnitude of the applied voltage, In X a Y' b Se c In the equation, X≠Y, a+b+c=1, a>0.12, b>0.18, c≥0.4, and X and Y′ are independently different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P.

2. The chalcogenide-based storage material according to claim 1, wherein The concentration of X in the ternary semiconductor compound is greater than 12 atomic % and less than or equal to 40 atomic %; The concentration of Y' in the ternary semiconductor compound is greater than 18 atomic % and less than or equal to 40 atomic %; and / or The concentration of Se in the ternary semiconductor compound is greater than or equal to 40 atomic % and less than 70 atomic %.

3. Storage devices, including: A plurality of storage units, wherein Each of the plurality of memory cells includes a first electrode and a second electrode that are spaced apart from and face each other, and a memory layer between the first electrode and the second electrode, The storage layer has a bidirectional threshold switching characteristic, The threshold voltage of the memory layer changes according to the polarity and intensity of the applied voltage, The storage layer comprises the chalcogenide-based storage material according to claim 1 or 2 . 4 . The memory device according to claim 3 , wherein a width of a space charge region in the memory layer caused by a reset operation of the memory cell is greater than or equal to 2 nm.

5. The memory device according to claim 3, wherein The first state of the storage layer has a first threshold voltage, The second state of the storage layer has a second threshold voltage, and The second threshold voltage is greater than the first threshold voltage.

6. The semiconductor device according to claim 5, wherein: When the memory layer is in the first state, in response to applying a negative bias voltage to the memory layer so that current flows from the first electrode to the second electrode, the memory layer changes from the first state to the second state.

7. The semiconductor device according to claim 5, wherein: When the storage layer is in the second state, in response to applying a positive bias voltage greater than or equal to the second threshold voltage to the storage layer so that current flows from the second electrode to the first electrode, the storage layer changes from the second state to the first state. 8 . The semiconductor device according to claim 5 , wherein a read voltage between the first threshold voltage and the second threshold voltage is applied to the memory layer in a read operation.

9. The memory device of claim 3, wherein the memory device has a three-dimensional cross-point structure.

10. The semiconductor device according to claim 9, further comprising: a plurality of bit lines extending in a first direction; as well as A plurality of word lines extending in a second direction intersecting the first direction, wherein The plurality of memory cells are respectively disposed at points where the plurality of bit lines and the plurality of word lines cross each other. The memory device according to claim 10 , wherein the memory device has a VNAND structure.

12. The semiconductor device according to claim 11, wherein The plurality of storage units are arranged in a third direction, and The third direction is perpendicular to a plane including the first direction and the second direction.

13. The semiconductor device according to claim 12, further comprising: a plurality of word planes extending along a plane including the first direction and the second direction, the plurality of word planes being spaced apart from each other in the third direction; a vertical bit line passing through the plurality of word planes and extending in the third direction; as well as A memory cell string extending in the third direction while surrounding the vertical bit line, wherein A memory cell is defined by: a corresponding one of the plurality of word planes surrounding a portion of the memory cell string, and a portion of the memory cell string surrounding a portion of the vertical bit line.

14. Electronic devices, including: A memory device according to any one of claims 3 to 13.

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