A preparation method for nanoelectrodes of a two-dimensional material memristor

Abstract

The present invention provides a method for preparing nanoelectrodes of a two-dimensional material memristor, which relates to the technical field of semiconductor device preparation, and includes: spin-coating a PMMA diluent on a substrate, performing electron beam exposure, and performing low-temperature development to form a patterned bottom contact electrode; subjecting the patterned bottom contact electrode to physical vapor deposition, and removing the glue by stripping to obtain the bottom contact electrode; preparing an insulating layer on the substrate for preparing the bottom contact electrode by means of atomic layer deposition; etching the copper substrate of the two-dimensional material with a copper substrate and transferring it above the insulating layer; performing patterning on the transferred two-dimensional material to obtain a patterned two-dimensional material electrode; spin-coating a PMMA diluent on the surface of the substrate after patterning the two-dimensional material, baking and solidifying the glue, then performing electron beam exposure and low-temperature development to form a patterned top contact electrode; subjecting the patterned top contact electrode to physical vapor deposition to obtain the top contact electrode. The present invention can greatly reduce the device size and improve the device performance uniformity.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device fabrication, and particularly to a method for fabricating nanoelectrodes of a two-dimensional material memristor. Background Art

[0002] In order to overcome the limitations of the von Neumann architecture in terms of speed and power consumption, it is necessary to integrate data storage and computing on the same architecture. Therefore, in-memory computing has become a research hotspot in the field of brain-inspired computing. The memristor has a simple structure and stores data in the form of resistance states. Its crossbar array structure can naturally store data and perform calculations, and has unique advantages in in-memory computing applications. It can simplify the neural network structure, improve the computing speed, and reduce the power consumption to a great extent. Due to the characteristics of high mobility, surface area ratio, and atomic-level thickness, two-dimensional materials can further reduce the device area and power consumption when applied in memristors.

[0003] However, the characteristic size of the current two-dimensional material memristor has remained at the micron level, and there is still a large gap from the integration size of silicon-based circuits. It is necessary to further miniaturize the device size, reduce the power consumption, and promote the high-density integration of the in-memory computing architecture. In addition, the poor uniformity of two-dimensional materials seriously limits the yield of devices in the memory-compute circuit. It is urgent to significantly reduce the device size and improve the uniformity of device performance. Summary of the Invention

[0004] The present invention provides a method for fabricating nanoelectrodes of a two-dimensional material memristor, which is used to solve the defects of large characteristic size and poor uniformity of the two-dimensional material memristor in the prior art, and to achieve miniaturization of the device size and high uniformity of device performance.

[0005] The present invention provides a method for fabricating nanoelectrodes of a two-dimensional material memristor. The structure of the two-dimensional material memristor includes, from bottom to top, a first substrate, a second substrate, a bottom contact electrode, an insulating layer, a two-dimensional material electrode layer, and a top contact electrode. The second substrate is grown on the first substrate. The method includes the following steps:

[0006] S1: Spin-coat a pre-prepared PMMA diluent on the second substrate, perform first mask pattern electron beam exposure on the second substrate according to a pre-designed contact electrode layout, and perform low-temperature development to form a patterned bottom contact electrode. The size of the first mask pattern is nanoscale.

[0007] S2: Subject the patterned bottom contact electrode to first physical vapor deposition, and after degluing and peeling, obtain a bottom contact electrode with a nanoscale size.

[0008] S3: Prepare an insulating layer on the second substrate with the bottom contact electrode prepared by atomic layer deposition.

[0009] S4: Etch the copper substrate of the two-dimensional material and transfer it above the insulating layer;

[0010] S5: Pattern the transferred two-dimensional material to obtain a patterned two-dimensional material electrode;

[0011] S6: Spin-coat the PMMA diluent on the surface of the second substrate after patterning the two-dimensional material. After baking and solidifying the glue, perform electron beam exposure of the second mask pattern and perform low-temperature development to form a top contact electrode pattern; wherein, the size of the second mask pattern is nanoscale, and the second mask pattern and the patterned bottom contact electrode are arranged in a cross shape;

[0012] S7: Obtain the top contact electrode by subjecting the top contact electrode pattern to second physical vapor deposition and then removing the glue by peeling.

[0013] According to the method for preparing a nanoelectrode of a two-dimensional material memristor provided by the present invention, the first substrate is a silicon substrate, and the second substrate is a silicon dioxide substrate; the material of the bottom contact electrode includes metallic palladium and gold; the material of the insulating layer includes hafnium oxide, tantalum oxide, and boron nitride; the material of the two-dimensional material electrode is graphene; the material of the top contact electrode includes titanium nitride and silver.

[0014] According to the method for preparing a nanoelectrode of a two-dimensional material memristor provided by the present invention, the thickness of the PMMA diluent is less than 100 nm;

[0015] The preparation method of the PMMA diluent includes:

[0016] Select a PMMA photoresist of the PMMA300.07.5 series;

[0017] Mix the PMMA photoresist and anisole in a ratio of 2:1 to obtain a PMMA diluent. Among them, the thickness of the diluent at this ratio is 70 - 75 nm.

[0018] According to the method for preparing a nanoelectrode of a two-dimensional material memristor provided by the present invention, the designed line dimensions of the first mask pattern and the second mask pattern are respectively 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, and 30 nm.

[0019] According to the method for preparing a nanoelectrode of a two-dimensional material memristor provided by the present invention, the method for preparing an insulating layer on the second substrate with a prepared bottom contact electrode by means of atomic layer deposition specifically includes:

[0020] Grow a hafnium oxide insulating layer with a thickness of 5 - 7 nm by atomic layer deposition.

[0021] According to the method for preparing nanoelectrodes of a two-dimensional material memristor provided by the present invention, the first physical vapor deposition is magnetron sputtering;

[0022] Among them, the vacuum degree of the magnetron sputtering is lower than 1E-6 Torr, and the deposition rate is 1 Å / s.

[0023] According to the method for preparing nanoelectrodes of a two-dimensional material memristor provided by the present invention, the insulating layer is prepared on the second substrate with the bottom contact electrode prepared by using atomic layer deposition, specifically including:

[0024] An hafnium oxide insulating layer with a thickness of 8-10 nm is grown by atomic layer deposition.

[0025] According to the method for preparing nanoelectrodes of a two-dimensional material memristor provided by the present invention, the first physical vapor deposition is electron beam evaporation;

[0026] Among them, the vacuum degree of the electron beam evaporation is lower than 1E-6 Torr, and the deposition rate is 1 Å / s.

[0027] According to the method for preparing nanoelectrodes of a two-dimensional material memristor provided by the present invention, the dose of the electron beam exposure is greater than 1000 mJ / cm 2 .

[0028] According to the method for preparing nanoelectrodes of a two-dimensional material memristor provided by the present invention, the developer for low-temperature development is a PMMA dilution solution stored in a refrigerated environment below 5°C.

[0029] According to the method for preparing nanoelectrodes of a two-dimensional material memristor provided by the present invention, before spin-coating the pre-prepared PMMA dilution solution on the second substrate, the method further includes:

[0030] Making alignment marks and bottom test electrodes on the second substrate;

[0031] The specific process of making alignment marks and bottom test electrodes includes:

[0032] Spin-coating a layer of photoresist negative on the second substrate in sequence with the spin-coating parameters of 700 r / 9 s and 4000 r / 40 s, pre-baking at 150°C for 60 s in sequence, exposing with a chromium mask plate, baking at 100°C for 120 s in the middle, developing, evaporating or sputtering 10 nm of metallic titanium and 30 nm of metallic palladium, and removing the glue by acetone stripping to form alignment marks and bottom test electrodes.

[0033] According to the method for preparing nanoelectrodes of a two-dimensional material memristor provided by the present invention, spin-coating the pre-prepared PMMA dilution solution on the second substrate specifically includes:

[0034] Spin-coat a layer of the PMMA diluent on the second substrate and the alignment marks in sequence with the spin-coating parameters of 700 r / 9 s and 3000 r / 40 s, and bake at 170 °C for 5 min.

[0035] According to the method for preparing a nanoelectrode of a two-dimensional material memristor provided by the present invention, the etching of the copper substrate of the two-dimensional material with the copper substrate specifically includes:

[0036] Prepare a 3% ammonium persulfate solution and let it stand for 24 hours, and place the single-layer two-dimensional material electrode with the copper substrate prepared by chemical vapor deposition in the ammonium persulfate solution after standing.

[0037] Wait until the copper substrate is etched clean, transfer the single-layer two-dimensional material electrode to deionized water and let it stand for more than 5 minutes, then repeat the transfer to fresh deionized water and let it stand for more than 5 minutes, and repeat five times.

[0038] According to the method for preparing a nanoelectrode of a two-dimensional material memristor provided by the present invention, the second physical vapor deposition is magnetron sputtering; the vacuum degree of the magnetron sputtering is lower than 1E-6 Torr, and the deposition rate is 1 Å / s.

[0039] According to the method for preparing a nanoelectrode of a two-dimensional material memristor provided by the present invention, after the top contact electrode is prepared, the method further includes: preparing a top test electrode;

[0040] The specific process of preparing the top test electrode includes:

[0041] Spin-coat a layer of photoresist on the top contact electrode in sequence with the spin-coating parameters of 700 r / 9 s and 4000 r / 40 s, pre-bake at 150 °C for 60 s, then expose using a chromium mask, post-bake at 100 °C for 120 s, develop, sputter 10 nm of metal titanium and 30 nm of metal palladium in sequence, and use acetone to remove the photoresist by peeling to form the top test electrode.

[0042] The present invention also provides a nanoelectrode of a two-dimensional material memristor, which is obtained by the method for preparing a nanoelectrode of a two-dimensional material memristor described in any one of the above.

[0043] The method for preparing nanoelectrodes of a two-dimensional material memristor provided by the present invention comprises the following steps: S1: Spin-coating a pre-prepared PMMA diluent on the second substrate, performing first mask pattern electron beam exposure on the second substrate according to a pre-designed contact electrode layout, and performing low-temperature development to form a patterned bottom contact electrode, wherein the size of the first mask pattern is nanoscale; S2: Subjecting the patterned bottom contact electrode to first physical vapor deposition, and then removing the glue by stripping to obtain a bottom contact electrode with a nanoscale size; S3: Preparing an insulating layer on the second substrate with the prepared bottom contact electrode by means of atomic layer deposition; S4: Etching the copper substrate of the two-dimensional material with the copper substrate, and transferring it above the insulating layer; S5: Performing patterning on the transferred two-dimensional material to obtain a patterned two-dimensional material electrode; S6: Spin-coating the PMMA diluent on the surface of the second substrate after patterning the two-dimensional material, baking and solidifying the glue, then performing second mask pattern electron beam exposure, and performing low-temperature development to form a top contact electrode pattern; wherein the size of the second mask pattern is nanoscale, and the second mask pattern and the patterned bottom contact electrode are arranged in a cross shape; S7: Subjecting the top contact electrode pattern to second physical vapor deposition, and then removing the glue by stripping to obtain a top contact electrode. In the present invention, both the bottom contact electrode and the top contact electrode of the two-dimensional material memristor are of nanoscale size, and the nanoscale memristor electrodes are prepared by means of electron beam exposure technology, diluting the PMMA solution to reduce the thickness of the photoresist, increasing the electron beam exposure dose, and low-temperature development method. The technology of the present invention has low cost and simple preparation method, and is compatible with traditional semiconductor device preparation and lithography process; using nanoscale lines as electrodes in two-dimensional material memristors can, on the one hand, cooperate with two-dimensional materials to reduce the on-state current and realize low-power neuromorphic devices, and on the other hand, can greatly reduce the device size, promote the high-density integration of neuromorphic devices and memory-computing integrated circuits. In addition, it can improve the uniformity of the performance of the devices in the array, and has great development prospects in the applications of memory-computing integration and integrated circuits. Description of the Drawings

[0044] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0045] Figure 1 It is a flow schematic diagram of the method for preparing nanoelectrodes of a two-dimensional material memristor provided by the present invention.

[0046] Figure 2 It is a structural schematic diagram of a two-dimensional material memristor provided by the present invention.

[0047] Figure 3 It is a top view structural diagram of a two-dimensional material memristor based on a nanoelectrode provided by the present invention.

[0048] Figure 4 It is a transmission electron microscope photograph of a memristor with a feature size of 20 nm provided by the present invention. Specific embodiments

[0049] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention fall within the scope of protection of the present invention.

[0050] The present invention will be specifically described below in conjunction with the drawings of the specification. The specific operation methods in the method embodiments can also be applied to the device embodiments or system embodiments. In the description of the present invention, unless otherwise specified, "at least one" includes one or more. "Multiple" means two or more. For example, at least one of A, B, and C includes: A alone, B alone, A and B existing simultaneously, A and C existing simultaneously, B and C existing simultaneously, and A, B, and C existing simultaneously. In the present invention, " / " means "or". For example, A / B can represent A or B; herein, "and / or" is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.

[0051] The present invention will be specifically described below in conjunction with the specific embodiments.

[0052] In some specific implementation schemes of the present invention, as Figure 1 shown, the present solution provides a method for preparing a nanoelectrode of a two-dimensional material memristor. The structure of the two-dimensional material memristor sequentially includes from bottom to top: a first substrate, a second substrate, a bottom contact electrode, an insulating layer, a two-dimensional material electrode layer, and a top contact electrode. Among them, the second substrate is grown through the first substrate;

[0053] The method includes:

[0054] S1: Spin-coat a pre-prepared PMMA diluent on the second substrate, perform first mask pattern electron beam exposure on the second substrate according to a pre-designed contact electrode layout, and perform low-temperature development to form a patterned bottom contact electrode. Among them, the size of the first mask pattern is nanoscale;

[0055] S2: The patterned bottom contact electrode is subjected to first physical vapor deposition, and after degluing and peeling, a bottom contact electrode with nanoscale dimensions is obtained;

[0056] S3: An insulating layer is prepared on the second substrate on which the bottom contact electrode has been prepared by means of atomic layer deposition;

[0057] S4: The two-dimensional material with a copper substrate is etched for the copper substrate and transferred above the insulating layer;

[0058] S5: The transferred two-dimensional material is patterned to obtain a patterned two-dimensional material electrode;

[0059] S6: The PMMA diluent is spin-coated on the surface of the second substrate after the two-dimensional material is patterned. After baking and solidifying the glue, second mask pattern electron beam exposure is carried out, and low-temperature development is carried out to form a top contact electrode pattern; wherein, the size of the second mask pattern is nanoscale, and the second mask pattern and the patterned bottom contact electrode are arranged in a cross shape. S7: The top contact electrode pattern is subjected to second physical vapor deposition, and after degluing and peeling, a top contact electrode is obtained.

[0060] It should be noted that in the existing electrode preparation scheme for two-dimensional material memristors, the characteristic size of two-dimensional material memristors remains in the micron range, which has a gap with silicon-based circuit integration. It is necessary to miniaturize the device size, reduce power consumption, and promote the high-density integration of in-memory computing architectures; moreover, the uniformity of two-dimensional materials is poor, which limits the yield of devices in memory computing circuits.

[0061] Therefore, based on the method for preparing nanoelectrodes of two-dimensional material memristors, based on electron beam exposure technology, a nano-scale memristor electrode is prepared by thinning the thickness of the photoresist by diluting the PMMA solution, increasing the electron beam exposure dose, and low-temperature development. Both the bottom contact electrode and the top contact electrode of the two-dimensional material memristor are of nanoscale dimensions. The preparation method of the nano-scale characteristic size electrode of the present invention is simple, easy to operate, and low in cost. When applied to two-dimensional material memristors, on the one hand, it can reduce the on-state current and realize low-power neuromorphic devices, and on the other hand, it can greatly reduce the device size and promote the high-density integration of neuromorphic devices and memory computing integrated circuits.

[0062] In some specific implementation manners of the present invention, a nanoelectrode of a two-dimensional material memristor is further provided, which is obtained by the method for preparing a nanoelectrode of a two-dimensional material memristor as described in any one of the above.

[0063] In some possible implementation manners of the present invention, such as Figure 2As shown, the structure of the two-dimensional material memristor from bottom to top is successively a silicon substrate 101 (the first substrate), a silicon dioxide substrate 102 (the second substrate), a bottom contact electrode 103, an insulating layer 104, a two-dimensional material 105, and a top contact electrode 106. Among them, the silicon dioxide substrate 102 is obtained by growing on the silicon substrate 101.

[0064] On this basis, the present invention is described in detail through two specific embodiments.

[0065] Embodiment 1: Still referring to Figure 2 , the first substrate is the silicon substrate 101, and the second substrate is the silicon dioxide substrate 102; the material of the bottom contact electrode 103 is metallic palladium; the material of the insulating layer 104 is hafnium oxide; the two-dimensional material 105 is graphene; the material of the top contact electrode 106 includes titanium nitride.

[0066] A preparation method of a two-dimensional material memristor based on a nanoelectrode includes the following steps:

[0067] S101: Substrate hydrophilicity treatment: The silicon substrate 101 / silicon dioxide substrate 102 is treated by oxygen plasma.

[0068] S102: Making alignment marks and bottom test electrodes: Spin-coat a layer of photoresist negative on the silicon substrate 101 / silicon dioxide substrate 102 successively at 700r / 9s and 4000r / 40s, prebake at 150°C for 60s, expose using a chromium mask plate, postbake at 100°C for 120s, develop, evaporate or sputter 10 nm of metallic titanium and 30 nm of metallic palladium, and use acetone to remove the glue and strip to form the designed alignment marks and bottom test electrodes.

[0069] S103: Preparing a PMMA diluent: Use anisole as the diluent and dilute PMMA at a ratio of PMMA:anisole of 2:1 to obtain a PMMA diluent.

[0070] S104: Patterning small-sized bottom contact electrodes: Spin-coat a layer of the PMMA diluent prepared in step S103 on the silicon substrate 101 / silicon dioxide substrate 102 with alignment marks prepared successively at 700r / 9s and 3000r / 40s, bake at 170°C for 5 min, and perform electron beam exposure, where the mask pattern sizes are 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, and 30 nm respectively, and then develop at low temperature.

[0071] S105: Evaporating the bottom contact electrode: Evaporate the sample patterned in step S104 by electron beam evaporation in a low-vacuum environment, evaporate 5 nm of metallic titanium and 30 nm of metallic palladium, and use acetone to remove the glue and strip to obtain a bottom contact electrode 103 with an actual size of 20 nm.

[0072] S106: Prepare the insulating layer 104: Use atomic layer deposition to grow a hafnium oxide insulating layer with a thickness of 5 - 7 nm;

[0073] S107: Transfer the two-dimensional material 105: Prepare a 3% ammonium persulfate solution and let it stand for one day. Place the graphene with a copper substrate prepared by chemical vapor deposition into the standing ammonium persulfate solution. Wait until the copper substrate is etched clean. Use a hydrophilic-treated silicon wafer to transfer the single-layer graphene into deionized water and let it stand for more than 5 minutes. Repeat the above transfer five times. After the hafnium oxide insulating layer substrate prepared in step S106 is hydrophilic-treated, transfer the graphene above the small-size bottom contact electrode of the substrate;

[0074] S108: Pattern the graphene material: Spin-coat a layer of positive photoresist on the sample obtained in step S107 at 700 r / 9 s and 3000 r / 60 s in sequence, pre-bake at 100 °C for 60 s, expose using a chromium mask, post-bake at 100 °C for 90 s, develop, treat with an oxygen plasma with a power of 150 W and a gas flow rate of 150 sccm for 7 min, and remove the photoresist using acetone, thereby patterning the graphene material;

[0075] S109: Prepare the small-size top contact electrode: Spin-coat a layer of the PMMA dilution solution prepared in step S103 on the patterned graphene material prepared in step S108 at 700 r / 9 s and 3000 r / 40 s in sequence, bake at 170 °C for 5 min, perform electron beam exposure, where the mask pattern sizes are 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, and 30 nm respectively, and are in a cross shape with the small-size bottom contact electrode, as Figure 3 shown, and then develop at low temperature;

[0076] S110: Evaporate the top contact electrode 106: Subject the sample patterned in step S109 to magnetron sputtering in a low-vacuum environment to sputter 36 nm of titanium nitride, and remove the photoresist using acetone to obtain a top contact electrode with an actual size equal to or less than 20 nm;

[0077] S111: Prepare the top test electrode: Spin-coat a layer of negative photoresist on the sample obtained in step S110 at 700 r / 9 s and 4000 r / 40 s in sequence, pre-bake at 150 °C for 60 s, expose using a chromium mask, post-bake at 100 °C for 120 s, develop, sputter 10 nm of metal titanium and 30 nm of metal palladium, and remove the photoresist using acetone to form the designed top test electrode, obtaining a two-dimensional material memristor with electrode lines equal to or less than 20 nm.

[0078] The scanning electron microscope image of the 20-nm line obtained in the first embodiment is as Figure 4As shown, in the two-dimensional material memristor prepared therefrom, titanium nitride serves as the top contact electrode. When a positive voltage is applied to the top contact electrode, oxygen ions in the HfO2 insulating layer are induced to migrate, forming a large number of oxygen vacancy defect states that accumulate throughout the insulating layer. The memristor changes from a high-resistance state to a low-resistance state, which is the SET process. When a negative voltage is applied to the top contact electrode, the oxygen vacancies combine with oxygen ions, the conductive channel breaks, and the device changes from a low-resistance state to a high-resistance state, which is the RESET process. In the memristor, graphene and nanoscale top and bottom contact electrodes can both reduce the amount of conductance channels, lower the on-state current, and realize low-power neuromorphic devices.

[0079] Example 2. Continuing to refer to Figure 2 , the first substrate is a silicon substrate 101; the second substrate is a silicon dioxide substrate 102; the material of the bottom contact electrode 103 is palladium metal; the material of the insulating layer 104 is hafnium oxide; the two-dimensional material 105 is graphene; the material of the top contact electrode 106 is silver.

[0080] The preparation method of the two-dimensional material memristor based on nanoelectrodes includes the following steps:

[0081] S201~S205 are the same as steps S101~S105 in Example 1; that is:

[0082] S201: Substrate hydrophilic treatment: The silicon substrate 101 / silicon dioxide substrate 102 is treated with oxygen plasma.

[0083] S202: Making alignment marks and bottom test electrodes: Spin-coat a layer of photoresist negative on the silicon substrate / silicon dioxide substrate at 700r / 9s and 4000r / 40s in sequence, pre-bake at 150°C for 60s, expose using a chromium mask, post-bake at 100°C for 120s, develop, evaporate or sputter 10nm of titanium metal and 30nm of palladium metal, and use acetone to remove the glue and peel off to form the designed alignment marks and bottom test electrodes.

[0084] S203: Preparing PMMA diluent: Use anisole as the diluent and dilute PMMA in a ratio of PMMA:anisole of 2:1 to obtain the PMMA diluent.

[0085] S204: Patterning small-size bottom contact electrodes: Spin-coat a layer of the PMMA diluent prepared in step S203 on the silicon substrate 101 / silicon dioxide substrate 102 with alignment marks prepared at 700r / 9s and 3000r / 40s in sequence, bake at 170°C for 5min, and perform electron beam exposure, where the mask pattern sizes are 1nm, 5nm, 10nm, 15nm, 20nm, 25nm, and 30nm respectively, and then perform low-temperature development.

[0086] S205: Evaporation of bottom contact electrode: The patterned sample from step S204 is subjected to electron beam evaporation in a low-vacuum environment to evaporate 5 nm of metallic titanium and 30 nm of metallic palladium, and then de-glued and peeled off with acetone to obtain a bottom contact electrode 103 with an actual size of 20 nm;

[0087] S206: Preparation of insulating layer 104: An 8 - 10 nm hafnium oxide insulating layer is grown by atomic layer deposition;

[0088] Steps S207 - S209 are the same as steps S107 - S109 in Embodiment 1, that is:

[0089] S207: Transfer of two-dimensional material 105: A 3% ammonium persulfate solution is prepared and left standing for one day. The graphene with a copper substrate prepared by chemical vapor deposition is placed in the standing ammonium persulfate solution. After the copper substrate is etched clean, the monolayer graphene is transferred to deionized water using a hydrophilic-treated silicon wafer and left standing for more than 5 minutes. After repeating the above transfer five times, after the substrate prepared in step S206 is hydrophilic-treated, the graphene is transferred above the small-size bottom contact electrode of the substrate;

[0090] S208: Patterning of graphene material: The sample obtained in step S207 is spin-coated with a layer of positive photoresist at 700 r / 9 s and 3000 r / 60 s in sequence, pre-baked at 100 °C for 60 s, exposed using a chromium mask, post-baked at 100 °C for 90 s, developed, and treated with oxygen plasma at a power of 150 W and a gas flow rate of 150 sccm for 7 min, and then de-glued with acetone, thereby patterning the graphene material;

[0091] S209: Preparation of small-size top contact electrode 106: A layer of the PMMA diluent prepared in step S203 is spin-coated on the graphene material prepared in step S208 at 700 r / 9 s and 3000 r / 40 s in sequence, baked at 170 °C for 5 min, and then electron beam exposed, where the mask pattern sizes are 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, and 30 nm respectively, and are in a cross shape with the small-size bottom contact electrode, and then developed at low temperature;

[0092] S210: Evaporation of top contact electrode 106: The patterned sample from step S209 is subjected to thermal evaporation in a low-vacuum environment to evaporate 30 nm of metallic silver, and then de-glued and peeled off with acetone to obtain a top contact electrode with a nanoscale actual size;

[0093] Step S211 is the same as step S111 in Embodiment 1, that is:

[0094] S211: Prepare the top test electrode: Spin-coat a layer of negative photoresist on the sample obtained in step S210 at 700 r / 9 s and 4000 r / 40 s successively, pre-bake at 150 °C for 60 s, expose using a chromium mask plate, post-bake at 100 °C for 120 s, develop, sputter 10 nm of metallic titanium and 30 nm of metallic palladium, and remove the photoresist by acetone stripping to form the designed top test electrode, obtaining a two-dimensional material memristor with electrode lines equal to or less than 20 nm.

[0095] Thus, a two-dimensional material memristor with electrode lines equal to or less than 20 nm is obtained.

[0096] For the two-dimensional material memristor obtained in this second embodiment, the top electrode material is silver. Silver atoms are oxidized to anions under the positive voltage of the top contact electrode and drift towards the bottom contact electrode, accumulating on the bottom contact electrode until they contact the top contact electrode, forming a conductive filament and converting to a resistive state, which is the SET process of the memristor. When a negative voltage is applied to the top contact electrode, silver ions drift from the bottom contact electrode to the top contact electrode, which is the RESET process. This is the working process of the memristor described in the second embodiment. Generally, the insulating layer is HfO2 deposited by atomic layer deposition at 190 °C, which has a relatively loose structure and is more conducive to the formation of conductive filaments. The nanoscale top and bottom contact electrodes can reduce the number of conductance filaments, lower the on-state current, and realize low-power neuromorphic devices.

[0097] It should be noted that each step process included in the present invention is prepared layer by layer on the second substrate, and each process such as growth or spin-coating is carried out on the basis of the previous process.

[0098] The method for preparing nanoelectrodes of the two-dimensional material memristor provided by the present invention. The bottom contact electrode and the top contact electrode of the two-dimensional material memristor are both of nanoscale size. Through electron beam lithography technology, the thickness of the photoresist is thinned by diluting the PMMA solution, the electron beam exposure dose is increased, and the nano-scale memristor electrode is prepared by the method of low-temperature development. The technology of the present invention has low cost and simple preparation method, and is compatible with traditional semiconductor device preparation and lithography processes; applying the nanoscale lines as electrodes in the two-dimensional material memristor can, on the one hand, cooperate with the two-dimensional material to reduce the on-state current and realize low-power neuromorphic devices, and on the other hand, can greatly reduce the device size, promote the high-density integration of neuromorphic devices and memory-computation integrated circuits. In addition, it can improve the uniformity of the device performance within the array, and has great development prospects in the applications of memory-computation integration and integrated circuits.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a nanoelectrode of a two-dimensional material memristor, wherein the structure of the two-dimensional material memristor comprises, from bottom to top: A first substrate, a second substrate, a bottom contact electrode, an insulating layer, a two-dimensional material electrode layer, and a top contact electrode, wherein the second substrate is obtained by growing on the first substrate, characterized in that the method comprises: S1: spin-coating a pre-prepared PMMA dilution solution on the second substrate, performing electron beam exposure of a first mask pattern on the second substrate according to a pre-designed contact electrode layout, and performing low-temperature development to form a patterned bottom contact electrode, wherein the size of the first mask pattern is nanometer-scale; S2: subjecting the patterned bottom contact electrode to a first physical vapor deposition process, and then performing debonding and peeling to obtain a bottom contact electrode of nanometer size; S3: forming an insulating layer on the second substrate on which the bottom contact electrode is formed by atomic layer deposition, wherein the insulating layer comprises hafnium oxide; S4: etching the copper substrate of the two-dimensional material, and transferring the two-dimensional material to above the insulating layer, wherein the two-dimensional material is graphene; S5: performing patterning on the transferred two-dimensional material to obtain a patterned two-dimensional material electrode; S6: Spin-coating the PMMA dilution solution on the surface of the second substrate after the two-dimensional material is patterned, baking the resin to solidify, performing electron beam exposure on a second mask pattern, and performing low-temperature development to form a top contact electrode pattern; wherein the size of the second mask pattern is nanometer-scale, and the second mask pattern and the patterned bottom contact electrode are arranged in a cross shape; S7: subjecting the top contact electrode pattern to a second physical vapor deposition process, followed by debonding and peeling to obtain a nanoscale top contact electrode, wherein the top contact electrode comprises titanium nitride and silver, and the design line sizes of the first mask pattern and the second mask pattern are 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, and 30 nm, respectively; The preparation method of the PMMA diluent comprises: Select PMMA photoresist from the PMMA300.07.5 series; PMMA photoresist and anisole were mixed in a ratio of 2:1 to obtain a PMMA dilution solution, wherein the dilution solution thickness under this ratio was 70-75 nm; The dose of the electron beam exposure is greater than 1000 mJ / cm 2 ; The developer for low-temperature development is a PMMA dilution solution stored in a refrigerated environment below 5°C.

2. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The first substrate is a silicon substrate, and the second substrate is a silicon dioxide substrate; the material of the bottom contact electrode includes metal palladium and gold.

3. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The step of preparing an insulating layer on the second substrate on which the bottom contact electrode is prepared by atomic layer deposition specifically includes: A 5-7nm hafnium oxide insulating layer was grown using atomic layer deposition.

4. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 3, characterized in that: The first physical vapor deposition is magnetron sputtering; The vacuum degree of the magnetron sputtering is lower than 1E-6 Torr, and the deposition rate is 1 Å / s.

5. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The step of preparing an insulating layer on the second substrate on which the bottom contact electrode is prepared by atomic layer deposition specifically includes: An 8-10nm hafnium oxide insulating layer is grown using atomic layer deposition.

6. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 5, characterized in that: The first physical vapor deposition is electron beam evaporation; The vacuum degree of the electron beam evaporation is lower than 1E-6 Torr, and the deposition rate is 1Å / s.

7. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: Before spin coating the pre-prepared PMMA dilution on the second substrate, the method further includes: forming an alignment mark and a bottom test electrode on the second substrate; The specific process of making the alignment mark and the bottom test electrode includes: A layer of negative photoresist was spin-coated on the second substrate with the coating parameters of 700r / 9s and 4000r / 40s, and then pre-baked at 150°C for 60s, exposed using a chrome mask, mid-baked at 100°C for 120s, developed, evaporated or sputtered 10nm of metal titanium and 30nm of metal palladium, and peeled off with acetone to form alignment marks and bottom test electrodes.

8. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: Spin coating a pre-prepared PMMA dilution on the second substrate, specifically comprising: A layer of the PMMA dilution solution was spin-coated on the second substrate with the alignment mark prepared thereon at the coating parameters of 700 r / 9 s and 3000 r / 40 s in sequence, and baked at 170° C. for 5 min.

9. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The etching of the copper substrate on the two-dimensional material with the copper substrate specifically includes: A 3% ammonium persulfate solution was prepared and allowed to stand for 24 hours, and a single-layer two-dimensional material electrode with a copper substrate formed by chemical vapor deposition was placed in the ammonium persulfate solution after standing; After the copper substrate is etched clean, the single-layer two-dimensional material electrode is transferred to deionized water and allowed to stand for more than 5 minutes, and then transferred to new deionized water and allowed to stand for more than 5 minutes, and repeated five times.

10. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: The second physical vapor deposition is magnetron sputtering; the vacuum degree of the magnetron sputtering is lower than 1E-6 Torr, and the deposition rate is 1 Å / s.

11. The method for preparing a nanoelectrode of a two-dimensional material memristor according to claim 1, characterized in that: After preparing the top contact electrode, the method further includes: preparing a top test electrode; The specific process of preparing the top test electrode includes: A layer of negative photoresist was spin-coated on the top contact electrode with the coating parameters of 700r / 9s and 4000r / 40s, pre-baked at 150°C for 60s, exposed using a chrome mask, mid-baked at 100°C for 120s, developed, and sputtered with 10nm of metal titanium and 30nm of metal palladium in sequence. The top test electrode was formed by debonding using acetone.

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