Fractional transforms for video coding

Abstract

The disclosure herein provides methods, apparatuses, and non-transitory computer-readable storage media for video decoding and encoding. In an example, a method for video encoding includes generating, by the encoder, an enable flag at a sequence parameter set (SPS) level for an intra coding mode and an inter coding mode, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) at a coding unit (CU) level is enabled for at least one mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 395,818, filed on August 6, 2022, entitled “Fraction Transform for Video Coding,” the entire contents of which are incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates to video coding and compression, and in particular, but not limited to, methods and apparatus for improving the coding efficiency of transform codecs. Background Art

[0004] Various video codec technologies can be used to compress video data. Video coding is performed according to one or more video codec standards. For example, video codec standards include Versatile Video Codec (VVC), High Efficiency Video Codec (H.265 / HEVC), Advanced Video Codec (H.264 / AVC), Moving Picture Experts Group (MPEG) codec, etc. Video codecs typically use prediction methods (e.g., inter-frame prediction, intra-frame prediction, etc.) that exploit redundancy present in video images or sequences. An important goal of video coding technology is to compress video data into a form that uses a lower bit rate while avoiding or minimizing the degradation of video quality.

[0005] The first version of the VVC standard was completed in July 2020, which provides approximately 50% bitrate savings or equivalent perceptual quality compared to the previous generation video codec standard HEVC. Although the VVC standard provides significant codec improvements over its predecessor, there is evidence that superior codec efficiency can be achieved by adopting additional codec tools. Recently, the Joint Video Exploration Team (JVET), in collaboration with ITU-TVECG and ISO / IEC MPEG, began exploring advanced technologies that can significantly improve codec efficiency over VVC. In April 2021, a software code base named Enhanced Compression Model (ECM) was established for future video codec exploration work. The ECM reference software is based on the VVC Test Model (VTM) developed by JVET for VVC, and further extends and / or improves several existing modules (e.g., intra / inter prediction, transform, loop filter, etc.). In the future, any new codec tools beyond the VVC standard will need to be integrated into the ECM platform and tested using the JVET Common Test Conditions (CTC). Summary of the invention

[0006] This disclosure provides examples of techniques related to improving encoding and decoding efficiency of inter-blocks.

[0007] A first example of the present disclosure includes a method for video encoding, comprising: generating, by an encoder, an enable flag at a sequence parameter set (SPS) level for an intra-frame coding mode and an inter-frame coding mode, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for at least one mode; in response to the FRDCT being enabled at the SPS level, generating, by the encoder, an FRDCT CU-level flag for indicating whether an FRDCT transform is applied to a coding unit (CU); in response to determining that the FRDCT transform is applied to the CU, obtaining a flag indicating one of the following: (i) a horizontal vector and a vertical vector share an FRDCT transform matrix, or (ii) a horizontal vector and a vertical vector use separate FRDCT transform matrices.

[0008] A second example of the present disclosure includes a method for video encoding, comprising: generating, by an encoder, an enable flag at a sequence parameter set (SPS) level for an intra-frame coding mode and an inter-frame coding mode, the enable flag indicating whether the fractional discrete cosine transform is enabled for at least one mode; in response to the FRDCT being enabled at the SPSP level, generating, by the encoder, an FRDCT CU level flag for indicating whether an FRDCT transform is applied to a coding unit (CU); in response to determining that the FRDCT transform is applied to the CU, determining that the CU includes one of the following: (i) a horizontal vector and a vertical vector that share an FRDCT transform matrix; or (ii) a horizontal vector and a vertical vector that use a separate FRDCT transform matrix.

[0009] A third example of the present disclosure includes a method for video encoding, comprising: generating a fractional discrete cosine transform (FRDCT) matrix at an encoder using received video data; performing eigenvalue decomposition on the FRDCT matrix at the encoder to obtain eigenvectors and eigenvalues, and the eigenvalue decomposition includes: raising the eigenvalues ​​to the power of a fractional number to obtain modified eigenvalues; and generating a derived FRDCT matrix at the encoder using the modified eigenvalues ​​and eigenvectors.

[0010] A fourth example of the present disclosure includes a method for video encoding, comprising: generating a coding unit (CU) level flag at an encoder to indicate that an FRDCT video coding scheme is enabled at a sequence parameter set (SPS) level; and in response to generating a CU level flag to indicate that the FRDCT video coding scheme is enabled at the SPS level, in response to determining that the position of the last significant coefficient of a luminance transform block (TB) is less than 1 or in response to determining that the last significant coefficient of the luminance TB is located within an MTS zero region, applying a multi-transform skip (MTS) video coding scheme instead of the FRDCT video coding scheme.

[0011] A fifth example of the present disclosure includes a method for video decoding, comprising: obtaining a fractional discrete cosine transform (FRDCT) coding unit (CU) level flag at a decoder; determining at the decoder that the FRDCT CU level flag indicates that FRDCT transform parameters for horizontal FRDCT transform and vertical FRDCT transform are shared between the decoder and the encoder; and in response to determining that the FRDCT CU flag indicates that the FRDCT transform parameters for horizontal FRDCT transform and vertical FRDCT transform are shared between the decoder and the encoder, defining the shared FRDCT transform parameters at the decoder.

[0012] A sixth example of the present disclosure includes a method for video decoding, comprising: receiving an enable flag at a sequence parameter set (SPS) level for an intra-frame coding mode and an inter-frame coding mode at a decoder, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for at least one mode; determining at the decoder an FRDCT coding unit (CU) level flag indicating that FRDCT transform parameters for horizontal FRDCT transform and vertical FRDCT transform are shared between the decoder and the encoder; defining the shared FRDCT transform parameters at the decoder in response to determining that the FRDCT CU flag indicates that the FRDCT transform parameters for horizontal FRDCT transform and vertical FRDCT transform are shared between the encoder and the decoder; and receiving at the decoder one or more FRDCT transform matrices that satisfy both DCT conditions and additivity including eigenvalue decomposition, the one or more FRDCT transform matrices including the FRDCT transform parameter set.

[0013] A seventh example of the present disclosure includes a method for video decoding, comprising: receiving at a decoder a derived fractional discrete cosine transform (FRDCT) matrix generated by an encoder using eigenvalue decomposition, the eigenvalue decomposition comprising raising eigenvalues ​​to the power of a fractional number to obtain modified eigenvalues, the FRDCT matrix comprising the modified eigenvalues; receiving at the decoder one or more encoded transform blocks generated at the encoder by applying the derived FRDCT matrix to one or more video frames; and storing the one or more encoded transform blocks in a memory at the decoder.

[0014] An eighth example of the present disclosure includes a device for video decoding, comprising one or more processors; and a memory coupled to the one or more processors and configured to store instructions executable by the one or more processors, wherein the one or more processors are configured to execute the method in the aforementioned example when executing the instructions.

[0015] A ninth example of the present disclosure includes a device for video encoding, comprising: one or more processors; and a memory coupled to the one or more processors and configured to store instructions executable by the one or more processors, wherein the one or more processors are configured to execute the method of any of the preceding examples when executing the instructions.

[0016] The tenth example of the present disclosure includes a non-transitory computer-readable storage medium for storing computer-executable instructions, which, when executed by one or more computer processors, cause the one or more computer processors to perform the following operations: receive a bit stream; and execute the method in any of the preceding examples based on the bit stream.

[0017] An eleventh example of the present disclosure includes a non-temporary computer-readable storage medium for storing computer-executable instructions, which, when executed by one or more computer processors, cause the one or more computer processors to perform the method in any of the preceding examples to encode the CU into a bitstream, and send the bitstream.

[0018] A twelfth example of the present disclosure includes a non-transitory computer-readable storage medium for storing a bit stream to be decoded by the method in any of the preceding examples.

[0019] A thirteenth example of the present disclosure includes a non-transitory computer-readable storage medium for storing a bitstream generated by the method of any one of claims 1-19. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] A more specific description of examples of the present disclosure will be presented by reference to specific examples shown in the accompanying drawings. Given that these drawings depict only some examples and are therefore not to be considered limiting in scope, the examples will be described and explained with additional specificity and detail through the use of the accompanying drawings.

[0021] Figure 1 is a block diagram illustrating a system for encoding and decoding video blocks according to some examples of the present disclosure.

[0022] Figure 2 is a block diagram illustrating an exemplary video encoder according to some examples of the present disclosure.

[0023] Figure 3 is a block diagram illustrating an exemplary video decoder according to some examples of the present disclosure.

[0024] Figure 4A is an illustration of an encoded representation of a frame according to some examples of the present disclosure.

[0025] Figure 4B is a diagram of a CTU of one CTB including luma samples according to some examples of the present disclosure.

[0026] Figure 4C is an illustration of a 64x64 CTU divided into four smaller CUs, each CU having a block size of 32x32, according to some examples of the present disclosure.

[0027] Figure 4D It is shown as Figure 4C An illustration of a quadtree data structure that is the end result of the partitioning process of a CTU 400 is depicted.

[0028] Figure 4E is a diagram of five partition types of coding blocks with width W and height H according to some examples of the present disclosure.

[0029] Figure 5 is a flowchart illustrating a method for video decoding according to some examples of the present disclosure.

[0030] Figure 6 is a flowchart illustrating a method for video decoding according to some examples of the present disclosure.

[0031] Figure 7 is a flowchart illustrating a method for video decoding according to some examples of the present disclosure.

[0032] Figure 8 is a flowchart illustrating a method for video decoding according to some examples of the present disclosure.

[0033] Fig. 9 is a flowchart illustrating a method for video decoding according to some examples of the present disclosure.

[0034] Fig.10 is a flowchart illustrating a method for video decoding according to some examples of the present disclosure.

[0035] Fig.11 is a diagram illustrating a computing environment coupled with a user interface according to some examples of the present disclosure. DETAILED DESCRIPTION

[0036] Reference will now be made in detail to specific implementations, examples of which are shown in the accompanying drawings. In the following detailed description, many non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to one of ordinary skill in the art that various alternatives may be used. For example, it will be apparent to one of ordinary skill in the art that the subject matter presented herein may be implemented on many types of electronic devices having digital video capabilities.

[0037] The terms used in this disclosure are only used for the purpose of describing specific embodiments and are not intended to limit the disclosure. Unless otherwise clearly indicated throughout the disclosure, the singular forms of "one", "said" and "the" in this disclosure and the appended claims are also intended to include plural forms. It should also be understood that the term "and / or" used in this disclosure refers to and includes one or any or all possible combinations of the listed multiple associated items.

[0038] References throughout this specification to "one embodiment," "an embodiment," "an example," "some embodiments," "some examples," or similar language mean that the particular features, structures, or characteristics being described are included in at least one embodiment or example. Unless explicitly stated otherwise, features, structures, elements, or characteristics described in conjunction with one or some embodiments are also applicable to other embodiments.

[0039] Unless otherwise explicitly indicated, throughout the present disclosure, the terms "first", "second", "third", etc. are used only as names for reference to related elements (e.g., devices, components, compositions, steps, etc.), without implying any spatial or temporal order. For example, "first device" and "second device" may refer to two separately formed devices, or two parts, components or operating states of the same device, and may be named arbitrarily.

[0040] The terms "module", "sub-module", "circuit", "sub-circuit", "circuitry", "sub-circuitry", "unit", or "sub-unit" may include a memory (shared, dedicated, or a memory group) that stores code or instructions that can be executed by one or more processors. A module may include one or more circuits with or without stored code or instructions. A module or circuit may include one or more components that are directly or indirectly connected. These components may or may not be physically attached to each other, or may be adjacent to each other.

[0041] As used herein, the terms "if" or "when..." may be understood to mean "at..." or "in response to...", depending on the context. If these terms appear in the claims, they may not indicate that the associated limitation or feature is conditional or optional. For example, a method may include the following steps: i) when condition X exists or if condition X exists, perform function or action X', and ii) when condition Y exists or if condition Y exists, perform function or action Y'. The method may be implemented with the ability to perform function or action X' and the ability to perform function or action Y'. Therefore, both functions X' and Y' may be performed at different times on multiple executions of the method.

[0042] A unit or module may be implemented purely by software, purely by hardware, or by a combination of hardware and software. In a pure software implementation, for example, a unit or module may include functionally related code blocks or software components that are linked together directly or indirectly to perform a specific function.

[0043] Reference will now be made in detail to specific embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to one of ordinary skill in the art that various alternatives may be used without departing from the scope of the claims, and that the subject matter may be practiced without these specific details. For example, it will be apparent to one of ordinary skill in the art that the subject matter presented herein may be implemented on many types of electronic devices having digital video capabilities.

[0044] It should be noted that the terms "first", "second", etc. used in the description, claims, and drawings of the present disclosure are used to distinguish objects and are not used to describe any specific order or sequence. It should be understood that the terms used in this manner can be interchanged under appropriate conditions, so that the embodiments of the present disclosure described herein can be implemented in an order other than the order shown in the drawings or described in the present disclosure.

[0045] Figure 1 A is a block diagram illustrating an exemplary system 10 for encoding and decoding video blocks in parallel according to some embodiments of the present disclosure. Figure 1 As shown in FIG. 1A , system 10 includes a source device 12 that generates and encodes video data to be later decoded by a destination device 14. Source device 12 and destination device 14 may include any of a wide variety of electronic devices, including desktop or laptop computers, tablet computers, smart phones, set-top boxes, digital televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, etc. In some implementations, source device 12 and destination device 14 are equipped with wireless communication capabilities.

[0046] In some embodiments, the target device 14 may receive the encoded video data to be decoded via the link 16. The link 16 may include any type of communication medium or device capable of moving the encoded video data from the source device 12 to the target device 14. In one example, the link 16 may include a communication medium that enables the source device 12 to send the encoded video data directly to the target device 14 in real time. The encoded video data may be modulated according to a communication standard (e.g., a wireless communication protocol) and sent to the target device 14. The communication medium may include any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form a portion of a packet-based network (e.g., a local area network, a wide area network, or a global network such as the Internet). The communication medium may include a router, a switch, a base station, or any other device that may be beneficial to facilitate communication from the source device 12 to the target device 14.

[0047] In some other embodiments, the encoded video data may be sent from the output interface 22 to the storage device 32. The encoded video data in the storage device 32 may then be accessed by the target device 14 via the input interface 28. The storage device 32 may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, a Blu-ray disc, a digital versatile disc (DVD), a compact disc read-only memory (CD-ROM), a flash memory, a volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data. In another example, the storage device 32 may correspond to a file server or another intermediate storage device that may hold the encoded video data generated by the source device 12. The target device 14 may access the stored video data from the storage device 32 via streaming or downloading. The file server may be any type of computer capable of storing encoded video data and sending the encoded video data to the target device 14. Exemplary file servers include a network server (e.g., for a website), a file transfer protocol (FTP) server, a network attached storage (NAS) device, or a local disk drive. Target device 14 may access the encoded video data through any standard data connection suitable for accessing encoded video data stored on a file server, including a wireless channel (e.g., a Wireless Fidelity (Wi-Fi) connection), a wired connection (e.g., a Digital Subscriber Line (DSL), a cable modem, etc.), or a combination of both wireless channels and wired connections. The transmission of the encoded video data from storage device 32 may be a streaming transmission, a download transmission, or a combination of both streaming and download transmissions.

[0048] like Figure 1As shown in A, source device 12 includes video source 18, video encoder 20 and output interface 22. Video source 18 may include a source such as a video capture device (e.g., a camera), a video archive containing previously captured video, a video feed interface for receiving video from a video content provider, and / or a computer graphics system for generating computer graphics data as source video. As an example, if video source 18 is a camera of a security monitoring system, source device 12 and target device 14 may form a camera phone or video phone. However, the embodiments described in this application may be generally applicable to video encoding and decoding, and may be applied to wireless and / or wired applications.

[0049] The captured, pre-captured, or computer-generated video may be encoded by the video encoder 20. The encoded video data may be sent directly to the target device 14 via the output interface 22 of the source device 12. The encoded video data may also (or alternatively) be stored on a storage device 32 for later access by the target device 14 or other device for decoding and / or playback. The output interface 22 may further include a modem and / or a transmitter.

[0050] Target device 14 includes input interface 28, video decoder 30, and display device 34. Input interface 28 may include a receiver and / or a modem and receives encoded video data via link 16. The encoded video data transmitted via link 16 or provided on storage device 32 may include various syntax elements generated by video encoder 20 for use by video decoder 30 in decoding the video data. Such syntax elements may be included within the encoded video data sent over a communication medium, stored on a storage medium, or stored on a file server.

[0051] In some implementations, the target device 14 may include a display device 34, which may be an integrated display device or an external display device configured to communicate with the target device 14. The display device 34 displays the decoded video data to a user, and may include any of a variety of display devices, such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0052] The video encoder 20 and the video decoder 30 can operate according to a proprietary standard or an industry standard (e.g., VVC, HEVC, Part 10 of MPEG-4, AVC) or an extension of such a standard. It should be understood that the present application is not limited to a specific video encoding / decoding standard and can be applied to other video encoding / decoding standards. It is generally believed that the video encoder 20 of the source device 12 can be configured to encode the video data according to any of these current standards or future standards. Similarly, it is also generally believed that the video decoder 30 of the target device 14 can be configured to decode the video data according to any of these current standards or future standards.

[0053] The video encoder 20 and the video decoder 30 can be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic devices, software, hardware, firmware, or any combination thereof. When partially implemented in software, the electronic device can store instructions for the software in a suitable non-transitory computer-readable medium, and use one or more processors to execute the instructions in the hardware to perform the video encoding / decoding operations disclosed in the present disclosure. Each of the video encoder 20 and the video decoder 30 can be included in one or more encoders or decoders, and either of the encoders or decoders can be integrated as part of a combined encoder / decoder (CODEC) in the corresponding device.

[0054] Figure 2 A is a block diagram illustrating another exemplary video encoder 20 according to some embodiments described in the present application. The video encoder 20 can perform intra-frame prediction coding and inter-frame prediction coding on video blocks within a video frame. Intra-frame prediction coding relies on spatial prediction to reduce or remove spatial redundancy in video data within a given video frame or picture. Inter-frame prediction coding relies on temporal prediction to reduce or remove temporal redundancy in video data within adjacent video frames or pictures of a video sequence. It should be noted that in the field of video coding and decoding, the term "frame" can be used as a synonym for the term "image" or "picture".

[0055] like Figure 2As shown in FIG. 4A , the video encoder 20 includes a video data memory 40, a prediction processing unit 41, a decoded picture buffer (DPB) 64, an adder 50, a transform processing unit 52, a quantization unit 54, and an entropy coding unit 56. The prediction processing unit 41 further includes a motion estimation unit 42, a motion compensation unit 44, a segmentation unit 45, an intra-frame prediction processing unit 46, and an intra-frame block copy (BC) unit 48. In some embodiments, the video encoder 20 also includes an inverse quantization unit 58, an inverse transform processing unit 60, and an adder 62 for video block reconstruction. A loop filter 63 such as a deblocking filter can be located between the adder 62 and the DPB 64 to filter the block boundary to remove the block effect from the reconstructed video. In addition to the deblocking filter, another loop filter (e.g., a sample adaptive offset (SAO) filter and / or an adaptive loop filter (ALF)) can also be used to filter the output of the adder 62. In some examples, the loop filter can be omitted, and the decoded video block can be directly provided to the DPB 64 by the adder 62. Video encoder 20 may take the form of a fixed or programmable hardware unit, or may be distributed among one or more of the fixed or programmable hardware units shown.

[0056] Video data memory 40 may store video data to be encoded by components of video encoder 20. Figure 1 The video source 18 shown in A obtains video data in the video data memory 40. The DPB 64 is a buffer that stores reference video data (e.g., reference frames or pictures) for use by the video encoder 20 (e.g., in intra-frame or inter-frame prediction coding mode) when encoding the video data. The video data memory 40 and the DPB 64 can be formed by any of a variety of memory devices. In various examples, the video data memory 40 can be on-chip with other components of the video encoder 20, or off-chip relative to those components.

[0057] like Figure 2As shown in FIG. 4A , after receiving the video data, the segmentation unit 45 within the prediction processing unit 41 segments the video data into video blocks. This segmentation may also include segmenting the video frame into strips, tiles (e.g., a set of video blocks) or other larger coding units (CUs) according to a predefined splitting structure associated with the video data (e.g., a quadtree (QT) structure). A video frame is or may be considered as a two-dimensional array or matrix of samples having sample values. The samples in the array may also be referred to as pixels or picture elements (pel). The number of samples in the horizontal and vertical directions (or axes) of the array or picture defines the size and / or resolution of the video frame. For example, a video frame may be divided into a plurality of video blocks by using QT segmentation. A video block is again or may be considered as a two-dimensional array or matrix of samples having sample values, but its dimension is smaller than the dimension of a video frame. The number of samples in the horizontal and vertical directions (or axes) of a video block defines the size of the video block. The video block may be further partitioned into one or more block partitions or sub-blocks (which may again form blocks) by, for example, iteratively using QT partitioning, binary tree (BT) partitioning or ternary tree (TT) partitioning or any combination thereof. It should be noted that the term "block" or "video block" used herein may be a portion of a frame or picture, in particular a rectangular (square or non-square) portion. With reference to, for example, HEVC and VVC, a block or video block may be or correspond to a coding tree unit (CTU), a CU, a prediction unit (PU) or a transform unit (TU) and / or may be or correspond to a corresponding block (e.g., a coding tree block (CTB), a coding block (CB), a prediction block (PB) or a transform block (TB)) and / or a sub-block.

[0058] The prediction processing unit 41 may select one of a plurality of feasible prediction coding modes for the current video block based on the error results (e.g., coding rate and distortion level), such as one of one or more inter-frame prediction coding modes in a plurality of intra-frame prediction coding modes. The prediction processing unit 41 may provide the resulting intra-frame prediction coding block or inter-frame prediction coding block to the adder 50 to generate a residual block, and to the adder 62 to reconstruct the coding block for subsequent use as part of a reference frame. The prediction processing unit 41 also provides syntax elements (e.g., motion vectors, intra-frame mode indicators, partition information, and other such syntax information) to the entropy coding unit 56.

[0059] To select an appropriate intra-prediction coding mode for the current video block, intra-prediction processing unit 46 within prediction processing unit 41 may perform intra-prediction coding of the current video block in relation to one or more neighboring blocks in the same frame as the current block to be encoded to provide spatial prediction. Motion estimation unit 42 and motion compensation unit 44 within prediction processing unit 41 may perform inter-prediction coding of the current video block in relation to one or more prediction blocks in one or more reference frames to provide temporal prediction. Video encoder 20 may perform multiple encoding passes, for example, to select an appropriate coding mode for each block of video data.

[0060] In some embodiments, the motion estimation unit 42 determines the inter-prediction mode for the current video frame by generating a motion vector according to a predetermined pattern within the sequence of video frames, the motion vector indicating the displacement of a video block within the current video frame relative to a prediction block within a reference video frame. Motion estimation performed by the motion estimation unit 42 is the process of generating a motion vector that estimates the motion for a video block. For example, a motion vector may indicate the displacement of a video block within a current video frame or picture relative to a prediction block within a reference frame associated with a current block being encoded within the current frame. The predetermined pattern may designate a video frame in a sequence as a P frame or a B frame. The intra BC unit 48 may determine a vector (e.g., a block vector) for intra BC coding in a manner similar to the motion vector determined by the motion estimation unit 42 for inter prediction, or may utilize the motion estimation unit 42 to determine the block vector.

[0061] In terms of pixel differences, the prediction block for the video block may be or may correspond to a block or reference block of a reference frame that is considered to closely match the video block to be encoded, and the pixel differences may be determined by the sum of absolute differences (SAD), the sum of squared differences (SSD), or other difference metrics. In some embodiments, the video encoder 20 may calculate values ​​for sub-integer pixel positions of the reference frames stored in the DPB 64. For example, the video encoder 20 may interpolate values ​​for quarter-pixel positions, one-eighth pixel positions, or other fractional pixel positions of the reference frame. Thus, the motion estimation unit 42 may perform a motion search relative to full pixel positions and fractional pixel positions and output a motion vector with fractional pixel accuracy.

[0062] Motion estimation unit 42 calculates a motion vector for a video block in an inter-prediction coded frame by comparing the position of the video block to the position of a prediction block of a reference frame selected from a first reference frame list (list 0) or a second reference frame list (list 1), each of which identifies one or more reference frames stored in DPB 64. Motion estimation unit 42 sends the calculated motion vector to motion compensation unit 44 and then to entropy encoding unit 56.

[0063] The motion compensation performed by the motion compensation unit 44 may involve obtaining or generating a prediction block based on the motion vector determined by the motion estimation unit 42. After receiving the motion vector for the current video block, the motion compensation unit 44 may locate the prediction block pointed to by the motion vector in one of the reference frame lists, retrieve the prediction block from the DPB 64, and forward the prediction block to the adder 50. The adder 50 then forms a residual video block of pixel difference values ​​by subtracting the pixel values ​​of the prediction block provided by the motion compensation unit 44 from the pixel values ​​of the current video block being encoded. The pixel difference values ​​forming the residual video block may include a luminance difference component or a chrominance difference component or both. The motion compensation unit 44 may also generate syntax elements associated with the video block of the video frame for use by the video decoder 30 when decoding the video block of the video frame. The syntax elements may include, for example, syntax elements defining a motion vector for identifying a prediction block, any flag indicating a prediction mode, or any other syntax information described herein. It should be noted that the motion estimation unit 42 and the motion compensation unit 44 may be highly integrated, but are shown separately for conceptual purposes.

[0064] In some embodiments, the intra BC unit 48 may generate vectors and obtain prediction blocks in a manner similar to that described above in conjunction with the motion estimation unit 42 and the motion compensation unit 44, but these prediction blocks are in the same frame as the current block being encoded, and these vectors are referred to as block vectors rather than motion vectors. Specifically, the intra BC unit 48 may determine the intra prediction mode to be used to encode the current block. In some examples, the intra BC unit 48 may encode the current block using various intra prediction modes, for example, during separate encoding passes, and test their performance through rate-distortion analysis. Next, the intra BC unit 48 may select a suitable intra prediction mode to use among the various tested intra prediction modes and generate an intra mode indicator accordingly. For example, the intra BC unit 48 may calculate rate-distortion values ​​for the various tested intra prediction modes using rate-distortion analysis, and select an intra prediction mode with optimized rate-distortion characteristics as a suitable intra prediction mode to use among the tested modes. The rate-distortion analysis generally determines the amount of distortion (or error) between a coded block and the original uncoded block that was encoded to produce the coded block, as well as the bit rate (i.e., the number of bits) used to produce the coded block. Intra BC unit 48 may calculate ratios based on the distortion and rates for the various coded blocks to determine which intra-prediction mode exhibits an optimal rate-distortion value for the block.

[0065] In other examples, intra BC unit 48 may use, in whole or in part, motion estimation unit 42 and motion compensation unit 44 to perform such functions for intra BC prediction in accordance with embodiments described herein. In either case, for intra block copying, the prediction block may be a block that is considered to closely match the block to be encoded in terms of pixel differences, which may be determined by SAD, SSD, or other difference metrics, and identifying the prediction block may include calculating values ​​for sub-integer pixel positions.

[0066] Regardless of whether the prediction block is from the same frame according to intra-frame prediction or from a different frame according to inter-frame prediction, video encoder 20 can form a residual video block by subtracting the pixel values ​​of the prediction block from the pixel values ​​of the current video block being encoded. The pixel difference values ​​forming the residual video block may include both luma component differences and chroma component differences.

[0067] As an alternative to the inter-frame prediction performed by the motion estimation unit 42 and the motion compensation unit 44 or the intra-frame block copy prediction performed by the intra BC unit 48 as described above, the intra-frame prediction processing unit 46 can perform intra-frame prediction on the current video block. Specifically, the intra-frame prediction processing unit 46 can determine the intra-frame prediction mode for encoding the current block. To this end, the intra-frame prediction processing unit 46 can use various intra-frame prediction modes to encode the current block, for example, during separate encoding passes, and the intra-frame prediction processing unit 46 (or in some examples, the mode selection unit) can select a suitable intra-frame prediction mode from the tested intra-frame prediction modes to use. The intra-frame prediction processing unit 46 can provide information indicating the intra-frame prediction mode selected for the block to the entropy coding unit 56. The entropy coding unit 56 can encode the information indicating the selected intra-frame prediction mode into the bitstream.

[0068] After prediction processing unit 41 determines a prediction block for the current video block via inter-prediction or intra-prediction, adder 50 forms a residual video block by subtracting the prediction block from the current video block. The residual video data in the residual block may be included in one or more TUs and provided to transform processing unit 52. Transform processing unit 52 transforms the residual video data into residual transform coefficients using a transform (e.g., a discrete cosine transform (DCT) or a conceptually similar transform).

[0069] Transform processing unit 52 may send the resulting transform coefficients to quantization unit 54. Quantization unit 54 quantizes the transform coefficients to further reduce the bit rate. The quantization process may also reduce the bit depth associated with some or all of the coefficients. The degree of quantization may be modified by adjusting a quantization parameter. In some examples, quantization unit 54 may then perform a scan on the matrix including the quantized transform coefficients. Alternatively, entropy encoding unit 56 may perform the scan.

[0070] After quantization, entropy coding unit 56 entropy encodes the quantized transform coefficients into a video bitstream using, for example, context adaptive variable length coding (CAVLC), context adaptive binary arithmetic coding (CABAC), syntax-based context adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or another entropy coding method or technique. The encoded bitstream may then be sent to a video bitstream such as a Figure 1 A video decoder 30, or archived in Figure 1 A for later transmission to or retrieval by the video decoder 30. The entropy encoding unit 56 may also entropy encode the motion vectors and other syntax elements for the current video frame being encoded.

[0071] Inverse quantization unit 58 and inverse transform processing unit 60 apply inverse quantization and inverse transform, respectively, to reconstruct the residual video block in the pixel domain for use in generating reference blocks for predicting other video blocks. As noted above, motion compensation unit 44 may generate a motion compensated prediction block from one or more reference blocks of a frame stored in DPB 64. Motion compensation unit 44 may also apply one or more interpolation filters to the prediction block to calculate sub-integer pixel values ​​for use in motion estimation.

[0072] Adder 62 adds the reconstructed residual block to the motion compensated prediction block generated by motion compensation unit 44 to generate a reference block for storage in DPB 64. The reference block may then be used as a prediction block by intra BC unit 48, motion estimation unit 42, and motion compensation unit 44 to inter-predict another video block in a subsequent video frame.

[0073] Figure 3 A is a block diagram showing an exemplary video decoder 30 according to some embodiments of the present application. The video decoder 30 includes a video data memory 79, an entropy decoding unit 80, a prediction processing unit 81, an inverse quantization unit 86, an inverse transform processing unit 88, an adder 90, and a DPB 92. The prediction processing unit 81 further includes a motion compensation unit 82, an intra-frame prediction unit 84, and an intra-frame BC unit 85. The video decoder 30 may perform the above-mentioned Figure 2 A is a decoding process that is substantially the inverse of the encoding process described with respect to video encoder 20. For example, motion compensation unit 82 may generate prediction data based on motion vectors received from entropy decoding unit 80, and intra-prediction unit 84 may generate prediction data based on intra-prediction mode indicators received from entropy decoding unit 80.

[0074] In some examples, units of the video decoder 30 may be tasked to perform embodiments of the present application. In addition, in some examples, embodiments of the present disclosure may be dispersed in one or more of the units of the video decoder 30. For example, the intra BC unit 85 may perform embodiments of the present application alone or in combination with other units of the video decoder 30 (e.g., the motion compensation unit 82, the intra prediction unit 84, and the entropy decoding unit 80). In some examples, the video decoder 30 may not include the intra BC unit 85, and the functions of the intra BC unit 85 may be performed by other components of the prediction processing unit 81 (e.g., the motion compensation unit 82).

[0075] The video data memory 79 may store video data, such as an encoded video bitstream, to be decoded by other components of the video decoder 30. The video data stored in the video data memory 79 may be obtained, for example, from the storage device 32, from a local video source (e.g., a camera), via a wired or wireless network communication of video data, or by accessing a physical data storage medium (e.g., a flash drive or hard disk). The video data memory 79 may include a coded picture buffer (CPB) that stores encoded video data from an encoded video bitstream. The DPB 92 of the video decoder 30 stores reference video data for use by the video decoder 30 when decoding the video data (e.g., in intra-frame or inter-frame prediction coding mode). The video data memory 79 and the DPB 92 may be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM) (including synchronous DRAM (SDRAM)), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. For illustrative purposes, the video data memory 79 and the DPB 92 are shown in FIG. Figure 3 A is depicted as two different components of the video decoder 30. However, it will be apparent to those skilled in the art that the video data memory 79 and the DPB 92 can be provided by the same memory device or a separate memory device. In some examples, the video data memory 79 can be on-chip with other components of the video decoder 30, or off-chip relative to those components.

[0076] During the decoding process, the video decoder 30 receives an encoded video bitstream representing video blocks of an encoded video frame and associated syntax elements. The video decoder 30 may receive syntax elements at the video frame level and / or the video block level. The entropy decoding unit 80 of the video decoder 30 entropy decodes the bitstream to generate quantization coefficients, motion vectors or intra-frame prediction mode indicators, and other syntax elements. The entropy decoding unit 80 then forwards the motion vectors or intra-frame prediction mode indicators, and other syntax elements to the prediction processing unit 81.

[0077] When a video frame is encoded as an intra-prediction coded (I) frame or for intra-coded prediction blocks in other types of frames, the intra-prediction unit 84 of the prediction processing unit 81 can generate prediction data for a video block of the current video frame based on the intra-prediction mode transmitted by the signal and reference data from a previously decoded block of the current frame.

[0078] When the video frame is encoded as an inter-frame prediction coding (i.e., B or P) frame, the motion compensation unit 82 of the prediction processing unit 81 generates one or more prediction blocks for the video block of the current video frame based on the motion vector and other syntax elements received from the entropy decoding unit 80. Each of the prediction blocks can be generated from a reference frame in one of the reference frame lists. The video decoder 30 can construct the reference frame lists, i.e., List 0 and List 1, based on the reference frames stored in the DPB 92 using a default construction technique.

[0079] In some examples, when the video block is encoded according to the intra BC mode described herein, intra BC unit 85 of prediction processing unit 81 generates a prediction block for the current video block based on the block vector and other syntax elements received from entropy decoding unit 80. The prediction block may be within a reconstructed region of the same picture as the current video block as defined by video encoder 20.

[0080] The motion compensation unit 82 and / or the intra BC unit 85 determine prediction information for a video block of the current video frame by parsing the motion vector and other syntax elements, and then use the prediction information to generate a prediction block for the current video block being decoded. For example, the motion compensation unit 82 uses some of the received syntax elements to determine a prediction mode (e.g., intra prediction or inter prediction) for encoding a video block of a video frame, an inter prediction frame type (e.g., B or P), construction information for one or more of a reference frame list for a frame, a motion vector for each inter prediction encoded video block of a frame, an inter prediction state for each inter prediction encoded video block of a frame, and other information for decoding a video block in the current video frame.

[0081] Similarly, the intra BC unit 85 may use some of the received syntax elements, such as flags, to determine whether the current video block is predicted using intra BC mode, construction information of which video blocks of the frame are within the reconstruction region and should be stored in the DPB 92, block vectors for each intra BC predicted video block of the frame, intra BC prediction status for each intra BC predicted video block of the frame, and other information for decoding the video blocks in the current video frame.

[0082] Motion compensation unit 82 may also perform interpolation using interpolation filters as used by video encoder 20 during encoding of the video blocks to calculate interpolated values ​​for sub-integer pixels of reference blocks. In this case, motion compensation unit 82 may determine the interpolation filters used by video encoder 20 based on the received syntax elements and use these interpolation filters to produce the prediction blocks.

[0083] Inverse quantization unit 86 inverse quantizes the quantized transform coefficients provided in the bitstream and entropy decoded by entropy decoding unit 80, using the same quantization parameters calculated by video encoder 20 for each video block in the video frame to determine the degree of quantization. Inverse transform processing unit 88 applies an inverse transform (e.g., an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process) to the transform coefficients to reconstruct the residual block in the pixel domain.

[0084] After the motion compensation unit 82 or the intra BC unit 85 generates a prediction block for the current video block based on the vector and other syntax elements, the adder 90 reconstructs the decoded video block for the current video block by adding the residual block from the inverse transform processing unit 88 to the corresponding prediction block generated by the motion compensation unit 82 and the intra BC unit 85. A loop filter 91 (e.g., a deblocking filter, an SAO filter, and / or an ALF) may be located between the adder 90 and the DPB 92 to further process the decoded video block. In some examples, the loop filter 91 may be omitted, and the decoded video block may be provided directly to the DPB 92 by the adder 90. The decoded video blocks in a given frame are then stored in the DPB 92, which stores reference frames for subsequent motion compensation of the next video block. The DPB 92 or a memory device separate from the DPB 92 may also store the decoded video for later presentation on a display device (e.g., Figure 1 on a display device 34).

[0085] In a typical video encoding and decoding process, a video sequence usually includes an ordered set of frames or pictures. Each frame may include three sample arrays, denoted as SL, SCb, and SCr. SL is a two-dimensional array of luma samples. SCb is a two-dimensional array of Cb chroma samples. SCr is a two-dimensional array of Cr chroma samples. In other examples, a frame may be monochrome and therefore include only a two-dimensional array of luma samples.

[0086] like Figure 4AAs shown in , the video encoder 20 (or more specifically, the segmentation unit 45) generates an encoded representation of a frame by first segmenting the frame into a set of CTUs. A video frame may include an integer number of CTUs ordered consecutively from left to right and from top to bottom in a raster scan order. Each CTU is the largest logical coding unit, and the width and height of the CTU are signaled by the video encoder 20 in a sequence parameter set so that all CTUs in a video sequence have the same size, one of 128×128, 64×64, 32×32, and 16×16. It should be noted, however, that the present application is not necessarily limited to a particular size. As Figure 4B As shown in , each CTU may include one CTB for luma samples, two corresponding coding tree blocks for chroma samples, and syntax elements for encoding the samples of the coding tree blocks. The syntax elements describe the properties of different types of units of coding pixel blocks and how the video sequence can be reconstructed at the video decoder 30, including inter-frame prediction or intra-frame prediction, intra-frame prediction mode, motion vectors, and other parameters. In a monochrome picture or a picture with three separate color planes, a CTU may include a single coding tree block and syntax elements for encoding the samples of the coding tree block. The coding tree block may be an N×N block of samples.

[0087] To achieve better performance, the video encoder 20 may recursively perform tree partitioning, such as binary tree partitioning, ternary tree partitioning, quadtree partitioning, or a combination thereof, on the coding tree block of the CTU and divide the CTU into smaller CUs. Figure 4C As depicted in , a 64×64 CTU 400 is first divided into four smaller CUs, each CU having a block size of 32×32. Among the four smaller CUs, CU 410 and CU 420 are respectively divided into four CUs with a block size of 16×16. Two 16×16 CUs 430 and CU 440 are further divided into four CUs with a block size of 8×8. Figure 4D Depicted is a diagram showing Figure 4C The quadtree data structure of the final result of the partitioning process of the CTU 400 depicted in FIG. 4 corresponds to a CU of a corresponding size ranging from 32×32 to 8×8. Figure 4B Each CU may include a CB of luma samples and two corresponding coding blocks of chroma samples of the same size frame, and syntax elements for encoding the samples of the coding blocks. In a monochrome picture or a picture with three separate color planes, a CU may include a single coding block and syntax structures for encoding the samples of the coding block. It should be noted that Figure 4C and Figure 4DThe quadtree partitioning depicted in FIG is for illustrative purposes only, and a CTU can be split into multiple CUs based on quadtree partitioning / ternary tree partitioning / binary tree partitioning to adapt to changing local characteristics. In the multi-type tree structure, a CTU is partitioned according to the quadtree structure, and each quadtree leaf CU can be further partitioned according to the binary and ternary tree structures. Figure 4E As shown, there are five possible partitioning types for a coding block with width W and height H, namely, quadruple partitioning, horizontal binary partitioning, vertical binary partitioning, horizontal ternary partitioning, and vertical ternary partitioning.

[0088] In some embodiments, the video encoder 20 may further partition the coding block of the CU into one or more (M×N) PBs. A PB is a rectangular (square or non-square) sample block to which the same prediction (inter or intra) is applied. The PU of a CU may include a PB of luma samples, two corresponding PBs of chroma samples, and syntax elements for predicting the PBs. In a monochrome picture or a picture with three separate color planes, a PU may include a single PB and a syntax structure for predicting the PB. The video encoder 20 may generate a predicted luma block, a predicted Cb block, and a predicted Cr block for the luma PB, Cb PB, and Cr PB of each PU of the CU.

[0089] The video encoder 20 may use intra prediction or inter prediction to generate a prediction block for a PU. If the video encoder 20 uses intra prediction to generate a prediction block for a PU, the video encoder 20 may generate the prediction block for the PU based on decoded samples of a frame associated with the PU. If the video encoder 20 uses inter prediction to generate a prediction block for a PU, the video encoder 20 may generate the prediction block for the PU based on decoded samples of one or more frames other than the frame associated with the PU.

[0090] After the video encoder 20 generates the predicted luma block, predicted Cb block, and predicted Cr block for one or more PUs of a CU, the video encoder 20 may generate a luma residual block for the CU by subtracting the predicted luma block of the CU from the original luma coding block of the CU, so that each sample in the luma residual block of the CU indicates the difference between a luma sample in one of the predicted luma blocks of the CU and a corresponding sample in the original luma coding block of the CU. Similarly, the video encoder 20 may generate a Cb residual block and a Cr residual block for the CU, respectively, so that each sample in the Cb residual block of the CU indicates the difference between a Cb sample in one of the predicted Cb blocks of the CU and a corresponding sample in the original Cb coding block of the CU, and each sample in the Cr residual block of the CU may indicate the difference between a Cr sample in one of the predicted Cr blocks of the CU and a corresponding sample in the original Cr coding block of the CU.

[0091] In addition, if Figure 4CAs shown in , the video encoder 20 can use quadtree partitioning to decompose the luma residual block, Cb residual block and Cr residual block of the CU into one or more luma transform blocks, Cb transform blocks and Cr transform blocks, respectively. A transform block is a rectangular (square or non-square) sample block to which the same transform is applied. A TU of a CU may include a transform block of luma samples, two corresponding transform blocks of chroma samples, and syntax elements for transforming the transform block samples. Therefore, each TU of a CU may be associated with a luma transform block, a Cb transform block and a Cr transform block. In some examples, the luma transform block associated with a TU may be a sub-block of the luma residual block of the CU. The Cb transform block may be a sub-block of the Cb residual block of the CU. The Cr transform block may be a sub-block of the Cr residual block of the CU. In a monochrome picture or a picture with three separate color planes, a TU may include a single transform block and a syntax structure for transforming the samples of the transform block.

[0092] The video encoder 20 may apply one or more transforms to the luma transform block of the TU to generate a luma coefficient block for the TU. The coefficient block may be a two-dimensional array of transform coefficients. The transform coefficient may be a scalar. The video encoder 20 may apply one or more transforms to the Cb transform block of the TU to generate a Cb coefficient block for the TU. The video encoder 20 may apply one or more transforms to the Cr transform block of the TU to generate a Cr coefficient block for the TU.

[0093] After generating a coefficient block (e.g., a luma coefficient block, a Cb coefficient block, or a Cr coefficient block), the video encoder 20 may quantize the coefficient block. Quantization generally refers to a process in which transform coefficients are quantized to potentially reduce the amount of data used to represent the transform coefficients, thereby providing further compression. After the video encoder 20 quantizes the coefficient block, the video encoder 20 may entropy encode syntax elements indicating the quantized transform coefficients. For example, the video encoder 20 may perform CABAC on the syntax elements indicating the quantized transform coefficients. Finally, the video encoder 20 may output a bitstream including a sequence of bits that form a representation of an encoded frame and associated data, and the bitstream is stored in the storage device 32 or sent to the target device 14.

[0094] After receiving the bitstream generated by the video encoder 20, the video decoder 30 can parse the bitstream to obtain syntax elements from the bitstream. The video decoder 30 can reconstruct a frame of video data based at least in part on the syntax elements obtained from the bitstream. The process of reconstructing video data is generally inverse to the encoding process performed by the video encoder 20. For example, the video decoder 30 can perform an inverse transform on the coefficient block associated with the TU of the current CU to reconstruct the residual block associated with the TU of the current CU. The video decoder 30 also reconstructs the coding block of the current CU by adding the samples of the prediction block for the PU of the current CU to the corresponding samples of the transform block of the TU of the current CU. After reconstructing the coding block for each CU of the frame, the video decoder 30 can reconstruct the frame.

[0095] As mentioned above, video coding mainly uses two modes, namely, intra-frame prediction (or intra-frame prediction) and inter-frame prediction (or inter-frame prediction) to achieve video compression. It should be noted that IBC can be regarded as intra-frame prediction or a third mode. Between the two modes, inter-frame prediction contributes more to coding efficiency than intra-frame prediction because motion vectors are used to predict the current video block based on the reference video block.

[0096] But with the ever-improving video data capture technology and finer video block sizes for retaining details in the video data, the amount of data required to represent the motion vector for the current frame has also increased significantly. One way to overcome this challenge benefits from the fact that not only a set of neighboring CUs in both the spatial and temporal domains have similar video data for prediction purposes, but also the motion vectors between these neighboring CUs are similar. Therefore, the motion information of spatially neighboring CUs and / or temporally co-located CUs can be used as an approximation of the motion information (e.g., motion vector) of the current CU (which is also called the "motion vector predictor" (MVP) of the current CU) by exploring their spatial and temporal correlations.

[0097] Instead of combining as above Figure 2 The actual motion vector of the current CU determined by the motion estimation unit 42 is encoded into the video bitstream as described in A, and the motion vector prediction value of the current CU is subtracted from the actual motion vector of the current CU to generate a motion vector difference (MVD) for the current CU. By doing so, the motion vector determined by the motion estimation unit 42 for each CU of the frame does not need to be encoded into the video bitstream, and the amount of data used to represent the motion information in the video bitstream can be significantly reduced.

[0098] Similar to the process of selecting a prediction block in a reference frame during inter-frame prediction of a coding block, both the video encoder 20 and the video decoder 30 need to adopt a set of rules for constructing a motion vector candidate list (also called a "merge list") for the current CU using those potential candidate motion vectors associated with the spatial neighboring CUs and / or temporal co-located CUs of the current CU, and then selecting a member from the motion vector candidate list as the motion vector prediction value for the current CU. By doing so, the motion vector candidate list itself does not need to be sent from the video encoder 20 to the video decoder 30, and the index of the selected motion vector prediction value within the motion vector candidate list is sufficient for the video encoder 20 and the video decoder 30 to use the same motion vector prediction value within the motion vector candidate list to encode and decode the current CU.

[0099] As explained in further detail herein, the discrete cosine transform (DCT) is extended to include the concept of a general fractional DCT. This extension allows the derivation of transform matrices with a wide range of different fractional values. Instead of constraining the transform kernel to an integer value, fractional values ​​can be used to determine the transform process. This allows a more accurate representation of the data and enables the derivation of a variety of transform matrices, each of which is suitable for a specific type of signal or image content.

[0100] In this disclosure, DCT is extended to a general fractional DCT. Assume C α is a linear operator that maps an N-dimensional vector s to another N-dimensional vector S given a fraction α. α =C α s. If the following conditions are met: (1) C α Satisfy DCT condition C1=C; (2) C α Additive C α+β =C α C β ; (3) C α In for all Both is true in the sense that C α is defined as the FRDCT operator.

[0101] It is obvious that the real power of the DCT matrix C can be used as the FRDCT operator, that is, C α =C α To obtain the real power of the DCT matrix, consider the eigenvalue decomposition. The fact that the DCT matrix is ​​a unitary matrix ensures that C has N eigenvectors u n An orthogonal set of ) and the corresponding eigenvalue λ n is located on the unit circle, that is, is a real number. Therefore, C can be decomposed in the following form:

[0102]

[0103] Among them U n Is a u n As its columns, Λ is a unitary matrix with diagonal entries λ n is a diagonal matrix, and is a unitary matrix with the following properties.

[0104] U m U n =δ mn U m as well as

[0105] In the present disclosure, eigenvalue decomposition is used to decompose the eigenvalue by using its αth power To replace the eigenvalue (That is, using its αth power Λ α Substituting the matrix Λ) to derive the FRDCT matrix. Then, the FRDCT matrix can be written in the following form that satisfies both the DCT condition and is additive.

[0106] C α =UΛ α U *

[0107] In defining the FRDCT matrix C for any sequence s α Afterwards, the corresponding FRDCTS with fraction α can be calculated α .

[0108] S α =C α s

[0109] By additivity, we have C -α C α = C0 = I, so that by using the matrix C -α , and obtain the inverse FRDCT, namely

[0110] s=C -α S α

[0111] Some typical FRDCT matrices with different parameters are provided in Tables 1 and 2 below, as examples of FRDCT matrices, including 4x4 (Table 1) and 8x8 FRDCT (Table 2) matrices. It should be noted that more FRDCT matrices with different sizes and α parameters can be derived from the above equations in a similar manner.

[0112]

[0113] Table 1

[0114]

[0115]

[0116] Table 2

[0117] In existing VVC and ECM designs, multi-level transform skip (MTS) is adopted in the main transform process. A specific MTS coding unit (CU) flag is used to indicate whether MTS should be applied. If the MTS CU flag is set to 0, conventional DCT2 is applied to both horizontal and vertical directions, which represents the default behavior. However, if the MTS CU flag is set to 1, MTS is used, and specific transform types for horizontal and vertical directions are signaled separately.

[0118] To control the use of FRDCT, similar to the MTS scheme, separate enable flags are specified at the sequence parameter set (SPS) level for intra prediction and inter prediction, respectively. When FRDCT is enabled in the SPS, a CU level flag indicating whether FRDCT should be applied to the current CU is signaled.

[0119] The application of the FRDCT can be specific to the luma (Y) component, the chroma (U and V) components, or both the luma and chroma components, allowing flexibility in the transform process based on the characteristics of different video content. However, there are specific conditions where FRDCT signaling is skipped and the conventional (discrete cosine transform) DCT2 is used instead. These conditions are as follows: (i) if the position of the last significant coefficient of the luma transform block (TB) is less than 1, indicating that only DC coefficients are present in the block; and (2) if the last significant coefficient of the luma TB is located within the MTS zeroing region, which is the region outside the low-frequency non-significant transform (LFNST) region where the primary transform coefficients are canonically zeroed during the MTS process. In both cases, the application of the FRDCT is avoided to prevent unnecessary computations and ensure that the transform process is optimized for the specific characteristics of the coding block.

[0120] If the FRDCT CU flag is set to zero, indicating that FRDCT is not applied, conventional DCT2 is used for both horizontal and vertical directions.

[0121] By employing these enabling flags and conditional checks, a video codec can effectively control the use of the FRDCT, selectively applying the FRDCT when it is beneficial and falling back to the conventional DCT2 in other cases. This adaptability allows for improved compression efficiency and better preservation of video quality in a variety of codec scenarios.

[0122] (A) Replace MTS with FRDCT

[0123] In example (A)(I-III), the existing MTS CU flag is replaced by the FRDCT CU flag. The FRDCT CU flag is introduced to indicate whether the FRDCT should be used for a particular CU. Typical codec schemes use the MTS CU flag to indicate whether the encoder should apply MTS to the main transform of a particular CU. The proposed method introduces a new FRDCT CU flag, which indicates whether the encoder intends to apply FRDCT in the main transform process (for example, if the FRDCT CU flag is set to 1, the encoder intends to apply FRDCT in the main transform process for the particular CU, or if the FRDCT CU flag is set to 0, the encoder will not apply FRDCT for the CU). Therefore, the introduction of the FRDCT CU flag provides greater flexibility and control over the transform process at the CU. By independently signaling the FRDCT CU flag for each CU, the encoder can adapt the transform scheme based on the specific characteristics and codec requirements of each CU. This allows for the effective use of both MTS and FRDCT, thereby optimizing compression efficiency and video quality for different codec scenarios.

[0124] Figure 5 is an example of a method 500 in which an MTS is replaced by an FRDCT when an FRDCT CU flag is set to 1. The method 500 includes: generating, by an encoder, an enable flag at a sequence parameter set (SPS) level for an intra coding mode and an inter coding mode, the enable flag indicating whether FRDCT is enabled for at least one mode; generating, by an encoder, an FRDCT CU level flag for indicating whether an FRDCT transform is applied to a CU; in response to determining that an FRDCT transform is applied to a CU, obtaining a flag indicating one of the following: (i) a horizontal vector and a vertical vector share an FRDCT transform matrix, or (ii) a horizontal vector and a vertical vector use separate FRDCY transform matrices, performing rate-distortion optimization, and selecting optimization parameters. By using an FRDCT CU flag to indicate whether an FRDCT should be applied to a particular CU and sharing the same FRDCT parameters for both a horizontal FRDCT transform and a vertical FRDCT transform, a video codec implements efficient transform selection and enhances compression performance and video quality for a particular codec sequence.

[0125] At step 505, the method 500 includes generating, by the encoder, an enable flag at a sequence parameter set (SPS) level for an intra coding mode and an inter coding mode, the enable flag indicating whether FRDCT is enabled for at least one mode. At step 510, the method 500 includes generating, by the encoder, an FRDCT CU level flag for indicating whether FRDCT transform is applied to the CU.

[0126] At step 515, in response to determining that the FRDCT transform is applied to the CU (e.g., determining that the FRDCT CU flag is set to 1), a flag indicating one of the following is obtained: (i) the horizontal vector and the vertical vector share the FRDCT transform matrix, or (ii) the horizontal vector and the vertical vector use separate FRDCT transform matrices. For example, when the FRDCT CU flag is set to a first signal (indicating that FRDCT is enabled), the encoder and the decoder use separate FRDCT parameters for horizontal FRDCT transform and vertical FRDCT transform. For example, when the FRDCT CU flag is set to a second signal (indicating that FRDCT is enabled), the encoder and the decoder share the same FRDCT parameter α for horizontal FRDCT transform and vertical FRDCT transform.

[0127] At step 520, method 500 includes performing rate-distortion optimization. By performing rate-distortion optimization, the encoder can adapt the transform process to the specific characteristics of each CU, thereby ensuring that the optimized transform parameters at step 525 can be used to determine the balance between compression efficiency and video quality. In one example, rate-distortion optimization includes checking K FRDCT parameters for each CU at the encoder side.

[0128] At step 525, method 500 includes selecting optimization parameters that optimize compression efficiency and video quality for each CU. In one example, the encoder selects FRDCT parameters that provide an optimal balance between compression efficiency and video quality. The encoder can use any type of standard or metric to determine the optimization parameters that optimize compression efficiency and video quality for each CU.

[0129] At step 530, method 500 includes generating a signal index of optimized FRDCT parameters. The index of the optimized FRDCT parameters is signaled in the bitstream to ensure that the decoder has selected the optimized parameters for the FRDCT. The decoder uses this information from the bitstream to correctly apply the specified horizontal FRDCT transform and vertical FRDCT transform during the decoding process for each CU.

[0130] For example, in addition to DCT2, 8 FRDCT transforms are defined. The transform index is binarized in the following table. In this example, in addition to traditional DCT2, 8 FRDCT transforms are defined. Each FRDCT transform is assigned a unique index ranging from 0 to 7. In order to effectively represent these indexes in the bit stream, 4 bits are used to represent them and binarize them. The binarized transform index for this example is provided in Table 3 below.

[0131]

[0132] Table 3

[0133] By using binarized transform indices, the bitstream can efficiently convey the necessary information about the selected FRDCT transform for each CU, minimizing overhead and allowing more efficient video encoding and decoding. The decoder can then accurately apply the appropriate FRDCT transform during the decoding process, ensuring efficient compression and high-quality video reconstruction.

[0134] Figure 6 is an example of method 600, wherein the encoder determines whether a horizontal vector and a vertical vector share an FRDCT transform matrix or use separate FRDCT transform matrices. Method 600 includes: generating, by the encoder, an enable flag at a sequence parameter set (SPS) level for an intra-frame coding mode and an inter-frame coding mode, the enable flag indicating whether a fractional discrete cosine transform is enabled for at least one mode; in response to FRDCT being enabled at the SPSP level, generating, by the encoder, an FRDCT CU-level flag for indicating whether an FRDCT transform is applied to a coding unit (CU); in response to determining that an FRDCT transform is applied to a CU, determining that the CU includes one of the following: (i) a horizontal vector and a vertical vector that share an FRDCT transform matrix; or (ii) a horizontal vector and a vertical vector that use separate FRDCT transform matrices; performing rate-distortion optimization; selecting optimization parameters; and generating an index of the optimization parameters.

[0135] At step 605, the method 600 includes: generating, by the encoder, an enable flag at a sequence parameter set (SPS) level for an intra coding mode and an inter coding mode, the enable flag indicating whether fractional discrete cosine transform is enabled for at least one mode;

[0136] At step 610, method 600 includes: in response to FRDCT being enabled at the SPSP level, generating, by the encoder, an FRDCT CU level flag indicating whether the FRDCT transform is applied to a coding unit (CU). In one example, upon receiving the FRDCT CU flag, the encoder checks the value of the FRDCT CU flag to determine whether to apply the FRDCT CU flag (e.g., if the FRDCT CU flag is equal to 1, the FRDCT should be used for the CU, and the encoder will apply the selected optimized FRDCT parameters according to step 625. If the FRDCT CU flag is equal to 0, the CU should not use the FRDCT). In one example, the decoder can receive and check the FRDCT CU flag, and determine whether to apply the same selected optimized FRDCT parameters as in the above example.

[0137] At step 615, method 660 includes, in response to determining that the FRDCT transform is applied to the CU, determining that the CU includes one of the following: (i) a horizontal vector and a vertical vector that share an FRDCT transform matrix; or (ii) a horizontal vector and a vertical vector that use separate FRDCT transform matrices. For example, when the FRDCT CU flag is set to a first signal (indicating that FRDCT is enabled), the encoder and decoder use separate FRDCT parameters for horizontal FRDCT transform and vertical FRDCT transform. For example, when the FRDCT CU flag is set to a second signal (indicating that FRDCT is enabled), the encoder and decoder share the same FRDCT parameter α for horizontal FRDCT transform and vertical FRDCT transform.

[0138] At step 620, method 600 includes performing rate-distortion optimization at the encoder. At the encoder side of each CU, K horizontal FRDCT parameters and M vertical FRDCT parameters are checked based on rate-distortion optimization. The optimization process aims to find the optimal parameters that maximize compression efficiency while maintaining video quality.

[0139] At step 625, method 600 includes selecting optimized parameters. Optimized horizontal FRDCT parameters and optimized vertical FRDCT parameters are selected for each CU that produce optimized compression efficiency and video quality.

[0140] At step 630, method 600 includes generating indices of optimized parameters. Indices of optimized horizontal and vertical FRDCT parameters are signaled in the bitstream, indicating parameters used for horizontal and vertical FRDCT transforms, respectively.

[0141] For example, Table 4 below provides an example binarization of transform types in this embodiment. In this example, a 1FRDCT transform is defined in addition to DCT2, ie, {DCT2, FRDCT} for both horizontal and vertical transforms.

[0142]

[0143] Table 4

[0144] (I) Intra-mode related FRDCT

[0145] Figure 7 is an example of a method 700 for defining FRDCT parameter sets according to intra-modes (i.e., different parameter sets for different intra-modes). The proposed intra-mode dependent FRDCT sets can be applied to all the examples discussed above. For example, (at step 705A), if the horizontal FRDCT vector and the vertical FRDCT vector share a transform, then for each intra-mode i, the FRDCT parameters are defined as Where K i is the number of FRDCT transforms (step 710A). For example, (at step 705B) if the horizontal FRDCT vector and the vertical FRDCT vector use separate transforms, then for each intra mode i, the horizontal FRDCT parameters and the vertical FRDCT parameters are defined as and Where K i and M i are the number of horizontal FRDCT transforms and vertical FRDCT transforms for intra mode i, respectively (at step 710B).

[0146] For example, in one aspect, the method for video encoding may include: generating, by an encoder, an enable flag at a first level for at least one of an intra-coding mode and an inter-coding mode, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for the at least one mode. In response to enabling FRDCT at the first level, generating, by the encoder, a second flag at a coding unit (CU) level for indicating whether the FRDCT transform is applied to the CU, and determining a third flag based on the second flag, wherein the third flag indicates the use of at least one FRDCT transform matrix for a horizontal vector and a vertical vector. In one example, the first level includes an SPS level (e.g., a level that serves as an initial configuration for an encoder and a decoder).

[0147] For example, in one aspect, the encoder may generate an enable flag at a first level for different coding modes (e.g., intra-coding mode and inter-coding mode). The enable flag at the first level may be obtained / received by a decoder. If FRDCT is enabled at the first level for a particular coding mode, the encoder continues to generate a second flag at the CU level. Like the first flag, the second flag may be obtained / received by a decoder. Once the second flag is set at the CU level, the method may include generating a third flag at the encoder, the third flag indicating: (i) whether the horizontal FRDCT vector and the vertical FRDCT vector share the FRDCT transform matrix, or (ii) whether the horizontal vector and the vertical vector use separate FRDCT transform matrices.

[0148] (B) Using both FRDCT and MTS

[0149] In one example, both FRDCT and MTS are used in the main transform process. To accommodate this dual use, an additional FRDCT CU flag is introduced and signaled together with the existing MTS CU flag. The purpose of the FRDCT CU flag is to indicate whether FRDCT should be used for a particular CU, while the MTS CU flag continues to indicate whether MTS should be used. By signaling the FRDCT CU flag as well as the MTS CU flag, the video encoder can determine whether to use a combination of both FRDCT and MTS in the main transform for each CU. This provides the ability to adapt the transform scheme based on the characteristics of each CU, optimizing codec efficiency and video quality for different coding scenarios.

[0150] Figure 8 An example of a method 800 for using both FRDCT and MTS in a main transform process. The method 800 includes: generating an FRDCT CU flag and an MTS CU flag; in response to obtaining the FRDCT CU flag and the MTS CU flag, obtaining a flag indicating one of the following: (i) the horizontal vector and the vertical vector share the FRDCT transform matrix, or (ii) the horizontal vector uses a separate FRDCT transform matrix, performing rate-distortion optimization, selecting optimization parameters, and indexing the optimized FRDCT parameters. By sharing the same FRDCT parameters for both the horizontal FRDCT transform and the vertical FRDCT transform, the video codec ensures consistency in the transform process, thereby resulting in improved coding efficiency and video quality.

[0151] At step 805, the method 800 includes generating FRDCT CU flag and MTS CU flag. The FRDCT CU flag and MTS CU flag are generated for intra coding mode and inter coding mode at SPS level, and the enable flag indicates whether FRDCT and MTS are enabled for at least one mode.

[0152] At step 810, the method includes, in response to obtaining the FRDCT CU flag and the MTS CU flag, obtaining a flag indicating one of the following: (i) the horizontal vector and the vertical vector share the FRDCT transform matrix, or (ii) the horizontal vector and the vertical vector use a separate FRDCT transform matrix. During the encoding process, the encoder checks the values ​​of the FRDCT CU flag and the MTS CU flag for each CU. Based on the value of the FRDCT CU flag, the encoder determines whether to proceed with steps 810-830. For example: if both the FRDCT CU flag and the MTS CU flag are set to the first signal, the encoder can use both FRDCT and MTS depending on the specific method of the application; if both the FRDCT CU flag and the MTS CU flag are set to the second signal, the encoder can select different transformation methods based on the video coding scheme. In response to obtaining the FRDCT CU flag and the MTS CU flag, the encoder obtains a flag indicating that the horizontal vector and the vertical vector share or use a separate FRDCT transform matrix. It should be noted that the decoder can also be configured to obtain / receive the flags herein, and to perform the methods and steps disclosed herein.

[0153] At step 815, the encoder checks the FRDCT parameters of each coding unit for rate-distortion optimization. Rate-distortion optimization is used to determine the optimized parameters that maximize compression efficiency while maintaining video quality. In one example, a set of FRDCT parameters is considered for each CU.

[0154] At step 820, the encoder determines the optimized FRDCT parameters that produce an optimal trade-off between compression efficiency and video quality for each CU. By determining the optimized FRDCT parameters for each CU, the encoder can adapt the transformation process to the characteristics of each CU. This can lead to higher encoding and decoding efficiency and improved video quality.

[0155] At step 825, the method includes indexing the optimized FRDCT parameters. When both the MTS CU flag and the FRDCT flag are equal to 1 (indicating that both MTS and FRDCT are in use), the index of the optimized FRDCT parameters is signaled in the bitstream. The index points to the selected parameters in the FRDCT parameter set. For example, as shown in Table 5, 8 FRDCT transforms are defined in addition to DCT2, and the FRDCT transform is binarized.

[0156]

[0157] Table 5

[0158] Fig. 9is an example of method 900, in which, in response to obtaining an FRDCT CU flag and an MTS CU flag, the following are determined: (i) the horizontal FRDCT vector and the vertical FRDCT vector share an FRDCT transform matrix, or (ii) the horizontal vector and the vertical vector use separate FRDCT transform matrices. Method 900 includes: determining: the horizontal FRDCT vector and the vertical FRDCT vector share or use separate FRDCT transform matrices; performing rate-distortion optimization; selecting optimization parameters; and indexing optimized horizontal FRDCT parameters and vertical FRDCT parameters. By using separate FRDCT parameters for horizontal transforms and vertical transforms, the video codec can adapt the transform process independently for each direction, which potentially leads to improved compression efficiency and higher video quality in various coding scenarios.

[0159] At step 905, method 900 includes, in response to obtaining the FRDCT CU flag and the MTS CU flag, determining the following: (i) the horizontal FRDCT vector and the vertical FRDCT vector share the FRDCT transform matrix, or (ii) the horizontal vector and the vertical vector use separate FRDCT transform matrices. During the encoding process, the encoder checks the values ​​of the FRDCT CU flag and the MTS CU flag for each CU. Based on the value of the FRDCT CU flag, the encoder determines whether to proceed with steps 905-920.

[0160] At step 910, method 900 includes performing rate-distortion optimization. At the encoder side, horizontal FRDCT parameters and M vertical FRDCT parameters for each CU are checked based on rate-distortion optimization. The optimization process aims to find the optimal parameters that maximize compression efficiency while maintaining video quality.

[0161] At step 915, method 900 includes determining an optimized horizontal FRDCT parameter and an optimized vertical FRDCT parameter that produce optimized compression efficiency and video quality for each CU. For example, the encoder considers a set of horizontal FRDCT parameters and vertical FRDCT parameters, and selects horizontal FRCT parameters and vertical FRCT parameters that provide optimized improved coding efficiency and video quality.

[0162] At step 920, method 900 includes generating an index for optimizing horizontal FRDCT parameters and vertical FRDCT parameters. When both the MTS CU flag and the FRDCT CU flag include a first signal, the index of the optimized horizontal FRDCT parameters and vertical FRDCT parameters is signaled in the bitstream. The index points to the selected parameters in the corresponding horizontal FRDCT parameter set and vertical FRDCT parameter set. The decoder uses this information from the bitstream to correctly apply the specified horizontal FRDCT transform and vertical FRDCT transform during the decoding process for each CU.

[0163] For example, Table 6 below provides example binarization when a 1FRDCT transform defined in addition to DCT2 (ie, {DCT2, FRDCT}) is used for both horizontal and vertical transforms.

[0164]

[0165] Table 6

[0166] (I) Intra-mode dependent FRDCT

[0167] When using both MTS and FRDCT, the selection of FRDCT transform can also depend on the intra-frame mode of the coding block. The use of intra-frame mode is further optimized based on the characteristics of the coding block to select FRDCT transform. For example, the method may include a third flag indicating one of the following items in response to determining that the second flag indicates that the FRDCT transform is applied to the CU: (i) the horizontal vector and the vertical vector share the FRDCT transform matrix, or (ii) the horizontal vector and the vertical vector use a separate FRDCT transform matrix. In response to obtaining a third flag indicating that the horizontal vector and the vertical vector share the FRDCT transform matrix, the encoder determines the FRDCT transform parameters in response to the first intra-frame mode of the CU, wherein the same FRDCT transform matrix is ​​shared by the horizontal vector and the vertical vector. Alternatively or in addition, in response to obtaining a third flag indicating that the horizontal vector and the vertical vector use a separate FRDCT transform matrix, the encoder determines the FRDCT transform parameters in response to the second intra-frame mode of the CU, wherein the horizontal vector and the vertical vector use different FRDCT transform matrices. This determination can be sent to the decoder. For example, the decoder may be configured to receive / obtain FRDCT transform parameters in response to an intra mode of the CU, or to receive / obtain horizontal FRDCT transform parameters and vertical FRDCT transform parameters in response to an intra mode of the CU.

[0168] Fig.10is an example of a method 1000 in which FRDCT parameters are set for each intra-frame mode. In one example, the method includes: obtaining both an FRDCT CU flag and an MTS CU flag; in response to obtaining an FRDCT CU flag and an MTS CU flag indicating that FRDCT and MTS are enabled; determining an intra-frame mode; obtaining an FRDCT CU flag and an MTS CU flag, determining the following: (i) the horizontal FRDCT vector and the vertical FRDCT vector share an FRDCT transform matrix, or (ii) the horizontal vector and the vertical vector use separate FRDCT transform matrices; performing rate-distortion optimization and transform selection; selecting optimization parameters; and signaling the optimized FRDCT parameters. By using an intra-frame mode-dependent FRDCT set, a video codec can adapt the transform process based not only on the overall characteristics of the coding block (using MTS and FRDCT) but also on the specific coding mode used for intra-frame prediction. For example, in one aspect of the present disclosure, FRDCT parameters are defined according to the intra-frame mode (i.e., different parameters for different intra-frame modes) (e.g., for intra-frame mode i, the FRDCT parameter set is defined as Where K i is the number of FRDCT transforms in the set. For intra mode i, the horizontal FRDCT parameter set and the vertical FRDCT parameter set are defined as as well as Where K i and M i are the number of horizontal and vertical FRDCT transforms in the set for intra mode i, respectively. ).

[0169] At step 1005, method 1000 includes obtaining flags for both the FRDCT CU flag and the MTS CU flag. Based on the value of the FRDCT CU flag, the encoder determines whether to proceed with steps 1015-1025. At step 1010, method 1000 includes determining an intra mode.

[0170] At step 1010, method 1000 includes defining FRDCT parameters for each intra-mode. The number of parameters in each set and their values ​​may vary depending on the characteristics of the coding block in a particular intra-mode.

[0171] At step 1015, the method includes performing rate-distortion optimization and transform selection. For example, in this step, the encoder examines the FRDCT parameters and performs rate-distortion optimization. The optimization aims to find the optimal parameters that maximize compression efficiency while maintaining video quality for the intra mode.

[0172] At step 1020 , the method includes selecting optimized FRDCT parameters from an intra-mode-dependent FRDCT set for each CU and for each intra-mode based on the rate-distortion optimization result.

[0173] At step 1025, the method includes optimizing FRDCT parameters for each intra-mode index in the bitstream. For example, when both the MTS CU flag and the FRDCT flag are equal to 1 (indicating that both MTS and FRDCT are in use), the encoder signals the index of the optimized FRDCT parameters for each intra-mode related set in the bitstream. This allows the decoder to correctly apply the specified FRDCT transform with the selected parameters for each CU and each intra-mode during the decoding process.

[0174] Fig.11 A computing environment 1110 is shown coupled to a user interface 1150. The computing environment 1110 may be part of a data processing server. The computing environment 1110 includes a processor 1120, a memory 1130, and an input / output (I / O) interface 1140.

[0175] The processor 1120 generally controls the overall operation of the computing environment 1110, such as operations associated with display, data acquisition, data communication, and image processing. The processor 1120 may include one or more processors to execute instructions for performing all or some steps in the above-mentioned method. In addition, the processor 1120 may include one or more modules that facilitate the interaction between the processor 1120 and other components. The processor may be a central processing unit (CPU), a microprocessor, a single-chip machine, a graphics processing unit (GPU), etc.

[0176] The memory 1130 is configured to store various types of data to support the operation of the computing environment 1110. The memory 1130 may include predetermined software 1132. Examples of such data include instructions for any application or method operating on the computing environment 1110, video data sets, image data, etc. The memory 1130 may be implemented by using any type of volatile memory device or non-volatile memory device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0177] I / O interface 1140 provides an interface between processor 1120 and peripheral interface modules such as a keyboard, a click wheel, buttons, etc. Buttons may include, but are not limited to, a home button, a start scan button, and a stop scan button. I / O interface 1140 may be coupled to an encoder and a decoder.

[0178] In one embodiment, a non-transitory computer-readable storage medium is also provided, which includes multiple programs, for example, the multiple programs are in the memory 1130 and can be executed by the processor 1120 in the computing environment 1110 to perform the above method. Alternatively, the non-transitory computer-readable storage medium may have a bit stream or data stream stored therein, the bit stream or data stream including the bit stream or data stream generated by the encoder (for example, Figure 2 The video encoder 20 in FIG. 1 uses a decoder (eg, Figure 3 The non-transitory computer-readable storage medium may be, for example, a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0179] In one embodiment, a computing device is also provided, which includes one or more processors (e.g., processor 1120); and a non-temporary computer-readable storage medium or memory 1130 has stored therein a plurality of programs executable by the one or more processors, wherein the one or more processors are configured to perform the above-mentioned method when executing the plurality of programs.

[0180] In one embodiment, a computer program product is also provided, which includes multiple programs, for example, the multiple programs are in the memory 1130 and can be executed by the processor 1120 in the computing environment 1110 to perform the above method. For example, the computer program product may include a non-transitory computer-readable storage medium.

[0181] In one embodiment, the computing environment 1110 may be implemented using one or more ASICs, DSPs, digital signal processing devices (DSPDs), programmable logic devices (PLDs), FPGAs, GPUs, controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0182] The description of the present disclosure has been presented for purposes of illustration and is not intended to be exhaustive or limiting of the present disclosure. Many modifications, variations, and alternative embodiments will be apparent to one of ordinary skill in the art having the benefit of the teachings presented in the foregoing description and the associated drawings.

[0183] Unless otherwise specifically shown, the order of steps of the method according to the present disclosure is intended to be illustrative only, and the steps of the method according to the present disclosure are not limited to the order specifically described above, but can be changed according to actual conditions. In addition, at least one step of the method according to the present disclosure can be adjusted, combined or deleted according to actual requirements.

[0184] The examples are chosen and described in order to explain the principles of the present disclosure and to enable other persons skilled in the art to understand the various embodiments of the present disclosure and to best utilize the basic principles and various embodiments with various modifications suitable for the specific use contemplated. Therefore, it should be understood that the scope of the present disclosure is not limited to the specific examples of the disclosed embodiments, and modifications and other embodiments are intended to be included within the scope of the present disclosure.

[0185] The above method can be implemented using an apparatus including one or more circuits, including an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor or other electronic components. The apparatus can use circuits in combination with other hardware or software components to perform the above method. Each module, submodule, unit or subunit disclosed above can be implemented at least in part using one or more circuits.

[0186] By considering the specification and practice of the present disclosure disclosed herein, other examples of the present disclosure will be apparent to those skilled in the art. This application is intended to cover any variation, use or adaptation of the present disclosure that follows the general principles of the present disclosure, and includes such deviations from the present disclosure as known in the art or within customary practice. This specification and examples are intended to be considered as exemplary only.

[0187] It will be understood that the present disclosure is not limited to the exact examples described above and shown in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A method for video encoding, comprising: generating, by an encoder for at least one of an intra coding mode and an inter coding mode, an enable flag at a first level, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for the at least one mode; In response to the FRDCT being enabled at the first level, generating, by the encoder, a second flag at a coding unit (CU) level for indicating whether an FRDCT transform is applied to a CU; as well as A third flag is determined based on the second flag, wherein the third flag indicates use of at least one FRDCT transform matrix for horizontal and vertical vectors.

2. The method for video encoding according to claim 1, wherein: The first level is the sequence parameter set (SPS) level.

3. The method for video encoding according to claim 2, wherein: Determining the third flag based on the second flag includes: In response to the second flag indicating that the FRDCT transform is applied to the CU, obtaining the third flag indicating one of the following: (i) The horizontal vector and the vertical vector share the same FRDCT transform matrix, or (ii) Separate FRDCT transform matrices are used for horizontal and vertical vectors.

4. The method for video encoding according to claim 3, further comprising: In response to determining that the horizontal vector and the vertical vector share the FRDCT transform matrix, performing rate-distortion optimization by the encoder to determine optimized FRDCT transform parameters; as well as The encoder encodes the index of the optimized FRDCT transform parameters into a video bitstream.

5. The method for video encoding according to claim 3, further comprising: In response to determining that the horizontal vector and the vertical vector use separate FRDCT transform matrices, performing rate-distortion optimization by the encoder to determine optimized horizontal FRDCT transform parameters and optimized vertical FRDCT transform parameters; and The encoder encodes the indexes of the optimized horizontal FRDCT parameters and the optimized vertical FRDCT transform parameters into a video bitstream.

6. The method for video encoding according to claim 3, further comprising: In response to determining that the horizontal vector and the vertical vector share the FRDCT transform matrix, FRDCT transform parameters are determined by the encoder.

7. The method for video encoding according to claim 3, further comprising: In response to determining that the horizontal vector and the vertical vector use separate FRDCT transform matrices, horizontal FRDCT transform parameters and vertical FRDCT transform parameters are determined by the encoder.

8. A method for video encoding, comprising: generating, by the encoder for at least one of an intra coding mode and an inter coding mode, an enable flag at a first level, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for the at least one mode; as well as In response to the FRDCT being enabled at the first level, a second flag at a coding unit (CU) level is generated by the encoder for indicating whether an FRDCT transform is applied to a CU.

9. The method for video encoding according to claim 8, further comprising: In response to determining that the FRDCT transform is applied to the CU, determining the CU includes one of the following: (i) share the horizontal and vertical vectors of the FRDCT transform matrix, or (ii) Use separate FRDCT transform matrices for the horizontal and vertical vectors.

10. The method for video encoding according to claim 9, wherein: In response to determining that the horizontal transform and the vertical transform share an FRDCT transform matrix, performing rate-distortion optimization by the encoder to determine optimized FRDCT transform parameters; and The encoder encodes the index of the optimized FRDCT transform parameters into a video bitstream.

11. The method for video encoding according to claim 9, further comprising: In response to determining that the horizontal transform and the vertical transform use separate FRDCT transform matrices, performing rate-distortion optimization by the encoder to determine optimized horizontal FRDCT transform parameters and optimized vertical FRDCT transform parameters; and The encoder encodes the indexes of the optimized horizontal FRDCT parameters and the optimized vertical FRDCT transform parameters into a video bitstream.

12. A method for video encoding, comprising: generating, by the encoder for at least one of an intra coding mode and an inter coding mode, an enablement flag at a first level indicating that use of a fractional discrete cosine transform (FRDCT) is enabled for the at least one mode; as well as In response to the FRDCT being enabled at the first level, a second flag at a coding unit (CU) level is generated by the encoder to indicate that an FRDCT transform is applied to a coding unit (CU).

13. The method for video encoding according to claim 12, wherein: The first level is the sequence parameter set (SPS) level.

14. The method for video encoding according to claim 13, wherein: In response to the second flag indicating that FRDCT is applied to the CU, obtaining a third flag indicating one of the following: (i) The horizontal vector and the vertical vector share the same FRDCT transform matrix, or (ii) Separate FRDCT transform matrices are used for horizontal and vertical vectors.

15. The method for video encoding according to claim 14, further comprising: In response to determining that the horizontal transform and the vertical transform share an FRDCT transform matrix, performing rate-distortion optimization by the encoder to determine optimized FRDCT transform parameters; as well as The encoder encodes the index of the optimized FRDCT transform parameters into a video bitstream.

16. The method for video encoding according to claim 15, further comprising: In response to determining that the horizontal transform and the vertical transform use separate FRDCT transform matrices, performing rate-distortion optimization by the encoder to determine optimized horizontal FRDCT transform parameters and optimized vertical FRDCT transform parameters; and The encoder encodes the indexes of the optimized horizontal FRDCT parameters and the optimized vertical FRDCT transform parameters into a video bitstream.

17. A method for video encoding, comprising: generating, by the encoder for at least one of an intra coding mode and an inter coding mode, an enable flag at a first level, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for the at least one mode; as well as In response to the FRDCT being enabled at the first level, a second flag at a coding unit (CU) level is generated by the encoder to indicate whether the FRDCT is applied to the CU.

18. The method for video encoding according to claim 17, wherein: The first level is the sequence parameter set (SPS) level.

19. The method for video encoding according to claim 17, further comprising: In response to determining that the FRDCT is applied to the CU, determining one of the following: (iii) the horizontal vector and the vertical vector share the same FRDCT transform matrix; or (iv) Horizontal and vertical vectors use separate FRDCT transform matrices.

20. The method for video encoding according to claim 19, wherein: In response to determining that the horizontal transform and the vertical transform share an FRDCT transform matrix, performing rate-distortion optimization by the encoder to determine optimized FRDCT transform parameters; and The encoder encodes the index of the optimized FRDCT transform parameters into a video bitstream.

21. The method for video encoding according to claim 20, further comprising: In response to determining that the horizontal transform and the vertical transform use separate FRDCT transform matrices, performing rate-distortion optimization by the encoder to determine optimized horizontal FRDCT transform parameters and optimized vertical FRDCT transform parameters; and The encoder encodes the indexes of the optimized horizontal FRDCT parameters and the optimized vertical FRDCT transform parameters into a video bitstream.

22. A method for video decoding, comprising: obtaining, at a decoder, an enable flag at a first level for at least one of an intra coding mode and an inter coding mode, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for the at least one mode; In response to FRDCT being enabled at the first level, obtaining, at the decoder, a second flag at a coding unit (CU) level for indicating whether an FRDCT transform is applied to a CU; as well as A third flag is obtained based on the second flag, wherein the third flag indicates use of at least one FRDCT transform matrix for a horizontal vector and a vertical vector.

23. The method for video decoding according to claim 22, wherein: The first level is the sequence parameter set (SPS) level.

24. The method for video decoding according to claim 22, wherein: Obtaining the third flag based on the second flag includes: In response to the second flag indicating that the FRDCT transform is applied to the CU, obtaining the third flag indicating one of the following: (i) The horizontal vector and the vertical vector share the same FRDCT transform matrix, or (ii) Separate FRDCT transform matrices are used for horizontal and vertical vectors.

25. The method for video decoding according to claim 24, further comprising: Indices of optimized FRDCT transform parameters in a bitstream are received at the decoder.

26. The method for video decoding according to claim 24, further comprising: An index of an optimized horizontal FRDCT transform parameter and an index of the optimized vertical FRDCT transform parameter in a bitstream are received at the decoder.

27. A method for video decoding, comprising: obtaining, at a decoder, an enable flag at a first level for at least one of an intra coding mode and an inter coding mode, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for the at least one mode; as well as In response to FRDCT being enabled at the first level, a second flag at a coding unit (CU) level is obtained at the decoder for indicating whether FRDCT transform is applied to the CU.

28. The method for video decoding according to claim 27, wherein: The first level is the sequence parameter set (SPS) level.

29. The method for video decoding according to claim 27, wherein: In response to the second flag indicating that the FRDCT transform is applied to the CU, obtaining one of the following: (i) share the horizontal and vertical vectors of the FRDCT transform matrix, or (ii) Use separate FRDCT transform matrices for the horizontal and vertical vectors.

30. The method for video decoding according to claim 29, further comprising: An index of optimized FRDCT transform parameters is received at the video decoder.

31. The method for video decoding according to claim 29, further comprising: An index of optimized horizontal FRDCT transform parameters and an index of optimized vertical FRDCT transform parameters are received at the video decoder.

32. A method for video encoding, comprising: generating, by the encoder for the intra coding mode and the inter coding mode, an enable flag at a sequence parameter set (SPS) level, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for at least one mode; In response to the FRDCT being enabled at the SPS level, generating, by the encoder, an FRDCT coding unit (CU) level flag for indicating whether an FRDCT transform is applied to a CU; In response to determining that the FRDCT transform is applied to the CU, obtaining a flag indicating one of the following: (i) The horizontal vector and the vertical vector share the same FRDCT transform matrix, or (ii) Separate FRDCT transform matrices are used for horizontal and vertical vectors.

33. The method for video encoding according to claim 32, further comprising: In response to determining that the horizontal vector and the vertical vector share a FRDCT transform matrix, performing rate-distortion optimization by the encoder to determine optimized FRDCT transform parameters; as well as The encoder encodes the index of the optimized FRDCT transform parameters into a video bitstream.

34. The method for video encoding according to claim 32, further comprising: In response to determining that the horizontal transform and the vertical transform use separate FRDCT transform matrices, performing rate-distortion optimization by the encoder to determine optimized horizontal FRDCT transform parameters and optimized vertical FRDCT transform parameters; and The index of the optimized horizontal FRDCT parameters and the index of the optimized vertical FRDCT transform parameters are encoded into a video bitstream by the encoder.

35. The method for video encoding according to claim 32, further comprising: Determining, by the encoder, one or more intra modes of the CU; Determining, by the encoder, FRDCT transform parameters in response to a first intra mode of the CU; as well as A horizontal FRDCT transform parameter and a vertical FRDCT transform parameter are determined by the encoder in response to a second intra mode of the CU.

36. A method for video encoding, comprising: generating, by the encoder for the intra coding mode and the inter coding mode, an enable flag at a sequence parameter set (SPS) level, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for at least one mode; In response to the FRDCT being enabled at the SPS level, generating, by the encoder, an FRDCT coding unit (CU) level flag for indicating whether an FRDCT transform is applied to a CU; and In response to determining that the FRDCT transform is applied to the CU, determining the CU includes one of the following: (v) sharing the horizontal vector and the vertical vector of the FRDCT transform matrix; or (vi) Use separate FRDCT transform matrices for the horizontal and vertical vectors.

37. The method for video encoding according to claim 36, wherein: In response to determining that the horizontal vector and the vertical vector share a FRDCT transform matrix, performing rate-distortion optimization by the encoder to determine optimized FRDCT transform parameters; and The encoder encodes the index of the optimized FRDCT transform parameters into a video bitstream.

38. The method for video encoding according to claim 36, further comprising: In response to determining that the horizontal vector and the vertical vector use separate FRDCT transform matrices, performing rate-distortion optimization by the encoder to determine optimized horizontal FRDCT transform parameters and optimized vertical FRDCT transform parameters; and The index of the optimized horizontal FRDCT parameters and the index of the optimized vertical FRDCT transform parameters are encoded into a video bitstream by the encoder.

39. A method for video encoding, comprising: generating, by the encoder, an enable flag at a sequence parameter set (SPS) level, the enable flag indicating use of fractional discrete cosine transform (FRDCT) and multi-transform skip (MTS) in a primary transform; and An FRDCT coding unit (CU) level flag and an MTS CU level flag are generated by the encoder to indicate that both the FRDCT and the MTS are applied to a CU.

40. The method for video encoding according to claim 39, further comprising: Determining, at the encoder, a shared FRDCT transform matrix for a horizontal FRDCT transform and a vertical FRDCT transform; performing rate-distortion optimization for the CU at the encoder to evaluate the FRDCT transform parameters; and Optimized FRDCT transform parameters are selected by the encoder based on the rate-distortion optimization.

41. The method for video encoding according to claim 40, further comprising: The encoder generates an index for optimizing FRDCT transform parameters; as well as The index of the optimized FRDCT transform parameters is encoded into a video bitstream at the encoder.

42. The method for video encoding according to claim 39, wherein: The first intra mode indicates that one or more FRDCT transform matrices share a horizontal FRDCT vector and a vertical FRDCT vector, and wherein the second intra mode indicates that one or more FRDCT transform matrices do not share the horizontal FRDCT vector and the vertical FRDCT vector.

43. The method for video encoding according to claim 42, further comprising: performing rate-distortion optimization for the CU at the encoder to evaluate horizontal FRDCT transform parameters and vertical FRDCT transform parameters; as well as An optimized horizontal FRDCT transform parameter and an optimized vertical FRDCT transform parameter are selected at the encoder based on a result of the rate-distortion optimization.

44. The method for video encoding according to claim 43, further comprising: The optimized horizontal FRDCT transform parameters and the optimized vertical FRDCT transform parameters are encoded into a video bitstream using a predefined binarization scheme at the encoder.

45. A method for video encoding, comprising: generating a fractional discrete cosine transform (FRDCT) matrix at an encoder using the received video data; performing eigenvalue decomposition on the FRDCT matrix at the encoder to obtain eigenvectors and eigenvalues, the eigenvalue decomposition comprising: raising the eigenvalues ​​to a power of a fractional number to obtain modified eigenvalues; as well as A derived FRDCT matrix is ​​generated at the encoder using the modified eigenvalues ​​and eigenvectors.

46. ​​The method for video encoding according to claim 45, further comprising: The derived FRDCT matrix is ​​applied to one or more video frames at the encoder to generate a transformed block of video data.

47. The method for video encoding according to claim 46, further comprising: The transform block is encoded by the encoder to generate an encoded video frame.

48. The method for video encoding according to claim 47, further comprising: The encoded video is stored by the encoder in a memory.

49. A method for video encoding, comprising: generating a coding unit (CU) level flag at the encoder to indicate enabling of a fractional discrete cosine transform (FRDCT) video coding scheme; as well as In response to generating the CU level flag to indicate that the FRDCT video coding scheme is enabled, the FRDCT is disabled in response to determining that the position of the last significant coefficient for a luma transform block (TB) is less than 1 or in response to determining that the last significant coefficient of the luma TB is located inside an MTS zero region.

50. The method for video encoding according to claim 49, further comprising: An enable flag at the SPS level is generated at the encoder to indicate enablement of a fractional discrete cosine transform (FRDCT) video coding scheme at the SPS level.

51. The method for video encoding according to claim 50, wherein: In response to determining that the FRDCT video coding scheme is enabled at the SPS level, the CU level flag is signaled by the encoder to indicate that the FRDCT video coding scheme applies to at least one of luma or (ii) chroma.

52. A method for video decoding, comprising: Obtaining, at a decoder, a fractional discrete cosine transform (FRDCT) CU level flag indicating whether a FRDCT transform is applied to a coding unit (CU); A flag is obtained at the decoder indicating one of: (i) The horizontal vector and the vertical vector share the same FRDCT transform matrix, or (ii) Separate FRDCT transform matrices are used for horizontal and vertical vectors.

53. The method for video decoding according to claim 52, further comprising: In response to obtaining, at the decoder, a flag indicating that the horizontal vector and the vertical vector use separate FRDCT transform matrices, an index for optimizing FRDCT transform parameters is received at the decoder.

54. The method for video decoding according to claim 53, further comprising: In response to obtaining at the decoder a flag indicating that the horizontal vector and the vertical vector use separate FRDCT transform matrices, an index of an optimized horizontal FRDCT parameter and an optimized vertical FRDCT parameter in a bitstream is received at the decoder.

55. The method for video decoding according to claim 54, further comprising: In response to an intra mode of the CU, one or more horizontal FRDCT transform parameters and one or more vertical FRDCT transform parameters are received at the decoder.

56. A method for video decoding, comprising: generating, at a decoder, an enable flag at a sequence parameter set (SPS) level for an intra coding mode and an inter coding mode, the enable flag indicating whether a fractional discrete cosine transform (FRDCT) is enabled for at least one mode; In response to an FRDCT CU flag indicating that the FRDCT is enabled for the CU, determining at the decoder to share a horizontal FRDCT transform and a vertical FRDCT transform between the decoder and an encoder; as well as In response to the FRDCT CU flag indicating that the FRDCT is enabled for the CU, determining at the decoder that the decoder and the encoder use separate horizontal and vertical FRDCT transforms.

57. The method for video decoding according to claim 56, further comprising: An index of optimized horizontal FRDCT transform parameters and an index of optimized vertical FRDCT transform parameters are received at the video decoder.

58. A method for video decoding, comprising: receiving at a decoder a derived fractional discrete cosine transform (FRDCT) matrix generated by an encoder using eigenvalue decomposition, the eigenvalue decomposition comprising raising eigenvalues ​​to a power of a fractional quantity to obtain modified eigenvalues, the FRDCT matrix comprising the modified eigenvalues; receiving, at the decoder, one or more coded transform blocks generated at the encoder by applying the derived FRDCT matrix to one or more video frames; as well as The one or more encoded transform blocks are stored in a memory at the decoder.

59. An apparatus for video decoding, comprising: one or more processors; as well as A memory coupled to the one or more processors and configured to store instructions executable by the one or more processors, wherein the one or more processors are configured to perform the method of claims 22-31 and claims 52-58 when executing the instructions.

60. An apparatus for video encoding, comprising: one or more processors; as well as A memory coupled to the one or more processors and configured to store instructions executable by the one or more processors, wherein the one or more processors are configured to perform the method of any one of claims 1-21 and claims 32-51 when executing the instructions.

61. A non-transitory computer-readable storage medium for storing computer-executable instructions, which, when executed by one or more computer processors, cause the one or more computer processors to receive a bit stream and perform the method in any one of claims 22-31 and claims 51-57 based on the bit stream.

62. A non-transitory computer-readable storage medium for storing computer-executable instructions, which, when executed by one or more computer processors, cause the one or more computer processors to perform the method of any one of claims 22-31 and claims 52-58 to encode a coding unit (CU) into a bitstream, and send the bitstream.

63. A non-transitory computer-readable storage medium for storing a bitstream to be decoded by the method of any one of claims 22-31 and claims 52-58.

64. A non-transitory computer-readable storage medium for storing a bitstream generated by the method of any one of claims 1-21 and claims 32-51.

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