Method for manufacturing semiconductor element
By stacking an insulating layer and a sacrificial layer in the semiconductor element and heat treatment of the dielectric layer, the problems of insufficient stability and electrical characteristics of the semiconductor element and large leakage current in the prior art are solved, and higher integration and lower leakage current are achieved.
Patent Information
- Application Number
- CN202380056969.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-07-26
- Filing Date
- 2023-07-20
- Publication Date
- 2025-03-18
AI Technical Summary
While the existing two-dimensional semiconductor component devices improve the integration and data storage capacity, it is difficult to effectively improve stability and electrical characteristics, and the leakage current is relatively large.
By stacking a plurality of insulating layers and sacrificial layers on the substrate, trenches are formed and a barrier layer and electrode layer are laminated therein, and the dielectric layer is heat treated, including performing heat treatment in a hydrogen atmosphere and an oxygen atmosphere to remove defects and impurities of the dielectric layer.
The stability and electrical characteristics of semiconductor components are improved, the leakage current is reduced, and the film quality of the dielectric layer is improved.
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Figure CN119654978A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor element. Background Art
[0002] In electronic systems that require data storage, a semiconductor component device that can store large amounts of data is needed. While increasing the data storage capacity, it is necessary to increase the integration of semiconductor component devices to meet the excellent performance and low prices required by consumers. In the case of two-dimensional or planar semiconductor component devices, since the integration is mainly determined by the area occupied by the unit storage unit, it is largely affected by the level of fine pattern formation technology. However, since the refinement of the pattern requires ultra-expensive equipment, although the integration of two-dimensional semiconductor component devices continues to increase, it is still limited. Therefore, a three-dimensional semiconductor component storage device having three-dimensionally arranged storage units is proposed. Summary of the invention
[0003] Technical issues
[0004] An object of the present invention is to provide a method for manufacturing a semiconductor element having improved stability and electrical characteristics.
[0005] Another object of the present invention is to provide a method for manufacturing a semiconductor element capable of reducing the magnitude of leakage current.
[0006] The purpose of this specification is not limited to the above-mentioned purpose, and other purposes and advantages of the present invention that are not mentioned can be more clearly understood through the following embodiments of this specification. In addition, the purposes and advantages of this specification can be achieved through the structural elements and their combinations recorded in the scope of the invention.
[0007] Technical Solution
[0008] According to one embodiment, a method for manufacturing a semiconductor element may include: a step of stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate; a step of forming openings penetrating the plurality of insulating layers and the plurality of sacrificial layers; a step of removing the sacrificial layers to form a groove; a step of stacking a barrier layer inside the groove; a step of stacking a first electrode layer on the barrier layer; a step of stacking a dielectric layer on the first electrode layer; a step of performing heat treatment on the dielectric layer; and a step of stacking a second electrode layer on the dielectric layer.
[0009] In one embodiment, the heat treatment may include a first heat treatment performed in a hydrogen atmosphere.
[0010] In one embodiment, the heat treatment may include a first heat treatment performed in a hydrogen atmosphere and a second heat treatment performed in an oxygen atmosphere.
[0011] In one embodiment, the heat treatment may be performed at a temperature of 200°C to 1000°C.
[0012] In one embodiment, the pressure of the gas supplied when performing the heat treatment may be 2 atm to 50 atm.
[0013] In one embodiment, the insulating layer may include silicon (Si), and the sacrificial layer may include silicon germanium (SiGe).
[0014] In one embodiment, the dielectric layer may include at least one of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), vanadium dioxide (VO2), titanium dioxide (TiO2), tin dioxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO) or niobium pentoxide (Nb2O5).
[0015] Effects of the Invention
[0016] According to the embodiment, defects or impurities of the dielectric layer can be removed by heat treatment performed in a hydrogen atmosphere, thereby improving the performance and reliability of the semiconductor element, and reducing the leakage current of the semiconductor element. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figures 1 to 6 A manufacturing process of a semiconductor element according to an embodiment is shown.
[0018] Figure 7 The graph is a graph comparing the leakage current of a common semiconductor device and the leakage current of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment.
[0019] Figure 8 The graph is a graph comparing the film density of a dielectric layer of a conventional semiconductor device and the film density of a dielectric layer of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION
[0020] The above-mentioned objects, features and advantages will be described in detail with reference to the accompanying drawings, so that a person of ordinary skill in the art can easily implement the embodiments of this specification. When describing this specification, when it is judged that the specific description of the known technology related to this specification may unnecessarily obscure the main idea of the present invention, its detailed description will be omitted. Hereinafter, the preferred embodiments in this specification are described in detail with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent the same or similar structural elements.
[0021] Figures 1 to 6 A manufacturing process of a semiconductor element according to an embodiment is shown.
[0022] Reference Figure 1 , multiple insulating layers 12 and multiple sacrificial layers 14 may be alternately and repeatedly stacked on the substrate 10. The multiple insulating layers 12 and the multiple sacrificial layers 14 may be epitaxially grown. In one embodiment, the substrate 10 may be made of a single crystal silicon chip. Each insulating layer 12 may include silicon (Si). Each sacrificial layer 14 may include silicon germanium (SiGe). Each sacrificial layer 14 may have substantially the same thickness, and each insulating layer 12 may have different thicknesses in some regions.
[0023] When the sacrificial layer 14 is made of silicon germanium (SiGe), the proportion of germanium (Ge) can be higher than that of silicon (Si) in the sacrificial layer 14. In this way, if the proportion of germanium (Ge) in the sacrificial layer 14 is higher than that of silicon (Si), the etching selectivity with respect to the insulating layer 12 can be improved in the manufacturing process described later. However, the composition or composition ratio of the sacrificial layer 14 is not limited to the above-mentioned embodiment, and the composition or composition ratio of the sacrificial layer 14 can be changed as needed.
[0024] Next, refer to Figure 2 , an opening 16 can be formed that vertically penetrates the sacrificial layer 14 and the insulating layer 12. For example, the sacrificial layer 14 and the insulating layer 12 can be etched by patterning to form the opening 16. The sidewalls of the sacrificial layer 14 and the insulating layer 12 can be exposed through the opening 16. In subsequent processes, the sacrificial layer 14 can be removed by using the opening 16.
[0025] Next, refer to Figure 3 , the sacrificial layer 14 can be removed by utilizing the etching selectivity of the sacrificial layer 14 and the insulating layer 12. As the sacrificial layer 14 is removed, a plurality of trenches 18 are formed. For example, the sacrificial layer 14 can be made of silicon germanium (SiGe). At this time, when the specific gravity of germanium (Ge) constituting the sacrificial layer 14 is higher than the specific gravity of silicon (Si), the etching selectivity relative to silicon (Si) contained in the insulating layer 12 can be increased. Therefore, the sacrificial layer 14 can be removed by wet etching using, for example, hydrochloric acid (HCl) or the like.
[0026] Next, refer to Figure 4 , the barrier layer 20, the first electrode layer 21 and the dielectric layer 22 may be sequentially stacked inside each trench 18. The barrier layer 20 may include a metal material (e.g., Ti, TiN or Co). The first electrode layer 21 may include a metal material. For example, the first electrode layer 21 may include a conductive layer of metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon or a combination thereof. As another example, the first electrode layer 21 may include TiN, Al, W or Ru. However, the type of metal material included in the first electrode layer 21 is not limited to the exemplified materials.
[0027] The dielectric layer 22 may include a high-k material and may be deposited by an atomic layer deposition (ALD) process.
[0028] In one embodiment, the high dielectric constant material included in the dielectric layer 22 is, for example, at least one of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), vanadium dioxide (VO2), titanium dioxide (TiO2), tin dioxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO) or niobium pentoxide (Nb2O5). However, the type of high dielectric constant material is not limited to the above embodiments.
[0029] like Figure 4 As shown, after the dielectric layer 22 is formed, a first heat treatment may be performed on the dielectric layer 22. In one embodiment, the first heat treatment of the dielectric layer 22 may be performed in a gas atmosphere containing a hydrogen component. For example, the first heat treatment of the dielectric layer 22 may be performed in an H2 or D2 atmosphere. In one embodiment, when the first heat treatment is performed on the dielectric layer 22, the gas pressure of the supplied gas containing a hydrogen component may be 2 atm to 50 atm. In one embodiment, the first heat treatment of the dielectric layer 22 may be performed at a temperature of 200°C to 1000°C.
[0030] In another embodiment, the first heat treatment of the dielectric layer 22 may be performed in a gas atmosphere containing a nitrogen component. For example, the first heat treatment of the dielectric layer 22 may be performed in an N2 atmosphere. In one embodiment, when the first heat treatment is performed on the dielectric layer 22, the gas pressure of the supplied gas containing a nitrogen component may be 2 atm to 50 atm. In one embodiment, the first heat treatment of the dielectric layer 22 may be performed at a temperature of 200° C. to 1000° C.
[0031] As semiconductor elements are scaled down, the thickness of the dielectric layer 22 becomes thinner than a limit, and the leakage current may increase as a result. The leakage current is generated by defects or impurities present in the dielectric layer 22. In particular, the structural defects of the dielectric layer 22 made of a material with a high dielectric constant (high-k) are about 100 times more than the structural defects of other insulating films (e.g., SiO2), thereby increasing the possibility of leakage current. However, if the above-mentioned first heat treatment is performed, the defects or impurities of the dielectric layer 22 can be removed. Therefore, the film quality of the dielectric layer 22 can be improved and the leakage current can be reduced.
[0032] In another embodiment, after performing the first heat treatment on the dielectric layer 22, a second heat treatment may be further performed on the dielectric layer 22. In another embodiment, the second heat treatment of the dielectric layer 22 may be performed in a gas atmosphere containing an oxygen component. For example, the second heat treatment of the dielectric layer 22 may be performed in an atmosphere of O2, O3, or H2O. In one embodiment, when the first heat treatment is performed on the dielectric layer 22, the gas pressure of the supplied gas containing an oxygen component may be 2atm to 50atm. In one embodiment, the second heat treatment of the dielectric layer 22 may be performed at a temperature of 200°C to 1000°C. Through the second heat treatment of the dielectric layer 22, the film quality of the dielectric layer 22 may be further improved and the leakage current may be further reduced.
[0033] According to an embodiment, only a first thermal treatment may be performed on the dielectric layer 22 .
[0034] Next, refer to Figure 5 , a second electrode layer 23 may be formed on the dielectric layer 22. The second electrode layer 23 may include a metal material. For example, the second electrode layer 23 may include a conductive layer such as a metal nitride, a metal oxide, a metal silicide, conductive carbon, polysilicon, or a combination thereof. As another example, the second electrode layer 23 may include TiN, Al, W, or Ru. However, the type of metal material included in the first electrode layer 23 is not limited to the listed materials.
[0035] Next, refer to Figure 6 A unit structure 30 may be formed inside the opening 16. In one embodiment, the unit structure 30 may include at least one structural element (e.g., a transistor) electrically connected to the first electrode layer 21 or the second electrode layer 23 or at least a portion of a conductive line (e.g., a word line or a bit line) electrically connected to at least one structural element electrically connected to the first electrode layer 21 or the second electrode layer 23.
[0036] Figure 7 The graph is a graph comparing the leakage current of a common semiconductor device and the leakage current of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment.
[0037] Figure 7 The "No anneal" in refers to the leakage current value of a general semiconductor element without performing a heat treatment on the dielectric layer. Figure 7 The “HPA” in represents the leakage current value of the semiconductor device after the first heat treatment is performed on the dielectric layer according to an embodiment. And, Figure 7"HPA+HPO" in hereinafter represents a leakage current value of a semiconductor element in which a first heat treatment and a second heat treatment are sequentially performed on a dielectric layer according to another embodiment. For reference, the first heat treatment and the second heat treatment are respectively performed at 500°C / 20 atm for 1 hour, and the first heat treatment is performed in a hydrogen atmosphere, and the second heat treatment is performed in an oxygen atmosphere.
[0038] like Figure 7 As shown, when the leakage current value of the semiconductor without heat treatment on the dielectric layer is 1, the leakage current value of the semiconductor element that performs the first heat treatment on the dielectric layer according to one embodiment is 0.87. And, the leakage current value of the semiconductor element that sequentially performs the first heat treatment and the second heat treatment on the dielectric layer according to another embodiment is 0.79. According to the experimental results, it can be seen that the leakage current of the semiconductor element can be reduced by removing defects or impurities of the dielectric layer through the first heat treatment or through the first and second heat treatments. In particular, it can be seen that when the second heat treatment is further performed in an oxygen atmosphere, the leakage current is further reduced by about 10% compared with the case where only the first heat treatment is performed.
[0039] Figure 8 The graph is a graph comparing the film density of a dielectric layer of a conventional semiconductor device and the film density of a dielectric layer of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment.
[0040] Figure 8 The term “no annealing” in refers to the film density of the dielectric layer of a general semiconductor element without performing a heat treatment on the dielectric layer. And, Figure 8 HPA in which HPA represents the film density of the dielectric layer of the semiconductor device according to an embodiment of the present invention, which performs the first heat treatment on the dielectric layer. And, Figure 8 HPA+HPO in the figure represents the film density of the dielectric layer of the semiconductor element according to another embodiment in which the dielectric layer is subjected to the first heat treatment and the second heat treatment sequentially. For reference, the first heat treatment and the second heat treatment are respectively performed at 500°C / 20atm for 1 hour, and the first heat treatment is performed in a hydrogen atmosphere, and the second heat treatment is performed in an oxygen atmosphere.
[0041] like Figure 8As shown, when the film density of a common semiconductor element that does not perform heat treatment on the dielectric layer is 1, the film density of the dielectric layer of the semiconductor element that performs the first heat treatment on the dielectric layer according to one embodiment is 1.05. And, the film density of the semiconductor element that sequentially performs the first heat treatment and the second heat treatment on the dielectric layer according to another embodiment is 1.21. According to the experimental results, it can be seen that the film quality of the dielectric layer can be improved by removing defects or impurities of the dielectric layer through the first heat treatment or through the first and second heat treatments. In particular, it can be seen that when the second heat treatment is further performed in an oxygen atmosphere, the film density is further increased by about 20% compared with the case where only the first heat treatment is performed.
[0042] According to the above-mentioned embodiment, the dielectric layer is subjected to a first heat treatment under a hydrogen atmosphere, or the dielectric layer is subjected to a first heat treatment under a hydrogen atmosphere and then subjected to a second heat treatment under an oxygen atmosphere, so that defects or impurities of the dielectric layer can be removed. Therefore, the film quality of the dielectric layer is improved and leakage current is reduced. Therefore, the stability and electrical characteristics of the semiconductor element can be improved. As an example of a semiconductor element according to an embodiment, a dynamic random access memory (DRAM) can be used.
[0043] As described above, the present specification is described with reference to the drawings shown, but the present specification is not limited to the embodiments and drawings disclosed herein, and various modifications can be made by those skilled in the art. In addition, although the effects of the configurations according to the present specification are not explicitly described when describing the embodiments of the present specification, it should also be recognized that the effects that can be predicted by the corresponding configurations.
Claims
1. A method for manufacturing a semiconductor element, characterized in that: include: The step of stacking a plurality of insulating layers and a plurality of sacrificial layers on the substrate; forming openings penetrating the plurality of insulating layers and the plurality of sacrificial layers; a step of removing the sacrificial layer to form a groove; A step of laminating a barrier layer inside the groove; A step of stacking a first electrode layer on the barrier layer; The step of stacking a dielectric layer on the first electrode layer; a step of performing a heat treatment on the dielectric layer; as well as The step of stacking a second electrode layer on the dielectric layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The heat treatment includes a first heat treatment performed in a hydrogen atmosphere.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The heat treatment includes a first heat treatment performed in a hydrogen atmosphere and a second heat treatment performed in an oxygen atmosphere.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The heat treatment is performed at a temperature of 200°C to 1000°C.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The gas pressure of the supplied gas when the heat treatment is performed is 2 atm to 50 atm.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The insulating layer includes silicon (Si), The sacrificial layer includes silicon germanium (SiGe).
7. The method for manufacturing a semiconductor device according to claim 1, wherein: The dielectric layer includes at least one of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), vanadium dioxide (VO2), titanium dioxide (TiO2), tin dioxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO) or niobium pentoxide (Nb2O5).