Superconducting interconnection structure

Abstract

A method for forming a superconducting interconnect structure, comprising: providing a substrate (1), forming a superconducting layer (21), forming a layer of a first dielectric material (22), removing a portion of the layer of the first dielectric material (22) and a portion of the superconducting layer (21) to form a pattern comprising a first set of line structures (4), the first set of line structures (4) comprising: a first set of superconducting line structures (41), and a first set of line structures made of a first dielectric material (42), forming a second dielectric material (50) between the respective line structures of the first set (4), forming a layer formed of a third dielectric material (6), providing a patterned mask (73), transferring the pattern into the first dielectric material (42) and the layer formed of the third dielectric material (6) to form at least one hole (43), the patterned mask (73) is removed, and a superconducting material layer (8) is formed, thereby forming at least one via (81).

Description

Technical Field

[0001] The present invention relates to the field of superconducting interconnects for integrated circuits. In particular, the present invention relates to a method for forming superconducting wires and vias.

[0002] Background of the Invention

[0003] Superconducting digital technology has high potential as a technology that surpasses CMOS. The advantages associated with superconducting digital technology are high energy efficiency, high computational density, and high interconnection bandwidth. Superconducting digital technology is usually based on single flux quantum (SFQ) pulses, which are fast, low power, and low dispersion / low loss on superconductor transmission lines.

[0004] Superconducting interconnects can connect different devices in an integrated circuit based on superconducting digital technology. In the prior art, metal etching is usually performed to form these superconducting interconnects. However, although metal etching is suitable for many superconducting materials, the possibility of reducing the size of the interconnect structure may be limited. For example, conventional niobium wires have high sensitivity to parasitic and magnetic coupling, requiring multiple ground planes and special layout and routing algorithms. On the other hand, high dynamic inductance wires have low sensitivity to parasitic magnetic coupling, allowing high-density routing, provided that strict control of the material parameter distribution can be ensured throughout the manufacturing method.

[0005] Therefore, technologies are needed to further reduce the size of superconducting interconnect structures. However, in order to obtain good superconducting logic and memory, a back-end process compatible with high dynamic inductance materials (such as NbTiN) is preferred, which enables the formation of several layers of superconducting wire structures with a pitch as low as 100nm or less, and allows the formation of vias that match the pitch of the superconducting wire structure. At the same time, strict cross-sectional control of the superconducting wire structure and the vias (the cross-sectional area determines the inductance per unit length) is preferred.

[0006] Therefore, there remains a need in the art for devices and methods that address at least some of the above-mentioned problems. Summary of the invention

[0007] The object of the present invention is to provide a good method for forming a superconducting interconnect structure of an integrated circuit, and a good superconducting interconnect structure obtained thereby.

[0008] The above objects are achieved by the method and structure according to the present invention.

[0009] An advantage of the embodiments of the present invention is that the superconducting interconnect structure can be reduced in size. In fact, an advantage of the embodiments of the present invention is that the spacing between the superconducting wire structure of the first entity and the superconducting wire structure of the second entity covering the first entity can be very small, for example, as small as 100 nm or even smaller.

[0010] An advantage of the embodiments of the present invention is that the superconducting interconnect structure can have a superconducting wire structure and a through hole whose cross section can be strictly controlled. Another advantage of the embodiments of the present invention is that the through hole can have a small parasitic inductance. Another advantage of the embodiments of the present invention is that a high filling ratio of the superconducting wire structure can be achieved.

[0011] An advantage of embodiments of the present invention is that shallow vias (ie, having a low aspect ratio) can be formed.

[0012] An advantage of embodiments of the present invention is that the method is compatible with high dynamic inductance materials (eg NbTiN) for which deposition in trenches may be difficult.

[0013] A method for forming a superconducting interconnect structure for an integrated circuit, comprising:

[0014] a. forming a first entity on a substrate by the following steps:

[0015] a1. Provide substrate,

[0016] a2. forming a first superconducting layer of a first superconducting material having a first critical temperature on a substrate,

[0017] a3. forming a layer of a first dielectric material over the first superconducting layer,

[0018] a3 '. A protective dielectric layer is optionally formed on top of the first dielectric material, for example having a thickness of 1 to 20 nm, for example 5 to 15 nm, such as 10 nm,

[0019] a4. removing a portion of the first dielectric material layer and a portion of the first superconducting layer, the portions extending from the bottom surface of the first superconducting layer to the top surface of the first dielectric material to form a pattern comprising a first set of line structures having a top surface, the first set of line structures comprising:

[0020] The first set of superconducting wire structures, and

[0021] a first set of wire structures made of a first dielectric material aligned with and overlying the first set of superconducting wire structures and comprising a top surface,

[0022] a5. forming a second dielectric material different from the first dielectric material over and between each line structure of the first group,

[0023] a6. planarizing the second dielectric material so that the top surface of the second dielectric material is coplanar with the top surface of the first set of line structures, and thereafter

[0024] a7. forming a layer formed of a third dielectric material over the first set of line structures and the second dielectric material,

[0025] Thus forming the first entity,

[0026] b. providing a patterned mask over the first entity, the pattern comprising at least one opening overlapping with an underlying superconducting wire structure of the first set of superconducting wire structures for forming at least one hole in the first dielectric material and in the layer formed by the third dielectric material,

[0027] c. transferring the pattern of the patterned mask into the first dielectric material and the layer formed by the third dielectric material to form at least one hole extending through the first dielectric material and the layer formed by the third dielectric material, thereby exposing a portion of the underlying superconducting wire structure,

[0028] d. removing the patterned mask, thereby exposing the perforated surface, and

[0029] e. forming a superconducting unit made of one or more superconducting materials above the perforated surface, each superconducting material having a critical temperature within 1K of the first critical temperature, thereby forming at least one through-hole by filling at least one hole, the at least one through-hole extending through the first dielectric material and the layer formed by the third dielectric material, so that the formed superconducting unit physically contacts the first group of superconducting wire structures below.

[0030] In a second aspect, the invention relates to a superconducting interconnect structure which can be formed by a method according to any embodiment of the first aspect, the interconnect structure comprising a first entity, the first entity comprising:

[0031] i. A first set of line structures having a top surface, comprising:

[0032] The first set of superconducting wire structures, and

[0033] a first set of wire structures made of a first dielectric material aligned with and overlying the first set of superconducting wire structures and comprising a top surface, and

[0034] ii. a second dielectric material different from the first dielectric material, located between each of the first set of line structures, and having a top surface coplanar with the top surface of the first set of line structures, and

[0035] iii. a third dielectric material covering the first set of line structures and the second dielectric material,

[0036] and wherein the via extends through the first dielectric material and the layer formed of the third dielectric material, wherein the via includes a superconducting material that physically contacts an underlying superconducting wire structure.

[0037] Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not just as explicitly set out in the claims.

[0038] While devices in the art are constantly improving, changing, and evolving, it is believed that the present inventive concepts represent a substantially new and original advancement involving a departure from prior practice, thereby providing a more efficient, stable, and reliable device of this nature.

[0039] The above and other characteristics, features and advantages of the present invention will become apparent from the following detailed description in conjunction with the accompanying drawings, which illustrate the principles of the present invention by way of example. This description is given for illustrative purposes only and does not limit the scope of the present invention. The reference figures cited below refer to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1-11 is a schematic diagram of a perspective view of different steps in a method of forming a superconducting interconnect structure according to an embodiment of the present invention.

[0041] The same reference numbers in different drawings refer to the same or similar elements. DETAILED DESCRIPTION

[0042] The present invention will be described with respect to specific embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the claims. The drawings described are merely illustrative and non-restrictive. In the drawings, for illustrative purposes, the size of some of the elements may be exaggerated and not drawn to scale. The dimensions and relative dimensions do not correspond to actual reductions to the practice of the invention.

[0043] In addition, the terms first, second, third, etc. in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a sequence in time, space, ranking or any other manner. It should be understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operating in a sequence different from that described or illustrated herein.

[0044] Furthermore, the terms top, bottom, over, under, etc. in the specification and claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in orientations other than those described or illustrated herein.

[0045] The terms "over," "overlying," and "over" are used as synonyms and cover situations with and without physical contact. The term "on" means "over and in physical contact with."

[0046] It should be noted that the term "comprising" used in the claims should not be interpreted as being limited to the means listed thereafter; it does not exclude other elements or steps. Thus, the term should be interpreted as specifying the presence of the stated features, integers, steps or components as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Therefore, the term "comprising" covers the case where only the stated features are present as well as the case where these features and one or more other features are present. The word "comprising" according to the present invention therefore also includes an embodiment as being absent of other components. Thus, the scope of the expression "device comprising means A and B" should not be interpreted as being limited to devices consisting only of components A and B. This means that for the present invention, the only relevant components in the device are A and B.

[0047] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in various embodiments" in various places throughout this specification do not necessarily all refer to the same embodiment, but may refer to different embodiments. Furthermore, in one or more embodiments, as would be apparent to one of ordinary skill in the art from this disclosure, the particular features, structures, or characteristics may be combined in any suitable manner.

[0048] Similarly, it should be appreciated that in the description of exemplary embodiments of the present invention, for the purpose of streamlining the present disclosure and assisting in the understanding of one or more of the various inventive aspects, the various features of the present invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than the features expressly recited in each claim. On the contrary, as reflected in the appended claims, the inventive aspects lie in fewer features than all of the features of a single preceding disclosed embodiment. Thus, the claims appended to the specific embodiments are hereby expressly incorporated into the specific embodiments, wherein each claim itself represents a separate embodiment of the present invention.

[0049] In addition, although some embodiments described herein include some features included in other embodiments but do not include other features included in other embodiments, as will be understood by those skilled in the art, the combination of features of different embodiments is intended to fall within the scope of the present invention and form different embodiments. For example, in the appended claims, any of the claimed embodiments may be used in any combination.

[0050] In addition, some of the embodiments are described herein as methods or combinations of elements of methods that can be implemented by a processor of a computer system or by other devices that implement functions. Thus, a processor with necessary instructions for executing such methods or elements of methods forms a device for executing the method or elements of the method. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements that implement the purpose of the present invention.

[0051] In the description provided herein, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known methods, structures, and techniques are not shown in detail to avoid obscuring the understanding of this specification.

[0052] The following items are provided solely to assist the understanding of the present invention.

[0053] As used herein and unless otherwise specified, when an entity is described as superconducting, this means that the entity has the ability to become superconducting at a temperature below a certain critical temperature. This does not mean that the entity is superconducting when it is formed during the method. Instead, the steps of the method are typically performed at a temperature above the critical temperature of the superconducting material involved. Thus, for example, forming a first superconducting layer does not result in a layer that has superconductivity once formed, but rather results in a layer that can become superconducting after the temperature of the layer is reduced below its critical temperature.

[0054] In a first aspect, the present invention relates to a method for forming a superconducting interconnect structure of an integrated circuit, comprising:

[0055] a. forming a first entity (44) on a substrate (1) by the following steps:

[0056] a1. Providing a substrate (1),

[0057] a2. forming a first superconducting layer (21) of a first superconducting material having a first critical temperature on the substrate (1),

[0058] a3. forming a first dielectric material layer (22) above the first superconducting layer (21),

[0059] a3 '. A protective dielectric layer is optionally formed on top of the first dielectric material (22), for example having a thickness of 1 to 20 nm, for example 5 to 15 nm, such as 10 nm,

[0060] a4. removing portions of the layer of the first dielectric material (22) and portions of the first superconducting layer (21), the portions extending from the bottom surface of the first superconducting layer to the top surface of the first dielectric material (22) to form a pattern comprising a first set of line structures (4) having a top surface (420), the first set of line structures comprising:

[0061] a first set of superconducting wire structures (41), and

[0062] a first set of wire structures made of a first dielectric material (42), aligned with and overlying the first set of superconducting wire structures (41), and comprising a top surface (420),

[0063] a5. forming a second dielectric material (50) different from the first dielectric material over and between each of the line structures of the first group of line structures (4),

[0064] a6. planarizing the second dielectric material (50) so that the top surface (51) of the second dielectric material is coplanar with the top surface (420) of the first set of line structures (4), and thereafter

[0065] a7. forming a layer formed of a third dielectric material (6) over the first set of line structures (4) and the second dielectric material (50),

[0066] Thereby forming a first entity (44),

[0067] b. providing a patterned mask (73) above the first entity, the pattern comprising at least one opening (730) overlapping with an underlying superconducting wire structure of the first set of superconducting wire structures (41) for forming at least one hole (43) in the first dielectric material (42) and in the layer formed by the third dielectric material (6),

[0068] c. transferring the pattern of the patterned mask (73) into the first dielectric material (42) and the layer formed by the third dielectric material (6) to form at least one hole (43) extending through the first dielectric material (42) and the layer formed by the third dielectric material (6) to expose a portion of the underlying superconducting wire structure (41),

[0069] d. removing the patterned mask (73) thereby exposing the perforated surface (60), and

[0070] e. forming a superconducting unit (81, 201, 8) made of one or more superconducting materials above the perforated surface (60), each superconducting material having a critical temperature within 1K of the first critical temperature, thereby forming at least one through hole (81) by filling at least one hole (43), the at least one through hole (81) extending through the first dielectric material (42) and the layer formed by the third dielectric material (6), so that the formed superconducting unit (81, 201, 8) physically contacts the first group of superconducting wire structures (41) below.

[0071] The inventors have found that several superconducting materials preferred in practical applications may be particularly difficult to deposit in holes or grooves with high aspect ratios. Here, the aspect ratio is the ratio of the height (e.g., of a through hole, hole, line or groove) in a direction perpendicular to the top surface of a superconducting wire structure to the width (e.g., of a through hole, hole, line or groove) in a direction parallel to the top surface of a superconducting wire structure. Therefore, it may be difficult to form a superconducting wire structure using a mosaic process, and the superconducting wire structure is preferably as narrow as possible in order to obtain a high density of interconnections in a superconducting interconnect structure. At the same time, the through hole is preferably shallow, i.e., preferably has a small aspect ratio, so that a high density of interconnections in a superconducting interconnect structure can be achieved. The inventors have found that by combining a metal etching process for forming a superconducting wire structure with a mosaic process for forming a through hole, a good size reduction of a superconducting interconnect structure can be achieved.

[0072] In various embodiments, the methods of the present invention are used to form superconducting interconnect structures in the back-end of integrated circuit fabrication.

[0073] The nature of the substrate is not important. The substrate typically comprises a semiconductor wafer with or without a dielectric layer thereon. For example, it may comprise a bare silicon wafer or a silicon wafer with a silicon oxide layer thereon.

[0074] In some embodiments, the substrate may include individual isolated devices. The top surface of the substrate may include a dielectric surface including conductive islands or superconducting islands for establishing connections with the individual isolated devices. In the method of the present invention, the first set of semiconductor wire structures formed during step a. may form physical contacts with one or more of these islands. When the temperature of the semiconductor wire structures is reduced below a critical temperature, these physical contacts may become electrical contacts.

[0075] The substrate may also include pre-existing vias connected to pre-existing superconducting wire structures. The top surface of the substrate may include a dielectric surface including a conductive or superconducting via top surface. In the method of the present invention, the first set of semiconductor wire structures formed during step a. may form physical contact with one or more of these pre-existing vias.

[0076] The method of the present invention is compatible with forming superconducting interconnects in most types of superconducting materials. For example, the first, second and third superconducting materials can be independently selected from superconducting chemical elements (such as Al, Ti, Nb, etc.) and superconducting compounds (such as MoN, Nb3Sn, NbTi, NbTiN and NbN). Preferred superconducting materials include Nb, more preferred superconducting materials include Nb and at least one of Ti and N, and most preferably include Nb, Ti and N (such as NbTiN). In these last compounds, the atomic ratio N / (Nb+Ti) is preferably equal to 0.5, and the atomic ratio Nb / (Nb+Ti) is preferably generally from 0.65 to 0.84. These last compounds have particularly high critical temperatures. Preferably, the critical temperature of the first superconducting material is 10K or higher. More preferably, it is 12K or higher. More preferably, it is 14K or higher. More preferably, it is 16K or higher. For example, it can be from 16.5K to 17.5K.

[0077] In various embodiments, the thickness of each superconducting layer used in the method may be independently selected within the range of 20 to 500 nm, preferably 30 to 350 nm, and more preferably 50 to 200 nm.

[0078] In a preferred embodiment, step a2. is performed by physical vapor deposition. Although atomic layer deposition or chemical vapor deposition can be used, the present invention can use physical vapor deposition technology, which is an easy-to-implement technology. The inventors have also found that when used in the present invention, good control of the dimensions of the through-hole and superconducting wire structure can be achieved by physical vapor deposition.

[0079] When step a3' is performed, step a4. comprises removing portions of the protective dielectric layer, portions of the layer of the first dielectric material (22) and portions of the first superconducting layer (21), said portions extending from the first bottom surface of the first superconducting layer to the top surface of the protective dielectric layer, to form a pattern comprising a first set of line structures (4), the first set of line structures comprising:

[0080] a first set of superconducting wire structures (41), and

[0081] a first set of wire structures made of a first dielectric material (42), aligned with and overlying the first set of superconducting wire structures (41), and comprising a top surface (420),

[0082] A first set of protective dielectric wire structures is aligned with and overlies the first set of wire structures made of a first dielectric material (42).

[0083] In various embodiments, step a4. of removing a portion of the layer of the first dielectric material and a portion of the first superconducting layer can be performed by first forming a hard mask (e.g., a layer or a stack of layers) above the layer of the first dielectric material, then forming a photoresist patterned mask on the hard mask, and then etching through the hard mask using the photoresist patterned mask as a mask, thereby transferring the pattern of the photoresist patterned mask to the hard mask, and then etching through the first dielectric layer and the superconducting layer using the hard mask as a mask.

[0084] In each embodiment, each wire structure of the first group of wire structures has a rectangular parallelepiped shape. In each embodiment, each wire structure of the first group of superconducting wire structures has a rectangular parallelepiped shape. In each embodiment, the height of the superconducting wire structure in a direction perpendicular to the top surface of the superconducting wire structure is 20 to 500nm, preferably 30 to 350nm, and more preferably 50 to 200nm. In each embodiment, the width of the superconducting wire structure in a direction parallel to the top surface of the superconducting wire structure is 20 to 500nm, preferably 30 to 350nm, and more preferably 50 to 200nm. In each embodiment, the length of the superconducting wire structure in a direction parallel to the top surface of the superconducting wire structure and perpendicular to the width is at least 200nm, preferably at least 500nm. Here, the length is longer than the width. In each embodiment, the aspect ratio of the wire structure, that is, the ratio between their height and width, is 1 to 4.

[0085] In various embodiments, the sidewall of the superconducting wire structure forms an angle of 85° to 93° with the top surface of the substrate, preferably 88° to 92°, more preferably 89° to 90°. Typically, the angle is 90°.

[0086] In various embodiments, each wire structure of the first group of wire structures made of the first dielectric material has a rectangular parallelepiped shape. In various embodiments, the height of the wire structure made of the first dielectric material in a direction perpendicular to the top surface of the wire structure made of the first dielectric material is 1 to 50 nm, preferably 5 to 20 nm. In various embodiments, the width of the wire structure made of the first dielectric material in a direction parallel to the top surface of the wire structure made of the first dielectric material is 20 to 500 nm, preferably 30 to 350 nm, more preferably 50 to 200 nm. In various embodiments, the length of the wire structure made of the first dielectric material in a direction parallel to the top surface of the wire structure made of the first dielectric material is at least 200 nm, preferably at least 500 nm. Here, the length is longer than the width. In various embodiments, the width of the wire structure made of the first dielectric material is within 2% of the width of the superconducting wire structure, for example within 1%, for example the same as the width of the superconducting wire structure. In various embodiments, the width of the wire structure made of the first dielectric material is within 2%, such as within 1%, such as the same as the width of the superconducting wire structure.

[0087] In various embodiments, the protective dielectric wire structure of the first group has a rectangular parallelepiped shape. In various embodiments, the height of the protective dielectric wire structure in a direction perpendicular to the top surface of the wire structure made of the first dielectric material may be 1 to 50 nm. In various embodiments, the width of the protective dielectric wire structure in a direction parallel to the top surface of the wire structure made of the first dielectric material is 20 to 500 nm, preferably 30 to 350 nm, and more preferably 50 to 200 nm. In various embodiments, the length of the protective dielectric wire structure in a direction parallel to the top surface of the wire structure made of the first dielectric material and perpendicular to the width is at least 200 nm, preferably at least 500 nm. Here, the length is longer than the width. In various embodiments, the width of the protective dielectric wire structure is within 2% of the width of the superconducting wire structure, for example within 1%, for example the same as the width of the superconducting wire structure. In various embodiments, the length of the protective dielectric wire structure is within 2% of the length of the superconducting wire structure, for example within 1%, for example the same as the length of the superconducting wire structure.

[0088] In various embodiments, the line structures of the first group are parallel to each other. In various embodiments, the line structures of the first group have the same width, the same length and the same height.

[0089] In various embodiments, the pitch of the individual line structures of the first group may be 30 to 500 nm, for example 100 to 400 nm.

[0090] In various embodiments, the first dielectric material may be selected from silicon nitride and silicon carbonitride, and the second dielectric material may be selected from silicon oxide and high-k oxides, such as aluminum oxide and hafnium oxide. In various embodiments, the first dielectric material is silicon nitride, and the second dielectric material is silicon oxide. Typically, the second dielectric material is the same material as the protective dielectric layer. In various embodiments, the first dielectric material is silicon nitride, the second dielectric material is silicon oxide, and the protective dielectric is silicon oxide. An advantage of these embodiments is that silicon nitride can be selectively etched relative to silicon oxide.

[0091] When the protective dielectric wire structure is present, step a6 stops when the protective dielectric wire structure has been removed.

[0092] In various embodiments, the layer formed of the third dielectric material preferably has a thickness of 1 to 50 nm, such as 2 to 30 nm.

[0093] Preferably, the third dielectric material is an oxide. For example, it may be selected from silicon oxide and high-k oxides, such as hafnium oxide and aluminum oxide. For example, it may include, for example, consist of silicon dioxide.

[0094] Typically, the patterned mask provided in step b. comprises a photoresist mask.

[0095] In various embodiments, the method further comprises, after step a7. and before step b., a step a7'. of forming a hard mask layer over (e.g., on) the first set of line structures, the second dielectric material, and the third dielectric material, wherein in step b., a patterned mask is provided over (e.g., on) the hard mask, wherein in step b1., after step b. and before step c., the pattern of the patterned mask is transferred into the hard mask, wherein in step c., the pattern of the patterned mask is transferred into the first dielectric material and into the layer formed by the third dielectric material, including transferring the pattern from the patterned hard mask layer into the layer formed by the third dielectric material and into the first dielectric material, and wherein step d. further comprises removing the patterned hard mask layer. In these embodiments, the perforated surface is exposed only after removing the patterned mask and the patterned hard mask layer. The removal of the patterned mask of step d. may be performed after step b1. and before step c. The removal of the patterned mask of step d. may be performed after step c and before step e. Preferably, said transferring of the pattern of the patterned mask to the hard mask layer is performed by etching the hard mask selectively with respect to the third dielectric material using the patterned mask as a mask.An advantage of these embodiments is that the third dielectric material may act as an etch stop layer.

[0096] Any hard mask layer / multilayers are suitable as long as it can be removed selectively with respect to the protective dielectric layer (if present) or with respect to the first dielectric material (when the protective dielectric layer is not present).

[0097] In some embodiments, the hard mask may include one or more layers selected from amorphous carbon, spin-on carbon (SOC), spin-on glass (SOG), and spin-on carbon (SiOC).

[0098] In some embodiments, the hard mask may be a thick (15-30 nm) silicon oxide layer, replacing a (typically thinner) protective dielectric layer.

[0099] In various embodiments, in step c., the transferring comprises etching the first dielectric material selectively relative to the second dielectric material. An advantage of these embodiments is that self-alignment of the holes on the underlying superconducting wire structure can be achieved.

[0100] In various embodiments, the perforated surface is a top surface of the third dielectric material obtained after step d.

[0101] In various embodiments, step e. may comprise depositing a second superconducting layer made of a single superconducting material having a critical temperature within 1 K of the first critical temperature above the perforated surface to fill at least one hole extending through the first dielectric material and the layer formed by the third dielectric material, and such that the deposited second superconducting layer is in electrical contact with the first set of superconducting wire structures below, and wherein step f. is performed immediately after step e. These embodiments are particularly advantageous when the density of the holes is below 5%. This density is calculated with reference to the total top surface consisting of the top surface of the second dielectric material and the top surface of the first set of wire structures coplanar therewith. In other words, it is the portion of the total top surface occupied by the holes. It is calculated by dividing the top surface occupied by the holes by the total top surface coplanar therewith. These embodiments are also particularly advantageous when no subsequent entity (see below) is provided, and therefore no more through holes and no more sets of superconducting wire structures are provided. In fact, in these embodiments, as the number of non-planar layers increases, the non-planarity increases to an unacceptable degree.

[0102] An advantage of these embodiments is that the layer of superconducting material deposited in step e. for forming at least one through hole can be used to form the second set of superconducting wire structures, thereby saving superconducting material and reducing the number of steps.

[0103] Preferably, the first superconducting layer and the second superconducting layer are made of the same material.

[0104] In various embodiments, step e. comprises: e1. forming a first portion of the superconducting unit by depositing a second superconducting layer made of a single superconducting material over the perforated surface, thereby forming at least one through hole by filling at least one hole to form at least one through hole, the critical temperature of the single superconducting material being within 1K of the first critical temperature, the at least one through hole extending through the first dielectric material and through the layer formed of the third dielectric material, so that the formed second superconducting layer is in electrical contact with the first set of superconducting wire structures below, e2. flattening the deposited second superconducting layer without removing the at least one through hole so as to remove the top portion of the second superconducting layer, and e3. forming a second portion of the superconducting unit by depositing a third superconducting layer (201) made of a single superconducting material having a critical temperature within 1K of the first critical temperature on the flattened second superconducting layer.

[0105] In various embodiments, the removed top portion exposes the top surface of the third dielectric layer. In such embodiments, all superconducting units are removed except for the vias.

[0106] In other embodiments, the top portion is removed so that the third dielectric layer remains covered by the bottom portion of the second superconducting layer. In these embodiments, the thickness of the top portion is at least equal to the depth of the recess.

[0107] Typically, the top surface of the superconducting unit formed in step e. may include recesses above the through-holes, so that the top surface of the superconducting unit may not be flat. This may be a problem, for example, when multiple alternating superconducting wire structures and through-holes are stacked on each other, for example because recesses that overlap each other may reinforce each other. Therefore, preferably, the superconducting unit has a flat top surface. By first flattening the deposited second superconducting layer and then depositing the third superconducting layer on the flattened superconducting material layer, the resulting superconducting unit does not include these recesses.

[0108] In various embodiments, step e2. comprises using chemical mechanical polishing and / or etching. In various embodiments, the chemical mechanical polishing is selectively performed on the superconducting material relative to the third dielectric material. As a result, all superconducting material extending above the third dielectric material may be removed so that the top surface of the at least one through hole and the top surface of the third dielectric material may be coplanar.

[0109] In various embodiments, the materials forming the first set of superconducting wire structures and the superconducting units are independently selected from MoN, Nb3Sn, NbTi, Nb, NbTiN and NbN. Preferably, the materials forming the first set of superconducting wire structures and the superconducting units are the same. The inventors have found that although these materials have good superconducting properties, these materials may be particularly difficult to deposit in holes or trenches with high aspect ratios.

[0110] In various embodiments, step e. of forming the superconducting unit may be performed by physical vapor deposition.

[0111] Preferably, the first, second and third superconducting layers are made of the same material.

[0112] In various embodiments, at least one hole (and at least one through hole) in the first dielectric material and in the layer formed by the third dielectric material has an aspect ratio of at most 0.5, wherein the aspect ratio is the ratio of the height of the hole (and through hole) in a direction perpendicular to the top surface of the superconducting wire structure to the width of the hole (or through hole) in a direction parallel to the top surface of the superconducting wire structure. In various embodiments, the hole (or through hole) may have an aspect ratio of 0.1 to 0.5, such as 0.10 to 0.40, more preferably 0.15 to 0.35, and even more preferably 0.20 to 0.30. In various embodiments, the height of the hole (or through hole) is 1nm to 100nm, preferably 5nm to 50nm, more preferably 10nm to 25nm. In various embodiments, the width of the hole (or through hole) is 2nm to 200nm, preferably 20nm to 100nm, more preferably 30nm to 70nm. In various embodiments, the length of the hole (or through hole) in the direction parallel to the top surface of the superconducting wire structure and perpendicular to the width is 5nm to 200nm, preferably 10nm to 100nm, more preferably 30nm to 70nm. In various embodiments, the length of the hole (or through hole) is 0.5 to 2 times the width of the hole (or through hole), preferably 0.9 to 1.1 times.

[0113] In various embodiments, the method includes, after step e., providing a second entity above the superconducting unit, comprising the following steps: f. forming a layer of a fourth dielectric material above the superconducting unit, g. removing portions of the layer of the fourth dielectric material and portions of the superconducting unit to form a pattern comprising a second group of wire structures, comprising: a second group of superconducting wire structures and a second group of wire structures made of the fourth dielectric material aligned with and covering the first group of superconducting wire structures, thereby providing the second entity above the first entity.

[0114] In various embodiments, the fourth dielectric material may be the same as the first dielectric material.

[0115] The second set of superconducting wire structures is at a non-zero angle to the first set of superconducting wire structures, preferably at an angle of 80° to 100°, preferably 90°.

[0116] The dimensions of the individual wires of the first set of superconducting wire structures may be the same as or different from the dimensions of the individual wires of the second set of superconducting wire structures.The dimensions of the individual wires of the second set of superconducting wire structures may be as defined for the individual wires of the first set of superconducting wires.

[0117] In each embodiment, each wire structure of the second group of wire structures has a rectangular parallelepiped shape. In each embodiment, each wire structure of the second group of superconducting wire structures has a rectangular parallelepiped shape. In each embodiment, the height of the superconducting wire structure in a direction perpendicular to the top surface of the superconducting wire structure is 20 to 500nm, preferably 30 to 350nm, and more preferably 50 to 200nm. In each embodiment, the width of the superconducting wire structure in a direction parallel to the top surface of the superconducting wire structure is 20 to 500nm, preferably 30 to 350nm, and more preferably 50 to 200nm. In each embodiment, the length of the superconducting wire structure in a direction parallel to the top surface of the superconducting wire structure and perpendicular to the width is at least 200nm, preferably at least 500nm. Here, the length is longer than the width. In each embodiment, the aspect ratio of the wire structure, that is, the ratio between their height and width, is 1 to 4.

[0118] In various embodiments, the sidewall of the superconducting wire structure forms an angle of 85° to 93° with the top surface of the substrate, preferably 88° to 90°, more preferably 89° to 90°. Typically, the angle is 90°.

[0119] In various embodiments, the line structures of the second group are parallel to each other. In various embodiments, the line structures of the second group have the same width, the same length and the same height.

[0120] In various embodiments, the pitch of the individual wire structures of the second group may be 30 to 500 nm, such as 100 to 400 nm.The pitch of the superconducting wire structures of the second group may be the same as or different from the pitch of the superconducting wire structures of the first group.

[0121] In various embodiments, step g. of removing a portion of the layer of fourth dielectric material and a portion of the superconducting unit may be performed by first forming a hard mask (e.g., a layer or a stack of layers) over the layer of fourth dielectric material, then forming a photoresist patterning mask on the hard mask, then etching through the hard mask using the photoresist patterning mask as a mask, thereby transferring the pattern of the photoresist patterning mask to the hard mask, and then etching through the fourth dielectric layer and the superconducting unit using the hard mask as a mask.

[0122] In various embodiments, subsequent entities may be provided after step g by repeating steps b. to g., thereby forming further through holes and further groups of superconducting wire structures. The subsequent groups of superconducting wire structures are at non-zero angles to each other. Preferably, the subsequent groups of superconducting wire structures are at an angle of 80° to 100°, preferably 90°, to each other.

[0123] In each embodiment, the method includes the following steps after step a. and before step b., or after step e. and before step f. (if present): h. providing a third patterned mask above the first entity, the pattern including at least one further opening overlapping with the underlying superconducting wire structure of the first group of superconducting wire structures, for forming at least one further hole in the first dielectric material and the layer formed by the third dielectric material, i. transferring the pattern of the third patterned mask to the first dielectric material and the layer formed by the third dielectric material to form at least one further hole extending through the first dielectric material and the layer formed by the third dielectric material to expose at least a portion of the underlying superconducting wire structure, j. removing the third patterned mask to expose the second perforated surface, and k. depositing a resistive material above the second perforated surface to fill the at least one further hole extending through the first dielectric material and the layer formed by the third dielectric material, and making the deposited resistive material contact the underlying superconducting wire structure, the resistive material having a resistivity of at least 100 μΩ.cm at a temperature of 1K. In some embodiments, the resistor may have no critical temperature or a critical temperature below 1K. An advantage of embodiments of the present invention is that a superconducting interconnect structure including a resistor may be formed, wherein the resistor may connect a superconducting wire structure of a first group of superconducting wire structures to a superconducting wire structure of a second group of superconducting wire structures (if any). In various embodiments, the resistive material is composed of the same chemical elements as the superconducting wire structure of the first group, wherein the chemical composition of the resistive material is different from the chemical composition of the superconducting wire structure of the first group. In other words, the resistive material is composed of the same chemical elements as the superconducting wire structure, but the relative amounts of the chemical elements between the resistive material and the first group of superconducting wire structures are different. By changing the relative amounts of different chemical elements, the critical temperature of the material may be adjusted so that the resistive material has a resistivity of at least 100 μΩ.cm at a temperature of 1K. An advantage of these embodiments is that superconducting vias may be formed using deposition materials and techniques similar to those used to form resistors.

[0124] Most preferably, all superconducting layers or cells and all resistors formed during the method are formed by physical vapour deposition, for example by DC magnetron sputtering.

[0125] Any feature of any embodiment of the first aspect may independently be as correspondingly described for any embodiment of the second aspect of the invention.

[0126] In a second aspect, the invention relates to a superconducting interconnect structure which can be formed by a method according to any one of the preceding claims, the interconnect structure comprising a first entity (44) comprising:

[0127] i. A first set of wire structures (4) having a top surface (420), comprising:

[0128] a first set of superconducting wire structures (41), and

[0129] a first set of wire structures made of a first dielectric material (42), aligned with and overlying the first set of superconducting wire structures (41), and comprising a top surface (420),

[0130] ii. a second dielectric material (50) different from the first dielectric material (42), located between the individual line structures of the first group (4), and having a top surface (51) coplanar with the top surface of the first group of line structures (4), and

[0131] iii. a third dielectric material (6) covering the first set of line structures (4) and the second dielectric material (50),

[0132] and wherein the through hole (81) extends through the first dielectric material (22) and the layer formed by the third dielectric material (6), wherein the through hole (81) comprises superconducting material in physical contact with the underlying superconducting wire structure (21). Any features of any embodiment of the second aspect may be independently as described correspondingly for any embodiment of the first aspect of the invention.

[0133] Any features of the second aspect may be the same as the corresponding description of the first aspect.

[0134] For example, the via, superconducting wire structure can be as follows:

[0135] the at least one through hole (81) in the first dielectric material (22) and the layer formed of the third dielectric material (6) may have an aspect ratio of at most 0.5, such as 0.10 to 0.40, more preferably 0.15 to 0.35, even more preferably 0.20 to 0.30,

[0136] - The height of the superconducting wire structure in a direction perpendicular to the top surface of the superconducting wire structure may be 20 to 500 nm, preferably 50 to 200 nm.

[0137] - The width of the superconducting wire structure in a direction parallel to the top surface of the superconducting wire structure may be 20 to 500 nm, preferably 50 to 200 nm.

[0138] - The length of the superconducting wire structure in a direction parallel to the top surface of the superconducting wire structure and perpendicular to the width is at least 200 nm, preferably at least 500 nm.

[0139] - the aspect ratio of the superconducting wire structures, ie the ratio between their height and width, is 1 to 3, and / or

[0140] The side wall of the superconducting wire structure forms an angle of 85° to 93°, preferably 88° to 90°, more preferably 89° to 90° with the top surface of the substrate. Typically, the angle is 90°.

[0141] The invention will now be described by a detailed description of several embodiments of the invention. Obviously, other embodiments of the invention can be configured according to the knowledge of those skilled in the art without departing from the technical teaching of the invention, and the invention is only limited by the terms of the appended claims.

[0142] Example: Forming superconducting interconnect structures

[0143] refer to Figure 1 . A substrate (1) is provided, which in this example comprises a silicon wafer (11) covered by an insulating layer (12) (e.g. a silicon oxide layer). A superconducting layer (21), e.g. NbTiN, is formed on the substrate 1, which may be deposited by any technique suitable for depositing superconducting materials. Preferably, physical vapour deposition is used to form the superconducting layer (21), as this technique is also well suited to forming vias (see below), which may simplify the manufacture of superconducting interconnect structures. Next, a layer of a first dielectric material (22), e.g. silicon nitride, is formed over the superconducting layer (21). A thin (1-10 nm, e.g. 5 nm) protective silicon oxide layer (not shown) may be present on top of the silicon nitride.

[0144] In this example, a patterned mask (31, 32, 33) including an ashable hard mask (31) is formed over a layer of a first dielectric material (22). The ashable hard mask (31) is a hard mask that can be removed by oxygen plasma. In some cases, such as when the ashable hard mask leaves any residue that cannot be removed by ashing alone, the hard mask can be completely removed by performing an additional wet or dry etching process after ashing. The patterned mask (31, 32, 33) also includes a silicon oxycarbide layer (32) covering the ashable hard mask (31). The patterned mask also includes a patterned photoresist (33) covering the silicon carbide layer (32). First, a pattern of the patterned photoresist (33) including a set of line structures is transferred into the ashable hard mask (31) and into the silicon carbide layer (32) using an etch that selectively etches the ashable hard mask (31) and the silicon carbide layer (32) relative to the patterned photoresist (33) (not shown). Subsequently, the patterned photoresist (33) is removed (not shown). An etch that selectively etches the layer of the first dielectric material (22) and the superconducting layer (21) relative to the ashable hard mask (31) and the silicon oxycarbide layer (32) is performed to transfer the pattern from the ashable hard mask (31) and the silicon oxycarbide layer (32) to the layer of the first dielectric material (22) and the superconducting layer (21) (not shown). As a result, a portion of the layer of the first dielectric material (22) extending from the bottom surface of the superconducting layer (21) to the top surface of the layer of the first dielectric material (22) and a portion of the superconducting layer (21) are removed (not shown). Finally, the ashable hard mask (31) and the silicon carbide layer (32) are removed (not shown).

[0145] refer to Figure 2 A first set of wire structures (4) is formed on the substrate (1) by transferring a pattern into the first dielectric material and the superconducting layer. The first set of wire structures (4) includes a first set of superconducting wire structures (41). In addition, the first set of wire structures (4) includes a first set of wire structures made of a first dielectric material (42), aligned with and covering the first set of superconducting wire structures (41). The first set of wire structures (4) includes a top surface (420), i.e., the top surface (420) of the first set of wire structures made of the first dielectric material (42).

[0146] refer to Figure 3 A second dielectric material (50) different from the first dielectric material is formed above (eg, on) and between the individual line structures of the first set of line structures (4). The second dielectric material (50) may be, for example, silicon oxide.

[0147] refer to Figure 4The second dielectric material (50) is planarized so that a top surface (51) of the second dielectric material (50) is coplanar with a top surface (420) of the first set of line structures made of the first dielectric material (42). For example, chemical mechanical polishing may be used, wherein the polishing is selective to the second dielectric material (50) relative to the first dielectric material (42).

[0148] refer to Figure 5 A layer formed of a third dielectric material (6) is formed above the first set of line structures (4), in this example, on the top surface of the first set of line structures made of the first dielectric material (42), and above the second dielectric material (50), for example thereon. Thus, a first entity is formed, which includes the first set of line structures (4), the second dielectric material (50) between the individual line structures of the first set of line structures (4), and a layer formed of the third dielectric material (6).

[0149] refer to Figure 6 . In order to form vias in the layer formed by the third dielectric material (6) and in the first group of wire structures (42) made of the first dielectric material (42), first, a spin-on carbon layer (71) is deposited above the layer formed by the third dielectric material (6), for example, thereon. Next, a spin-on glass layer (72) is formed above the spin-on carbon layer (71), for example, thereon. Although this example specifically describes spin-on carbon and spin-on glass, different masks, such as hard masks, may also be used. A mask that is selectively etchable relative to the third dielectric material (6) is used so that the third dielectric material (6) can act as an etch stop layer. Finally, a photoresist mask is deposited above the spin-on glass layer (72), for example, thereon, and then it is patterned to form a patterned photoresist mask (73). The patterned photoresist mask (73) includes at least one opening (730) (six openings in this example) that overlaps with the underlying superconducting wire structure of the first group of superconducting wire structures (41). Each opening 730 is used to form a hole in the first dielectric material (42) and the third dielectric material (6). The pattern of the patterned photoresist mask (73) is transferred to the spin-on-glass layer (72) and the spin-on-carbon layer (71). In this example, etching is used, which selectively etches the spin-on-glass layer (72) and the spin-on-carbon layer (71) relative to the patterned photoresist mask (73) and the third dielectric material (6). In this way, the third dielectric material (6) acts as an etch stop layer, that is, the etching of the spin-on-glass layer (72) and the spin-on-carbon layer (71) can stop at the third dielectric material (6). In this example, the patterned photoresist mask (73) and the patterned spin-on-glass layer (72) are subsequently removed.

[0150] refer to Figure 7The pattern of the patterned spin-on carbon layer (71) above the first entity (44) can be transferred into the layer formed by the third dielectric material (6) and the first dielectric material (42) to form a hole (43) extending through the layer formed by the third dielectric material (6) and through the first dielectric material (42). As a result, a portion of the underlying superconducting wire structure (41) is exposed. Preferably, an etch is used that selectively etches the first dielectric material (41), such as silicon nitride, relative to the second dielectric material (50), such as silicon oxide. As a result, self-alignment of the hole (43) on the superconducting wire structure (41) can be achieved.

[0151] refer to Figure 8 In this example, the patterned spin-on carbon layer (71) is removed selectively relative to the third dielectric material (6), thereby exposing the perforated surface, which in this example is the top surface (60) of the third dielectric material (6) perforated by the holes (43).

[0152] refer to Fig. 9 A layer of superconducting material (8) is formed over the perforated surface, in this example, over the top surface of the third dielectric material (6), so as to form a through hole (81) by filling at least one hole. The superconducting material (8) is deposited so that the superconducting material (8) is in electrical contact, such as physical contact, with the exposed underlying superconducting wire structure (41).

[0153] For superconducting materials (8) such as MoN, Nb3Sn, NbTi, Nb, NbTiN and NbN, the deposition may include pits (82) covering the through holes (81), so that it is possible for a non-planar superconducting layer to be formed over the perforated surface. Fig.10 . In order to provide a planar superconducting layer above the perforated surface, the deposited superconducting material layer can be planarized to remove the top portion of the superconducting material layer without removing the portion of the superconducting material layer that fills at least one hole, i.e., the through hole (81). In this example, all of the deposited superconducting material extending above the perforated surface (60) is removed so that the top surface of the through hole (81) is coplanar with the top surface of the third dielectric material (6). For example, chemical mechanical polishing can be performed, which selectively polishes the deposited superconducting material relative to the third dielectric material (6), so that the polishing can stop at the third dielectric material (6). Alternatively, etching can be used. In addition, the removal of the superconducting material layer can be limited to the top portion of the superconducting material layer. This can result in the formation of a planar superconducting material layer on the perforated surface.

[0154] refer to Fig.11 To form the second entity, in this example, stacking, similar to Figure 1The stack deposited on the substrate in the embodiment of the present invention is deposited on the perforated surface, i.e., the top surface of the third dielectric material (6). To this end, first, when (as in this example) it does not exist (or is not thick enough), another superconducting material layer (201) is deposited in physical contact with the through hole (81). The superconducting material layer (201) preferably includes the same superconducting material as the through hole (81) and the superconducting wire structure (41). A layer of a fourth dielectric material (202) which may be the same as the first dielectric material is deposited above, for example, the layer of the further superconducting material (201), for example, on it. In this example, a patterned mask including an ashable hard mask (301) is formed above the layer of the fourth dielectric material (202). The patterned mask also includes a silicon oxycarbide layer (302) covering the ashable hard mask (301). The patterned mask also includes a patterned photoresist (303) covering the silicon carbide layer (32). The patterned photoresist (303) includes individual line structures for forming a second group of line structures, the second group of line structures including a second group of superconducting wire structures formed by the further superconducting material layer (201) and a second group of line structures made of a fourth dielectric material (202). Here, the line structures of the patterned photoresist (303) are oriented so that the second group of line structures are oriented at a certain angle (e.g., perpendicular) relative to the first group of line structures. Steps similar to the above steps for forming the first entity can be used to form the second entity.

[0155] It is understood that although preferred embodiments, specific structures and configurations, and materials have been discussed herein for the apparatus according to the present invention, various changes or modifications in form and detail may be made without departing from the scope of the present invention. Steps may be added or deleted from the method within the scope of the present invention.

Claims

1. A method for forming a superconducting interconnect structure for an integrated circuit, comprising: a. forming a first entity (44) on a substrate (1) by the following steps: a1. Providing a substrate (1), a2. forming a first superconducting layer (21) of a first superconducting material having a first critical temperature on the substrate (1), a3. forming a layer of a first dielectric material (22) above the first superconducting layer (21), a4. removing portions of the layer of the first dielectric material (22) and portions of the first superconducting layer (21), the portions extending from the bottom surface of the first superconducting layer (21) to the top surface of the first dielectric material (22) to form a pattern comprising a first set of line structures (4) having a top surface (420), the first set of line structures (4) comprising: a first set of superconducting wire structures (41), and a first set of wire structures made of the first dielectric material (42), aligned with and overlying the first set of superconducting wire structures (41), and comprising a top surface (420), a5. forming a second dielectric material (50) different from the first dielectric material above and between each line structure of the first group of line structures (4), a6. planarizing the second dielectric material (50) so that the top surface (51) of the second dielectric material is coplanar with the top surface (420) of the first set of line structures (4), and thereafter a7. forming a layer formed of a third dielectric material (6) over the first set of line structures (4) and the second dielectric material (50), thereby forming said first entity (44), b. providing a patterned mask (73) above the first entity, the pattern comprising at least one opening (730) overlapping with an underlying superconducting wire structure of the first set of superconducting wire structures (41) for forming at least one hole (43) in the first dielectric material (42) and in the layer formed by the third dielectric material (6), cc transferring the pattern of the patterned mask (73) into the first dielectric material (42) and the layer formed by the third dielectric material (6) to form at least one hole (43) extending through the first dielectric material (42) and the layer formed by the third dielectric material (6) to expose a portion of the underlying superconducting wire structure (41), d. removing the patterned mask (73) thereby exposing the perforated surface (60), and e. forming a superconducting unit (81, 201, 8) made of one or more superconducting materials above the perforated surface (60), each superconducting material having a critical temperature within 1K of the first critical temperature, thereby also forming at least one through hole (81) by filling the at least one hole (43), the at least one through hole (81) extending through the first dielectric material (42) and the layer formed by the third dielectric material (6), so that the formed superconducting unit (81, 201, 8) physically contacts the first group of superconducting wire structures (41) below.

2. The method according to claim 1, characterized in that: Also included after step a7. and before step b.: a7′: forming a hard mask layer (71, 72) over the first group of line structures (41), the second dielectric material (50) and the third dielectric material (6), wherein in step b., the patterned mask (73) is provided above the hard mask layer (71, 72), wherein in step b1., after step b. and before step c., the pattern of the patterned mask (73) is transferred into the hard mask layer (71, 72), wherein in step c, transferring the pattern of the patterned mask (73) to the first dielectric material (42) and the layer formed by the third dielectric material (6) comprises transferring the pattern from the patterned hard mask layer (71, 72) to the layer formed by the third dielectric material (6) and the first dielectric material (42), and Wherein step d. further comprises removing the patterned hard mask layer (71, 72).

3. The method according to claim 1 or 2, characterized in that: After step e., providing a second entity above the superconducting unit (81, 201, 8), comprising the following steps: f. forming a layer of a fourth dielectric material (202) above the superconducting unit (81, 201, 8), g. removing portions of the layer of the fourth dielectric material (202) and portions of the superconducting unit (81, 201, 8) to form a pattern comprising a second set of line structures, comprising: A second set of superconducting wire structures, and A second set of wire structures made of the fourth dielectric material is aligned with and overlies the second set of superconducting wire structures to provide the second entity above the first entity.

4. The method according to claim 3, characterized in that Step e. comprises depositing a second superconducting layer (8) made of a single second superconducting material having a critical temperature within 1K of the first critical temperature above the perforated surface (60) to fill at least one hole (43) extending through the first dielectric material (42) and the layer formed by the third dielectric material (6), and making the deposited second superconducting layer (8) physically contact the first set of superconducting wire structures (41) below, and wherein step f. is performed immediately after step e.

5. The method according to any one of the preceding claims, characterized in that Step e. includes: e1. forming a first portion (81) of the superconducting unit (81, 201) by depositing a second superconducting layer (8) made of a single superconducting material having a critical temperature within 1K of a first critical temperature over the perforated surface (60) to form at least one through hole (81) by filling the at least one hole (43), the at least one through hole (81) extending through the first dielectric material (22) and through the layer formed of the third dielectric material (6), so that the formed second superconducting layer (8) physically contacts the first set of superconducting wire structures (41) below, e2. planarizing the deposited second superconducting layer (8) without removing the at least one through hole (81) so as to remove the top portion of the second superconducting layer (8), and e3. The second part (201) of the superconducting unit (81, 201) is formed by depositing a third superconducting layer (201) made of a single third superconducting material having a critical temperature within 1K of the first critical temperature on the flattened second superconducting layer (8).

6. The method according to claim 5, characterized in that Step e2. comprises using chemical mechanical polishing and / or etching.

7. The method according to any one of the preceding claims, characterized in that The materials forming the first group of superconducting wire structures (41) and the superconducting units (81, 201, 8) are independently selected from MoN, Nb3Sn, NbTi, Nb, NbTiN and NbN.

8. The method according to any one of the preceding claims, characterized in that The at least one hole (43) in the first dielectric material (22) and the layer formed of the third dielectric material (6) has an aspect ratio of at most 0.

5.

9. The method according to any one of the preceding claims, characterized in that The following steps are included after step a. and before step b., or, if present, after step e. and before step f.: h. providing a third patterned mask over the first entity, the pattern comprising at least one further opening overlapping with a lower superconducting wire structure (21) of the first set of superconducting wire structures (21) for forming at least one further hole in the first dielectric material (22) and in the layer formed by the third dielectric material (6), i. transferring the pattern of the third patterned mask into the first dielectric material and the layer formed by the third dielectric material (6) to form at least one further hole extending through the first dielectric material and the layer formed by the third dielectric material (6) to expose a portion of the underlying superconducting wire structure (21), j. removing the third patterned mask to expose the second perforated surface, and k. depositing a resistive material over the second perforated surface to fill at least one further hole extending through the first dielectric material (22) and the layer formed by the third dielectric material (6), and such that the deposited resistive material physically contacts the underlying superconducting circuit structure (21), the resistive material having a resistivity of at least 100 μΩ.cm at a temperature of 1 K.

10. The method according to claim 9, characterized in that The resistive material comprises the same chemical elements as the superconducting wire structure (21), wherein the chemical composition of the resistive material is different from the chemical composition of the first superconducting material.

11. The method according to any one of the preceding claims, characterized in that The first dielectric material (22) is silicon nitride, and wherein the second dielectric material (50) is silicon oxide.

12. The method according to any one of the preceding claims, characterized in that Step e. comprises the step of depositing said layer of superconducting material (8) by physical vapour deposition.

13. The method according to claim 12, characterized in that Step a2. is performed by physical vapor deposition.

14. A superconducting interconnect structure that can be formed by the method of claim 1, the interconnect structure comprising a first entity (44), the first entity comprising: i. A first set of wire structures (4) having a top surface (420), comprising: a first set of superconducting wire structures (41), and a first set of wire structures made of a first dielectric material (42), aligned with and overlying the first set of superconducting wire structures (41), and comprising a top surface (420), ii. a second dielectric material (50) different from the first dielectric material (42), located between the individual line structures of the first group (4), and having a top surface (51) coplanar with the top surface of the first group of line structures (4), and iii. a third dielectric material (6) covering the first set of line structures (4) and the second dielectric material (50), and wherein a via (81) extends through the first dielectric material (22) and the layer formed by the third dielectric material (6), wherein the via (81) comprises superconducting material that physically contacts an underlying superconducting wire structure (21).

15. The superconducting interconnect structure according to claim 14, characterized in that: The at least one through hole (81) in the first dielectric material (22) and the layer formed of the third dielectric material (6) has an aspect ratio of at most 0.5.

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