Conversion circuit, electronic device and operation method

Abstract

A conversion circuit, an electronic device and an operating method, the conversion circuit comprising a front-end resistance-capacitance circuit and a modulation circuit, the front-end resistance-capacitance circuit being coupled to the modulation circuit; the front-end resistor-capacitor circuit comprises a capacitor to be measured and is configured to output a current phase shift corresponding to the capacitor to be measured under the driving of the first differential frequency signal; the modulation circuit is configured to modulate the current phase shift and output a digital signal. According to the conversion circuit, a wider measurement range can be realized, and external common-mode interference can be better inhibited.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a conversion circuit, an electronic device, and an operating method. Background Art

[0002] In high-precision sub-nanometer mechatronic systems, the positions of key parts need to be accurately located. However, due to the complexity of the working environment, it is not practical to manually adjust a component in engineering. Therefore, it is necessary to design a displacement sensor with sufficiently high accuracy. At the same time, in order to measure displacement over a wide range, requirements are placed on the dynamic range of the sensor.

[0003] In the complex environment of industrial production, many external factors need to be considered. In wireless, battery-powered applications, a high-efficiency system is required. At the same time, low-frequency and high-frequency interference from the external environment will couple into the readout circuit, affecting the accuracy of the measurement. In addition, the parasitic capacitance on the electrode plate to be measured will also reduce the accuracy. Therefore, it is necessary to design a capacitive displacement sensor chip with high energy efficiency, external interference suppression, and parasitic capacitance suppression. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a conversion circuit, which includes: a front-end resistor-capacitor circuit and a modulation circuit, wherein the front-end resistor-capacitor circuit is coupled to the modulation circuit; the front-end resistor-capacitor circuit includes a capacitor to be measured, and is configured to output a current phase shift corresponding to the capacitor to be measured under the drive of a first differential frequency signal; the modulation circuit is configured to modulate the current phase shift and output a digital signal.

[0005] For example, in the conversion circuit provided by at least one embodiment of the present disclosure, the capacitor to be measured includes a first capacitor and a second capacitor; the first differential frequency signal includes a first frequency signal and a second frequency signal, and the first frequency signal and the second frequency signal are inverted; the front-end resistor-capacitor circuit also includes: a first resistor, a second resistor, a third resistor and a fourth resistor; the first end of the first resistor is electrically connected to the first pole of the first capacitor, the first end of the second resistor is electrically connected to the first pole of the second capacitor, the second pole of the first capacitor is electrically connected to the second pole of the second capacitor, the first end of the third resistor is connected to the first node between the first capacitor and the first resistor, the first end of the fourth resistor is connected to the second node between the second capacitor and the second resistor, the second end of the third resistor is connected to the first frequency signal, and the second end of the fourth resistor is connected to the second frequency signal.

[0006] For example, in the conversion circuit provided in at least one embodiment of the present disclosure, the front-end resistor-capacitor circuit is coupled to the modulation circuit, including: the first input end of the modulation circuit is electrically connected to the second end of the first resistor, and the second input end of the modulation circuit is electrically connected to the second end of the second resistor to couple with the front-end resistor-capacitor circuit.

[0007] For example, the conversion circuit provided by at least one embodiment of the present disclosure also includes: a resistor-capacitor compensation circuit, which is connected to the same node as the front-end resistor-capacitor circuit to couple with the modulation circuit, and the resistor-capacitor compensation circuit is configured to be driven by a second differential frequency signal, and the second differential frequency signal has an opposite polarity to the first differential frequency signal.

[0008] For example, in the conversion circuit provided by at least one embodiment of the present disclosure, the resistance-capacitance compensation circuit includes: a first adjustable capacitor, a second adjustable capacitor, a first compensation resistor, a second compensation resistor, a third compensation resistor and a fourth compensation resistor; the first end of the first compensation resistor is electrically connected to the first pole of the first adjustable capacitor, the first end of the second compensation resistor is electrically connected to the first pole of the second adjustable capacitor, the second pole of the first adjustable capacitor and the second pole of the second adjustable capacitor are electrically connected and connected to the first voltage end, the first end of the third compensation resistor is connected to the third node between the first adjustable capacitor and the first compensation resistor, the first end of the fourth compensation resistor is connected to the fourth node between the second adjustable capacitor and the second compensation resistor, the second end of the third compensation resistor is connected to the second frequency signal, and the second end of the fourth compensation resistor is connected to the first frequency signal.

[0009] For example, in the conversion circuit provided by at least one embodiment of the present disclosure, the modulation circuit includes an integrator, an input chopper and an output chopper; the integrator includes a first-stage integrator and a second-stage integrator; the input end of the first-stage integrator is connected to the front-end resistor-capacitor circuit, and the first-stage integrator and the second-stage integrator are cascaded to form a second-order integrator; the first-stage integrator includes an integrating capacitor and an amplifying circuit, and the amplifying circuit includes a first-stage operational amplifier, a second-stage operational amplifier and a feedforward-stage operational amplifier; the first-stage operational amplifier is cascaded with the second-stage operational amplifier, and the output end of the feedforward-stage amplifier is electrically connected to the output end of the second-stage operational amplifier; the first end of the integrating capacitor is electrically connected to the input end of the first-stage operational amplifier, and the second end of the integrating capacitor is electrically connected to the output end of the second-stage operational amplifier; the first-stage operational amplifier adopts a common source and common gate structure, and the drain of the first-stage operational amplifier is electrically connected to the output chopper; the input chopper is electrically connected to the first end of the integrating capacitor and is multiplexed as a demodulator.

[0010] For example, in the conversion circuit provided by at least one embodiment of the present disclosure, the input end of the feedforward stage operational amplifier is electrically connected to the first end of the integrating capacitor.

[0011] For example, in the conversion circuit provided in at least one embodiment of the present disclosure, the input end of the feedforward stage operational amplifier is electrically connected to the input end of the first stage operational amplifier, and the modulation circuit also includes an intermediate chopper; the intermediate chopper is electrically connected to the input end of the feedforward stage operational amplifier.

[0012] For example, the conversion circuit provided by at least one embodiment of the present disclosure also includes: a comparator and a phase selector; the input end of the comparator is electrically connected to the output end of the integrator, the output end of the comparator is electrically connected to the input end of the phase selector, the comparator is configured to sample the signal output by the integrator to obtain an output signal, and feed the output signal back to the input end of the phase selector; the input end of the phase selector is electrically connected to the output end of the comparator, the output end of the phase selector is electrically connected to the input chopper and the output chopper respectively, the phase selector is configured to select a reference phase signal, and obtain a phase error signal based on the output signal and the reference phase signal, so as to feed the phase error signal back to the integrator.

[0013] For example, in the conversion circuit provided by at least one embodiment of the present disclosure, the second-stage integrator includes a transconductance-capacitance integrator.

[0014] For example, the conversion circuit provided by at least one embodiment of the present disclosure further includes: an on-chip reference frequency source, wherein the on-chip reference frequency source is configured to generate a reference frequency signal and generate the first differential frequency signal based on the reference frequency signal.

[0015] At least one embodiment of the present disclosure further provides an electronic device, which includes the conversion circuit provided by at least one embodiment of the present disclosure.

[0016] For example, the electronic device provided by at least one embodiment of the present disclosure further includes an electrode plate, a first side of which is electrically connected to the capacitor to be measured so as to be coupled to the front-end resistor-capacitor circuit.

[0017] At least one embodiment of the present disclosure also provides an operating method for an electronic device, the operating method comprising: obtaining a first digital signal output by the conversion circuit when there is no displacement change of the electrode plate; obtaining a second digital signal output by the conversion circuit after the electrode plate undergoes a displacement change; determining a change amount of the first digital signal and the second digital signal, and determining a magnitude of the displacement change based on a mapping relationship between the change amount and capacitance and displacement. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0019] Figure 1A A schematic diagram of a capacitive displacement sensor (Single-ended CDC) using a single-point detection structure;

[0020] Figure 1B A schematic diagram of a capacitive displacement sensor (Pseudo-differential CDC) using a double-end input structure;

[0021] Figure 2 A schematic block diagram of a conversion circuit provided in at least one embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of a conversion circuit provided by at least one embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of an amplifier circuit provided in at least one embodiment of the present disclosure;

[0024] Figure 5 A schematic block diagram of another conversion circuit provided for at least one embodiment of the present disclosure;

[0025] Figure 6 A schematic diagram of another conversion circuit provided by at least one embodiment of the present disclosure;

[0026] Figure 7 A schematic diagram of a frequency source for generating a reference frequency signal provided by at least one embodiment of the present disclosure;

[0027] Figure 8 A schematic diagram of a basic timing sequence of a frequency source circuit for generating a reference frequency signal provided by at least one embodiment of the present disclosure;

[0028] Fig. 9 A schematic diagram of a chopper error amplifier and a notch filter provided in at least one embodiment of the present disclosure;

[0029] Fig.10 A schematic diagram of suppressing external common-mode noise interference by a conversion circuit provided by at least one embodiment of the present disclosure;

[0030] Fig.11 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure; and

[0031] Fig.12 The present invention is a flowchart of an operating method of an electronic device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components (elements) may be omitted. When any component (component) of the embodiments of the present disclosure appears in more than one drawing, the component (component) is represented by the same or similar reference numeral in each drawing.

[0035] The current sensor circuits can be roughly divided into two technical solutions: eddy-current sensors (ECS) and capacitive displacement sensors. Eddy-current sensors have good robustness and stability, and are less affected by temperature, humidity, electromagnetic interference, etc., but there are also some problems. For example, in order to eliminate the skin effect and obtain sufficiently high accuracy, a very high excitation frequency (>100MHz) is required, which causes this structure to consume very large power and also leads to adverse effects caused by self-heating effects; capacitive displacement sensors use passive components on the chip as the front end, and the readout circuit processes the signals input by the front end, such as voltage, current, phase, frequency, etc. The advantage of this solution is that it is more power-efficient and area-friendly, but the disadvantage is that the absolute accuracy of the passive components on the chip is poor and is easily affected by temperature changes.

[0036] Figure 1AThis is a schematic diagram of a capacitive displacement sensor (Single-ended CDC) using a single-point detection structure. Figure 1A As shown in the figure, the capacitance Cs to be measured is formed between a single probe and the electrode plate to be measured. The probe is an active part of the capacitive displacement sensor and is usually connected to the object to be measured. When the probe moves relative to the electrode plate to be measured, the distance d between them changes, resulting in a change in the capacitance value to be measured. By measuring the change in capacitance, the displacement can be inferred. However, this single-point detection structure causes the floating target node to have no clear potential. If there is a parasitic capacitance Cp between the electrode plate to be measured and the external environment, it will cause external noise charge Q N and the useful signal charge Q S , then the measured capacitance, parasitic capacitance and readout circuit form a loop, and the measured capacitance is the series connection of the measured capacitance and the parasitic capacitance; in addition, external electromagnetic interference will couple to the input end of the readout circuit. Both of these will cause the performance of the sensor to deteriorate.

[0037] Figure 1B This is a schematic diagram of a capacitive displacement sensor (Pseudo-differential CDC) with a dual-end input structure. Figure 1B As shown in the figure, the dual-end input structure solves the above-mentioned parasitic capacitance Cp and floating detection problems; for the suppression of external interference, it is necessary to ensure that the capacitances to be measured at both ends, namely Cs1 and Cs2, match. This structure reduces the impact of external interference by averaging multiple probes, but the circuit does not have measures designed to suppress common-mode interference in the presence of mismatch.

[0038] There are some solutions that achieve wide-range capacitance / resistance measurement by providing multiple current values ​​to the front-end circuit. However, the disadvantage is that multi-range measurement reduces the linearity of the transfer curve and the signal-to-noise ratio (SNR) of the measurement.

[0039] The present disclosure provides a conversion circuit, comprising: a front-end resistor-capacitor circuit and a modulation circuit, wherein the front-end resistor-capacitor circuit is coupled to the modulation circuit; the front-end resistor-capacitor circuit comprises a capacitor to be measured, and is configured to output a current phase shift corresponding to the capacitor to be measured under the drive of a first differential frequency signal; the modulation circuit is configured to modulate the current phase shift and output a digital signal.

[0040] The conversion circuit provided in at least one embodiment of the present disclosure can output a wider current phase shift variation range by setting a front-end resistor-capacitor circuit, thereby achieving a wider measurement range; and, by respectively realizing low-frequency and high-frequency filtering through the front-end resistor-capacitor circuit and the modulation circuit, external common-mode interference can be better suppressed.

[0041] Figure 2 A schematic block diagram of a conversion circuit provided in at least one embodiment of the present disclosure.

[0042] For example, Figure 2 As shown, the conversion circuit 100 includes a front-end resistor-capacitor circuit 101 and a modulation circuit 102, and the front-end resistor-capacitor circuit 101 is coupled to the modulation circuit 102. The front-end resistor-capacitor circuit 101 includes a capacitor to be measured, and is configured to output a current phase shift corresponding to the capacitor to be measured under the drive of a first differential frequency signal; the modulation circuit 102 is configured to modulate the current phase shift and output a digital signal.

[0043] For example, the front-end resistor-capacitor circuit can generate a current phase shift (phase offset) related to the capacitance value to be measured under the drive of the first differential frequency signal. For example, the magnitude of the current phase shift is proportional to the capacitance value to be measured. In some examples, the front-end resistor-capacitor circuit can include a first-order current mode low-pass filter composed of a passive RC (resistance and capacitance).

[0044] For example, the modulation circuit can convert a continuously changing analog signal (such as the above-mentioned current phase shift) into a discrete digital signal. The modulation circuit can be, for example, a first-order phase domain continuous time Delta-Sigma modulator, a second-order phase domain continuous time Delta-Sigma modulator, etc., and the embodiments of the present disclosure are not limited to this.

[0045] For example, the digital signal may include a bit stream or other forms of discrete time signals, which are not limited in the embodiments of the present disclosure. The digital signal output by the modulation circuit may be read and analyzed by the digital signal processing unit, thereby achieving measurement of the capacitance value to be measured.

[0046] For example, the first differential frequency signal includes a signal form that represents information through the difference between two frequency signals. The first differential frequency signal can be provided by an external circuit or by other modules built into the conversion circuit, which is not limited in the embodiment of the present disclosure.

[0047] The conversion circuit provided in the above embodiment of the present disclosure realizes the suppression of external common-mode interference. The external common-mode interference will pass through the front-end resistor-capacitor circuit and the modulation circuit in sequence. The front-end resistor-capacitor circuit acts as a high-pass network and can filter low-frequency interference; the modulation circuit has an anti-aliasing effect and can be regarded as a low-pass filter that can filter input high-frequency interference. Therefore, the conversion circuit provided in the above embodiment of the present disclosure can suppress external common-mode low-frequency and high-frequency interference.

[0048] Figure 3 A schematic diagram of a conversion circuit provided according to at least one embodiment of the present disclosure. Figure 3 for Figure 2 A specific example of the conversion circuit shown.

[0049] For example, Figure 3 As shown, the conversion circuit 200 includes a front-end resistor-capacitor circuit 201 and a modulation circuit 202, and the front-end resistor-capacitor circuit 201 is coupled to the modulation circuit 202. The front-end resistor-capacitor circuit 201 includes a capacitor C to be measured. S1 and C S2 , and is configured as a differential frequency signal at the first and Under driving, the output capacitance C to be measured S1 and C S2 The corresponding current phase shift; the modulation circuit 202 adopts a second-order phase domain continuous time Delta-Sigma modulator (PD-DSM) scheme, and is configured to modulate the current phase shift and output a digital signal BS.

[0050] For example, Figure 3 As shown, in the front-end resistor-capacitor circuit 201, the capacitor to be measured includes a first capacitor C S1 and the second capacitor C S2 ; The first differential frequency signal includes a first frequency signal and the second frequency signal , the first frequency signal and the second frequency signal Invert.

[0051] For example, Figure 3 As shown, the front-end resistor-capacitor circuit 201 also includes a first resistor R S1 , the second resistor R S2 , the third resistor R S3 and the fourth resistor R S4 The first resistor R S1 ~The fourth resistor R S4 Each of them includes a first terminal and a second terminal, a first capacitor C S1 and the second capacitor C S2 Each of the first and second electrodes includes a first resistor R S1 The first end of the first capacitor C S1 The first electrode is electrically connected to the second resistor R S2 The first end and the second capacitor C S2 The first electrode is electrically connected to the first capacitor C S1 The second electrode and the second capacitor C S2 The second pole is electrically connected to the third resistor R S3 The first end is connected to the first capacitor C S1 and the first resistor R S1 The first node N1 between the fourth resistor RS4 The first end is connected to the second capacitor C S2 and the second resistor R S2 The second node N2 between the third resistor R S3 The second end is connected to the first frequency signal , the fourth resistor R S4 The second end of the second frequency signal is connected .

[0052] For example, the values ​​of the first capacitor and the second capacitor may be equal, and the capacitance value of the capacitor to be measured may be equal to the value of the first capacitor or the second capacitor.

[0053] For example, the resistance values ​​of the first resistor, the second resistor, the third resistor, and the fourth resistor may be equal.

[0054] For example, the front-end resistor-capacitor circuit is a first-order current mode low-pass filter composed of a passive RC (resistor-capacitor). Under the drive of the first differential frequency signal, the output current phase shift is obtained as shown in formula (1):

[0055]

[0056] in, is the resistance value in the front-end resistor-capacitor circuit (i.e., the value of the first resistor, the second resistor, the third resistor, or the fourth resistor), and Cs is the capacitance value to be measured (i.e., the value of the first capacitor or the second capacitor).

[0057] For example, Figure 3 As shown, the first input terminal I1 of the modulation circuit 202 is connected to the first resistor R S1 The second end (not connected to the first capacitor C S1 The second input terminal I2 of the modulation circuit 202 is electrically connected to the second resistor R S2 The second end of is electrically connected to be coupled to the front-end resistor-capacitor circuit 201, thereby forming a closed loop. Under the action of negative feedback, the feedback phase of the modulation circuit is orthogonal to the input current phase determined by the capacitor to be measured, and the mean value of the bit stream is stable and corresponds one-to-one with the capacitor to be measured.

[0058] For example, the modulation circuit may include an integrator, an input chopper, and an output chopper. Figure 3 As shown, the modulation circuit 202 includes an integrator, an input chopper 202a and an output chopper 202b, the integrator includes a first-stage integrator 2021 and a second-stage integrator 2022; the input end of the first-stage integrator 2021 is connected to the front-end resistor-capacitor circuit 201, and the first-stage integrator 2021 and the second-stage integrator 2022 are cascaded to form a second-order integrator; the first-stage integrator includes an integral capacitor C int1 and amplifier circuits.

[0059] The modulation circuit provided by the embodiment of the present disclosure adopts a second-order feedforward scheme, and the first-stage integrator adopts an active integrator, which can make the input point of the modulation circuit a low-resistance virtual ground point and reduce the phase error. The integration capacitor uses a large capacitor, such as a 64pF capacitor, to reduce the output swing of the first-stage integrator and ensure the linearity of the second-stage integrator. For the sake of simplicity, the second-stage integrator can use, for example, a transconductance-capacitance (gm-C) integrator structure. The feedforward coefficient c1 and the integration coefficient c2 are respectively expressed as:

[0060]

[0061] in, is the transconductance of the second-stage integrator, is the sampling frequency, is the capacitance of the gm-C integrator.

[0062] For example, Figure 3 The modulation circuit 202 shown may further include a comparator 2023 and a phase selector 2024 .

[0063] For example, Figure 3 As shown, the input end of the comparator 2023 and the output end of the integrator (i.e. Figure 3 The output end of the comparator 2023 is electrically connected to the input end of the phase selector 2024. The comparator 2023 is configured to sample the signal output by the integrator to obtain an output signal, and feed the output signal back to the input end of the phase selector 2024.

[0064] For example, Figure 3 As shown, the input end of the phase selector 2024 is electrically connected to the output end of the comparator 2023, and the output end of the phase selector 2024 is electrically connected to the input chopper 202a and the output chopper 202b respectively. The phase selector 2024 is configured to select a reference phase signal, obtain a phase error signal based on the output signal and the reference phase signal, and feed the phase error signal back to the integrator.

[0065] The specific working principle of the above modulation circuit is: the chopper demodulator receives the current phase shift output by the front-end resistor-capacitor circuit, and selects the reference phase according to the phase selector. , controls the polarity of the integrated current. In a sampling cycle, the DC part of the current integration is positive or negative. Since the modulation circuit has a large loop gain, when it finally stabilizes, the average integrated current is 0. At this time, the average phase of the phase selector output is orthogonal to the input phase shift, and the average value of the bit stream represents the current phase shift of the front-end resistor-capacitor circuit input and the capacitance value to be measured.

[0066] For example, the reference phase of the phase selector in the embodiment of the present disclosure is , can be 90 degrees and 180 degrees to achieve a higher capacitance measurement range.

[0067] Figure 4 A schematic diagram of an amplifier circuit provided according to at least one embodiment of the present disclosure. Figure 4 for Figure 3 A specific example of the amplifier circuit in the first-stage integrator in the modulation circuit shown.

[0068] For example, Figure 4 As shown, the amplifier circuit is arranged in the first stage integrator, which is a two-stage common source and common gate amplifier of feedforward compensation, and is used to provide a larger loop gain for the entire loop to ensure the accuracy of negative feedback.

[0069] For example, Figure 4 As shown, the amplifier circuit includes a first-stage operational amplifier gm1, a second-stage operational amplifier gm2, and a feedforward operational amplifier gm3. The first-stage operational amplifier gm1 is cascaded with the second-stage operational amplifier gm2, and the output end of the feedforward amplifier gm3 is electrically connected to the output end of the second-stage operational amplifier gm2. The first-stage operational amplifier gm1 adopts current multiplexing and common source and common gate technology. The two ends of bc are the input ends of the first-stage operational amplifier gm1, and Figure 3 Integral capacitor C int1 The first end is electrically connected to the

[0070] For example, Figure 4 As shown, the first-stage operational amplifier gm1 uses both PMOS and NMOS transistors as inputs. Under the same current, it can achieve a larger transconductance than a single input transistor, which is beneficial for reducing thermal noise. For better energy efficiency, the second-stage operational amplifier gm2 and the third-stage operational amplifier gm3 use the same current multiplexing structure.

[0071] For common mode stability, e.g. Figure 4 As shown, common-mode feedback circuits (CMFB1 and CMFB3) are used at the output end (gh) of the first-stage operational amplifier gm1 and the output ends (ef) of the second and third-stage operational amplifiers. Since the third-stage operational amplifier gm3 uses a larger current, the second common-mode feedback circuit (CMFB3) is fed back to the PMOS current source tube of the third-stage operational amplifier gm3.

[0072] For example, Figure 4 As shown, the first-stage operational amplifier gm1 adopts a current multiplexing and common-source common-gate structure, and the drain (gh terminal) of the first-stage operational amplifier gm1 is electrically connected to the output chopper to reduce the influence of chopping.

[0073] In at least one embodiment of the present disclosure, the input chopper can be set at different positions.

[0074] Figure 3 and Figure 4 shows one way to set up the input chopper. Figure 3 and Figure 4 As shown, the input terminal (bc) of the feedforward stage operational amplifier is connected to the integral capacitor C int1 The first end is electrically connected to the input chopper and the integrating capacitor C int1 The first end is electrically connected to and multiplexed as a demodulator to reduce the number of choppers in the phase domain Delta-Sigma modulator.

[0075] For example, another setting method of the input chopper can be: the input end of the feedforward stage operational amplifier is electrically connected to the input end of the first stage operational amplifier, and the input chopper is still electrically connected to the first end of the integrating capacitor; in this case, the modulation circuit also includes an intermediate chopper, which is electrically connected to the input end of the feedforward stage operational amplifier.

[0076] In some examples, the conversion circuit provided by at least one embodiment of the present disclosure includes a front-end resistor-capacitor circuit and a modulation circuit, and may further include a resistor-capacitor compensation circuit, wherein the resistor-capacitor compensation circuit is connected to the same node as the front-end resistor-capacitor circuit to couple with the modulation circuit, and the resistor-capacitor compensation circuit is configured to be driven by a second differential frequency signal, and the second differential frequency signal has an opposite polarity to the first differential frequency signal.

[0077] In some examples, the conversion circuit provided by at least one embodiment of the present disclosure includes a front-end resistor-capacitor circuit and a modulation circuit, and may further include an on-chip reference frequency source. The on-chip reference frequency source is configured to generate a reference frequency signal and generate a first differential frequency signal based on the reference frequency signal.

[0078] Figure 5 A schematic block diagram of another conversion circuit provided for at least one embodiment of the present disclosure.

[0079] For example, Figure 5 As shown, the conversion circuit 300 provided by at least one embodiment of the present disclosure includes a front-end resistor-capacitor circuit 301 and a modulation circuit 302, and may further include a resistor-capacitor compensation circuit 303 and an on-chip reference frequency source 304. For the description of the front-end resistor-capacitor circuit 301 and the modulation circuit 302, reference may be made to the description of the front-end resistor-capacitor circuit and the modulation circuit in the above embodiment, which will not be repeated here.

[0080] For example, Figure 5As shown, the resistor-capacitor compensation circuit 303 and the front-end resistor-capacitor circuit 301 are connected to the same node to couple with the modulation circuit 302, and the resistor-capacitor compensation circuit 303 is configured to be driven by the second differential frequency signal, and the second differential frequency signal has a polarity opposite to the first differential frequency signal. The on-chip reference frequency source 304 is configured to generate a reference frequency signal, and generates a first differential frequency signal based on the reference frequency signal.

[0081] Figure 6 A schematic diagram of another conversion circuit provided by at least one embodiment of the present disclosure. Figure 6 for Figure 5 A specific example of the conversion circuit shown.

[0082] For example, Figure 6 As shown, the conversion circuit 400 provided by at least one embodiment of the present disclosure includes a front-end resistor-capacitor circuit 401 , a modulation circuit 402 , a resistor-capacitor compensation circuit 403 , and an on-chip reference frequency source 404 .

[0083] For example, Figure 6 As shown, the on-chip reference frequency source 404 includes a resistor-capacitor oscillator (RC OSC) and a clock generation circuit. The RC OSC generates a reference frequency signal , reference frequency signal and external reference frequency signal The output signal is processed by the clock generation circuit to obtain the reference phase signal. , and the first frequency signal , thereby obtaining the first differential frequency signal.

[0084] For example, Figure 6 As shown, the resistor-capacitor compensation circuit 403 is connected to the same node as the front-end resistor-capacitor circuit 401 to couple with the modulation circuit 402, and the resistor-capacitor compensation circuit 403 is configured to be driven by a second differential frequency signal, and the second differential frequency signal has an opposite polarity to the first differential frequency signal.

[0085] For example, Figure 6 As shown, the resistor-capacitor compensation circuit 403 includes a first adjustable capacitor C T1 , the second adjustable capacitor C T2 , the first compensation resistor R c1 , the second compensation resistor R c2 , the third compensation resistor R c3 and the fourth compensation resistor R c4 The first compensation resistor R c1 The first end of the first adjustable capacitor C T1 The first electrode is electrically connected to the second compensation resistor Rc2 The first end and the second adjustable capacitor C T2 The first electrode is electrically connected to the first adjustable capacitor C T1 The second electrode and the second adjustable capacitor C T2 The second pole of the third compensation resistor R is electrically connected to and connected to the first voltage terminal, and the first voltage terminal can be grounded; c3 The first end is connected to the first adjustable capacitor C T1 and the first compensation resistor R c1 The third node M1 between the fourth compensation resistor R c4 The first end is connected to the second adjustable capacitor C T2 and the second compensation resistor R c2 The fourth node M2 ​​between the third compensation resistor R c3 The second end of the second frequency signal is connected , the second end of the fourth resistor is connected to the first frequency signal It should be noted that the first compensation resistor R in the resistor-capacitor compensation circuit 403 c1 ~The fourth compensation resistor R c4 Can be used with the first resistor R in the front-end resistor-capacitor circuit s1 ~The fourth resistor R s1 The first adjustable capacitor and the second adjustable capacitor in the resistor-capacitor compensation circuit 403 may be of the same type as the first capacitor and the second capacitor in the front-end resistor-capacitor circuit.

[0086] See also Figure 6 The resistor-capacitor compensation circuit is similar to the front-end resistor-capacitor circuit, including the same type of on-chip resistors and adjustable capacitors. The driving signal of the resistor-capacitor compensation circuit uses a polarity opposite to that of the front-end resistor-capacitor circuit. When there is parasitic capacitance such as that generated by the pin (PAD) or package, since the front-end resistor-capacitor circuit and the resistor-capacitor compensation circuit are connected to the same node and have opposite polarities, by adjusting the first adjustable capacitor C T1 and the second adjustable capacitor C T2 The size of the first adjustable capacitor C can completely compensate for the influence of parasitic capacitance. T1 Or the second adjustable capacitor C T2 It is not a single capacitor, but a form of multiple capacitors in parallel. However, whether it is connected in parallel depends on the switch on the branch, and the switch is configured by the register and can be manually adjusted outside. So the actual first adjustable capacitor C T1 Or the second adjustable capacitor C T2 The size of is adjusted externally based on the size of the parasitic capacitance in actual conditions. Different parasitic capacitances may result in different configured register values.

[0087] Figure 7A schematic diagram of a frequency source for generating a reference frequency signal provided in at least one embodiment of the present disclosure is Figure 6 A specific example of RC OSC in the on-chip reference frequency source.

[0088] For example, Figure 7 As shown, the frequency source includes a differential RC front end (Differential RC), a chopper error amplifier, a notch filter (Notch filter), a voltage-controlled oscillator (VCO), and a clock generator circuit (Clock Generator).

[0089] The differential RC front end provides the initial oscillation signal, which is processed by the differential structure to generate a stable and interference-resistant signal; the chopper error amplifier detects the error between signals and eliminates the offset voltage and low-frequency noise through chopping technology; the notch filter removes the specific frequency noise introduced by chopping and other circuits; the voltage-controlled oscillator (VCO) adjusts the output frequency according to the control voltage provided by the chopper error amplifier to ensure that the frequency is stable at the set value; the clock generation circuit further processes the high-frequency signal output by the VCO to generate a clock signal that meets the system requirements.

[0090] Figure 8 A schematic diagram of a basic timing sequence of a frequency source circuit for generating a reference frequency signal provided by at least one embodiment of the present disclosure.

[0091] See also Figure 7 and Figure 8 The frequency source circuit works in three stages: reset stage, discharge stage and integration stage. In the reset stage, the signal and Reset the upper plate of capacitor C0 to VDD / GND; during the charge and discharge phase, control and The signal causes the charge on C0 to flow in or out through R0; in the integration phase, the chopper error amplifier and The voltage difference is amplified, and the notch filter flattens the output of the chopper error amplifier. The voltage-controlled oscillator outputs a signal of the corresponding frequency according to this level. The entire system acts as a frequency-locked-loop (FLL) to lock the output period of the voltage-controlled oscillator into equation (3):

[0092]

[0093] in, is the frequency division number, and are the resistance and capacitance values ​​of the differential RC front end.

[0094] Fig. 9 A schematic diagram of a chopper error amplifier and a notch filter provided in at least one embodiment of the present disclosure.

[0095] For example, Fig. 9 As shown in the figure, the error amplifier used in the frequency source is a high-gain common-source common-gate structure, which is used to provide a large loop gain for the entire loop and ensure the accuracy of negative feedback; at the same time, its output impedance and output load capacitance constitute the main pole of the entire system, which is used to ensure the loop stability of the entire system. At the same time, chopping technology is introduced on this basis to reduce the impact of low-frequency noise and offset on the system. The input chopper (not shown in the figure) is set at the differential RC front end, and the output chopper is set as follows Figure 7 Position shown.

[0096] The output of the chopper error amplifier is filtered through a notch filter to restore the output signal to a DC level for controlling the subsequent voltage-controlled oscillator. At the same time, D1 and D2 transistors are added to reduce the impact of charge injection on the output DC level.

[0097] The working principle of the on-chip reference frequency source for temperature effect compensation in the embodiment of the present disclosure includes the following: Since the on-chip resistor has a large temperature coefficient (TC), if the front-end resistor-capacitor circuit is driven only by a fixed frequency, the output current phase shift of the front-end resistor-capacitor circuit will have a large drift with temperature. Formula (4) is an expression of the resistance change with temperature in the front-end resistor-capacitor circuit, where: is R at room temperature T0 S The resistance value, YesR S The temperature coefficient of

[0098]

[0099] Substituting equation (4) into equation (1), we get equation (5). It can be seen from equation (5) that if a fixed frequency is used to drive the front-end resistor-capacitor circuit, the output current phase shift is not only related to the capacitor to be measured, but also changes with temperature.

[0100]

[0101] To address the above problem, the disclosed embodiment generates a reference frequency signal with the same temperature coefficient on-chip, and the frequency-locked-loop (FLL) circuit locks the output period of the voltage-controlled oscillator to equation (3). Substituting into equation (1), the output current phase shift of the front-end resistor-capacitor circuit can be obtained as equation (6), and are resistors of the same type, so / It is a fixed value that is independent of temperature.

[0102]

[0103] Therefore, according to the above method, the output current phase shift of the front-end resistor-capacitor circuit will not drift with temperature.

[0104] Fig.10 A schematic diagram of the suppression of external common-mode noise interference by the conversion circuit provided in at least one embodiment of the present disclosure. The sampling theorem requires that when the input signal frequency is less than FS / 2 (Nyquist bandwidth), there will be no aliasing in the frequency domain. External input noise can be considered as an input signal to a certain extent. When the interference (i.e., external noise) frequency is very high, assuming it is 10Fs+1k (Fs is much larger than 1k), aliasing will occur, that is, the signal energy of the high frequency 10Fs+1k will be folded into the useful signal band (within the range of 0-FS / 2), and the energy of the high frequency 10Fs+1k will appear at 1khz, so the interference needs to be suppressed first. For example, Fig.10 As shown, its front end and the first-stage integrator exhibit a bandpass transfer function, which has a suppressive effect on high-frequency noise. Therefore, the high-frequency noise is first suppressed and then folded, reducing the impact on the useful signal.

[0105] Fig.11 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0106] For example, Fig.11 As shown, the electronic device 600 includes a conversion circuit 601 and an electrode plate 602. The electronic device 600 may be, for example, a capacitive displacement sensor.

[0107] For example, the conversion circuit 601 may be a conversion circuit provided by any of the above embodiments.

[0108] For example, a first side of the electrode plate 602 is electrically connected to the capacitor to be measured so as to be coupled to the front-end resistor-capacitor circuit.

[0109] The electronic device provided by at least one embodiment of the present disclosure can provide more accurate and reliable measurement results by providing a conversion circuit that can achieve a wider measurement range and better suppress external common-mode interference.

[0110] Fig.12 A flowchart of an operating method of an electronic device provided by at least one embodiment of the present disclosure. Fig.12 As shown, the operating method of the electronic device provided by at least one embodiment of the present disclosure includes the following steps S10-S30.

[0111] Step S10, obtaining a first digital signal output by the conversion circuit when there is no displacement change of the electrode plate.

[0112] For example, the first digital signal corresponds to the capacitance value to be measured when there is no displacement change of the electrode plate.

[0113] Step S20, obtaining a second digital signal output by the conversion circuit after the electrode plate has undergone displacement change.

[0114] For example, the second digital signal corresponds to the capacitance value to be measured when the electrode plate undergoes a displacement change.

[0115] Step S30, determining the variation of the first digital signal and the second digital signal, and determining the magnitude of the displacement variation according to the mapping relationship between the variation and the capacitance and the displacement.

[0116] For example, the change in the first digital signal and the second digital signal reflects the change in the capacitance to be measured, and the magnitude of the displacement change can be determined according to the change in the capacitance to be measured and the mapping relationship between the capacitance and the displacement. The mapping relationship includes a calculation formula for the capacitance, as shown in formula (7):

[0117]

[0118] Where S represents the area between the two electrode plates, d represents the distance between the two electrode plates, is a constant, called the dielectric constant, which is related to the properties of the dielectric, and k is the electrostatic force constant. The change in distance between the two electrode plates is the displacement.

[0119] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0120] There are a few points to note about this disclosure:

[0121] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to the general design.

[0122] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0123] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0124] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A conversion circuit, comprising a front-end resistor-capacitor circuit and a modulation circuit, wherein the front-end resistor-capacitor circuit is coupled to the modulation circuit; wherein: The front-end resistor-capacitor circuit includes a capacitor to be measured, and is configured to output a current phase shift corresponding to the capacitor to be measured under the drive of a first differential frequency signal; The modulation circuit is configured to modulate the current phase shift and output a digital signal.

2. The conversion circuit according to claim 1, wherein: The capacitor to be measured includes a first capacitor and a second capacitor; the first differential frequency signal includes a first frequency signal and a second frequency signal, and the first frequency signal and the second frequency signal are in anti-phase; The front-end resistor-capacitor circuit further includes: a first resistor, a second resistor, a third resistor and a fourth resistor; The first end of the first resistor is electrically connected to the first electrode of the first capacitor, the first end of the second resistor is electrically connected to the first electrode of the second capacitor, the second electrode of the first capacitor is electrically connected to the second electrode of the second capacitor, the first end of the third resistor is connected to the first node between the first capacitor and the first resistor, the first end of the fourth resistor is connected to the second node between the second capacitor and the second resistor, the second end of the third resistor is connected to the first frequency signal, and the second end of the fourth resistor is connected to the second frequency signal.

3. The conversion circuit as claimed in claim 2, wherein: The front-end resistor-capacitor circuit is coupled to the modulation circuit and includes: The first input end of the modulation circuit is electrically connected to the second end of the first resistor, and the second input end of the modulation circuit is electrically connected to the second end of the second resistor to couple with the front-end resistor-capacitor circuit.

4. The conversion circuit as claimed in claim 2 further comprises a resistor-capacitor compensation circuit, wherein: The resistor-capacitor compensation circuit is connected to the same node as the front-end resistor-capacitor circuit to couple with the modulation circuit, and the resistor-capacitor compensation circuit is configured to be driven by a second differential frequency signal having an opposite polarity to the first differential frequency signal.

5. The conversion circuit as claimed in claim 4, wherein: The resistor-capacitor compensation circuit comprises: a first adjustable capacitor, a second adjustable capacitor, a first compensation resistor, a second compensation resistor, a third compensation resistor and a fourth compensation resistor; The first end of the first compensation resistor is electrically connected to the first pole of the first adjustable capacitor, the first end of the second compensation resistor is electrically connected to the first pole of the second adjustable capacitor, the second pole of the first adjustable capacitor and the second pole of the second adjustable capacitor are electrically connected and connected to the first voltage terminal, the first end of the third compensation resistor is connected to the third node between the first adjustable capacitor and the first compensation resistor, the first end of the fourth compensation resistor is connected to the fourth node between the second adjustable capacitor and the second compensation resistor, the second end of the third compensation resistor is connected to the second frequency signal, and the second end of the fourth compensation resistor is connected to the first frequency signal.

6. The conversion circuit according to any one of claims 1 to 5, wherein: The modulation circuit includes an integrator, an input chopper and an output chopper; the integrator includes a first-stage integrator and a second-stage integrator; wherein, The input end of the first-stage integrator is connected to the front-end resistor-capacitor circuit, and the first-stage integrator and the second-stage integrator are cascaded to form a second-order integrator; The first-stage integrator includes an integrating capacitor and an amplifier circuit, and the amplifier circuit includes a first-stage operational amplifier, a second-stage operational amplifier, and a feedforward-stage operational amplifier; wherein, The first-stage operational amplifier is cascaded with the second-stage operational amplifier, and the output end of the feedforward stage amplifier is electrically connected to the output end of the second-stage operational amplifier; the first end of the integrating capacitor is electrically connected to the input end of the first-stage operational amplifier, and the second end of the integrating capacitor is electrically connected to the output end of the second-stage operational amplifier; The first-stage operational amplifier adopts a common-source common-gate structure, and the drain of the first-stage operational amplifier is electrically connected to the output chopper; The input chopper is electrically connected to the first end of the integrating capacitor and multiplexed as a demodulator.

7. The conversion circuit according to claim 6, wherein: The input terminal of the feedforward stage operational amplifier is electrically connected to the first terminal of the integrating capacitor.

8. The conversion circuit as claimed in claim 6, wherein: The input terminal of the feedforward stage operational amplifier is electrically connected to the input terminal of the first stage operational amplifier, and the modulation circuit further includes an intermediate chopper; Wherein, the intermediate chopper is electrically connected to the input end of the feedforward stage operational amplifier.

9. The conversion circuit according to claim 6, further comprising: comparator and phase selector; wherein, The input end of the comparator is electrically connected to the output end of the integrator, the output end of the comparator is electrically connected to the input end of the phase selector, and the comparator is configured to sample the signal output by the integrator to obtain an output signal, and feed the output signal back to the input end of the phase selector; The input end of the phase selector is electrically connected to the output end of the comparator, and the output end of the phase selector is electrically connected to the input chopper and the output chopper respectively. The phase selector is configured to select a reference phase signal, obtain a phase error signal based on the output signal and the reference phase signal, and feed the phase error signal back to the integrator.

10. The conversion circuit according to claim 6, wherein: The second stage integrator includes a transconductance-capacitance integrator.

11. The conversion circuit according to any one of claims 1 to 5, further comprising an on-chip reference frequency source, in, The on-chip reference frequency source is configured to generate a reference frequency signal, and to generate the first differential frequency signal based on the reference frequency signal.

12. An electronic device comprising the conversion circuit according to any one of claims 1 to 11.

13. The electronic device as claimed in claim 12, further comprising an electrode plate, in, The first side of the electrode plate is electrically connected to the capacitor to be measured so as to be coupled to the front-end resistor-capacitor circuit.

14. A method for operating an electronic device according to claim 13, comprising: Acquire a first digital signal output by the conversion circuit when there is no displacement change of the electrode plate; Acquire a second digital signal output by the conversion circuit after the electrode plate undergoes a displacement change; Determine the variation of the first digital signal and the second digital signal, and determine the magnitude of the displacement variation according to a mapping relationship between the variation and capacitance and displacement.

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