A power semiconductor device continuous switching test circuit and method

Abstract

This application discloses a continuous switching test circuit and method for power semiconductor devices, relating to the field of power electronics. The test circuit includes: a current generator for generating a test current; a voltage balancing module for generating a test voltage; an auxiliary module connected to the current generator and the voltage balancing module for providing the required test voltage and test current to the power semiconductor device under test (T1) in continuous switching mode; and a capacitor discharge module for controlling the voltage applied across the power semiconductor device under test (T1). The voltage balancing module includes the power semiconductor device T1... c2 Capacitor C1; Power semiconductor device T c2 The control capacitor C1 applies a voltage to the inductor L in the auxiliary module, balancing the voltage across inductor L. This application satisfies the simulation of the continuous switching condition of the power semiconductor device under test T1 and achieves voltage-current stress decoupling. Therefore, the voltage source does not require greater voltage stress, reducing the power supply requirements.

Description

Technical Field

[0001] This application relates to the field of power electronics, and particularly to a continuous switching test circuit and method for power semiconductor devices. Background Art

[0002] In power electronics applications, IGBTs mainly operate in a switching state, experiencing periodic static and dynamic operations, which can lead to energy losses and cause power losses in the devices, thereby causing fluctuations in the junction temperature of IGBTs. To quickly verify the service life of IGBTs, IGBT power cycling tests can be conducted. This test verifies the ability of the chip to withstand electrical and thermal stresses by applying intermittent large currents to heat the chip, helping to accelerate the confirmation of the IGBT's life.

[0003] In the equivalent test of IGBT devices, the key lies in simulating the switching transient process and ensuring that the effective current is consistent with the actual working conditions, and the switching frequency is close to the actual application. The existing series valve condition power cycling test platform is a test platform that includes a switching transient process, and simulates the arm current through PWM control and high-frequency switching. On this platform, the switching frequency of IGBT devices is very high. However, for the MMC condition, the switching frequency of IGBT devices is relatively low, and the main loss is the on-state loss. Therefore, the test platform needs to be able to provide high voltage and large current capabilities.

[0004] Designing a test power supply that can meet these requirements faces great challenges. It is huge in size and high in cost, and it is almost impossible to achieve. This has also become one of the key design problems in the equivalent test of IGBT device operation under MMC conditions. Summary of the Invention

[0005] The purpose of this application is to provide a continuous switching test circuit and method for power semiconductor devices, which can achieve continuous switching of power semiconductor devices, and the voltage source does not require a greater voltage stress, reducing the requirements for the power supply.

[0006] To achieve the above purpose, this application provides the following solutions:

[0007] In a first aspect, this application provides a continuous switching test circuit for power semiconductor devices, including:

[0008] A current generator for generating a test current;

[0009] A voltage balancing module for generating a test voltage;

[0010] An auxiliary module, connected to the current generator and the voltage balancing module, for providing the test voltage and test current required for the power semiconductor device under test T1 in a continuous switching state;

[0011] A capacitor discharge module is used to control the voltage applied across the two ends of the power semiconductor device T1 under test;

[0012] The voltage balancing module includes a power semiconductor device T. c2 and capacitor C1; the power semiconductor device T c2 The capacitor C1 is controlled to apply voltage to the inductor L in the auxiliary module, thereby balancing the voltage across the inductor L.

[0013] Secondly, this application provides a method for continuous switching testing of a power semiconductor device, the method being applied to the aforementioned continuous switching test circuit for a power semiconductor device, the method comprising:

[0014] The capacitor C2 in the capacitor discharge module is charged to the set voltage Us, and the capacitor C1 in the voltage balance module is charged to the set voltage Us1. The power semiconductor device T0 in the current generator and the power semiconductor device T1 under test are turned on. At this time, the current generator, the inductor L in the auxiliary module, the power semiconductor device T1 under test and the power semiconductor device T4 in the auxiliary module form a circuit to charge the inductor L until the current reaches the set value Is.

[0015] Turn off power semiconductor device T0 and the power semiconductor device under test T1, and turn on power semiconductor device T in the voltage balancing module. c0 This causes one end of inductor L to bear the voltage of capacitor C1. At this time, inductor L, power semiconductor device T2, capacitor C2, power semiconductor device T4, capacitor C1, and power semiconductor device T5 in the auxiliary module are all connected. c0 A circuit is formed, with inductor L charging capacitor C2. Simultaneously, since the voltage of capacitor C1 is higher than that of capacitor C2, capacitor C1 discharges. After a dead time, power semiconductor device T2 and power semiconductor device T3 in the auxiliary module are turned on, and power semiconductor device T3 is turned off. c0 At this point, inductor L, power semiconductor device T2, power semiconductor device T3, and diode D2 in the auxiliary module form a circuit, and the two ends of the power semiconductor device T1 under test are subjected to the voltage of capacitor C2; then the power semiconductor device T in the capacitor discharge module is turned on. c1 and the power semiconductor device T in the voltage balancing module c2 The power semiconductor device T will shut down when the voltage of capacitor C1 returns to the set voltage Us1 and the voltage of capacitor C2 falls below Us. c1 and power semiconductor devices T c2 ;

[0016] Power semiconductor devices T2 and T3 are turned off, and power semiconductor device T1 is turned on. c0The voltage across capacitor C1 is applied to one end of inductor L. At this time, inductor L, power semiconductor device T2, capacitor C2, power semiconductor device T4, capacitor C1, and power semiconductor device T5 are all connected. c0 A circuit is formed; inductor L charges capacitor C1, C1 discharges, and after a dead time, the voltage of capacitor C2 is charged back to the set voltage Us, turning on the power semiconductor device T1 under test and turning off the power semiconductor device T2. c0 At this time, the inductor L, the power semiconductor device under test T1, the power semiconductor device T4 and the diode D2 form a circuit. The power semiconductor device under test T1 is turned on under the condition of being subjected to the set voltage Us. This process completes the turn-on test of the power semiconductor device under test T1.

[0017] Turn on power semiconductor device T c2 The power semiconductor device T will be turned off once the voltage across capacitor C1 returns to the set voltage Us1. c2 Turn off the power semiconductor device under test T1, and turn on the power semiconductor device T2. c0 The voltage across capacitor C1 is applied to one end of inductor L. At this time, inductor L, power semiconductor device T2, capacitor C2, power semiconductor device T4, capacitor C1, and power semiconductor device T5 are all connected. c0 A circuit is formed; the power semiconductor device under test T1 is turned off when the current flowing through it is the set value Is. This process completes the turn-off test of the power semiconductor device under test T1.

[0018] Repeat the above steps to achieve a loop, thereby realizing the continuous switching test of the power semiconductor device T1 under test.

[0019] According to the specific embodiments provided in this application, this application has the following technical effects:

[0020] (1) The current generator provided in this application provides test current to the power semiconductor device T1 under test by forming a circuit with the switching element. The circuit is simple and can meet the large current required for the experiment.

[0021] (2) The balanced voltage module provided in this application uses a power semiconductor device T c2 The control capacitor C1 applies voltage to the inductor L in the auxiliary module, balancing the voltage across the inductor L and reducing the energy loss caused by the discharge of inductor L when the power semiconductor device under test T1 is turned off.

[0022] (3) The power semiconductor device continuous switching test circuit provided in this application satisfies the simulation of the continuous switching condition of the power semiconductor device under test T1, and realizes voltage and current stress decoupling. Therefore, the voltage source does not need to have greater voltage stress, which reduces the power supply requirements. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a structural diagram of a power semiconductor device continuous switching test circuit provided in an embodiment of this application;

[0025] Figure 2 A schematic flowchart of a continuous switching test method for power semiconductor devices provided in an embodiment of this application;

[0026] Figure 3 This is a key timing waveform diagram of a power semiconductor device in a continuous switching test circuit. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] Currently, there are three main methods for evaluating the long-term operation of IGBT devices: DC power cycling test platforms, parallel-drive test platforms, and full-bridge current source platforms. DC power cycling test platforms are considered the standard reliability testing method for IGBT devices, but they do not involve switching operations during the test, thus significantly differing from the electrical stresses experienced in real-world applications. Parallel-drive test platforms are primarily used for the joint testing of multi-level submodules, simulating the current and voltage stresses during MMC steady-state operation. However, they are more suitable for testing after the submodules are assembled, and their time and economic costs are high. Furthermore, parallel-drive test platforms cannot provide further reliability assessments of IGBT devices, nor can they monitor key reliability parameters. As for full-bridge current source platforms, although they can generate the current and voltage stresses during MMC steady-state operation, their reliability is low due to the need for high-frequency switching operations, limiting their application in evaluating MMC steady-state IGBT devices.

[0029] Therefore, this application provides a power semiconductor device continuous switching test circuit that can simulate power semiconductor devices under continuous switching conditions and achieve voltage and current stress decoupling to provide high voltage and high current for the test circuit at low cost.

[0030] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] In one exemplary embodiment, such as Figure 1 As shown, a continuous switching test circuit for power semiconductor devices is provided, including: a current generator 1, a voltage balancing module 2, an auxiliary module 3, and a capacitor discharge module 4. Wherein:

[0032] Current generator 1 is used to generate test current. Current generator 1 includes a voltage source V1, a resistor R1, a diode D1, and a power semiconductor device T0 connected in series. The voltage source V1 is controlled by the power semiconductor device T0 and forms a circuit with the inductor L to charge the inductor L, thereby supplying test current to the test circuit.

[0033] Voltage balancing module 2 is used to generate the test voltage. Voltage balancing module 2 includes a power semiconductor device T. c0 Capacitor C1, voltage source V2, resistor R3, power semiconductor device T c2 Among them, power semiconductor devices T c0 The voltage across capacitor C1 is applied to one end of inductor L to balance the voltage across inductor L and reduce inductor L's discharge. Power semiconductor device T c2 Control voltage source V2 to charge capacitor C1.

[0034] In one specific embodiment, the positive terminal of the voltage source V2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the power semiconductor device T. c2 The collector connection of the power semiconductor device T c2 The emitter is connected to one end of the capacitor C1 and the power semiconductor device T, respectively. c0 The collector of the capacitor is connected, and the other end of the capacitor C1 is connected to the negative terminal of the voltage source V2, the negative terminal of the voltage source V1, and the auxiliary module, respectively. The power semiconductor device T c0 The emitter is connected to the auxiliary module.

[0035] Auxiliary module 3 is connected to the current generator 1 and the voltage balancing module 2, and is used to provide the required test voltage and test current for the power semiconductor device under test (T1, which is connected in series with the current generator 1 in the main test circuit and receives the large current generated by the current generator 1) under continuous switching conditions. Auxiliary module 3 includes inductor L, power semiconductor device T2, power semiconductor device T3, power semiconductor device T4, and diode D2.

[0036] In one specific embodiment, one end of the inductor L is connected to the power semiconductor device T. c0The emitter of the power semiconductor device T0 is connected to the emitter of the diode D2 and the cathode of the power semiconductor device T1 under test. The other end of the inductor L is connected to the emitters of the power semiconductor device T1 and the power semiconductor device T2 under test. The collector of the power semiconductor device T2 is connected to the capacitor discharge module and the collector of the power semiconductor device T3 under test. The emitter of the power semiconductor device T3 is connected to the collector of the power semiconductor device T4, the cathode of the diode D2 and the other end of the capacitor C1 under test. The emitter of the power semiconductor device T4 is connected to the capacitor discharge module and the power semiconductor device T1 under test.

[0037] The capacitor discharge module 4 is used to control the voltage of capacitor C2, that is, the voltage across the two ends of the power semiconductor device T1 under test.

[0038] In one specific embodiment, one end of the capacitor C2 is connected to the emitter of the power semiconductor device T2 and the power semiconductor device T... c1 The collector connection of the power semiconductor device T c1 The emitter of the device is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the other end of the capacitor C2 and the emitter of the power semiconductor device T4.

[0039] In this application, the current stress of the power semiconductor device T1 under test is applied through the current generator 1, and the voltage stress is applied through the capacitor C2.

[0040] The test circuit provided in this application satisfies the simulation of continuous switching conditions of power semiconductor devices and achieves voltage and current stress decoupling. Therefore, the voltage source does not need to have greater voltage stress, which reduces the power supply requirements.

[0041] In one exemplary embodiment, such as Figure 2 As shown, a method for continuous switching testing of power semiconductor devices is provided. This method is applied to the aforementioned continuous switching test circuit for power semiconductor devices. Figure 3 This method provides key timing waveforms for power semiconductor devices in a continuous switching test circuit. The method includes the following steps:

[0042] (1) In this test circuit, firstly, capacitor C2 in capacitor discharge module 4 is charged to the set voltage Us, and capacitor C1 in voltage balance module 2 is charged to the set voltage Us1, which is higher than Us. Then, power semiconductor device T0 in current generator 1 and power semiconductor device T1 under test are turned on. At this time, current generator 1, inductor L in auxiliary module 4, power semiconductor device T1 under test and power semiconductor device T4 in auxiliary module 4 form a loop to charge inductor L until the current reaches the set value Is.

[0043] (2) Turn off power semiconductor devices T0 and T1, and turn on power semiconductor device T1 in voltage balancing module 2. c0 This causes one end of inductor L to bear the voltage of capacitor C1. At this time, inductor L, power semiconductor device T2, capacitor C2, power semiconductor device T4, capacitor C1, and power semiconductor device T1 in auxiliary module 4 are all connected. c0 A circuit is formed, with inductor L charging capacitor C2. Simultaneously, because the voltage of capacitor C1 is higher than that of capacitor C2, capacitor C1 discharges. Due to the presence of capacitor C1, the discharge amount of inductor L is reduced compared to when C1 is not present. After a dead time, power semiconductor device T2 and power semiconductor device T3 in auxiliary module 4 are turned on, and power semiconductor device T3 is turned off. c0 At this point, inductor L, power semiconductor device T2, power semiconductor device T3, and diode D2 in auxiliary module 4 form a circuit, and the two ends of the power semiconductor device T1 under test are subjected to the voltage of capacitor C2; then the power semiconductor device T1 in capacitor discharge module 4 is turned on. c1 and the power semiconductor device T in voltage balancing module 2 c2 The power semiconductor device T is turned off when the voltage of capacitor C1 returns to the set voltage Us1 and the voltage of capacitor C2 returns to slightly below Us. c1 and power semiconductor devices T c2 .

[0044] (3) Turn off power semiconductor devices T2 and T3, and turn on power semiconductor device T4. c0 The voltage across capacitor C1 is applied to one end of inductor L. At this time, inductor L, power semiconductor device T2, capacitor C2, power semiconductor device T4, capacitor C1, and power semiconductor device T5 are all connected. c0 This forms a circuit; similarly, inductor L charges capacitor C1, C1 discharges, and after a dead time, the voltage of capacitor C2 returns to the set voltage Us, turning on the power semiconductor device T1 under test and turning off the power semiconductor device T2. c0 At this time, the inductor L, the power semiconductor device under test T1, the power semiconductor device T4 and the diode D2 form a circuit. The power semiconductor device under test T1 is turned on under the condition of bearing the set voltage Us. This process completes the turn-on test of the power semiconductor device under test T1.

[0045] (4) Turn on the power semiconductor device T c2 The power semiconductor device T will be turned off once the voltage across capacitor C1 returns to the set voltage Us1. c2 Turn off the power semiconductor device under test T1, and turn on the power semiconductor device T2. c0The voltage across capacitor C1 is applied to one end of inductor L. At this time, inductor L, power semiconductor device T2, capacitor C2, power semiconductor device T4, capacitor C1, and power semiconductor device T5 are all connected. c0 A circuit is formed. The power semiconductor device under test T1 is turned off when the current flowing through it is the set value Is. This process completes the turn-off test of the power semiconductor device under test T1.

[0046] Repeat the above steps to achieve a loop, thereby realizing the continuous switching test of the power semiconductor device T1 under test.

[0047] As can be seen from the above process, the voltage source does not need to bear the voltage setpoint Us. The current stress of the power semiconductor device under test T1 is applied through the current generator 1, and the voltage stress is applied through the capacitor. Moreover, after each test, the system current returns to the setpoint Is, which can realize the continuous shutdown of the power semiconductor device under test T1. Furthermore, the voltage source does not need to bear a larger voltage stress, thus reducing the power supply requirements.

[0048] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A continuous switching test circuit for power semiconductor devices, characterized in that, include: A current generator is used to generate test current. Voltage balancing module, used to generate test voltage; An auxiliary module, connected to the current generator and the voltage balancing module, is used to provide the test voltage and test current required for the power semiconductor device under test T1 in continuous switching state. A capacitor discharge module is used to control the voltage applied across the two ends of the power semiconductor device T1 under test; The voltage balancing module includes a power semiconductor device T. c2 and capacitor C1; the power semiconductor device T c2 The capacitor C1 is controlled to apply a voltage to the inductor L in the auxiliary module, thereby balancing the voltage across the inductor L; The voltage balancing module also includes power semiconductor devices T c0 Voltage source V2 and resistor R3; The positive terminal of the voltage source V2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the power semiconductor device T. c2 The collector connection of the power semiconductor device T c2 The emitter is connected to one end of the capacitor C1 and the power semiconductor device T, respectively. c0 The collector of the capacitor is connected, and the other end of the capacitor C1 is connected to the negative terminal of the voltage source V2, the negative terminal of the voltage source V1, and the auxiliary module, respectively. The power semiconductor device T c0 The emitter is connected to the auxiliary module; The auxiliary module includes: inductor L, power semiconductor device T2, power semiconductor device T3, power semiconductor device T4, and diode D2; One end of the inductor L is respectively connected to the power semiconductor device T c0 The emitter of the power semiconductor device T0, the emitter of the power semiconductor device T0, and the cathode of the diode D2 are connected. The other end of the inductor L is connected to the emitters of the power semiconductor device T1 and the power semiconductor device T2, respectively. The collector of the power semiconductor device T2 is connected to the capacitor discharge module and the collector of the power semiconductor device T3, respectively. The emitter of the power semiconductor device T3 is connected to the collector of the power semiconductor device T4, the cathode of the diode D2, and the other end of the capacitor C1, respectively. The emitter of the power semiconductor device T4 is connected to the capacitor discharge module and the power semiconductor device T1, respectively. The capacitor discharge module includes: capacitor C2 and power semiconductor device T. c1 and resistor R2; One end of capacitor C2 is connected to the emitter of power semiconductor device T2 and the power semiconductor device T... c1 The collector connection of the power semiconductor device T c1 The emitter of the device is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the other end of the capacitor C2 and the emitter of the power semiconductor device T4.

2. The power semiconductor device continuous switching test circuit according to claim 1, characterized in that, The current generator includes a voltage source V1, a resistor R1, a diode D1, and a power semiconductor device T0 connected in series.

3. The power semiconductor device continuous switching test circuit according to claim 1, characterized in that, The power semiconductor device T c2 The voltage source V2 is controlled to charge the capacitor C1.

4. The power semiconductor device continuous switching test circuit according to claim 1, characterized in that, The current stress of the power semiconductor device under test T1 is applied through the current generator, and the voltage stress of the power semiconductor device under test T1 is applied through the capacitor C2.

5. A method for continuous switching testing of power semiconductor devices, characterized in that, The method is applied to the power semiconductor device continuous switching test circuit according to any one of claims 1-4, and the method includes: The capacitor C2 in the capacitor discharge module is charged to the set voltage Us, and the capacitor C1 in the voltage balance module is charged to the set voltage Us1. The power semiconductor device T0 in the current generator and the power semiconductor device T1 under test are turned on. At this time, the current generator, the inductor L in the auxiliary module, the power semiconductor device T1 under test and the power semiconductor device T4 in the auxiliary module form a circuit to charge the inductor L until the current reaches the set value Is. Turn off power semiconductor device T0 and the power semiconductor device under test T1, and turn on power semiconductor device T in the voltage balancing module. c0 This causes one end of inductor L to bear the voltage of capacitor C1. At this time, inductor L, power semiconductor device T2, capacitor C2, power semiconductor device T4, capacitor C1, and power semiconductor device T5 in the auxiliary module are all connected. c0 A circuit is formed, with inductor L charging capacitor C2. Simultaneously, since the voltage of capacitor C1 is higher than that of capacitor C2, capacitor C1 discharges. After a dead time, power semiconductor device T2 and power semiconductor device T3 in the auxiliary module are turned on, and power semiconductor device T3 is turned off. c0 At this point, inductor L, power semiconductor device T2, power semiconductor device T3, and diode D2 in the auxiliary module form a circuit, and the two ends of the power semiconductor device T1 under test are subjected to the voltage of capacitor C2; then the power semiconductor device T in the capacitor discharge module is turned on. c1 and the power semiconductor device T in the voltage balancing module c2 The power semiconductor device T will shut down when the voltage of capacitor C1 returns to the set voltage Us1 and the voltage of capacitor C2 falls below Us. c1 and power semiconductor devices T c2 ; Power semiconductor devices T2 and T3 are turned off, and power semiconductor device T1 is turned on. c0 The voltage across capacitor C1 is applied to one end of inductor L. At this time, inductor L, power semiconductor device T2, capacitor C2, power semiconductor device T4, capacitor C1, and power semiconductor device T5 are all connected. c0 A circuit is formed; inductor L charges capacitor C1, C1 discharges, and after a dead time, the voltage of capacitor C2 is charged back to the set voltage Us, turning on the power semiconductor device T1 under test and turning off the power semiconductor device T2. c0 At this time, the inductor L, the power semiconductor device under test T1, the power semiconductor device T4 and the diode D2 form a circuit. The power semiconductor device under test T1 is turned on under the condition of being subjected to the set voltage Us. This process completes the turn-on test of the power semiconductor device under test T1. Turn on power semiconductor device T c2 The power semiconductor device T will be turned off once the voltage across capacitor C1 returns to the set voltage Us1. c2 Turn off the power semiconductor device under test T1, and turn on the power semiconductor device T2. c0 The voltage across capacitor C1 is applied to one end of inductor L. At this time, inductor L, power semiconductor device T2, capacitor C2, power semiconductor device T4, capacitor C1, and power semiconductor device T5 are all connected. c0 A circuit is formed; the power semiconductor device under test T1 is turned off when the current flowing through it is the set value Is. This process completes the turn-off test of the power semiconductor device under test T1. Repeat the above steps to achieve a loop, thereby realizing the continuous switching test of the power semiconductor device T1 under test.

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