Integrated circuit packaging body chip access detection method

Abstract

The invention belongs to the technical field of electronic manufacturing, and particularly relates to an integrated circuit package chip access detection method, which comprises the following steps of: introducing multi-dimensional non-contact scanning, constructing a three-dimensional mapping graph based on real-time data, intelligently planning a probe access sequence and other innovative measures; the method can dynamically adapt to chips with various sizes and pin layouts, so that high-efficiency and high-precision detection results are realized. In addition, through real-time analysis of response parameters and application of a feedback mechanism, the probe operation strategy can be automatically adjusted, the test process is further optimized, and the detection efficiency and accuracy are improved. Finally, the method not only improves the flexibility and adaptability of detection, but also remarkably reduces the detection time and cost, and brings important technical progress to the electronic manufacturing industry.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic manufacturing, and in particular relates to a method for detecting a chip path of an integrated circuit package. Background Art

[0002] In the modern electronic manufacturing industry, the inspection of integrated circuit (IC) packages is an important part of ensuring product quality and reliability. Existing chip path inspection methods usually rely on pre-set fixed patterns, that is, they are designed for chips of specific sizes and pin layouts. Although this method can effectively detect specific types of chips, it lacks flexibility and adaptability. When faced with chips of different models, sizes or pin configurations, it is often necessary to recalibrate the equipment or adjust the inspection procedures, which not only increases the inspection cost, but may also lead to inefficiency.

[0003] Existing technical solutions generally include: Fixed-mode inspection: Using probe cards and inspection platforms designed for certain standard package sizes, these tools can typically only accommodate a limited range of chip types.

[0004] Contact scanning: Electrical characteristics are measured by directly contacting the chip pins with a physical probe. This method is prone to mechanical damage, and accuracy is difficult to guarantee for chips with high-density pin distribution.

[0005] Preset path access: The probe moves along a predetermined path and applies a test signal. This process is not adaptive and cannot be dynamically adjusted to cope with different chip structures.

[0006] Offline data analysis: The collected data needs to be processed afterwards to draw conclusions, which affects the speed and accuracy of immediate decision-making.

[0007] The main technical problems faced by the above methods are their static and non-adaptive nature, which makes it difficult for them to efficiently and accurately handle a variety of chip products. In particular, with the miniaturization and increasing complexity of electronic products, traditional detection methods are increasingly unable to meet the market's demand for fast, flexible and high-precision detection. Summary of the invention

[0008] The purpose of the present invention is to provide an integrated circuit package chip path detection method, which not only improves the flexibility and adaptability of detection, but also significantly reduces the detection time and cost, bringing important technological progress to the electronic manufacturing industry to solve the static and non-adaptive problems in the prior art.

[0009] To achieve the above object, the present invention proposes a method for detecting a chip path in an integrated circuit package, comprising the following steps: The chip to be tested is placed on the testing platform and the positioning information is given. Based on the positioning information, the multi-dimensional scanning system is started to perform non-contact scanning around the chip surface; Based on the acquired scanning data, a three-dimensional structure map is constructed to reflect the chip pin distribution and connection path. The formed map is used to plan the probe access sequence so that the probe can reach each target position in an orderly manner. According to the set access sequence, the probe is driven to move to the specified coordinate point and a preset signal is applied. After the signal is applied, the response parameters fed back from the chip are collected as the basis for evaluation. Combine the obtained response parameters, compare with the ideal value range, identify abnormal conditions or impedance changes, record any deviations found, and adjust subsequent probe operation strategies to optimize the test; After completing all the scheduled probe actions, all the test data are summarized and a final report is output to indicate the chip path status.

[0010] Preferably, placing the chip to be tested on a testing platform comprises: Use an optical system to perform initial imaging on the chip surface to obtain boundary contour information; According to the obtained boundary contour, the center point coordinate Zc is calculated, where Zc=(Xzc, Yzc), Xzc and Yzc represent the position of the chip geometric center in the plane rectangular coordinate system; With the determined center point Zc as the reference, establish a local coordinate system and measure the distances L1 to L4 from the four corners of the chip to Zc, using the formula Ln=sqrt((Xn-Xzc)^2+(Yn-Yzc)^2), where n=1 to 4 represents the four corners; The measured data is used to adjust the angle and height of the detection platform to ensure that the chip fits perfectly with the contact surface and eliminate any gaps that affect signal transmission.

[0011] Preferably, the multi-dimensional scanning system is started to perform a non-contact scanning operation around the chip surface, including: According to the obtained chip position data, the initial scanning starting point Sc is set to be located at the edge of the chip; Starting from the determined starting point Sc, the scanning probe is gradually moved along a preset path Q, where the path Q is composed of a series of discrete points, satisfying Q={Sc,S1,...,Sn}; At each point Sn on the defined path Q, the reflection intensity J value is recorded, and the formula J=A*exp(-B*d), A and B are coefficients related to material properties, and d represents the scanning depth, which is used to quantify the reflection difference between different layers; After completing the data collection of all points Sn, compare the reflection intensity change ΔJ between adjacent points and calculate ΔJ=|Jn-Jn-1| to determine whether there are potential defects or abnormalities.

[0012] Preferably, the three-dimensional structure mapping diagram is constructed based on the acquired scan data to reflect the chip pin distribution and connection path, including: The obtained reflection intensity J value is used to perform layer processing on the chip surface to determine the boundary Lm of each layer, where m represents the number of layers; For each layer Lm determined, the thickness Hm of each layer is calculated based on the data recorded at point Sn on path Q, using the formula Hm=(Zn-Zn-1), where Z represents the position coordinate along the vertical direction; Based on the obtained thickness Hm of each layer and the reflection intensity J, draw the interlayer connecting line segment Ei, where i is the pin number, to ensure that each pin position accurately corresponds to the specific coordinates in the three-dimensional space; By using the established connection line segment Ei, all pin distribution and connection path information are integrated to generate a complete three-dimensional mapping diagram F.

[0013] Preferably, the use of the formed mapping diagram to plan the probe access sequence so that the probe can reach each target position in an orderly manner includes: According to the position coordinates of each pin in the three-dimensional mapping diagram F, the shortest path Spq between adjacent pins is calculated, where p and q represent different pin numbers respectively; According to the established connecting line segment Ei and the shortest path Spq, the probe moving direction Vr is determined by the formula Vr=(Xq-Xp) / Spq, where X represents the horizontal coordinate of the pin on the mapping diagram; Based on the generated complete three-dimensional map F and the probe moving direction Vr, the probe access order O is constructed to ensure that the probe reaches each target point in the most efficient order; Using the constructed probe access order O, the probe starting position S0 is adjusted to optimize the overall access path length Pl, using the formula Pl=Sum(Spq), where Sum represents the sum of the distances between all adjacent probe access positions.

[0014] Preferably, the step of driving the probe to move to a specified coordinate point and applying a preset signal according to a set access sequence includes: According to the coordinate point information in the probe access sequence O, the displacement ΔPn required for each movement phase is calculated, where n represents the position index in the access sequence; According to the calculated displacement ΔPn, adjust the current position Pcur of the probe to the next target coordinate Pt, and use the formula Pt=Pcur+ΔPn to complete the position update; After the probe reaches the new coordinate Pt, the signal output module Uo is activated according to the preset conditions, and is ready to apply the specified signal strength Si to the target position; When the signal output module Uo is activated, the signal duration Ti is controlled by adjusting the parameter K, and the formula Ti=G(K,Si) is applied, where G represents the functional relationship between time, intensity and control parameters.

[0015] Preferably, after the signal is applied, collecting the response parameters fed back from inside the chip includes: After the signal is applied, the data acquisition module Do is started to capture the initial response value Ro fed back by the chip within the preset time window Tw; According to the set signal duration Ti, adjust the time interval Δt of the data acquisition module Do to ensure that the data at each time point is recorded. The formula is Δt=Tw / N, where N represents the number of acquisition cycles; At each time interval Δt, the change in the response parameter ΔRi is recorded, where i represents the i-th acquisition cycle, and the formula ΔRi=Ri-R(i-1) is used to track the trend of the response over time; After completing all scheduled acquisition cycles, all response parameter changes ΔRi are integrated to construct a response parameter sequence Rs, i.e., Rs = {ΔR1, ΔR2, ..., ΔRN}, which serves as the basis for subsequent evaluation.

[0016] Preferably, the response parameters obtained by combining are compared with the ideal value range to identify abnormal conditions or impedance changes, including: According to the constructed response parameter sequence Rs, the response change rate Rri of each acquisition cycle is calculated using the formula Rri=ΔRi / Δt, where ΔRi is the change in the response parameter and Δt is the time interval; Compare the preset ideal response change rate range Rri_ideal to determine whether the actual change rate Rri exceeds the limit. If |Rri-Rri_ideal|>ε, it is marked as a potential abnormal point Pi, where ε represents the allowable error; For the identified abnormal point Pi, analyze the impedance change Zci in the corresponding cycle, and apply the formula Zci=V / Ic, where V and Ic represent the voltage and current of the applied signal, respectively, to evaluate the internal state of the chip; Integrate all abnormal points Pi and their corresponding impedance changes Zci to generate an abnormal report Ar, which lists all responses that deviate from the ideal value range and the associated impedance changes.

[0017] Preferably, recording any deviations found and adjusting subsequent probe operation strategies to optimize the test include: According to the generated abnormal report Ar, all responses that deviate from the ideal value range and the associated impedance changes Zci are recorded in the database Db; Analyze the deviation records in the database Db, calculate the weight Wpi of each abnormal point Pi, and use the formula Wpi=H(Zci,Rri), where H represents a comprehensive evaluation function based on impedance change and response change rate; According to the obtained weight Wpi, adjust the probe access order O, re-plan the detection path P' with higher priority, and ensure that the key areas are inspected more carefully. Apply the formula P'=sort(O,Wpi), where sort represents the operation of sorting by weight; Under the guidance of the updated detection path P', the new probe movement speed Vnew and signal strength Si_new are set, through the formula Vnew=M(Wpi) and Si_new=N(Wpi), where M and N represent functions for adjusting speed and strength according to weights, respectively.

[0018] Preferably, after completing all the predetermined probe actions, all the detection data are summarized and a final report is output to indicate the chip channel status, including: Collect the test results after all probe operations, including the response change rate Rri, impedance change Zci and abnormal point Pi data, and integrate them into the comprehensive data set Ds; According to the adjusted detection path P' and the set new probe movement speed Vnew and signal strength Si_new, the effect Ei of each detection point is evaluated, and the formula Ei=O(Vnew,Si_new,Rri) is used, where O represents the effect evaluation function, to quantify the test quality of each point; Based on the effect evaluation Ei and the historical deviation records in the database Db, the overall health index HI of the chip pathway is determined, and the formula HI=P(Ei,Wpi) is applied, where P is the function for calculating the health index and Wpi is the weight of the outlier point; All information is summarized to generate a final report Rf, which not only lists the status of all detection points, but also includes the overall health index HI and improvement suggestions for the problems found.

[0019] Technical effects and advantages of the present invention: Compared with the prior art, the present invention provides a method for detecting a path of an integrated circuit package chip, which has the following advantages: The present invention introduces innovative measures such as multi-dimensional non-contact scanning, building a three-dimensional mapping diagram based on real-time data, and intelligently planning the probe access sequence. This method can dynamically adapt to chips of various sizes and pin layouts, thereby achieving efficient and high-precision detection results. In addition, through the real-time analysis of response parameters and the application of feedback mechanisms, the present invention can also automatically adjust the probe operation strategy, further optimize the test process, and improve detection efficiency and accuracy. Ultimately, this method not only improves the flexibility and adaptability of detection, but also significantly reduces detection time and cost, bringing important technological advances to the electronics manufacturing industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is a flow chart of the integrated circuit package chip path detection method. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0022] The present invention provides a method for detecting a chip path in an integrated circuit package. Figure 1 As shown, the following steps are included: Step 1: Place the chip to be tested on the testing platform and provide positioning information; further use the optical system to perform initial imaging on the chip surface to obtain boundary contour information; calculate the center point coordinates Zc based on the obtained boundary contour, where Zc=(Xzc, Yzc), Xzc and Yzc represent the position of the chip geometric center in the plane rectangular coordinate system; Take the determined center point Zc as the reference, establish a local coordinate system, and measure the distances L1 to L4 from the four corners of the chip to Zc, using the formula Ln=sqrt((Xn-Xzc)^2+(Yn-Yzc)^2), where n=1 to 4 represent the four corners; use the measured data to adjust the angle and height of the detection platform to ensure that the chip fits perfectly with the contact surface and eliminate any gaps that affect signal transmission.

[0023] Assume that there is a chip to be tested, the size of which is 20 mm × 20 mm, and the four corner coordinates are A(0,0), B(20,0), C(20,20) and D(0,20), in millimeters. The test will be performed according to the following steps: Optical imaging to obtain profiles: The chip surface is initially imaged using a high-resolution optical system to capture clear boundary contour information.

[0024] Calculate the center point coordinates Zc: According to the obtained boundary contour, the coordinates of the four corner points of the chip are determined, and the geometric center position is calculated. For the above rectangular chip, the coordinates of the center point Zc can be obtained by simple arithmetic averaging: Xzc=(Xa+Xb+Xc+Xd) / 4; Yzc=(Ya+Yb+Yc+Yd) / 4; After substituting specific values, we get: Xzc=(0+20+20+0) / 4=10mm; Yzc=(0+0+20+20) / 4=10mm; Therefore, the center point coordinates Zc=(10,10).

[0025] Set up a local coordinate system and measure distances: Establish a new local rectangular coordinate system with Zc as the center, and then calculate the distance Ln from each corner point to the center according to the formula: Ln=sqrt((Xn-Xzc)^2+(Yn-Yzc)^2); Calculate the distances L1 to L4 from the four corner points to the center point respectively: L1=sqrt((0-10)^2+(0-10)^2)=sqrt(100+100)=sqrt(200)≈14.14mm; L2=sqrt((20-10)^2+(0-10)^2)=sqrt(100+100)=sqrt(200)≈14.14mm; L3=sqrt((20-10)^2+(20-10)^2)=sqrt(100+100)=sqrt(200)≈14.14mm; L4=sqrt((0-10)^2+(20-10)^2)=sqrt(100+100)=sqrt(200)≈14.14mm; Adjust the detection platform: Using the measured distances L1 to L4, the angle and height of the inspection platform are fine-tuned by a robotic arm or precision adjustment mechanism to ensure that the chip fits the contact surface perfectly and eliminate any gaps that may affect signal transmission. This step is critical to ensuring the effectiveness of subsequent non-contact scanning and other electrical tests.

[0026] This method can accurately locate each chip to be tested and dynamically adapt to chips of different sizes and shapes. This adaptive positioning mechanism not only improves the detection accuracy, but also enhances the flexibility and versatility of the system. In addition, ensuring a good fit between the chip and the contact surface can effectively reduce misjudgments caused by poor contact, thereby improving overall detection efficiency and reliability. At the same time, the use of mathematical formulas for calculations simplifies the operation process, reduces the possibility of human error, and further improves the level of automation and the value of technical application.

[0027] Step 2: Starting from the positioning information, starting the multi-dimensional scanning system to perform non-contact scanning around the chip surface; further comprising: According to the obtained chip position data, the initial scanning starting point Sc is set to be located at the edge of the chip; starting from the determined starting point Sc, the scanning probe is gradually moved along the preset path Q, where the path Q is composed of a series of discrete points, satisfying Q={Sc,S1,...,Sn}; At each point Sn on the defined path Q, record the reflection intensity J value, and use the formula J=A*exp(-B*d), where A and B are coefficients related to material properties and d represents the scanning depth, to quantify the reflection differences between different layers. After completing data collection for all points Sn, compare the reflection intensity change ΔJ between adjacent points and calculate ΔJ=|Jn-Jn-1| to determine whether there are potential defects or abnormalities.

[0028] Assume that there is a chip to be tested, the size of which is 20 mm × 20 mm, and the four corner coordinates are A(0,0), B(20,0), C(20,20) and D(0,20), in millimeters. The non-contact scanning operation will be performed according to the following steps: Set the initial scan starting point Sc: According to the chip position data, a point located at the edge of the chip is selected as the initial scanning starting point Sc. For example, the lower left corner point A (0,0) can be selected as Sc.

[0029] Define the preset path Q: Set a scanning path Q along the chip surface, which consists of a series of discrete points, satisfying Q={Sc,S1,...,Sn}. In order to cover the entire chip surface, the path can be designed to start from the lower left corner and gradually move inward along the edge until all key areas are covered. The position of each point Si is represented by the coordinates (xi,yi).

[0030] Record the reflection intensity J value: At each point Sn on the path Q, a non-contact scanning probe is used to record the reflection intensity J value. The reflection intensity J can be calculated by the formula: J = A*exp(-B*d); Among them, A and B are coefficients related to material properties, and d represents the scanning depth. For different materials, the specific values ​​of A and B will be different. For example, assuming A=1.0, B=0.5, and the scanning depth d=2 mm at a certain point Sn, the reflection intensity J is calculated as follows: Jn=1.0*exp(-0.5*2)=1.0*exp(-1)≈0.3679; Compare the change ΔJ of reflection intensity between adjacent points: After completing the data collection of all points Sn, calculate the reflection intensity change ΔJ between adjacent points to determine whether there are potential defects or abnormalities. The reflection intensity change ΔJ is calculated by the formula: ΔJ=|Jn-Jn-1|; Assuming that the reflection intensities measured at two consecutive points Sn and Sn-1 are Jn=0.3679 and Jn-1=0.4 respectively, the reflection intensity change ΔJ between them is: ΔJ=|0.3679-0.4|=0.0321; This method can achieve efficient and accurate scanning of the chip surface, ensuring full coverage and detecting any subtle structural differences or defects. This method is applicable to chips of various sizes and shapes, without the need to adjust the equipment settings for each chip type, greatly improving the flexibility and versatility of the system.

[0031] Step 3: Based on the acquired scan data, a three-dimensional structure map is constructed to reflect the chip pin distribution and connection path, further including: The obtained reflection intensity J value is used to perform layer processing on the chip surface to determine the boundary Lm of each layer, where m represents the number of layers; For each layer Lm determined, the thickness Hm of each layer is calculated based on the data recorded at point Sn on path Q, using the formula Hm=(Zn-Zn-1), where Z represents the position coordinate along the vertical direction; Based on the obtained thickness Hm of each layer and the reflection intensity J, draw the interlayer connecting line segment Ei, where i is the pin number, to ensure that each pin position accurately corresponds to the specific coordinates in the three-dimensional space; By using the established connection line segment Ei, all pin distribution and connection path information are integrated to generate a complete three-dimensional mapping diagram F.

[0032] Assume that there is a chip to be tested, and the reflection intensity J value and other related data of multiple points on its surface are obtained through non-contact scanning. The three-dimensional structure mapping diagram will be constructed according to the following steps: Layer processing and boundary determination: According to the obtained reflection intensity J value, the chip surface is layered. For example, suppose it is identified that the chip has three layers, namely the top layer, the middle layer and the bottom layer, which are marked as L1, L2, and L3 respectively. The boundary Lm of each layer can be determined by analyzing the change in reflection intensity, because the reflection characteristics between different materials or layers usually vary significantly.

[0033] Calculate the thickness of each layer Hm: For each layer Lm, the thickness Hm of each layer is calculated based on the data recorded at point Sn on path Q (including the position coordinate Zn). The formula used here is: Hm=Zn-Zn-1; Among them, Zn represents the position coordinate of the current point along the vertical direction, and Zn-1 represents the position coordinate of the previous point. Assuming that there are two consecutive points Sn and Sn-1 in a layer, and their position coordinates along the vertical direction are Zn=5 mm and Zn-1=3 mm respectively, then the thickness Hm of the layer is calculated as follows: Hm=5mm-3mm=2mm; Draw the inter-layer connecting line segment Ei: Based on the obtained thickness Hm of each layer and the reflection intensity J, draw the connecting line segments Ei between layers, where i is the pin number. These line segments are used to accurately correspond the position of each pin to the specific coordinates in three-dimensional space. For example, for a specific pin, if it is located in the second layer and its horizontal position (Xi, Yi) in the plane rectangular coordinate system and the corresponding vertical position Zi are known, a connecting line segment Ei from the first layer to the second layer can be established.

[0034] Generate a complete three-dimensional map F: By using the established connection line segments Ei, all pin distribution and connection path information are integrated to generate a complete three-dimensional mapping diagram F. This diagram not only shows the geometric morphology of the chip surface, but also includes the structure of each internal layer and the electrical connection relationship between the pins, providing comprehensive visualization information.

[0035] This method can achieve high-precision 3D reconstruction of the internal structure of the chip. The specific technical effects include: Accurate stratification: Through the effective use of the reflection intensity J value, the different layers of the chip can be clearly distinguished, ensuring that the boundaries of each layer are accurately identified, thereby improving the accuracy of subsequent analysis.

[0036] High-precision thickness measurement: Based on the discrete point data on path Q, a simple difference method is used to calculate the thickness Hm of each layer. This method is simple and efficient, and can reduce the calculation complexity while ensuring accuracy.

[0037] Detailed pin positioning: By drawing the inter-layer connection line segments Ei, it is ensured that each pin position can be accurately mapped into the three-dimensional space, which helps the subsequent evaluation of pin function and connectivity.

[0038] Comprehensive information display: The final generated 3D map F integrates all the key information of the chip, including geometry, internal structure and pin distribution, providing engineers with an intuitive and detailed reference tool for further analysis and diagnosis.

[0039] Improve detection efficiency: The entire process is highly automated, reducing manual intervention, improving detection speed and efficiency, while ensuring the consistency and reliability of results.

[0040] Step 4: using the formed mapping graph, planning the probe access sequence so that the probe can reach each target position in an orderly manner; further comprising: According to the position coordinates of each pin in the three-dimensional mapping diagram F, the shortest path Spq between adjacent pins is calculated, where p and q represent different pin numbers respectively; according to the established connecting line segment Ei, combined with the shortest path Spq, the probe moving direction Vr is determined, and the formula is Vr=(Xq-Xp) / Spq, where X represents the horizontal coordinate of the pin on the mapping diagram; Based on the generated complete three-dimensional mapping graph F and the probe movement direction Vr, a probe access order O is constructed to ensure that the probe reaches each target point in the most efficient order; using the constructed probe access order O, the probe starting position S0 is adjusted to optimize the overall access path length Pl, using the formula Pl=Sum(Spq), where Sum represents the sum of the distances between all adjacent probe access positions.

[0041] Assuming that the three-dimensional map F of the chip has been constructed, it is now necessary to plan the probe access sequence to ensure that the probes can reach each target position in an orderly manner. The following steps will be followed: Calculate the shortest path Spq between adjacent pins: According to the position coordinates of each pin in the three-dimensional map F, calculate the shortest path Spq between any two adjacent pins p and q. For example, if the position coordinates of pin p are (Xp, Yp, Zp) = (2, 3, 4), and the position coordinates of pin q are (Xq, Yq, Zq) = (5, 7, 8), then the Euclidean distance (i.e., the shortest path) between them can be calculated using the following formula: Spq=sqrt((Xq-Xp)^2+(Yq-Yp)^2+(Zq-Zp)^2); Substituting the above coordinate values ​​into the formula we get: Spq=sqrt((5-2)^2+(7-3)^2+(8-4)^2)=sqrt(9+16+16)=sqrt(41)≈6.4; Determine the probe movement direction Vr: According to the established connecting line segment Ei, combined with the shortest path Spq, determine the direction Vr in which the probe moves from one pin to another. The formula used here is: Vr=(Xq-Xp) / Spq; Assuming that in the above example, the probe is to be moved from pin p to pin q, the horizontal movement direction of the probe is: Vr=(5-2) / 6.4≈0.47; Note that Vr here only represents the movement ratio in the horizontal direction; for practical applications, changes in the vertical direction and other dimensions also need to be considered.

[0042] Construct probe visit order O: Based on the generated complete three-dimensional map F and the probe movement direction Vr, the probe visit order O is constructed. This process can be implemented by a variety of algorithms, such as the Traveling Salesman Problem (TSP) algorithm, which aims to find a path that allows the probe to reach each target point in the most efficient order while minimizing the total movement distance.

[0043] Adjust the probe starting position S0: Using the constructed probe access order O, adjust the probe's starting position S0 to optimize the overall access path length Pl. Here the formula is used: Pl = Sum(Spq); Where Sum represents the sum of the distances between all adjacent probe access locations. For example, if there are three consecutive probe access locations p, q, and r, and the shortest paths between them are Spq=6.4 and Sqr=5.0, respectively, then the total access path length Pl is: Pl=Sum(Spq+Sqr)=6.4+5.0=11.4; The probe start position S0 should be selected to make Pl as small as possible to improve the probe access efficiency.

[0044] This method can significantly improve the efficiency and accuracy of probe testing. The specific technical effects include: Accurate path planning: By calculating the shortest path Spq between adjacent pins, it can ensure that the probe moves along the shortest and most direct route, reducing unnecessary moving distance.

[0045] Efficient moving direction: According to the probe moving direction Vr, the probe can smoothly transition between different layers and avoid sharp turns or unstable movements, which helps protect the probe equipment and ensure test accuracy.

[0046] Optimize the access order: By constructing the probe access order O, the probe can visit each target point in the optimal order, which not only improves the work efficiency but also reduces the movement time of the probe in the non-working state.

[0047] Global path optimization: Adjusting the probe starting position S0 to optimize the overall access path length Pl can further shorten the time of the entire test process and improve production efficiency.

[0048] Enhanced reliability: Planning the probe access sequence in this way reduces potential errors due to improper path selection, such as probe jamming or damage, thereby enhancing the reliability of the entire test process.

[0049] Step 5: According to the set access sequence, the probe is driven to move to the specified coordinate point and a preset signal is applied, further comprising: According to the coordinate point information in the probe access sequence O, the displacement ΔPn required for each movement phase is calculated, where n represents the position index in the access sequence; According to the calculated displacement ΔPn, adjust the current position Pcur of the probe to the next target coordinate Pt, and use the formula Pt=Pcur+ΔPn to complete the position update; After the probe reaches the new coordinate Pt, the signal output module Uo is activated according to the preset conditions, and is ready to apply the specified signal strength Si to the target position; When the signal output module Uo is activated, the signal duration Ti is controlled by adjusting the parameter K, and the formula Ti=G(K,Si) is applied, where G represents the functional relationship between time, intensity and control parameters.

[0050] Assume that the probe's moving path has been planned according to the three-dimensional map F and the probe access sequence O. Now, it is necessary to drive the probe to move to the specified coordinate point according to the set access sequence and apply the preset signal. The following steps will be followed: Calculate the displacement ΔPn: For each moving phase, the required displacement ΔPn is calculated based on the coordinate point information in the probe access order O. For example, if the current probe position is Pcur=(3,4,5) and the next target coordinate Pt=(6,8,9), the displacement ΔPn is: ΔPn=Pt-Pcur=(6-3,8-4,9-5)=(3,4,4); Update the probe position: According to the calculated displacement ΔPn, adjust the probe's current position Pcur to the next target coordinate Pt. Use the formula: Pt=Pcur+ΔPn; Substituting the above values ​​into the formula, we get the new probe position Pt: Pt=(3,4,5)+(3,4,4)=(6,8,9); Activate signal output module Uo: After the probe reaches the new coordinate Pt, the signal output module Uo is activated according to the preset conditions, and is ready to apply the specified signal strength Si to the target position. Assuming that the signal strength Si to be applied is 5V, the probe will set its output voltage to match this value.

[0051] Control signal duration Ti: When the signal output module Uo is activated, the signal duration Ti is controlled by adjusting the parameter K. Here, the function relationship G(K,Si) is used to determine the duration, where K is the control parameter that affects the duration. Assuming that it is known that when K=0.5, for a signal of Si=5V, the duration is Ti=2 seconds, then: Ti=G(K,Si)=G(0.5,5)=2 seconds; The specific form of the function G depends on the characteristics of the actual system and may be an empirical formula derived from experiments or a theoretical expression based on a physical model.

[0052] This method enables precise control of probe movement and signal application. Specific technical effects include: Precise positioning: By accurately calculating the displacement ΔPn of each moving stage and updating the position Pt of the probe accordingly, it can be ensured that the probe can accurately reach the predetermined target coordinates every time.

[0053] Stable signal output: Activate the signal output module Uo and apply the specified signal strength Si according to the preset conditions to ensure the consistency and reliability of the signal output during the test.

[0054] Flexible time control: By using parameter K to adjust the signal duration Ti, the signal action time can be flexibly adjusted according to different test requirements, thus adapting to a variety of test scenarios.

[0055] Step 6: After the signal is applied, the response parameters fed back from the chip are collected as a basis for evaluation; further comprising: After the signal is applied, the data acquisition module Do is started to capture the initial response value Ro fed back by the chip within the preset time window Tw; According to the set signal duration Ti, adjust the time interval Δt of the data acquisition module Do to ensure that the data at each time point is recorded. The formula is Δt=Tw / N, where N represents the number of acquisition cycles; At each time interval Δt, the change in the response parameter ΔRi is recorded, where i represents the i-th acquisition cycle, and the formula ΔRi=Ri-R(i-1) is used to track the trend of the response over time; After completing all scheduled acquisition cycles, all response parameter changes ΔRi are integrated to construct a response parameter sequence Rs, i.e., Rs = {ΔR1, ΔR2, ..., ΔRN}, which serves as the basis for subsequent evaluation.

[0056] Assuming that the probe movement has been completed and the preset signal has been applied, it is now necessary to collect the response parameters fed back from the chip. The following steps will be followed: Start the data acquisition module Do: After the signal is applied, the data acquisition module Do is immediately started to capture the initial response value Ro fed back by the chip within the preset time window Tw. For example, assuming that the preset time window Tw is 5 seconds, the initial response value is recorded during this period.

[0057] Adjust the time interval Δt of the data acquisition module: According to the set signal duration Ti, adjust the time interval Δt of the data acquisition module Do to ensure that the data at each time point is recorded. The formula used here is: Δt=Tw / N; Assuming that in the above example, the preset time window Tw is 5 seconds and the number of acquisition cycles N is 10, the time interval Δt is calculated as follows: Δt=5 seconds / 10=0.5 seconds; Record the change in response parameter ΔRi: At each time interval Δt, record the change in the response parameter ΔRi, where i represents the i-th acquisition cycle. Use the formula: ΔRi=Ri-R(i-1); Assume that in the first acquisition cycle (i=1), the recorded response value R1 is 2.0V, and in the second acquisition cycle (i=2), the recorded response value R2 is 2.3V, then the change in the response parameter ΔR2 is: ΔR2=R2-R1=2.3V-2.0V=0.3V; Construct the response parameter sequence Rs: After completing all the scheduled acquisition cycles, all response parameter changes ΔRi are integrated to construct the response parameter sequence Rs. For example, if there are 10 acquisition cycles, the response parameter sequence Rs can be expressed as: Rs={ΔR1,ΔR2,...,ΔR10}; This sequence not only shows the change in response at each time point, but also provides information on the trend of the response over time.

[0058] This method can achieve efficient and accurate acquisition of the chip's internal feedback response. The specific technical effects include: Real-time data capture: By starting the data acquisition module Do and capturing the initial response value Ro within the preset time window Tw, it is possible to ensure timely acquisition of the first-time feedback after the signal is applied, thereby enhancing the timeliness of the detection.

[0059] Uniform time sampling: According to the set signal duration Ti, the time interval Δt of the data acquisition module Do is adjusted so that the data at each time point can be recorded evenly, improving the integrity and reliability of the data.

[0060] Accurate trend tracking: By recording the change in response parameters ΔRi, the trend of the response over time can be accurately tracked, which helps to identify potential problems or abnormal situations and provide a basis for more in-depth analysis.

[0061] Step 7: Combine the obtained response parameters, compare with the ideal value range, identify abnormal conditions or impedance changes, further including: According to the constructed response parameter sequence Rs, the response change rate Rri of each acquisition cycle is calculated using the formula Rri=ΔRi / Δt, where ΔRi is the change in the response parameter and Δt is the time interval; Compare the preset ideal response change rate range Rri_ideal to determine whether the actual change rate Rri exceeds the limit. If |Rri-Rri_ideal|>ε, it is marked as a potential abnormal point Pi, where ε represents the allowable error; For the identified abnormal point Pi, analyze the impedance change Zci in the corresponding cycle, and apply the formula Zci=V / Ic, where V and Ic represent the voltage and current of the applied signal, respectively, to evaluate the internal state of the chip; Integrate all abnormal points Pi and their corresponding impedance changes Zci to generate an abnormal report Ar, which lists all responses that deviate from the ideal value range and the associated impedance changes.

[0062] Assume that the response parameter sequence Rs of the chip internal feedback has been collected and constructed. Now it is necessary to combine these data, compare them with the ideal value range, and identify abnormal situations or impedance changes. The following steps will be followed: Calculate the response rate of change Rri: According to the constructed response parameter sequence Rs, calculate the response change rate Rri for each acquisition cycle. Use the formula: Rri=ΔRi / Δt; Where ΔRi is the response parameter change, and Δt is the time interval. For example, if in the i-th acquisition cycle, the response parameter change ΔRi is 0.3V and the time interval Δt is 0.5 seconds, the response change rate Rri is calculated as follows: Rri=0.3V / 0.5s=0.6V / s; Compare the ideal response rate range Rri_ideal: Compare the preset ideal response rate range Rri_ideal to determine whether the actual rate of change Rri exceeds the limit. Assuming the ideal response rate range is [0.4V / s, 0.8V / s] and the allowable error ε is 0.1V / s, the judgment condition is: |Rri-Rri_ideal|>ε; If |Rri-0.6V / s|>0.1V / s (assuming the ideal value is the middle value of 0.6V / s), it is marked as a potential abnormal point Pi. For example, if Rri in a certain cycle is 0.9V / s, then: |0.9V / s-0.6V / s|=0.3V / s>0.1V / s; Therefore, this point is marked as a potential outlier point Pi.

[0063] Analyze impedance change Zci: For the identified abnormal point Pi, analyze the impedance change Zci in the corresponding period. Application formula: Zci=V / Ic; Where V and Ic represent the voltage and current of the applied signal, respectively. Assuming that at the abnormal point Pi, the applied voltage V is 5V and the measured current Ic is 0.5A, the impedance change Zci is calculated as follows: Zci=5V / 0.5A=10Ω; Generate an exception report Ar: Integrate all abnormal points Pi and their corresponding impedance changes Zci to generate an abnormal report Ar. The report lists all responses that deviate from the ideal value range and the associated impedance changes. For example, assuming there are two abnormal points P1 and P2, and their corresponding impedance changes are Zc1=10Ω and Zc2=12Ω respectively, then the abnormal report Ar can be expressed as: Ar={ "Abnormal point": [P1, P2], "Impedance change":[10Ω,12Ω] }; In summary, this method of identifying abnormal conditions or impedance changes not only ensures the accuracy of the detection results, but also provides rich information support for subsequent fault analysis and performance optimization, greatly promoting the quality control and technological development of electronic products.

[0064] Step 8: Record any deviations found and adjust subsequent probe operation strategies to optimize testing; further including: According to the generated abnormal report Ar, all responses that deviate from the ideal value range and the associated impedance changes Zci are recorded in the database Db; Analyze the deviation records in the database Db, calculate the weight Wpi of each abnormal point Pi, and use the formula Wpi=H(Zci,Rri), where H represents a comprehensive evaluation function based on impedance change and response change rate; According to the obtained weight Wpi, adjust the probe access order O, re-plan the detection path P' with higher priority, and ensure that the key areas are inspected more carefully. Apply the formula P'=sort(O,Wpi), where sort represents the operation of sorting by weight; Under the guidance of the updated detection path P', the new probe movement speed Vnew and signal strength Si_new are set, through the formula Vnew=M(Wpi) and Si_new=N(Wpi), where M and N represent functions for adjusting speed and strength according to weights, respectively.

[0065] Assume that an exception report Ar has been generated and all responses that deviate from the ideal value range and the associated impedance changes Zci have been recorded. Now it is necessary to record any deviations found and adjust the subsequent probe operation strategy to optimize the test. The following steps will be followed: Record abnormal points to database Db: According to the generated abnormal report Ar, all responses that deviate from the ideal value range and the associated impedance changes Zci are recorded in the database Db. For example, assuming that the abnormal report Ar contains two abnormal points P1 and P2, and their corresponding impedance changes are Zc1=10Ω and Zc2=12Ω respectively, then the following information is recorded in the database Db: Db={ "Abnormal point": [P1, P2], "Impedance change":[10Ω,12Ω], "Response change rate": [0.9V / s, 1.1V / s] }; Calculate the outlier weight Wpi: Analyze the deviation records in the database Db and calculate the weight Wpi of each abnormal point Pi. Use the formula: Wpi=H(Zci,Rri); Where H represents a comprehensive evaluation function based on impedance change and response change rate. Assume that the specific form of H function is: H(Zci,Rri)=0.6*Zci+0.4*Rri; For abnormal points P1 (Zc1=10Ω, Rri=0.9V / s) and P2 (Zc2=12Ω, Rri=1.1V / s), the calculation results are: Wp1=0.6*10+0.4*0.9=6+0.36=6.36; Wp2=0.6*12+0.4*1.1=7.2+0.44=7.64; Adjust the probe access order O: According to the obtained weight Wpi, the probe access order O is adjusted and the detection path P' with higher priority is replanned to ensure that the key areas are inspected more carefully. Application formula: P'=sort(O,Wpi); Assume that the original probe access order O is [P1, P2, P3], and the new path P' after sorting according to the weights calculated above is [P2, P1, P3].

[0066] Set the new probe movement speed Vnew and signal strength Si_new: Under the guidance of the updated detection path P', set the new probe movement speed Vnew and signal strength Si_new. Through the formula: Vnew=M(Wpi); Si_new = N(Wpi); Assume that the specific forms of M and N functions are: M(Wpi)=5+0.5*Wpi; N(Wpi)=5+0.2*Wpi; For the outlier points P1 (Wp1=6.36) and P2 (Wp2=7.64), the new probe movement speed and signal strength are calculated: Vnew_P1=5+0.5*6.36=8.18 (unit: mm / s); Si_new_P1=5+0.2*6.36=6.27 (unit: V); Vnew_P2=5+0.5*7.64=8.82 (unit: mm / s); Si_new_P2=5+0.2*7.64=6.53 (unit: V); In summary, this method of adjusting the probe operation strategy not only ensures the efficiency and pertinence of the detection process, but also provides a solid foundation for continuous optimization of the test process, greatly promoting the quality control and technological development of electronic products.

[0067] Step 9: After completing all the predetermined probe actions, all the test data are summarized and a final report is output to indicate the chip channel status, further including: Collect the test results after all probe operations, including the response change rate Rri, impedance change Zci and abnormal point Pi data, and integrate them into the comprehensive data set Ds; According to the adjusted detection path P' and the set new probe movement speed Vnew and signal strength Si_new, the effect Ei of each detection point is evaluated, and the formula Ei=O(Vnew,Si_new,Rri) is used, where O represents the effect evaluation function, to quantify the test quality of each point; Based on the effect evaluation Ei and the historical deviation records in the database Db, the overall health index HI of the chip pathway is determined, and the formula HI=P(Ei,Wpi) is applied, where P is the function for calculating the health index and Wpi is the weight of the outlier point; All information is summarized to generate a final report Rf, which not only lists the status of all detection points, but also includes the overall health index HI and improvement suggestions for the problems found.

[0068] Assume that all the scheduled probe actions have been completed and the relevant test results have been collected. Now it is necessary to summarize all the test data and output a final report indicating the chip channel status. The following steps will be followed: Integrate the comprehensive dataset Ds: Collect the test results after all probe operations, including the response change rate Rri, impedance change Zci and abnormal point Pi data, and integrate them into the comprehensive data set Ds. For example, assuming there are three test points P1, P2, and P3, their corresponding response change rates Rri are 0.9V / s, 1.1V / s, and 0.7V / s, respectively, impedance changes Zci are 10Ω, 12Ω, and 8Ω, respectively, and abnormal points Pi are P1 and P2, then the comprehensive data set Ds can be expressed as: Ds={ "Detection point": [P1, P2, P3], "Response change rate": [0.9V / s, 1.1V / s, 0.7V / s], "Impedance change":[10Ω,12Ω,8Ω], "Outliers": [P1, P2] }; Evaluate the effect Ei of each detection point: According to the adjusted detection path P' and the set new probe movement speed Vnew and signal strength Si_new, the effect Ei of each detection point is evaluated. Use the formula: Ei=O(Vnew,Si_new,Rri); Where O represents the effect evaluation function. Assume that the specific form of O function is: O(Vnew,Si_new,Rri)=0.4*Vnew+0.3*Si_new+0.3*Rri; For the detection point P1 (Vnew_P1=8.18mm / s, Si_new_P1=6.27V, Rri=0.9V / s), the calculation results are: Ei_P1=0.4*8.18+0.3*6.27+0.3*0.9≈5.71; Similarly, for detection point P2: (Vnew_P2=8.82mm / s,Si_new_P2=6.53V,Rri=1.1V / s), calculated: Ei_P2=0.4*8.82+0.3*6.53+0.3*1.1≈6.12; Determine the overall health index HI: Based on the effect evaluation Ei and the historical deviation records in the database Db, the overall health index HI of the chip pathway is determined. Application formula: HI = P(Ei,Wpi); Where P is the function for calculating the health index, and Wpi is the weight of the outlier. Assume that the specific form of the P function is: P(Ei,Wpi)=0.7*Ei+0.3*Wpi; For the detection points P1 (Ei_P1=5.71, Wp1=6.36) and P2 (Ei_P2=6.12, Wp2=7.64), the calculation results are: HI_P1=0.7*5.71+0.3*6.36≈5.93; HI_P2=0.7*6.12+0.3*7.64≈6.46; Generate the final report Rf: Summarize all the information and generate a final report Rf. The report not only lists the status of all detection points, but also includes the overall health index HI, as well as improvement suggestions for the problems found. For example, the final report Rf can be expressed as: Rf={ "Checkpoint Status":[ {"Point":P1,"Effect":5.71,"Health Index":5.93}, {"Point":P2,"Effect":6.12,"Health Index":6.46}, {"Point":P3,"Effect":N / A,"Health Index":N / A} ], "Overall health index": (5.93+6.46) / 2≈6.20, "Improvement Suggestions":"For abnormal points P1 and P2, it is recommended to further check the cause of impedance change and optimize the design of related areas to improve stability."}; This method can achieve a comprehensive assessment of the chip channel status and provide a detailed final report. The specific technical effects include: Comprehensive data integration: By integrating all test results into a comprehensive data set Ds, the data of each test is fully preserved for subsequent analysis and improvement.

[0069] Accurate effect evaluation: The effect evaluation function O based on probe movement speed, signal strength and response change rate is used to quantify the test quality of each detection point, providing a scientific evaluation basis.

[0070] Dynamic health index: Determine the overall health index HI of the chip pathway based on the effect evaluation Ei and historical deviation records, which can intuitively reflect the overall performance status of the chip and facilitate quick decision-making.

[0071] Systematic report generation: The final report Rf not only lists the status of all detection points in detail, but also provides the overall health index HI and improvement suggestions, providing engineers with clear and intuitive information support.

[0072] Improved diagnostic accuracy: Summarizing test data and generating reports in this way reduces the possibility of misdiagnosis, improves the accuracy and reliability of diagnosis, and thus improves product quality.

[0073] In summary, this method of aggregating test data and generating a final report not only ensures the accuracy of the evaluation results, but also provides rich information support for subsequent fault diagnosis and performance optimization, greatly promoting the quality control and technological development of electronic products.

[0074] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for detecting a path of an integrated circuit package chip, characterized in that: The following steps are involved: The chip to be tested is placed on the testing platform and the positioning information is given. Based on the positioning information, the multi-dimensional scanning system is started to perform non-contact scanning around the chip surface; Based on the acquired scanning data, a three-dimensional structure map is constructed to reflect the chip pin distribution and connection path. The formed map is used to plan the probe access sequence so that the probe can reach each target position in an orderly manner. According to the set access sequence, the probe is driven to move to the specified coordinate point and a preset signal is applied. After the signal is applied, the response parameters fed back from the chip are collected as the basis for evaluation. Combine the obtained response parameters, compare with the ideal value range, identify abnormal conditions or impedance changes, record any deviations found, and adjust subsequent probe operation strategies to optimize the test; After completing all the scheduled probe actions, all the test data are summarized and a final report is output to indicate the chip path status.

2. The method for detecting a path of an integrated circuit package chip according to claim 1, characterized in that: Placing the chip to be tested on the testing platform includes: Use an optical system to perform initial imaging on the chip surface to obtain boundary contour information; According to the obtained boundary contour, the center point coordinate Zc is calculated, where Zc=(Xzc, Yzc), Xzc and Yzc represent the position of the chip geometric center in the plane rectangular coordinate system; With the determined center point Zc as the reference, establish a local coordinate system and measure the distances L1 to L4 from the four corners of the chip to Zc, using the formula Ln=sqrt((Xn-Xzc)^2+(Yn-Yzc)^2), where n=1 to 4 represents the four corners; The measured data is used to adjust the angle and height of the detection platform to ensure that the chip fits perfectly with the contact surface and eliminate any gaps that affect signal transmission.

3. The method for detecting a path of an integrated circuit package chip according to claim 2, characterized in that: The multi-dimensional scanning system is started to perform non-contact scanning around the chip surface, including: According to the obtained chip position data, the initial scanning starting point Sc is set to be located at the edge of the chip; Starting from the determined initial scanning starting point Sc, the scanning probe is gradually moved along a preset path Q, where the path Q is composed of a series of discrete points, satisfying Q={Sc,S1,...,Sn}; At each point Sn on the defined path Q, the reflection intensity J value is recorded, and the formula J=A*exp(-B*d), A and B are coefficients related to material properties, and d represents the scanning depth, which is used to quantify the reflection difference between different layers; After completing the data collection of all points Sn, compare the reflection intensity change ΔJ between adjacent points and calculate ΔJ=|Jn-Jn-1| to determine whether there are potential defects or abnormalities.

4. The method for detecting a path of an integrated circuit package chip according to claim 3, characterized in that: The three-dimensional structure mapping diagram is constructed based on the acquired scanning data to reflect the chip pin distribution and connection path, including: The obtained reflection intensity J value is used to perform layer processing on the chip surface to determine the boundary Lm of each layer, where m represents the number of layers; For each layer Lm determined, the thickness Hm of each layer is calculated based on the data recorded at point Sn on path Q, using the formula Hm=(Zn-Zn-1), where Z represents the position coordinate along the vertical direction; Based on the obtained thickness Hm of each layer and the reflection intensity J, draw the interlayer connecting line segment Ei, where i is the pin number, to ensure that each pin position accurately corresponds to the specific coordinates in the three-dimensional space; By using the established connection line segment Ei, all pin distribution and connection path information are integrated to generate a complete three-dimensional mapping diagram F.

5. The method for detecting a path of an integrated circuit package chip according to claim 4, characterized in that: The method of using the formed mapping graph to plan the probe access sequence so that the probe can reach each target position in an orderly manner includes: According to the position coordinates of each pin in the three-dimensional mapping diagram F, the shortest path Spq between adjacent pins is calculated, where p and q represent different pin numbers respectively; According to the established connecting line segment Ei and the shortest path Spq, the probe moving direction Vr is determined by the formula Vr=(Xq-Xp) / Spq, where X represents the horizontal coordinate of the pin on the mapping diagram; Based on the generated complete three-dimensional map F and the probe moving direction Vr, the probe access order O is constructed to ensure that the probe reaches each target point in the most efficient order; Using the constructed probe access order O, the probe starting position S0 is adjusted to optimize the overall access path length Pl, using the formula Pl=Sum(Spq), where Sum represents the sum of the distances between all adjacent probe access positions.

6. The method for detecting a path of an integrated circuit package chip according to claim 5, characterized in that: The step of driving the probe to move to a specified coordinate point and applying a preset signal according to a set access sequence includes: According to the coordinate point information in the probe access sequence O, the displacement ΔPn required for each movement phase is calculated, where n represents the position index in the access sequence; According to the calculated displacement ΔPn, adjust the current position Pcur of the probe to the next target coordinate Pt, and use the formula Pt=Pcur+ΔPn to complete the position update; After the probe reaches the new coordinate Pt, the signal output module Uo is activated according to the preset conditions, and is ready to apply the specified signal strength Si to the target position; When the signal output module Uo is activated, the signal duration Ti is controlled by adjusting the parameter K, and the formula Ti=G(K,Si) is applied, where G represents the functional relationship between time, intensity and control parameters.

7. The method for detecting a path of an integrated circuit package chip according to claim 6, characterized in that: After the signal is applied, the response parameters fed back from the chip are collected, including: After the signal is applied, the data acquisition module Do is started to capture the initial response value Ro fed back by the chip within the preset time window Tw; According to the set signal duration Ti, adjust the time interval Δt of the data acquisition module Do to ensure that the data at each time point is recorded. The formula is Δt=Tw / N, where N represents the number of acquisition cycles; At each time interval Δt, the change in the response parameter ΔRi is recorded, where i represents the i-th acquisition cycle, and the formula ΔRi=Ri-R(i-1) is used to track the trend of the response over time; After completing all scheduled acquisition cycles, all response parameter changes ΔRi are integrated to construct a response parameter sequence Rs, i.e., Rs = {ΔR1, ΔR2, ..., ΔRN}, which serves as the basis for subsequent evaluation.

8. The method for detecting a chip path in an integrated circuit package according to claim 7, characterized in that: The response parameters obtained by combining are compared with the ideal value range to identify abnormal conditions or impedance changes, including: According to the constructed response parameter sequence Rs, the response change rate Rri of each acquisition cycle is calculated using the formula Rri=ΔRi / Δt, where ΔRi is the change in the response parameter and Δt is the time interval; Compare the preset ideal response change rate range Rri_ideal to determine whether the actual change rate Rri exceeds the limit. If |Rri-Rri_ideal|>ε, it is marked as a potential abnormal point Pi, where ε represents the allowable error; For the identified abnormal point Pi, analyze the impedance change Zci in the corresponding cycle, and apply the formula Zci=V / Ic, where V and Ic represent the voltage and current of the applied signal, respectively, to evaluate the internal state of the chip; Integrate all abnormal points Pi and their corresponding impedance changes Zci to generate an abnormal report Ar, which lists all responses that deviate from the ideal value range and the associated impedance changes.

9. The method for detecting a path of an integrated circuit package chip according to claim 8, characterized in that: Any deviations found are recorded and subsequent probe operation strategies are adjusted to optimize the test, including: According to the generated abnormal report Ar, all responses that deviate from the ideal value range and the associated impedance changes Zci are recorded in the database Db; Analyze the deviation records in the database Db, calculate the weight Wpi of each abnormal point Pi, and use the formula Wpi=H(Zci,Rri), where H represents a comprehensive evaluation function based on impedance change and response change rate; According to the obtained weight Wpi, adjust the probe access order O, re-plan the detection path P' with higher priority, and ensure that the key areas are inspected more carefully. Apply the formula P'=sort(O,Wpi), where sort represents the operation of sorting by weight; Under the guidance of the updated detection path P', the new probe movement speed Vnew and signal strength Si_new are set, through the formula Vnew=M(Wpi) and Si_new=N(Wpi), where M and N represent functions for adjusting speed and strength according to weights, respectively.

10. The method for detecting a path of an integrated circuit package chip according to claim 9, characterized in that: After all the predetermined probe actions are completed, all the test data are summarized and a final report is output to indicate the chip channel status, including: Collect the test results after all probe operations, including the response change rate Rri, impedance change Zci and abnormal point Pi data, and integrate them into the comprehensive data set Ds; According to the adjusted detection path P' and the set new probe movement speed Vnew and signal strength Si_new, the effect Ei of each detection point is evaluated, and the formula Ei=O(Vnew,Si_new,Rri) is used, where O represents the effect evaluation function, to quantify the test quality of each point; Based on the effect evaluation Ei and the historical deviation records in the database Db, the overall health index HI of the chip pathway is determined, and the formula HI=P(Ei,Wpi) is applied, where P is the function for calculating the health index and Wpi is the weight of the outlier point; All information is summarized to generate a final report Rf, which not only lists the status of all detection points, but also includes the overall health index HI and improvement suggestions for the problems found.

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