Image sonar signal compression processing method based on FPGA

Abstract

The invention relates to the technical field of image sonar signal processing, in particular to an image sonar signal compression processing method based on an FPGA. The design method comprises the following steps of: performing orthogonal demodulation on a digital echo signal output by an ADC (Analog to Digital Converter) to obtain an IQ orthogonal signal; the data rate of the orthogonal signals is reduced through the decimation filter bank, and echo bandwidth signals can be output. The digital echo signal is subjected to a signal compression processing method, the data rate of the signal is compressed to the maximum extent, and the quality of a bandwidth signal is ensured. According to the invention, the conversion of the image sonar signal from the array element domain signal to the baseband domain signal is realized through a digital method, and the signal compression method has certain universality and is especially suitable for the field of high-frequency image sonar narrowband signal processing. According to the image sonar multi-channel data compression system, the filter bank operation unit is independently designed, multiple sampling channels multiplex one operation unit, image sonar multi-channel data compression is achieved, the resource expenditure of an FPGA is saved, and the image sonar multi-channel data compression system has wide applicability in the field of image sonar signal processing.

Description

Technical Field

[0001] The present invention relates to the technical field of image sonar signal processing, and in particular to an image sonar signal compression processing method based on FPGA. Background Art

[0002] In a specific underwater environment, various complex noises have a great impact on the performance of image sonar. A more common signal compression method is to filter, digitally convert and downsample the echo signal within the bandwidth B with the frequency f0 as the working center frequency of the image sonar.

[0003] For downsampling processing, if the traditional multi-factorial-accumulation FIR filter method is adopted, it will place stringent requirements on the hardware resources inside the FPGA (Field-Programmable Gate Array), and the FIR filter with fewer coefficients is difficult to achieve the technical requirements of the narrowband characteristics of the image sonar echo signal. If the CIC filter is mainly adopted, although the cascaded half-band HB filter and CIC compensation filter can be relied on to partially improve the inherent shortcoming of the CIC filter's passband drop too fast, there are still shortcomings such as excessive loss of data accuracy. The decimation filtering method using multi-channel multiplexing can effectively solve the problems of high resource consumption of the traditional FIR filter method and data distortion caused by the CIC filter method.

[0004] In the field of imaging sonar, the sonar operating center frequency f0 is typically high (f0 ≥ 100kHz) and the bandwidth B is relatively narrow (B ≈ 0.1·f0). This results in similar signal compression processing specifications, such as decimation rate, for imaging sonars operating at similar frequencies. Therefore, an imaging sonar signal compression processing method is urgently needed to achieve multi-channel signal data compression from the array element domain to the baseband domain, improve the versatility of FPGA software, and enable rapid porting of imaging sonars with different operating frequencies. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide an image sonar signal compression processing method based on FPGA to realize multi-channel signal data compression from the array element domain to the baseband domain, improve the versatility of FPGA software, and realize the rapid transplantation of image sonars with different operating frequencies.

[0006] In view of the shortcomings of the prior art, the present invention solves the technical problems thereof by adopting a technical solution: a method for image sonar signal compression processing based on FPGA, the method being applied in FPGA, comprising the following steps:

[0007] An IQ signal is obtained by orthogonal demodulation according to the input digitized echo signal, wherein the orthogonal signal source is a configurable orthogonal signal source;

[0008] Passing the IQ signal through a first-stage multi-channel multiplexing decimation filter to obtain a primary filtered signal;

[0009] The primary filter signal is input into a secondary multi-channel multiplexing extraction filter to obtain a digitized echo bandwidth signal.

[0010] Preferably, the configurable orthogonal signal source is independent of the IP core, and the internal software of the FPGA adopts the BRAM storage method, and the pre-generated sin(2·π·f1·n) and cos(2·π·f1·n) orthogonal signal source sequences are stored in the BRAM or configured after real-time calculation; the orthogonal demodulation adopts the orthogonal signal source sequence and the digitized echo signal for fixed-point multiplication to obtain the IQ signal.

[0011] Preferably, the coefficients of the first-level multi-channel multiplexing decimation filter can be configured in a real-time writing manner, thereby improving the application range of the method in image sonars with similar bandwidth and similar operating frequency.

[0012] Preferably, the secondary multi-channel multiplexing decimation filter performs secondary filtering on the input primary filtering signal and performs downsampling again to obtain a digitized echo bandwidth signal. Similarly, the secondary multi-channel multiplexing decimation filter can adopt a real-time write configuration method.

[0013] Preferably, the first-level multi-channel multiplexing decimation filter and the second-level multi-channel multiplexing decimation filter do not use the IP core method. At the same time, in order to adapt to the multi-channel characteristics of the image sonar, the basic operation unit of the filter is built using the channel multiplexing technology. The basic operation unit is an 8-coefficient multiplication and accumulator, and the number of multiplexing channels of the multi-channel multiplexing filter is calculated according to the FPGA operation frequency. Finally, the signal extraction preprocessing of the image sonar echo signal is achieved with less FPGA resource consumption. This method also avoids the defects such as the rapid decline of the bandwidth signal tail brought about by the CIC filter group technology route.

[0014] Preferably, the 8-coefficient multiplication and accumulation unit includes a data RAM, a coefficient RAM, a multiplication and addition unit and a control unit. The depth of the coefficient RAM is 8*16 bits. The single-channel data x m (n) When performing 8-coefficient multiplication and accumulation operations, the depth of the dual-port RAM is also 8*16 bits, which is used to store the x values ​​at 8 moments. m (n) data; x m (n) Input a data, x m (n) out Then 8 data are output for multiplication with the filter coefficients and then accumulated. The output speed of coefficient RAM is the same as that of x in dual-port RAM. m(n) at the same speed.

[0015] The beneficial effects of the present invention are as follows:

[0016] 1. The present invention adopts an independently designed FPGA-based signal compression method to effectively realize the transplantation of image sonars with different working frequencies, which reduces manual work and effectively improves the versatility of the software;

[0017] 2. The method of the present invention adopts a multi-channel multiplexed decimation filter to replace the traditional FIR filter and CIC filter bank, effectively solving the shortcomings of the traditional method;

[0018] 3. The advantages of the 8-coefficient multiplier-accumulator and 16-channel multiplexing filter of the present invention are that the independently designed operation unit can operate at a higher operating frequency. By adopting the 16-channel multiplexing technology, the internal resource consumption of the FPGA can be effectively reduced, thereby providing the possibility for FPGA implementation of image sonar data compression of more receiving channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a flow chart of the image sonar signal compression processing method based on FPGA of the present invention;

[0020] Figure 2 This is a flow chart of IQ quadrature demodulation involved in the present invention;

[0021] Figure 3 This is a schematic diagram of the structure of an 8-coefficient multiplier-accumulator according to the present invention;

[0022] Figure 4 The present invention is a schematic structural diagram of a 16-channel multiplexing filter. DETAILED DESCRIPTION

[0023] The present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. The embodiments of the present invention are provided for purposes of illustration and description and are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art. The embodiments are chosen and described to better illustrate the principles of the invention and its practical application, and to enable those skilled in the art to understand the invention and design various embodiments with various modifications suitable for specific applications.

[0024] In order to solve the problem of multi-channel signal data compression from the array element domain to the baseband domain of image sonar, the present invention provides an image sonar signal compression processing method based on FPGA, which is implemented through the following process:

[0025] First, quadrature demodulation is performed on the input digitized echo signal to obtain an IQ signal. The quadrature signal source is a configurable quadrature signal source. The configurable quadrature signal source is independent of the IP core. The FPGA internal software uses a BRAM storage method, storing a pre-generated orthogonal signal source sequence in the BRAM or configuring it through real-time calculation. The quadrature demodulation performs fixed-point multiplication of the orthogonal signal source sequence with the digitized echo signal to obtain the IQ signal. The digitized echo signal typically has a central operating frequency of f0 and a bandwidth of B, typically B≈0.1·f0. The input digitized echo signal is a digitized echo signal data stream output by the image sonar device after high-speed ADC sampling. The input digitized echo signal is quadrature demodulated to obtain the IQ signal. The orthogonal signal source sequence used in the quadrature demodulation operation is stored in the FPGA internal BRAM after pre-calculation based on the central operating frequency of the image sonar. The input digitized echo signal is multiplied by the orthogonal signal source sequence to obtain the quadrature IQ signal. The digitized echo signal is assumed to be x n =cos(ω0·n+ω0·(n-1)·τ), where ω0=2·π·f0, the orthogonal signal source sequences are: -2·sin(ω1·n) and 2·cos(ω1·n), and the orthogonal demodulation operation is the multiplication operation of the two inside the FPGA, and the orthogonal demodulation real and imaginary part values ​​are:

[0026] Demodule_I=sin[(ω1+ω0)·n+ω0·(n-1)·τ]+sin[(ω1-ω0)·n-ω0·(n-1)·τ];

[0027] Demodule_R=cos[(ω1+ω0)·n+ω0·(n-1)·τ]+cos[(ω1-ω0)·n-ω0·(n-1)·τ];

[0028] Where ω0 is the center frequency of the digitized echo signal, and ω1 is the frequency of the orthogonal signal source sequence, which can be configured according to the different center operating frequencies of the imaging sonar. The multiplication operation also uses multi-channel multiplexing to reduce the consumption of multiplier resources within the FPGA. The expression of the digitized echo signal x(n) uses a single-frequency CW signal form, which is one of the signal forms commonly used in imaging sonar. Orthogonal demodulation operations of linear frequency modulation (LFM) signals, hyperbolic frequency modulation (HFM) signals, or other combined signals can reach similar conclusions. Single-frequency CW signals are quite common in the field of imaging sonar.

[0029] Then, the IQ signal is passed through a first-stage multi-channel multiplexing extraction filter to obtain a primary filtered signal; the coefficients of the first-stage multi-channel multiplexing extraction filter can be configured in a real-time writing manner, thereby improving the application range of this method in image sonars with similar bandwidth and similar operating frequency.

[0030] Finally, the primary filter signal is input into a secondary multi-channel multiplexing decimation filter to obtain a digitized echo bandwidth signal. The secondary multi-channel multiplexing decimation filter performs secondary filtering on the input primary filter signal and downsamples it again to obtain a digitized echo bandwidth signal. Similarly, the secondary multi-channel multiplexing decimation filter can be configured using real-time write.

[0031] The IQ signal undergoes a first-level multi-channel multiplexing decimation filter to obtain a primary filtered signal. Multi-channel multiplexing decimation is characterized by determining the number of channel multiplexing and the first-level decimation ratio based on the data input ADC data rate. The decimation ratio determines the output rate of the primary filtered signal to meet the echo signal bandwidth requirements of different image sonars. The primary filtered signal undergoes a second-level multi-channel multiplexing decimation filter to obtain a digitized echo bandwidth signal. Neither the first-level nor the second-level multi-channel multiplexing decimation filter utilizes an IP core. To accommodate the multi-channel characteristics of image sonars, a basic filter operation unit is constructed using channel multiplexing technology. The basic operation unit is an 8-coefficient multiplication and accumulation unit. The number of multiplexing channels of the multi-channel multiplexing filter is calculated based on the FPGA operation frequency. Ultimately, signal extraction preprocessing of image sonar echo signals is achieved with minimal FPGA resource consumption. This method also avoids the drawbacks of the bandwidth signal tail, such as the rapid drop-off, that arises from the use of CIC filter bank technology.

[0032] The first-stage multi-channel multiplexing filter and the second-stage multi-channel multiplexing filter use the same implementation structure. Their basic operation units avoid using IP cores and adopt an independently designed pure logic method to reduce dependence on specific FPGA manufacturers. The coefficients of the first and second-stage multi-channel multiplexing filters are pre-calculated according to different decimation rates and bandwidths and input into the BRAM inside the FPGA. They can also be updated by real-time writing, ultimately obtaining a digitized bandwidth echo signal. The multi-channel multiplexing decimation filter uses an 8-coefficient multiplier accumulator as its basic structure and adopts a 16-channel multiplexing basic structure, greatly reducing the consumption of FPGA multiplier resources by traditional methods. The digitized echo bandwidth signal can be obtained by cascading two or even multiple stages of multi-channel multiplexing decimation filters. The correlation coefficients in this method can be configured in real time according to the actual needs of the image sonar.

[0033] The present invention discloses an FPGA-based image sonar signal compression and processing method. First, the orthogonal demodulation and decimation filtering of the input digitized echo signal are all implemented digitally within the FPGA via software. Second, a configurable orthogonal signal source sequence adapts to the different central operating frequencies of the image sonar, and orthogonal sin(ω1·n) and cos(ω1·n) signals of different frequencies are output in real time via command parameter configuration. Finally, compared to conventional technologies, the present invention replaces traditional FIR filters and CIC filter banks with multi-channel multiplexing decimation filters, effectively addressing the shortcomings of conventional methods. The decimation rate of the multi-channel multiplexing filter is determined by the ratio of the image sonar ADC sampling rate and the bandwidth data output rate, generally taking integer form. The decimation rates of the primary and secondary filters are then determined using the principle of approximate distribution. This method allows for convenient adjustment of the decimation rate and filter coefficients to accommodate the varying bandwidth requirements of the image sonar. Finally, the orthogonal signal source sequence and multi-channel multiplexing decimation filter described in this method do not utilize IP cores or dedicated DDS chips provided by FPGA manufacturers, and possesses independent intellectual property rights. This method can be widely used in the field of image sonar and has certain practical and scientific research value.

[0034] The present invention sequentially cascades an orthogonal demodulation operation, a first-level multichannel multiplexing decimation filter, and a second-level multichannel multiplexing decimation filter within an FPGA. The orthogonal signal source sequence involved in the orthogonal demodulation operation is configurable using command parameters. This means that all operations are implemented digitally, independent of the IP core. The multichannel multiplexing filter in this method replaces traditional analog filtering, FIR filtering, and CIC compensation filter bank methods. This demonstrates that the present method implements orthogonal demodulation, filtering, and downsampling of digitized echo signals, thereby obtaining a digitized echo bandwidth signal.

[0035] To facilitate understanding, the basic principles and implementation points of each link are analyzed through specific examples. The image sonar of the implementation example uses a type of basic parameters from mainstream products on the market: the image sonar center operating frequency is 450kHz, the bandwidth is 45kHz, the number of channels is 96, and the ADC sampling rate is f s =5MSPS, the final digitized echo bandwidth signal is 62.5kHz, and the total decimation rate is 80:1.

[0036] The specific implementation steps are as follows:

[0037] 1.1Digital echo signal

[0038] The input signal adopts a single-frequency CW signal which is common in the image sonar signal form. Its digital echo signal expression is:

[0039]

[0040] Where m is the number of image sonar array elements, n is the sampling point time, and Δt is the ADC sampling interval, that is, Δt = 1f s , ω0 is the center operating frequency, It is the standard delay quantity under far-field conditions with array element No. 1 as the reference.

[0041] 1.2 Quadrature Demodulation

[0042] The real and imaginary signals can be obtained by multiplying the digitized echo signal with the orthogonal signal source sequence -2·sin(ω1·n) and 2·cos(ω1·n).

[0043] Its expression is:

[0044]

[0045] Where ω1 is the frequency of the orthogonal signal source sequence. When ω1=ω0, the orthogonal demodulation is called the same-frequency orthogonal demodulation, and when ω1≈ω0, it is called the difference-frequency orthogonal demodulation.

[0046] The generation of orthogonal signal source sequences does not rely on IP cores such as the CORDI C provided by FPGA manufacturers, nor does it use pre-stored fixed-frequency sine and cosine sequences. Instead, a combination of lookup tables and linear interpolation is used to achieve real-time output of parameter-configurable signal source sequences to adapt to the use scenarios of imaging sonars with different central operating frequencies.

[0047] Among all kinds of hardware resources inside the FPGA, multiplier resources are the most scarce. To effectively reduce the consumption of multipliers in the orthogonal demodulation stage, the following method is adopted.

[0048] The channel sampling data from the ADC's parallel input is sequentially stored in the FPGA's internal BRAM memory cells and multiplied with the orthogonal signal source sequence through a parallel-to-serial conversion operation. The multipliers utilize channel multiplexing technology, requiring only two multiplier resources for the entire orthogonal demodulation operation.

[0049] Passing the real and imaginary signals through a low-pass filter removes the high-frequency (ω1 + ω0) components and retains the low-frequency (ω1 - ω0) components. This method achieves spectrum shifting of the digitized echo signal, thereby obtaining orthogonal IQ signals. In this embodiment, ω1 can be 451 kHz.

[0050] 1.3 Multi-channel multiplexing decimation filter

[0051] Traditional FIR filters are implemented using multiplication and addition operations. First-order filtering requires one multiplier. For high-rate multi-stage cascade filters, more than a hundred filters are required. If each channel IQ uses a separate filter, tens of thousands of multipliers are required, which will seriously consume the FPGA's internal multiplier resources, making it difficult to implement extraction filtering functions on a single FPGA.

[0052] The traditional CIC filter consists of a multi-stage integrator, a decimator, and a multi-stage comb filter. It is a high-efficiency filter that does not require complex multiplication operations, has a simple structure, and is easy to implement in engineering. Because the CIC filter does not use multipliers but instead uses adder operations, it can be implemented in an FPGA with fewer hardware resources. However, in actual use, CIC has disadvantages such as large passband attenuation, transition bandwidth, and unclear stopband suppression characteristics. To further reduce sidelobe attenuation, a half-band HB filter and a CIC compensation filter can be cascaded to effectively alleviate the passband attenuation problem of the CIC filter within the frequency band, but this also brings defects such as loss of data accuracy.

[0053] Based on the above two commonly used image sonar signal preprocessing methods, the present invention proposes a decimation filter design based on an improved FIR filter as follows:

[0054] (1) 8-coefficient multiplication accumulator

[0055] The basic structure of the 8-coefficient multiplier accumulator consists of data RAM, coefficient RAM, multiplication and addition unit and control unit, as shown below Figure 3 shown.

[0056] In the 8-coefficient multiplication and accumulation unit, the coefficient RAM depth is 8*16bit, and the single-channel data x m (n) When performing 8-coefficient multiplication and accumulation operations, the depth of the dual-port RAM is also 8*16 bits, which is used to store the x values ​​at 8 moments. m (n) Data. x m (n) Input a data, x m (n) out Then 8 data are output for multiplication with the filter coefficients and then accumulated. The output speed of coefficient RAM is the same as that of x in dual-port RAM. m (n) has the same speed, the read clock frequency in the figure should be 8 times the write clock frequency.

[0057] (2) 16-channel multiplexing filter

[0058] The structure of a 16-channel multiplexing filter differs from that of a single-channel filter in that all 16 data points must be multiplied by the filter coefficients. The multiplication of the data by the next coefficient is delayed by 16 cycles, resulting in a total delay of 16 cycles for the 16 channels. For a single channel, the equivalent delay is still 1 cycle, as shown in the figure below. Here, h(k) is the filter order. When using a 16-channel multiplexing filter, the signal processing clock must be increased by 16 times. Figure 4 The basic structure of the 16-channel multiplexing filter is an 8-coefficient multiplier-accumulator, and the filter coefficients for each channel are identical. The dual-port RAM stores data from 16 channels at eight different times, resulting in a depth of 128. The address changes are shown in the following equation, where j increases at a rate eight times that of i.

[0059] addra(m(i+1))=[addra(m(i))+1]%160

[0060] addrb(m(j+1))=[addrb(l(j))+16]%160

[0061] When 16 channels multiplex eight coefficient accumulators, the coefficient RAM depth is 8. While the address increments by 16 when reading data from the data RAM, the coefficient RAM address remains unchanged, initially set to 0, and cycles through the address cycle with a period of eight. The data and coefficients are multiplied after the readout clock and added to the previous multiplication result, completing the addition of all eight multiplication results and outputting the accumulated result, completing the multiplication-addition operation required by the filter.

[0062] Based on a 16-channel multiplexing filter, an 8-coefficient multiplier-accumulator (MC) is used to achieve 128x multiplexing, reducing the FPGA's multiplier resources by a factor of 128. Taking a 24th-order, first-stage decimation filter as an example, 16-channel data filtering consists of five 8-coefficient MCAs and four delay structures. An 83rd-order, second-stage decimation filter, similar to the first-stage decimation filter, requires a total of 11 8-coefficient MCAs. Using a two-stage cascade, a total of 16 multipliers are required for 16 channels. Each channel signal undergoes orthogonal demodulation to transform it into two I / Q signals. The I and Q signals pass through independent filter structures. Therefore, 32 multipliers are required for each of the 16 I / Q signals, and 192 multipliers are required for 96 channels. This is achievable within mainstream mid-range FPGAs.

[0063] In summary, the present invention provides an FPGA-based image sonar signal compression processing method, the processing flow is as follows: Figure 1As shown, the fully digital design approach effectively alleviates the pressure of analog circuit design and improves the accuracy of orthogonal demodulation. The configurable orthogonal signal source sequence eliminates the need for circuit operating frequency adjustment, enhancing the software's flexibility and versatility. A two-stage multi-channel multiplexing decimation filter cascade method, while meeting the narrowband technical requirements of imaging sonar echo signals, progressively decimates and downsamples the echo signal data stream, ultimately outputting a digitized echo bandwidth signal, effectively reducing the pressure on subsequent signal processing and transmission bandwidth. The orthogonal demodulation and filtering operations in the process are all performed digitally. The image sonar signal compression processing method of the present invention achieves multi-channel signal data compression from the array element domain to the baseband domain. The software configurability of the coefficients in the present method improves the versatility of the FPGA software for the processing method, enabling rapid porting to image sonars with different operating frequencies. Compared to traditional technologies, the configurable orthogonal signal source sequence and multi-channel multiplexing filter technology in the present method effectively enhance software flexibility and versatility. Finally, the present method effectively reduces the workload of software porting for different imaging sonar products, demonstrating its broad applicability.

[0064] It should be understood that the above-described method and the following detailed description of the implementation are merely exemplary and do not limit the present invention.

Claims

1. An image sonar signal compression processing method based on FPGA, characterized in that: The method is applied in FPGA and includes the following process: An IQ signal is obtained by orthogonal demodulation according to the input digitized echo signal, wherein the orthogonal signal source is a configurable orthogonal signal source; The IQ signal is subjected to a first-stage multi-channel multiplexing extraction filter to obtain a primary filtering signal; The primary filter signal is input into a secondary multi-channel multiplexing extraction filter to obtain a digitized echo bandwidth signal.

2. The FPGA-based image sonar signal compression processing method according to claim 1 is characterized in that: The configurable orthogonal signal source is independent of the IP core. The internal software of the FPGA adopts the BRAM storage method. The pre-generated sin(2·π·f1·n) and cos(2·π·f1·n) orthogonal signal source sequences are stored in the BRAM or configured after real-time calculation. The orthogonal demodulation adopts the fixed-point multiplication of the orthogonal signal source sequence and the digitized echo signal to obtain the IQ signal.

3. The FPGA-based image sonar signal compression processing method according to claim 2 is characterized in that: The coefficients of the first-stage multi-channel multiplexing decimation filter can be configured in a real-time writing manner, thereby improving the application range of the method in image sonars with similar bandwidth and similar operating frequency.

4. The FPGA-based image sonar signal compression processing method according to claim 3 is characterized in that: The two-level multi-channel multiplexing decimation filter performs secondary filtering on the input primary filtering signal and performs downsampling decimation again, thereby obtaining a digital echo bandwidth signal. Similarly, the two-level multi-channel multiplexing decimation filter can adopt a real-time write configuration method.

5. The FPGA-based image sonar signal compression processing method according to claim 1, characterized in that: The first-level multi-channel multiplexing decimation filter and the second-level multi-channel multiplexing decimation filter do not use the IP core method. At the same time, in order to adapt to the multi-channel characteristics of image sonar, the basic operation unit of the filter is built by using the channel multiplexing technology. The basic operation unit is an 8-coefficient multiplication accumulator, and the number of multiplexing channels of the multi-channel multiplexing filter is calculated according to the FPGA operation frequency. Finally, the signal extraction preprocessing of the image sonar echo signal is realized with less FPGA resource consumption. At the same time, this method avoids the defects such as the rapid decline of the bandwidth signal tail caused by the CIC filter group technology route.

6. The FPGA-based image sonar signal compression processing method according to claim 5 is characterized in that: The 8-coefficient multiplication accumulator includes a data RAM, a coefficient RAM, a multiplication and addition unit, and a control unit. The depth of the coefficient RAM is 8*16 bits. m (n) When performing 8-coefficient multiplication and accumulation operations, the depth of the dual-port RAM is also 8*16 bits, which is used to store the x at 8 moments m (n) data; x m (n) Input a data, x m (n) out The output of 8 data is used for multiplication with the filter coefficients and accumulation. The output speed of the coefficient RAM is the same as that of the dual-port RAM. m (n) at the same speed.

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