Method for performing data access control for host device, controller, data access device and electronic device

Abstract

The invention provides a method for performing data access control for a host device, a controller, a data access device and an electronic device. The method may include receiving a plurality of host commands from a host device for data access to media according to the plurality of host commands; and performing a data access optimization procedure to maintain the correctness of data reception, for example: performing data reception on the media to obtain at least one codeword; performing a first low density parity check (LDPC) code decoding operation on the plurality of row segments, wherein a part of the row segments are abnormal row segments corresponding to puncture variable nodes; searching at least one row segment satisfying at least one predetermined selection condition to perform at least one second LDPC code decoding operation on the at least one row segment; performing a plurality of third LDPC code decoding operations on the plurality of line segments; and returning the error-free data to the host device.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a method for performing data access control for a host device and related apparatus such as a data access device, a controller in the data access device, and an electronic device including the data access device. Background Art

[0002] A memory device may include a flash memory for storing data, and access management for the flash memory is quite complex. For example, the memory device may be a memory card, a solid state drive (SSD), or an embedded storage device (e.g., an embedded storage device that complies with the universal flash storage specification (UFS)). When manufacturers try to use downgraded flash memory dies to reduce overall costs, certain problems may occur. In particular, the associated characteristics of downgraded flash memory dies are unstable and data errors are prone to occur, which may lead to reduced overall performance of the memory device. Related technologies attempt to solve this problem, however, additional problems such as certain side effects may be introduced. For example, in the event of an uncorrectable error, it may take a lot of time to use a more powerful data processing mechanism to try to recover the data. Therefore, a novel method and related architecture are needed to solve these problems without introducing side effects or in a manner that is less likely to introduce side effects. Summary of the invention

[0003] One of the purposes of the present invention is to provide a method and related equipment such as a data access device, a controller in the data access device and an electronic device including the data access device for controlling data access for a host device, so as to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a method for controlling data access for a host device, wherein the method can be applied to a controller of a data access device. The method can include: receiving a plurality of host commands from the host device for performing data access to at least one medium according to the plurality of host commands, wherein the data access includes data reception; and performing a data access optimization procedure for maintaining the correctness of the data reception. For example, the data access optimization procedure may include: receiving the data from the at least one medium to obtain at least one codeword, wherein the at least one codeword includes a plurality of column segments; in a first decoding stage, performing a plurality of first low-density parity-check (LDPC) code decoding operations on the plurality of column segments, wherein a portion of the plurality of column segments are abnormal column segments corresponding to puncture variable nodes; in a second decoding stage, finding at least one column segment that satisfies at least one predetermined selection condition to perform at least one second low-density parity-check code decoding operation on the at least one column segment; in a third decoding stage, performing a plurality of third low-density parity-check code decoding operations on the plurality of column segments; and after decoding is completed, returning error-free data corresponding to the at least one codeword to the host device.

[0005] In addition to the above method, the present invention also provides a controller of a data access device, wherein the data access device can be used to perform data access control for a host device. In addition, the controller includes a processing circuit, a transmission interface circuit, and a low-density parity check code decoding circuit, wherein the processing circuit is used to control the controller according to a plurality of host commands from the host device to allow the host device to access at least one medium through the controller, the transmission interface circuit is used to communicate with the host device, and the low-density parity check code decoding circuit is used to perform low-density parity check code decoding. In addition, the controller receives the plurality of host commands from the host device through the transmission interface circuit in the controller, so as to perform data access to the at least one medium according to the plurality of host commands, wherein the data access includes data reception. The controller performs a data access optimization procedure to maintain the correctness of the data reception. For example, the data access optimization program includes: receiving the data from at least one medium to obtain at least one codeword, wherein the at least one codeword includes multiple row segments; using the low-density parity-check code decoding circuit to perform multiple first low-density parity-check code decoding operations on the multiple row segments in a first decoding stage, wherein a portion of the multiple row segments are abnormal row segments corresponding to puncturing variable nodes; using the low-density parity-check code decoding circuit to find at least one row segment that meets at least one predetermined selection condition in a second decoding stage to perform at least one second low-density parity-check code decoding operation on the at least one row segment; using the low-density parity-check code decoding circuit to perform multiple third low-density parity-check code decoding operations on the multiple row segments in a third decoding stage; and after decoding is completed, returning error-free data corresponding to the at least one codeword to the host device.

[0006] In addition to the above method, the present invention also provides a data access device including the above controller, wherein the data access device includes: the controller, which is used to control the operation of the data access device.

[0007] In addition to the above method, the present invention also provides an electronic device including the above data access device, wherein the electronic device further includes the host device coupled to the data access device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor and used to provide power to the at least one processor and the data access device.

[0008] The method and related equipment of the present invention can ensure that the data access device can operate properly under different circumstances, and in particular, can ensure the correctness of the data. Although the relevant characteristics of the degraded flash memory die are unstable, the method and related equipment of the present invention can perform at least one read retry operation to obtain relevant information for soft decoding. For example, the method and related equipment of the present invention can find the at least one row segment that meets the at least one predetermined selection condition in the soft decoding process, and perform decoding processing on the at least one row segment with a higher priority to control the rapid convergence of relevant decoding parameters to improve the overall decoding speed, so that the overall data access performance is greatly improved in the case of abnormal row segments corresponding to punctured variable nodes. In addition, the method and related equipment of the present invention can solve the problems of the related technology without introducing side effects or in a way that is unlikely to introduce side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0010] Figure 2A FIG. 4 is a schematic diagram of a LDPC code decoding control scheme according to an embodiment of the present invention.

[0011] Figure 2B According to an embodiment of the present invention, Figure 2A The low-density parity-check code decoding control scheme shown involves a barrel shifter.

[0012] Figure 2C According to an embodiment of the present invention, Figure 2B Certain implementation details of the barrel shifter are shown.

[0013] Figure 3 According to an embodiment of the present invention, Figure 2A The LDPC code decoding control scheme shown involves a codeword, wherein the codeword may include a set of channel values.

[0014] Figure 4A According to an embodiment of the present invention, Figure 2A A plurality of sign bits involved in the LDPC code decoding control scheme are shown.

[0015] Figure 4B According to an embodiment of the present invention, Figure 2A The LDPC decoding control scheme shown involves a sign bit and a plurality of soft bits.

[0016] Figure 5AAccording to an embodiment of the present invention, Figure 2A A parity check matrix involved in the low density parity check code decoding control scheme shown in FIG. 1 , wherein a basic matrix is ​​also shown in FIG. Figure 5A for better understanding.

[0017] Figure 5B According to an embodiment of the present invention, Figure 5A Multiple cases of the basic matrix are shown.

[0018] Figure 5C According to an embodiment of the present invention, Figure 5A Multiple base matrices within the parity check matrix are shown.

[0019] Figure 5D According to an embodiment of the present invention, Figure 5C The case where some of the multiple basic matrices are zero matrices is shown.

[0020] Fig. 6A According to an embodiment of the present invention, Figure 2A The LDPC code decoding control scheme shown involves message bits and parity bits within the codeword.

[0021] Figure 6B According to an embodiment of the present invention, Fig. 6A The situation shown is that some of the multiple parity bits become puncture bits.

[0022] Figure 7 FIG. 4 is a schematic diagram of a rearrangement decoding control scheme of a method for performing data access control for a host device according to an embodiment of the present invention.

[0023] Fig. 8A According to an embodiment of the present invention, Figure 7 A workflow of the rearranged decoding control scheme is shown.

[0024] Figure 8B According to an embodiment of the present invention, Fig. 8A Some implementation details of this workflow are shown.

[0025] Fig. 9 The relationship between the elements in the parity-check matrix and certain row segments to be processed in the method is illustrated according to an embodiment of the present invention.

[0026] Fig.10 A schematic diagram of an electronic device involved in the method is shown according to an embodiment of the present invention, wherein the electronic device may include a data access device.

[0027] Fig.11A According to another embodiment of the present invention, a schematic diagram of an electronic device involved in the method is shown, wherein the electronic device may include an optical fiber transceiver.

[0028] Fig. 11B According to another embodiment of the present invention, a schematic diagram of an electronic device involved in the method is shown, wherein the electronic device may include a wired network transceiver.

[0029] Fig. 11C According to another embodiment of the present invention, a schematic diagram of an electronic device involved in the method is shown, wherein the electronic device may include a wireless network transceiver.

[0030] Fig.12 A workflow of a data access optimization procedure of the method is described according to an embodiment of the present invention.

[0031]

Explanation of symbols

[0032] 10,11,11_1~11_3: Electronic devices

[0033] 50: Host device

[0034] 52: Processor

[0035] 54: Power supply circuit

[0036] 58: Transmission interface circuit

[0037] 100: memory device

[0038] 110: memory controller

[0039] 112: Microprocessor

[0040] 112C: Program code

[0041] 112M: Read-only memory

[0042] 114: Control logic circuit

[0043] 114D,200,700: Low-density parity check (LDPC) code decoding circuit

[0044] 116: Random Access Memory

[0045] 116AM: Temporary logical to physical (L2P) address mapping table

[0046] 118: Transmission interface circuit

[0047] 120: Non-volatile (NV) memory

[0048] 120C: Memory Cells

[0049] 120AM: Global logical to physical (L2P) address mapping table

[0050] 122-1~122-N E :Non-volatile (NV) memory devices

[0051] 205: Channel value (CV) memory

[0052] 210: Variable Node Unit (VNU)

[0053] 221,222: Barrel shifter (BS) circuit

[0054] 220,221_1,221_2~221_F,222_1,222_2~222_F: Barrel shifter (BS)

[0055] 220D:Decoder

[0056] 220S: Shift circuit

[0057] 230: Check Node Unit (CNU)

[0058] 710: Normal row segment processing subcircuit

[0059] 720: Abnormal row segment processing subcircuit

[0060] 730: Line segment s processing subcircuit

[0061] 1000: Data access device

[0062] 1000_1: Fiber optic transceiver

[0063] 1000_2: Wired network transceiver

[0064] 1000_3: Wireless network transceiver

[0065] 1010, 1010_1~1010_3: transmission media controller

[0066] 1014, 1014_1~1014_3: Transmission media interface circuit

[0067] a,b: line segment

[0068] B,B 0,0 ,B 0,1 ~B 0,G-2 ,B 0,G-1 ,B 1,0 ,B 1,1 ~B 1,G-2 ,B 1,G-1 ,B F-1,0 ,B F-1,1 ~BF-1,G-2 ,B F-1,G-1 ,B 0,0 ~B 0,6 ,B 1,0 ~B 1,6 ,B 2,0 ~B 2,6 ,B 3,0 ~B 3,6 :Basic Matrix

[0069] Bit0, Bit1, Bit2~Bit w-1 :Bit

[0070] CH(i): Channel

[0071] CK(0), CK(1)~CK(G-1): data block (or "row segment")

[0072] CNT SHIFT : Shift number

[0073] CV: Channel value

[0074] MR: Memory Region

[0075] Phase(0)~Phase(3): Phase

[0076] P1~P8: Programming status

[0077] Sign_bit(0)~Sign_bit(2),Sign_bit(j): Sign bit

[0078] Soft_bit(j,k): soft bit

[0079] Vth: threshold voltage

[0080] x: input signal

[0081] x0,x1~x Z-1 :Input bits

[0082] y: output signal

[0083] y0,y1~y Z-1 : Output bits

[0084] S11, S12, S21, S211~S213, S213A, S214, S31~S33, S40~S45: Steps DETAILED DESCRIPTION

[0085] Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors; which may be collectively referred to as a processor 52), a power supply circuit 54, and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other through a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 may be used to provide storage space for the host device 50, and may obtain the one or more driving voltages from the host device 50 as a power source for the memory device 100. Examples of the host device 50 may include, but are not limited to: a multi-function mobile phone, a tablet computer, a wearable device, and a personal computer, such as a desktop computer and a notebook computer. Examples of the memory device 100 may include, but are not limited to, portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS or XD specifications, solid state drives (SSDs), and different types of embedded memory devices (e.g., embedded memory devices conforming to the Universal Flash Storage (UFS) specification or the embedded multi-media card (eMMC) specification). According to the present embodiment, the memory device 100 may include a controller such as a memory controller 110, and may further include a non-volatile (NV) memory 120 (abbreviated as “NV memory”), wherein the memory controller 110 is used to access the NV memory 120, and the NV memory 120 is used to store information. The NV memory 120 may include at least one NV memory element (e.g., one or more NV memory elements), such as a plurality of non-volatile (NV) memory elements 122-1, 122-2, ..., and 122-N. E (abbreviated as “NV memory element”), where “NV E " may represent a positive integer greater than 1. For example, the NV memory 120 may be a flash memory, and the plurality of NV memory elements 122-1, 122-2, ..., and 122-N may be E It may be a plurality of flash memory chips or a plurality of flash memory bare dies, but the present invention is not limited thereto.

[0086] like Figure 1As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a read-only memory (ROM) 112M, a control logic circuit 114, a random access memory (RAM) 116 (which can be implemented by a static random access memory (SRAM) for example) and a transmission interface circuit 118, wherein at least a portion (for example, a portion or all) of the above components can be coupled to each other through a bus. The random access memory 116 can be used to provide internal storage space to the memory controller 110 (for example, temporarily storing information), but the present invention is not limited to this. In addition, the read-only memory 112M of this embodiment is used to store program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access of the NV memory 120. Please note that the program code 112C can also be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 can be used to control the NV memory 120. The transmission interface circuit 118 may comply with one or more communication specifications among different communication specifications (e.g., Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, embedded multimedia card specification, or universal flash storage specification), and may enable the memory device 100 to communicate with the host device 50 (or its transmission interface circuit 58) according to the one or more communication specifications. Similarly, the transmission interface circuit 58 may comply with the one or more communication specifications, and may enable the host device 50 to communicate with the memory device 100 (or its transmission interface circuit 118) according to the one or more communication specifications.

[0087] In the present embodiment, the host device 50 can indirectly access the NV memory 120 in the memory device 100 by transmitting a plurality of host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives the plurality of host commands and corresponding logical addresses, and converts the plurality of host commands into a plurality of memory operation commands (which may be referred to as operation commands), and then uses the plurality of operation commands to control the NV memory 120 to read or write / program the memory cells or data pages of the corresponding physical addresses in the NV memory 120, etc., wherein the physical addresses may be associated with the logical addresses. For example, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical addresses and the logical addresses, wherein the NV memory 120 may store a global logical-to-physical address mapping table 120AM for the memory controller 110 to control the memory device 100 to access the data in the NV memory 120, but the present invention is not limited thereto.

[0088] For better understanding, the global logical to physical address mapping table 120AM may be located in a predetermined area (e.g., a system area) within the NV memory 122-1 element, but the present invention is not limited thereto. For example, the global logical to physical address mapping table 120AM may be divided into a plurality of local logical to physical address mapping tables, and the plurality of local logical to physical address mapping tables may be stored in the NV memory elements 122-1, 122-2, and 122-N. E In the one or more NV memory elements, in particular, the NV memory elements 122-1, 122-2 and 122-N may be stored respectively. E When necessary, the memory controller 110 may load at least a portion (e.g., a portion or all) of the global logical-to-physical address mapping table 120AM into the random access memory 116 or other memory. For example, the memory controller 110 may load a local logical-to-physical address mapping table among the multiple local logical-to-physical address mapping tables into the random access memory 116 as a temporary logical-to-physical address mapping table 116AM, so as to access data in the NV memory 120 according to the local logical-to-physical address mapping table stored as the temporary logical-to-physical address mapping table 116AM, but the present invention is not limited thereto.

[0089] In addition, the at least one NV memory element (eg, the one or more NV memory elements, such as {122-1, 122-2, ..., 122-N E}) may include a plurality of blocks {BLK}, wherein the minimum unit for the memory controller 110 to perform a data erase operation on the NV memory 120 is a block, and the minimum unit for the memory controller 110 to perform a data write operation on the NV memory 120 is a page, but the present invention is not limited thereto. For example, the NV memory elements 122-1, 122-2, ... and 122-N E Any NV memory element 122-n E (Symbol “n E " can represent the interval [1,N E ] may include multiple blocks, and a block within the multiple blocks may include and record a specific number of pages, wherein the memory controller 110 may access a page of a block within the multiple blocks according to a block address and a page address.

[0090] According to some embodiments, the control logic circuit 114 may include a randomization circuit and an error correction code (ECC) circuit (not shown). Figure 1 ), wherein the randomization circuit may perform a randomization operation on write data (e.g., data to be written to the NV memory 120 during a write / programming operation of the NV memory 120 in response to a write command from the host device 50) and de-randomize read data (e.g., data read from the NV memory 120 during a read operation of the NV memory 120 in response to a read command from the host device 50), and the ECC circuit may perform ECC encoding on the write data and ECC decoding on the read data to protect the data and / or perform error correction, but the present invention is not limited thereto. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E This may be implemented by using a degraded flash memory die. In this case, the error correction code decoding may not be successful, and in particular, uncorrectable ECC (UECC) errors may easily occur. The memory controller 110 may have a more robust reading mechanism to avoid the high error rate that may be caused by using a degraded flash memory die.

[0091] At Figure 1In the illustrated architecture, the control logic circuit 114 may include a plurality of data processing sub-circuits to provide the above-mentioned more robust reading mechanism, and the plurality of data processing sub-circuits may include at least one low-density parity-check (LDPC) code decoding circuit 114D (referred to as "LDPC code decoding circuit") such as one or more LDPC code decoding circuits {114D}, wherein the at least one LDPC code decoding circuit 114D may access the read data buffered in at least one memory region MR to perform relevant decoding operations to obtain correct data for transmission back to the host device 50, but the present invention is not limited thereto. According to some embodiments, Figure 1 The illustrated architecture may be varied. For example, at least a portion (eg, a portion or all) of the plurality of data processing subcircuits, such as the one or more LDPC code decoding circuits {114D}, may be integrated into at least one other circuit (not the control logic circuit 114).

[0092] Figure 2A Schematic diagram of an LDPC code decoding control scheme according to an embodiment of the present invention, wherein an LDPC code decoding circuit 200 can be used as an example of the at least one LDPC code decoding circuit 114D described above, but the present invention is not limited thereto. During a read operation of the NV memory 120 in response to a read command from the host device 50, the memory controller 110 can obtain multiple channel values ​​{CV} from the NV memory 120 through at least one channel CH (e.g., one or more channels {CH}, such as multiple channels {CH(i)}) for the multiple data processing sub-circuits to perform correlation processing to obtain correct data. For example, the memory controller 110 can perform a read optimization procedure to utilize the LDPC code decoding circuit 200 to receive the multiple channel values ​​{CV} from at least one medium such as the NV memory 120 through the channel CH(i) to perform correlation decoding operations to generate correct data.

[0093] based on Figure 2AIn the LDPC code decoding control scheme shown, the multiple data processing sub-circuits in the memory controller 110 may include at least one LDPC code decoding circuit 200 corresponding to the at least one channel CH mentioned above, and in particular, may include multiple LDPC code decoding circuits {200} corresponding to the multiple channels {CH(i)} respectively. For example, the LDPC code decoding circuit 200 corresponding to the channel CH(i) among the plurality of LDPC code decoding circuits {200} may include a volatile memory such as a channel value (CV) memory 205 and a column-segment processing sub-circuit, and the column-segment processing sub-circuit may include a variable node unit (VNU) 210, a plurality of barrel shifter (BS) circuits 221 and 222, and a check node unit (CNU) 230 (respectively labeled “CV memory”, “VNU”, “BS circuit” and “CNU” for simplicity), wherein, assuming that “F” may represent a positive integer greater than one, the barrel shifter circuit 221 may include a set of barrel shifters {221_1, 221_2, …, 221_F} (represented by “BS_ V2C ” for simplicity), and the barrel shifter circuit 222 may include a set of barrel shifters {222_1, 222_2, . . . , 222_F} (labeled “BS_ C2V " for simplicity).

[0094] For better understanding, the channel value memory 205 can be implemented by the at least one memory region MR (e.g., one or more memory regions {MR}) mentioned above. In particular, the channel value memory 205 can be implemented as a memory region MR corresponding to the channel CH(i) among the multiple memory regions {MR} corresponding to the multiple channels {CH(i)} in the random access memory 116, but the present invention is not limited thereto. According to some embodiments, the channel value memory 205 can be implemented by a dedicated memory (e.g., other random access memory).

[0095] Figure 2B According to an embodiment of the present invention, Figure 2AThe LDPC code decoding control scheme shown in FIG. 1 is a barrel shifter 220, wherein the barrel shifter 220 can be used as an example of any barrel shifter in the group of barrel shifters {221_1, 221_2, ..., 221_F}, and can also be used as an example of any barrel shifter in the group of barrel shifters {222_1, 222_2, ..., 222_F}. Assuming that "Z" can represent a positive integer greater than one, the barrel shifter 220 can be based on a shift number CNT SHIFT Perform CNT on an input signal x with Z bits SHIFT A shift operation is performed to generate an output signal y having Z bits, but the present invention is not limited thereto. For example, the shift number CNT SHIFT It can be an integer greater than or equal to zero. SHIFT =0, the barrel shifter 220 may directly output the Z bits of the input signal x as the Z bits of the output signal y, so that the output signal y is equal to the input signal x. In addition, the Z bits of the input signal x may include input bits x0, x1, ... and x Z-1 , and the Z bits of the output signal y may include output bits y0, y1, ... and y Z-1 .

[0096] Figure 2C According to an embodiment of the present invention, Figure 2B 2 shows some implementation details of the barrel shifter 220. The barrel shifter 220 may include a decoder 220D and a shift circuit 220S. The decoder 220D may be configured to receive the bit positions of the barrel shifter 220 according to the shift number CNT. SHIFT A plurality of shift control signals are generated to control a plurality of shift sub-circuits in the shift circuit 220S to perform corresponding shift operations, and the shift circuit 220S (or the plurality of shift sub-circuits therein) may shift the input bits x0, x1, ... and x1 according to the plurality of shift control signals. Z-1 The corresponding shift operations are performed to generate output bits y0, y1, ... and y Z-1 , but the present invention is not limited thereto. According to some embodiments, Figure 2C The architecture and / or related operations shown may be varied.

[0097] Figure 3 According to an embodiment of the present invention, Figure 2AThe LDPC code decoding control scheme shown involves a codeword, wherein the codeword may include a set of channel values ​​{CV} among the plurality of channel values ​​{CV} mentioned above. For example, assuming that "G" can represent a positive integer greater than one and the total number of bits of the codeword can be equal to N, the entire N bits of this set of channel values ​​{CV} can be divided into G data chunks CK(0), CK(1), ... and CK(G-1) (each of which can have a length equal to Z bits, if G = (N / Z)) for LDPC code decoding, wherein when any one of the multiple LDPC code decoding operations of the LDPC code decoding is implemented by multiple predetermined operations (for example, a horizontal decoding operation and a vertical decoding operation) of a Min-Sum-Algorithm-based column-layered decoding method, the G data chunks CK(0), CK(1), ... CK(G-1) can be used as G column segments, and therefore can also be referred to as G column segments CK(0), CK(1), ... CK(G-1), but the present invention is not limited to this. In addition, the codeword may be configured as w bits per channel value and (Z / w) channel values ​​per column segment (labeled as “w bits per CV; (Z / w) CV per CK” for simplicity). Any channel value CV in the set of channel values ​​{CV} of the codeword may have w bits, and any row segment CK(g) (e.g., “g” may represent any integer in the interval [0, (G-1)]) in the G row segments CK(0), CK(1), …CK(G-1) may have (Z / w) channel values ​​{CV}. For example, when w=4 and Z=400, the codeword may be configured as 4 bits per channel value and 100 channel values ​​per column segment (labeled as “4 bits per CV; 100 CV per CK” for simplicity).

[0098] Figure 4A According to an embodiment of the present invention, Figure 2A The LDPC code decoding control scheme shown in FIG. 1 includes a plurality of sign bits Sign_bit(0), Sign_bit(1), and Sign_bit(2). A group of memory cells 120C in the NV memory 120 may be configured as J-order cells, and any memory cell in the group of memory cells 120C may be in a plurality of candidate programming states {P} such as 2 J programming states {P1,…,P2 J}. For example, when J=3, the group of memory cells 120C can be configured as three-level cells, and any memory cell in the group of memory cells 120C can be in a programming state P selected from the plurality of candidate programming states {P}, such as 8 programming states {P1, ..., P8}, where Figure 4A The horizontal axis shown in the lower half of may represent a threshold voltage Vth, and according to some viewpoints, the threshold voltage Vth may be referred to as a read voltage, but the present invention is not limited thereto. According to some embodiments, Figure 4A The plurality of candidate programming states {P1, ..., P8} and / or the level count J of the group of memory cells 120C shown may be varied. For example, the level count J may be equal to any value in a series of values ​​{1, 2, 3, 4, ...}.

[0099] like Figure 4A As shown in the upper half of FIG. 1 , the memory controller 110 may refer to a predetermined encoding rule to encode the 2 J programming states {P1,…,P2 J} Such as the 8 programming states {P1, ..., P8} associated with 2 J The predetermined codes are such as the 8 predetermined codes {111,011,001,101,100,000,010,110}, where the 2 J Any of the predetermined codes may include J sign bits {Sign_bit(j)|j=0, ..., (J-1)} such as 3 sign bits Sign_bit(0), Sign_bit(1) and Sign_bit(2), but the present invention is not limited thereto. According to some embodiments, the predetermined encoding rule, the 2 J A reservation code such as Figure 4A The 8 predetermined codes {111, 011, 001, 101, 100, 000, 010, 110} shown and / or the order J may be varied.

[0100] Figure 4B According to an embodiment of the present invention, Figure 2A The LDPC code decoding control scheme shown in FIG. 1 involves a sign bit Sign_bit(j) and (w-1) soft bits Soft_bit(j,k)|k=1,…,(w-1)}. For example, the w bits of any channel value CV may include bits {Bit0, Bit1, Bit2,…, Bit w-1During the read optimization process, the memory controller 110 may perform a first read operation to obtain the sign bit Sign_bit(j) as bit Bit0, and perform a read retry process to perform multiple read retry operations to obtain the (w-1) soft bits {Soft_bit(j,k)|k=1,…,(w-1)} as bits Bit1, Bit2,… and Bit w-1 , wherein the (w-1) soft bits {Soft_bit(j,k)|k=1,…,(w-1)} can indicate how strong or weak the sign bit Sign_bit(j) is as bit 1 (if Sign_bit(j)=1), or indicate how strong or weak the sign bit Sign_bit(j) is as bit 0 (if Sign_bit(j)=0), and according to some viewpoints, these soft bits {Soft_bit(j,k)|k=1,…,(w-1)} can be used to accurately indicate the position of the programming state P associated with the sign bit Sign_bit(j) on the Vth axis to improve the accuracy of detecting the position of the programming state P on the Vth axis, but the present invention is not limited thereto. For example, when k=1, the memory controller 110 may perform the first read retry operation to obtain the first soft bit Soft_bit(j,1); when k=2, the memory controller 110 may perform the first read retry operation to obtain the first soft bit Soft_bit(j,2); when k=3, the memory controller 110 may perform the third read retry operation to obtain the third soft bit Soft_bit(j,3); when k=4, the memory controller 110 may perform the fourth read retry operation to obtain the fourth soft bit Soft_bit(j,4); and the rest may be deduced accordingly.

[0101] For better understanding, arrows corresponding to k=1, k=2, k=3, k=4, etc. can be drawn on Figure 4B The operations for detecting the position of the programming state P on the Vth axis are indicated, but the present invention is not limited thereto. According to some embodiments, these operations, the related detection directions on the Vth axis (e.g., positive direction or negative direction), and / or the related detection positions on the Vth axis may be changed.

[0102] Figure 5A According to an embodiment of the present invention, Figure 2A The LDPC code decoding control scheme shown in FIG. 1 involves a parity check matrix H, wherein a basic matrix B is also shown in FIG. Figure 5A For better understanding. The parity check matrix H may include a plurality of sub-matrices having the same size, and the plurality of sub-matrices may be implemented as a plurality of base matrices {B} such as the base matrix {{B 0,0 ,B 0,1,…,B 0,G-2 ,B 0,G-1},{B 1,0 ,B 1,1 ,…,B 1,G-2 ,B 1,G-1},…,{B F-1,0 ,B F-1,1 ,…,B F-1,G-2 ,B F-1,G-1 For example, when M=(F*Z) and N=(G*Z), the parity check matrix H may have a size of (M*N) (or have (M*N) elements), and any one of the multiple base matrices {B}, such as the base matrix B, may have a size of (Z*Z) (or have (Z*Z) elements).

[0103] Figure 5B According to an embodiment of the present invention, Figure 5A The base matrix B can be an identity matrix with a size Z. Z (e.g., a matrix whose elements on the main diagonal are all 1 and the rest are all 0), the identity matrix I Z An X-cyclically-shifted matrix (for example, the identity matrix I Z For example, for case (a), if the base matrix B is equal to the identity matrix I Z , then in the parity check matrix H, the base matrix B can be labeled as "0", where no cyclic shift operation is required (labeled "X=0" for ease of understanding); for case (b), if the base matrix B is equal to the X-cyclic shifted matrix, then in the parity check matrix H, the base matrix B can be labeled as "X"; and for case (c), if the base matrix B is equal to the zero matrix, then in the parity check matrix H, the base matrix B can be labeled as "-1".

[0104] Figure 5C According to an embodiment of the present invention, Figure 5A The multiple basic matrices {{B 0,0 ,B 0,1 ,B 0,2 ,B 0,3 ,B 0,4 ,B 0,5 ,B 0,6},{B 1,0 ,B 1,1 ,B 1,2 ,B 1,3 ,B 1,4,B 1,5 ,B 1,6},{B 2,0 ,B 2,1 ,B 2,2 ,B 2,3 ,B 2,4 ,B 2,5 ,B 2,6},{B 3,0 ,B 3,1 ,B 3,2 ,B 3,3 ,B 3,4 ,B 3,5 ,B 3,6}}, wherein F=4 and G=7, but the present invention is not limited thereto. For the sake of brevity, similar contents in this embodiment are not repeated here.

[0105] Figure 5D According to an embodiment of the present invention, Figure 5C The multiple basic matrices {{B 0,0 ,B 0,1 ,B 0,2 ,B 0,3 ,B 0,4 ,B 0,5 ,B 0,6},{B 1,0 ,B 1,1 ,B 1,2 ,B 1,3 ,B 1,4 ,B 1,5 ,B 1,6},{B 2,0 ,B 2,1 ,B 2,2 ,B 2,3 ,B 2,4 ,B 2,5 ,B 2,6},{B 3,0 ,B 3,1 ,B 3,2 ,B 3,3 ,B 3,4 ,B 3,5 ,B 3,6}} is a case where a portion of the basic matrices are zero matrices (marked with "-1" for simplicity), but the present invention is not limited to this. For the sake of simplicity, similar contents in this embodiment are not repeated here.

[0106] Some implementation details of the row-level decoding method based on the minimum sum algorithm are further described as follows. According to some embodiments, let C be a binary (N, K) LDPC code specified by a parity check matrix H. In the parity check matrix H, any of the multiple rows can be associated with a check node c, and any of the multiple rows can be associated with a variable node v. Let N(c) = {v:H cv = 1} represents the set of all variable nodes {v} participating in (or connected to) the check node c through the parity check matrix H, and let M(v) = {c:H cv =1} represents the set of all check nodes {c} associated with (or connected to) the variable node v through the parity check matrix H. Let I v represents the intrinsic message for the variable node v and R cv represents a check-to-variable message conveyed from check node c to variable node v, and L cv represents a variable-to-check message transmitted from a variable node v to a check node c. Assume that the N bits of the codeword are divided into G groups of the same size {N0, N1, ..., N G-1}(For example: Figure 3 The G row segments CK(0), CK(1), ... and CK(G-1) are shown. Thus, the parity check matrix H can be divided into G block columns. For better understanding, taking at least one set of pseudo codes as an example, the minimum sum-based row layered decoding method can include the following operations:

[0107]

[0108]

[0109] The two layers of "For{}" in "iterative decoding" may represent a For-loop, "Iter" may represent an iteration index, "Iter_maximum" may represent a predetermined maximum value of the iteration index Iter, "sgn()" may represent a positive or negative sign, and "α" may represent a scaling factor, but the present invention is not limited thereto. According to some embodiments, the above operations, the related parameters of these operations, and / or the above equations Eq(1), Eq(2) and Eq(3) may be changed.

[0110] Fig. 6AAccording to an embodiment of the present invention, Figure 2A The message bits and parity bits in the codeword involved in the LDPC code decoding control scheme shown. For example, the codeword can be completely transmitted from the at least one medium such as the NV memory 120, so these message bits and these parity bits can be regarded as transmitted bits, but the present invention is not limited to this. According to some embodiments, it may be unnecessary for all bits in the codeword to be completely transmitted from the at least one medium such as the NV memory 120, and some of the operations in the above-listed operations of the minimum sum-based row layered decoding method can be modified to efficiently obtain error-free data.

[0111] Figure 6B According to an embodiment of the present invention, Fig. 6A The case where a portion of the multiple parity bits shown becomes puncture bits. For example, a portion of the bits in the codeword, such as a portion of the parity bits of all the message bits, can be completely transmitted from the above-mentioned at least one medium such as the NV memory 120, so these message bits and the portion of the parity bits can be regarded as transmitted bits. In addition, due to one or more reasons (for example: at least one unexpected factor, at least one expected factor, and / or at least one predetermined transmission rule), another portion of the bits in the codeword, such as these puncture bits, are not transmitted from the above-mentioned at least one medium such as the NV memory 120. In this case, it is assumed that all of the above operations of the minimum sum-based row layered decoding method are performed, which seems to be very inefficient for certain time-limited scenarios. For example, the N bits of the codeword can be divided into the G groups {N0, N1, …, N G-1} such as the G row segments CK(0), CK(1), ... and CK(G-1), and the parity check matrix H can be divided into the G block rows, such as Figure 5A The basic matrix {B 0,0 ,B 1,0 ,…,B F-1,0}, the 0th block row, the basic matrix {B 0,1 ,B 1,1 ,…,B F-1,1}, ... and the basic matrix {B 0,G-1 ,B 1,G -1,…,B F-1,G-1} composed of the (G-1)th block row (for example: Figure 5C The basic matrix {B 0,0 ,B 1,0 ,B 2,0 ,B 3,0}, the 0th block row, the basic matrix {B 0,1 ,B 1,1 ,B2,1 ,B 3,1}, ... and the basic matrix {B 0,6 ,B 1,6 ,B 2,6 ,B 3,6}, if F=4 and G=7), where as shown in the second layer For-loop corresponding to the loop index g (e.g., g=0,1,…,(G-1)), the minimum sum-based row layered decoding method may include for the G groups {N0,N1,…,N G-1} Such as the G row segments CK(0), CK(1), ... and CK(G-1) (or the G block rows) to perform the related LDPC code decoding operation. According to some embodiments, part of the above operations of the minimum sum-based row layered decoding method can be modified, in particular, it can be changed to selectively target one or more groups {N g} (e.g., one or more row segments {CK(g)}) to perform the corresponding LDPC code decoding operation, rather than for the G groups {N0, N1, ..., N G-1 All groups in {N g} (for example, all row segments {CK(g)} among the G row segments CK(0), CK(1), ... and CK(G-1)) perform all LDPC code decoding operations to efficiently obtain error-free data.

[0112] Figure 7 Schematic diagram of a rearranged decoding control scheme for a method for data access control for a host device (e.g., host device 50) according to an embodiment of the present invention, wherein an LDPC code decoding circuit 700 can be used as an example of the at least one LDPC code decoding circuit 114D, but the present invention is not limited thereto. For better understanding, the at least one iteration can include a single iteration, such as the second iteration corresponding to Iter=2, to achieve the best overall performance, but the present invention is not limited thereto. For example, the single iteration can be another iteration corresponding to Iter>2. In some examples, the at least one iteration can include multiple iterations.

[0113] based on Figure 7In the rearranged decoding control scheme shown, the plurality of data processing subcircuits in the memory controller 110 may include at least one LDPC code decoding circuit 700 corresponding to the at least one channel CH, and in particular, may include a plurality of LDPC code decoding circuits {700} corresponding to the plurality of channels {CH(i)}, respectively. For example, the LDPC code decoding circuit 700 corresponding to the channel CH(i) among the plurality of LDPC code decoding circuits {700} may include the volatile memory such as the channel value memory 205, and may include a plurality of row segment processing subcircuits such as a normal row segment processing subcircuit 710, an abnormal row segment processing subcircuit 720, and a row segment s processing subcircuit 730, wherein any one of the plurality of row segment processing subcircuits may be used Figure 2A The row segment processing subcircuit in the illustrated architecture (which includes a variable node unit 210, barrel shifter circuits 221 and 222, and a check node unit 230) is implemented.

[0114] Compared to Figure 2A In the LDPC code decoding circuit 200 shown, the LDPC code decoding circuit 700 can use the normal line segment processing subcircuit 710 and the abnormal line segment processing subcircuit 720 to perform LDPC code decoding operations on normal line segments and abnormal line segments in the first iteration corresponding to Iter=1, and use the line segment s processing subcircuit 730 to selectively perform corresponding LDPC code decoding operations on one or more line segments {CK(g)} in the codeword in the second iteration corresponding to Iter=2, rather than performing all LDPC code decoding operations on all line segments {CK(g)} in the codeword. In addition, the LDPC code decoding circuit 700 can use the normal line segment processing subcircuit 710 and the abnormal line segment processing subcircuit 720 to perform LDPC code decoding operations on normal line segments and abnormal line segments in at least one subsequent iteration corresponding to Iter>2. Since the LDPC code decoding circuit 700 can perform decoding processing on the one or more row segments {CK(g)} with a higher priority in the at least one iteration, such as the second iteration corresponding to Iter=2, the relevant decoding parameters can converge rapidly to improve the overall decoding speed.

[0115] Fig. 8A According to an embodiment of the present invention, Figure 7 The LDPC code decoding circuit 700 can be based on the rearranged decoding control scheme. Fig. 8AThe process of the present invention is operated according to the workflow shown in the figure, in particular, steps S11 and S12, step S21 and steps S31 to S33 are executed in multiple decoding stages such as phases Phase (1), Phase (2) and Phase (3), respectively, wherein phase Phase (1) may correspond to Iter=1, phase Phase (2) may correspond to Iter=2, and phase Phase (3) may correspond to Iter>2, but the present invention is not limited to this.

[0116] In step S11, the LDPC code decoding circuit 700 may utilize the normal row segment processing subcircuit 710 to process the normal variable node {v} (eg, non-puncture variable node {v}, such as corresponding to Figure 6B The normal row segments of the variable nodes {v}) of the message bits and the parity bits are shown, and in particular, the LDPC code decoding operation is performed on the normal row segments in the first iteration corresponding to Iter=1. For example, the v axis can be plotted at Figure 6B In the direction along which the N bits of the codeword are arranged, the normal variable node {v} among all the variable nodes {v} is indicated.

[0117] In step S12, the LDPC code decoding circuit 700 may utilize the abnormal row segment processing subcircuit 720 to process the node {v} containing (or corresponding to) any puncturing variable node {v} (e.g., corresponding to Figure 6B The abnormal row segments of the variable nodes {v}) of the punctured bits are shown, and in particular, the LDPC code decoding operation is performed on the abnormal row segments in the first iteration corresponding to Iter=1. For example, the v axis can be plotted at Figure 6B In the direction along which the N bits of the codeword are arranged, the punctured variable node {v} among all the variable nodes {v} is indicated.

[0118] In step S21, the LDPC code decoding circuit 700 may utilize the row segment s processing subcircuit 730 to find at least one row segment s satisfying at least one predetermined selection condition to process the at least one row segment s, and in particular, selectively perform corresponding LDPC code decoding operations on the at least one row segment s, such as the one or more row segments CK(g)}, in the second iteration corresponding to Iter=2, instead of performing all LDPC code decoding operations on all row segments {CK(g)} in the codeword.

[0119] In step S31, the LDPC code decoding circuit 700 may utilize the normal row segment processing sub-circuit 710 to process the normal variable node {v} (eg, corresponding to Figure 6BThe normal row segments of the variable nodes {v}) of the message bits and the parity bits shown are shown, and in particular, the LDPC code decoding operation is performed on the normal row segments in the Iter-th iteration corresponding to Iter>2.

[0120] In step S32, the LDPC code decoding circuit 700 may utilize the abnormal row segment processing subcircuit 720 to process the node {v} containing (or corresponding to) any of the above-mentioned puncturing variable nodes (e.g., corresponding to Figure 6B The abnormal row segments of the variable nodes {v}) of the punctured bits shown, in particular, perform LDPC code decoding operations on the abnormal row segments in the Iter-th iteration corresponding to Iter>2.

[0121] In step S33, the LDPC code decoding circuit 700 may determine whether to continue the next iteration. If yes, proceed to step S31; if no, Fig. 8A The illustrated workflow ends. For example, the LDPC code decoding circuit 700 may be based on L v The above hard decision is made based on the sign of to determine whether any valid codeword is found. When no valid codeword has been found, the LDPC code decoding circuit 700 may continue to the next iteration until a valid codeword is found or Iter=Iter_maximum.

[0122] For a better understanding, the method can be used Fig. 8A According to some embodiments, one or more steps may be performed in Fig. 8A Add, delete or modify the workflow shown.

[0123] Figure 8B According to an embodiment of the present invention, Fig. 8A Some implementation details of this workflow are shown. Fig. 8A The step S21 shown may include multiple sub-steps such as Figure 8B In the steps S211 to S213, S213A and S214 shown in the figure, the present invention is not limited thereto. In addition, in the second iteration corresponding to Iter=2, the set of line segments to be processed when the step S211 is executed for the first time is All row segments {CK(g)} in the codeword may be included (eg, the G row segments CK(0), CK(1), ... and CK(G-1)).

[0124] In step S211, the LDPC code decoding circuit 700 may utilize the line segment processing subcircuit 730 to process the line segment set to be processed. Find a row segment s (e.g., a row segment CK(g)) that satisfies the above-mentioned at least one predetermined selection condition, wherein the above-mentioned at least one predetermined selection condition includes: for the variable node v belonging to the set N(c) and the variable node v belonging to the row segment s, among all the variable nodes {v} except the variable node v itself, the number of variable nodes {v} with a trust value of 0 is the least. For example, the above-mentioned at least one predetermined selection condition can be expressed by the following equation:

[0125]

[0126] However, the present invention is not limited thereto. According to some embodiments, the above equation Eq (4) may be changed.

[0127] In step S212, the LDPC code decoding circuit 700 may utilize the line segment s processing subcircuit 730 to process the line segment s (e.g., the line segment CK(g)) just found, and in particular, perform a corresponding LDPC code decoding operation on the line segment s. For example, the corresponding LDPC code decoding operation may include the horizontal decoding operation (or the horizontal step) and the vertical decoding operation (or the vertical step).

[0128] In step S213, the LDPC code decoding circuit 700 may utilize the line segment s processing subcircuit 730 to remove the line segment s from the set of line segments to be processed. Remove to update the pending row segment collection .

[0129] In step S213A, the LDPC code decoding circuit 700 may utilize the line segment s processing subcircuit 730 to check whether the updated line segment set to be processed is If it is an empty set, go to step S31; if not, go to step S214.

[0130] In step S214, the LDPC code decoding circuit 700 can use the row segment s processing subcircuit 730 to check whether all the confidence values ​​are not 0. If yes, go to step S31; if not, go to step S211. For example, the checking operation of step S214 can be represented by the following equation:

[0131]

[0132] Wherein "|Lcn|" may represent the trust value corresponding to the check node c and the variable n∈N(c)\v (for example, the variable n belongs to all variable nodes {v} in the set N(c) except the variable node v itself), but the present invention is not limited thereto. According to some embodiments, the above equation Eq(5) may be varied.

[0133] For a better understanding, the details of the method can be found in Figure 8BAccording to some embodiments, one or more steps may be performed in Figure 8B For example, step S213A may be added, deleted or modified in the workflow shown in FIG. Figure 8B In the workflow shown in FIG. 2 , the relevant local processes can be modified accordingly. In particular, step S214 can be directly entered after executing step S213. Typically, in the case where there is an abnormal row segment corresponding to the puncture variable node, the judgment result of step S214 "yes" can be obtained after executing steps S211 and S212 a small number of times, or even after the first execution of steps S211 and S212. Therefore, deleting step S213A can further improve the overall performance. For the sake of simplicity, similar contents in these embodiments are not repeated here.

[0134] According to some embodiments, in the second iteration corresponding to Iter=2, the second layer For-loop corresponding to the loop index g (e.g., g=0, 1, ..., (G-1)) may be changed to first select a row segment CK(g) satisfying the at least one predetermined selection condition as the row segment s satisfying the at least one predetermined selection condition (as described in step S211), so as to perform the horizontal decoding operation (or the horizontal step) and the vertical decoding operation (or the vertical step) on the selected row segment CK(g) (or the row segment s just found), wherein similar operations may be performed until the condition defined in equation Eq(5) is satisfied. For the sake of brevity, similar contents in these embodiments are not repeated here.

[0135] Fig. 9 According to an embodiment of the present invention, the relationship between the elements in the parity check matrix H and certain rows to be processed (e.g., rows a and b) in the method is illustrated. For example, assuming that "f" can represent any integer in the interval [0, (F-1)], when Z=3, among the multiple basic matrices {B} in the parity check matrix H, the basic matrix B located in the a-th block row f,a The basic matrix B located in the next block row, for example, the b-th block row, may correspond to the row segment a. f,b can correspond to each other with row segment b. In addition, the basic matrix B f,a and B f,b Each basic matrix in can be the identity matrix I Z (For example, the identity matrix I3, when Z=3), and the set of unprocessed row segments described in step S211 It may include row segments a and b. Assuming that the number of non-punctured bits of the codeword may be equal to ((a*Z)+2) (e.g.: ((3*a)+2), when Z=3), in the basic matrix B f,aThe first two elements on the main diagonal of can be the elements in the parity check matrix H corresponding to the normal variable nodes and equal to 1, and the basic matrix B f,a The third element on the main diagonal of and in the basic matrix B f,b The three elements on the main diagonal of can be the elements in the parity check matrix H corresponding to the puncture variable nodes and equal to 1, wherein the row segment b satisfies the above-mentioned at least one predetermined selection condition, and the row segment a does not satisfy the above-mentioned at least one predetermined selection condition, but the present invention is not limited thereto. According to some embodiments, the parity check matrix H, the row segments to be processed such as the row segments a and b, and / or the size of each row segment can be changed. For the sake of simplicity, similar contents in this embodiment are not repeated here.

[0136] According to some embodiments, the method may be applied to any of various data access devices, and in particular, may be applied to a controller in any of the above data access devices. For example, the above at least one medium may include a storage medium such as the NV memory 120, any of the above data access devices may represent the memory device 100, and the controller may represent the memory controller 110, but the present invention is not limited thereto. In some examples, the above at least one medium may include a transmission medium, and any of the above data access devices may include one or a combination of an optical fiber transceiver, a wired network transceiver, and a wireless network transceiver.

[0137] Fig.10 According to an embodiment of the present invention, a schematic diagram of an electronic device 11 involved in the method is shown, wherein the electronic device 11 may include a data access device 1000, which may be used as an example of any of the above-mentioned data access devices. Figure 1 In the illustrated structure, the transmission medium controller 1010 and its transmission medium interface circuit 1014 in the data access device 1000 replace the memory controller 110 and its control logic circuit 114, and the transmission medium interface circuit 1014 can be used to control the data access operation of the data access device 1000 on the transmission medium, such as data transmission operation and data receiving operation, wherein the transmission medium interface circuit 1014 can include the at least one LDPC code decoding circuit 114D mentioned above. For the sake of simplicity, similar contents in this embodiment are not repeated here.

[0138] Fig.11A According to another embodiment of the present invention, a schematic diagram of an electronic device 11_1 involved in the method is shown, wherein the electronic device 11_1 may include an optical fiber transceiver 1000_1, which may be used as an example of any of the above-mentioned data access devices, or may be used as Fig.10The example of the data access device 1000 shown in FIG. 1 is a diagram of a transmission medium that may include an optical-fiber cable, wherein the optical-fiber cable includes at least one optical fiber. A transmission medium controller 1010_1 of the optical fiber transceiver device 1000_1 may include a transmission medium interface circuit 1014_1, and the transmission medium interface circuit 1014_1 may be used to control the data access operation of the optical fiber transceiver device 1000_1 on the optical fiber cable, such as data transmission operation and data reception operation, wherein the transmission medium interface circuit 1014_1 may include the above-mentioned at least one LDPC code decoding circuit 114D. For the sake of simplicity, similar contents in this embodiment are not repeated here.

[0139] Fig. 11B According to another embodiment of the present invention, a schematic diagram of an electronic device 11_2 involved in the method is shown, wherein the electronic device 11_2 may include a wired network transceiver 1000_2, which may be used as an example of any of the above-mentioned data access devices, or may be used as a wireless network transceiver 1000_2. Fig.10 The example of the data access device 1000 shown in FIG. 1 is a diagram of a transmission medium. The transmission medium may include a network cable. A transmission medium controller 1010_2 of the wired network transceiver 1000_2 may include a transmission medium interface circuit 1014_2, and the transmission medium interface circuit 1014_2 may be used to control the data access operation of the wired network transceiver 1000_2 to the network cable, such as data transmission operation and data reception operation, wherein the transmission medium interface circuit 1014_2 may include the at least one LDPC code decoding circuit 114D mentioned above. For the sake of simplicity, similar contents in this embodiment are not repeated here.

[0140] Fig. 11C According to another embodiment of the present invention, a schematic diagram of an electronic device 11_3 involved in the method is shown, wherein the electronic device 11_3 may include a wireless network transceiver device 1000_3, which may be used as an example of any of the above-mentioned data access devices, or may be used as Fig.10 An example of a data access device 1000 is shown. The transmission medium may include an air medium for transmitting radio waves. A transmission medium controller 1010_3 of the wireless network transceiver device 1000_3 may include a transmission medium interface circuit 1014_3, and the transmission medium interface circuit 1014_3 may be used to control the data access operation of the wireless network transceiver device 1000_3 on the air medium, such as data transmission operation and data reception operation, wherein the transmission medium interface circuit 1014_3 may include the at least one LDPC code decoding circuit 114D mentioned above.

[0141] For the sake of brevity, similar contents in this embodiment are not repeated here.

[0142] Fig.12 According to one embodiment of the present invention, a workflow of a data access optimization procedure (e.g., the read optimization procedure) of the method is described. Any of the above-mentioned data access devices, such as the memory device 100 for accessing the storage medium such as the NV memory 120, and the data access device 1000 for accessing the transmission medium (e.g., data access devices 1000_1, 1000_2, and 1000_3), can receive the plurality of host commands from the host device 50 to access data to the at least one medium according to the plurality of host commands, and according to Fig.12 The data access optimization procedure is performed according to the workflow shown in the figure to maintain the correctness of the data reception, wherein the data access may include data reception. For example, when any of the above data access devices represents the memory device 100, the plurality of host commands may include at least one read command, and the data reception includes data reading, but the present invention is not limited thereto.

[0143] In step S40 , any of the data access devices (eg, memory device 100 or data access device 1000 ) may receive the data from the at least one medium through the at least one channel CH(i) to obtain at least one codeword, wherein the at least one codeword may include a plurality of row segments {CK(g)}.

[0144] In step S41, any of the above-mentioned data access devices (for example, the memory device 100 or the data access device 1000) may perform multiple first LDPC code decoding operations on the multiple row segments {CK(g)} in a first decoding phase (for example, phase Phase(1)), wherein a portion of the row segments {CK(g)} among the multiple row segments {CK(g)} are abnormal row segments corresponding to the puncturing variable nodes.

[0145] In step S42, any of the above-mentioned data access devices (for example, the memory device 100 or the data access device 1000) can search for at least one row segment s (for example, at least one row segment CK(g)) that satisfies the above-mentioned at least one predetermined selection condition in a second decoding phase (for example, phase Phase (2)) to perform at least one second LDPC code decoding operation on the above-mentioned at least one row segment, without performing any LDPC code decoding operation on at least one remaining row segment CK(g) among the multiple row segments {CK(g)}.

[0146] In step S43 , any of the data access devices (eg, memory device 100 or data access device 1000 ) may perform a plurality of third LDPC code decoding operations on the plurality of row segments {CK(g)} in a third decoding phase (eg, phase (3)).

[0147] In step S44, any of the above data access devices (e.g., memory device 100 or data access device 1000) can check whether decoding is completed in the third decoding phase (e.g., phase (3)). If yes, proceed to step S45; if no, proceed to step S43 to continue decoding.

[0148] In step S45 , after decoding is completed, any of the data access devices (eg, the memory device 100 or the data access device 1000 ) may return correct data corresponding to the at least one codeword to the host device 50 .

[0149] Any one of the plurality of first LDPC code decoding operations, the at least one second LDPC code decoding operation, and the plurality of third LDPC code decoding operations can be implemented by the horizontal decoding operation and the vertical decoding operation of the row-layered decoding method based on the minimum sum algorithm. For example, the horizontal decoding operation and the vertical decoding operation belong to a decoding operation for a single row segment CK(g) in an iteration among a plurality of iterations. In addition, the first decoding stage can correspond to a first iteration among a plurality of iterations, the second decoding stage can correspond to a second iteration among the plurality of iterations, and the third decoding stage can correspond to at least a third iteration among the plurality of iterations, in particular, the first iteration is the first iteration among the plurality of iterations (e.g., corresponding to the first iteration with Iter=1), the second iteration is the next iteration of the first iteration (e.g., corresponding to the second iteration with Iter=2), and the at least one third iteration is at least one subsequent iteration of the next iteration (e.g., corresponding to at least one subsequent iteration with Iter>2).

[0150] Any of the above data access devices (eg, memory device 100 or data access device 1000 ) operated according to the method can achieve fast decoding speed and rapid convergence, so that the overall data access performance is greatly improved in the case of abnormal row segments corresponding to punctured variable nodes.

[0151] For a better understanding of the data access optimization process of this method, the Fig.12 According to some embodiments, one or more steps may be performed in Fig.12For example, step S41 may include the operations of steps S11 and S12, step S42 may include the operations of step S21, and in particular, may include the operations of at least a portion of the multiple sub-steps of step S21 (e.g., steps S211, S212, S213, and S214), step S43 may include the operations of steps S31 and S32, and step S44 may include the operations of step S33. For the sake of simplicity, similar contents in these embodiments are not repeated here.

[0152] According to some embodiments, the at least one predetermined selection condition may include: for a variable node v belonging to a predetermined variable node set N(c) and the variable node v belongs to the row segment s, among all variable nodes {v} except the variable node v itself, the number of variable nodes v with a trust value of 0 is the least. In addition, any of the above data access devices (e.g., the memory device 100 or the data access device 1000) may selectively leave the second decoding stage according to whether a predetermined stop condition of the second decoding stage is satisfied. In particular, the predetermined stop condition may include: there is no longer any variable node v with the trust value of 0. For the sake of simplicity, similar contents in these embodiments are not repeated here.

[0153] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for controlling data access for a host device, the method being applied to a controller of a data access device, the method comprising: receiving a plurality of host commands from the host device for performing data access to at least one medium according to the plurality of host commands, wherein the data access includes data reception; and A data access optimization procedure is performed to maintain the accuracy of the data reception, wherein the data access optimization procedure includes: Performing the data receiving on the at least one medium to obtain at least one code word, wherein the at least one code word includes a plurality of column segments; In a first decoding stage, performing a plurality of first low-density parity-check (LDPC) code decoding operations on the plurality of line segments, wherein a portion of the plurality of line segments are abnormal line segments corresponding to puncture variable nodes; In a second decoding stage, searching for at least one row segment satisfying at least one predetermined selection condition, so as to perform at least one second LDPC code decoding operation on the at least one row segment; In a third decoding stage, performing a plurality of third LDPC code decoding operations on the plurality of row segments; and After decoding is completed, error-free data corresponding to the at least one codeword is returned to the host device.

2. The method according to claim 1, characterized in that The at least one medium includes a storage medium; and the data access device represents a memory device, and the controller represents a memory controller, wherein the storage medium includes a non-volatile memory, and the non-volatile memory includes at least one non-volatile memory element.

3. The method according to claim 2, characterized in that The plurality of host commands include at least one read command, and the data receiving includes data reading.

4. The method according to claim 1, characterized in that The at least one medium includes a transmission medium; and the data access device includes one or a combination of an optical fiber transceiver, a wired network transceiver, and a wireless network transceiver.

5. The method according to claim 1, characterized in that Any one of the plurality of first LDCC decoding operations, the at least one second LDCC decoding operation and the plurality of third LDCC decoding operations is implemented by a horizontal decoding operation and a vertical decoding operation of a Min-Sum-Algorithm-based column-layered decoding method.

6. The method according to claim 5, characterized in that The horizontal decoding operation and the vertical decoding operation belong to a decoding operation for a single row segment in one of a plurality of iterations.

7. The method according to claim 1, characterized in that The first decoding stage corresponds to a first iteration of a plurality of iterations, the second decoding stage corresponds to a second iteration of the plurality of iterations, and the third decoding stage corresponds to at least a third iteration of the plurality of iterations.

8. The method according to claim 7, characterized in that The first iteration is a first iteration of the plurality of iterations, the second iteration is a next iteration of the first iteration, and the at least one third iteration is at least a subsequent iteration of the next iteration.

9. The method according to claim 1, characterized in that In the second decoding stage, finding the at least one row segment satisfying the at least one predetermined selection condition to perform the at least one second LDPC code decoding operation on the at least one row segment further comprises: In the second decoding stage, the at least one row segment satisfying the at least one predetermined selection condition is found to perform the at least one second LDCC decoding operation on the at least one row segment, while no LDCC decoding operation is performed on at least one remaining row segment of the plurality of row segments.

10. The method according to claim 1, characterized in that At the beginning of the second decoding stage, a to-be-processed line segment set includes the plurality of line segments; and in the second decoding stage, finding the at least one line segment satisfying the at least one predetermined selection condition to perform the at least one second LDPC code decoding operation on the at least one line segment further comprises: Finding a row segment satisfying the at least one predetermined selection condition in the set of row segments to be processed; performing a second low-density parity-check code decoding operation on the one row segment; Remove the one row segment from the to-be-processed row segment set to update the to-be-processed row segment set; as well as The second decoding stage is selectively exited according to whether a predetermined stop condition of the second decoding stage is satisfied.

11. The method according to claim 10, characterized in that The at least one predetermined selection condition includes: for a variable node belonging to a predetermined variable node set and the variable node belongs to the one row segment, among all variable nodes except the variable node itself, the number of variable nodes with a trust value of 0 is the least.

12. The method according to claim 11, characterized in that The predetermined stopping condition includes: there is no longer any variable node with the confidence value of 0.

13. A controller of a data access device, the data access device being used to perform data access control for a host device, the controller comprising: a processing circuit for controlling the controller according to a plurality of host commands from the host device to allow the host device to access at least one medium through the controller; a transmission interface circuit for communicating with the host device; and A low-density parity-check (LDPC) code decoding circuit for decoding low-density parity-check codes; in: The controller receives the plurality of host commands from the host device through the transmission interface circuit in the controller, so as to perform data access to the at least one medium according to the plurality of host commands, wherein the data access includes data reception; and The controller performs a data access optimization procedure to maintain the accuracy of the data reception, wherein the data access optimization procedure includes: Performing the data receiving on the at least one medium to obtain at least one code word, wherein the at least one code word includes a plurality of column segments; Using the low-density parity-check code decoding circuit to perform a plurality of first low-density parity-check code decoding operations on the plurality of line segments in a first decoding stage, wherein a portion of the plurality of line segments are abnormal line segments corresponding to puncture variable nodes; Using the LDPC decoding circuit to find at least one row segment satisfying at least one predetermined selection condition in a second decoding phase, so as to perform at least one second LDPC decoding operation on the at least one row segment; Using the LDPC decoding circuit to perform a plurality of third LDPC decoding operations on the plurality of row segments in a third decoding phase; as well as After decoding is completed, error-free data corresponding to the at least one codeword is returned to the host device.

14. The controller according to claim 13, characterized in that The at least one medium includes a storage medium; and the data access device represents a memory device, and the controller represents a memory controller, wherein the storage medium includes a non-volatile memory, and the non-volatile memory includes at least one non-volatile memory element.

15. The controller according to claim 13, characterized in that The at least one medium includes a transmission medium; and the data access device includes one or a combination of an optical fiber transceiver, a wired network transceiver, and a wireless network transceiver.

16. A data access device, comprising the controller according to claim 13, the data access device comprising: The controller is used to control the operation of the data access device.

17. The data access device according to claim 16, wherein: The at least one medium comprises a storage medium; the data access device represents a memory device, and the controller represents a memory controller, wherein the storage medium comprises a non-volatile memory, and the non-volatile memory comprises at least one non-volatile memory element; And the memory device comprises: The non-volatile memory is used to store information; as well as The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

18. The data access device according to claim 16, wherein: The at least one medium includes a transmission medium; and the data access device includes one or a combination of an optical fiber transceiver, a wired network transceiver, and a wireless network transceiver.

19. An electronic device comprising the data access device according to claim 16, and further comprising: The host device is coupled to the data access device, wherein the host device includes: at least one processor for controlling the operation of the host device; and A power supply circuit is coupled to the at least one processor and is used to provide power to the at least one processor and the data access device.

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