Instruction processing method and device, electronic equipment and computer readable storage medium

Abstract

The invention provides an instruction processing method and device, electronic equipment and a computer readable storage medium, and the method comprises the steps: obtaining a plurality of instruction fragments of a current to-be-processed composite program instruction according to a plurality of pieces of address information stored in a plurality of address registers; wherein the multiple pieces of address information stored in the multiple address registers are dynamically updated according to a pre-configured instruction updating program; performing combination processing on the plurality of instruction fragments to obtain the current to-be-processed composite program instruction; wherein the current to-be-processed composite program instruction is any instruction in a target program, and a plurality of composite program instructions in the target program multiplex the same instruction fragment. According to the mode, the problem of redundant storage of the same instruction fragment can be avoided by designing the instruction updating program, so that the storage space is saved, and the storage overhead is saved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to an instruction processing method and device, an electronic device, and a computer-readable storage medium. Background Art

[0002] Program instructions are instructions or commands issued by the computer to complete a basic operation. An instruction usually consists of two parts: an opcode and an operand. The opcode indicates the type or nature of the operation to be performed, while the operand is the data to be used when performing the specified operation (or the address where the data is stored).

[0003] However, in the related art, there are a lot of redundancies in the instruction contents of some programs, which results in a huge waste of storage space. Therefore, how to improve the storage efficiency of program instructions has become a problem to be solved urgently. Summary of the invention

[0004] The present disclosure provides an instruction processing method and device, an electronic device, and a computer-readable storage medium.

[0005] In a first aspect, the present disclosure provides an instruction processing method, the method comprising:

[0006] Acquire multiple instruction fragments of the composite program instruction to be processed currently according to multiple address information stored in multiple address registers; wherein the multiple address information stored in the multiple address registers is dynamically updated according to a pre-configured instruction update program;

[0007] The multiple instruction fragments are combined and processed to obtain the composite program instruction currently to be processed; wherein the composite program instruction currently to be processed is any instruction in the target program, and multiple composite program instructions in the target program reuse the same instruction fragment.

[0008] In a second aspect, the present disclosure provides an instruction processing device, the device comprising:

[0009] An address register group, an instruction control unit, an instruction storage unit, and an instruction processing unit; wherein the address register group includes: a plurality of address registers for storing address information of a plurality of instruction fragments of a composite program instruction to be processed currently in the instruction storage unit;

[0010] The instruction control unit is used to obtain multiple instruction fragments of the composite program instruction to be processed currently according to the multiple address information stored in the multiple address registers; wherein the multiple address information stored in the multiple address registers is dynamically updated according to a pre-configured instruction update program;

[0011] The instruction processing unit is used to combine and process the multiple instruction fragments to obtain the current composite program instruction to be processed; wherein the current composite program instruction to be processed is any instruction in the target program, and multiple composite program instructions in the target program reuse the same instruction fragment.

[0012] In a third aspect, the present disclosure provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, and one or more of the computer programs are executed by the at least one processor to enable the at least one processor to perform the above-mentioned method.

[0013] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above method when executed by a processor / processing core.

[0014] In the embodiment provided by the present disclosure, first, based on the multiple address information stored in the multiple address registers, multiple instruction fragments of the composite program instruction to be processed are obtained. Then, the multiple instruction fragments are combined and processed to obtain the composite program instruction to be processed. The composite program instruction to be processed can be any instruction in the target program, and multiple composite program instructions in the target program reuse the same instruction fragment. This method can dynamically update the multiple address information stored in the multiple address registers through a pre-configured instruction update program, so that the multiple address information stored in the multiple address registers points to the storage address of the multiple instruction fragments of the composite program instruction to be processed. Accordingly, by reading the multiple address information stored in the multiple address registers, the multiple instruction fragments of the composite program instruction to be processed can be obtained, and the multiple instruction fragments are combined to obtain the composite program instruction to be processed.

[0015] It can be seen that this method enables multiple composite program instructions in the target program to reuse the same instruction fragment, and dynamically update the address register through the instruction update program to dynamically adapt the storage location of multiple instruction fragments in the composite program instruction to be processed. Therefore, the same instruction fragment does not need to be stored repeatedly, only one copy is needed, and the instruction update program can flexibly point to multiple instruction fragments in the composite program instruction to be processed by dynamically adjusting the value of the address register. In short, by designing the instruction update program, the problem of redundant storage of the same instruction fragment can be avoided, thereby saving storage space and saving storage overhead.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings. In the accompanying drawings:

[0018] Figure 1 A flowchart of an instruction processing method provided by an embodiment of the present disclosure is shown;

[0019] Figure 2 shows a schematic diagram of instruction processing when the target program is of the second type;

[0020] Figure 3 Another instruction processing schematic diagram is shown when the target program is of the second type;

[0021] Figure 4 A hardware architecture diagram for implementing the above instruction processing method is shown;

[0022] Figure 5 A block diagram of an instruction processing device provided by an embodiment of the present disclosure;

[0023] Figure 6 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0025] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0026] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0029] In the related art, some programs have a lot of redundant instruction content, which results in a huge waste of storage space. In order to solve the above problem, the present application designs an instruction update program to avoid the problem of redundant storage of the same instruction fragments, thereby saving storage space and storage overhead.

[0030] Figure 1 FIG. 1 is a flow chart of an instruction processing method provided by an embodiment of the present disclosure. Figure 1 As shown, the instruction processing method includes:

[0031] Step S110: acquiring multiple instruction fragments of the currently processed composite program instruction according to multiple address information stored in multiple address registers; wherein the multiple address information stored in the multiple address registers is dynamically updated according to a pre-configured instruction update program.

[0032] The compound program instruction refers to an instruction or instruction sequence composed of multiple simple instructions for implementing a more complex function. The simple instruction can be in various forms such as an instruction fragment, instruction local data, etc. The specific form of the compound program instruction is not limited in this application.

[0033] Since the instruction information contained in the compound program instruction is usually large, it can be divided into multiple instruction fragments. In the present application, multiple address registers are pre-set to store the storage addresses of multiple instruction fragments contained in the same compound program instruction. Among them, the number of multiple address registers can be determined according to the instruction complexity of the compound program instruction. If the instruction complexity of the compound program instruction is higher, the number of address registers is greater; if the instruction complexity of the compound program instruction is lower, the number of address registers is smaller.

[0034] Among them, the multiple address registers in the present application are used to record the storage addresses of the instruction fragments, which can be program counters or other various forms of registers. The present application does not limit the specific types and implementation methods of the address registers. In addition, since the instruction fragments corresponding to different composite program instructions are different, in the process of processing different composite program instructions, the value of the address register is also dynamically updated to point to the multiple instruction fragments in the composite program instruction currently being processed.

[0035] Step S120: Combining and processing the multiple instruction fragments to obtain a composite program instruction to be processed currently; wherein the composite program instruction to be processed currently is any instruction in the target program, and multiple composite program instructions in the target program reuse the same instruction fragment.

[0036] Among them, the combination processing includes: splicing processing according to the order of acquisition of multiple instruction fragments, splicing processing after adjusting the arrangement order of the acquired multiple instruction fragments, inserting preset instruction content into multiple instruction fragments and then splicing them. In short, this application does not limit the specific implementation method of the combination processing. It can be a simple splicing of multiple instruction fragments directly, or it can be splicing after adjusting multiple instruction fragments according to preset common instruction content or preset common instruction parameters.

[0037] Among them, the currently processed composite program instruction can be any instruction in the target program. For example, each composite program instruction can be sequentially used as the currently processed composite program instruction according to the arrangement order of the multiple composite program instructions contained in the target program. Moreover, in the present application, each instruction fragment only stores one copy of data, and the same instruction fragment does not need to be stored repeatedly. Instead, through the dynamic processing of the instruction update program, multiple composite program instructions in the target program can reuse the same instruction fragment.

[0038] In the embodiments provided by the present disclosure, multiple composite program instructions in the target program can reuse the same instruction fragment, and the address register is dynamically updated through the instruction update program to dynamically adapt the storage locations of multiple instruction fragments in the composite program instruction to be processed. Therefore, the same instruction fragment does not need to be stored repeatedly, and only needs to be stored in one copy, and the instruction update program can flexibly point to multiple instruction fragments in the composite program instruction to be processed by dynamically adjusting the value of the address register. In short, by designing the instruction update program, the problem of redundant storage of the same instruction fragment can be avoided, thereby saving storage space and saving storage overhead.

[0039] In addition, those skilled in the art may also make various modifications and variations to the embodiments of the present disclosure:

[0040] In an optional implementation, before obtaining multiple instruction fragments of the current composite program instruction to be processed based on multiple address information stored in multiple address registers, the following operations are further performed: when the previous composite program instruction is processed, a pre-configured instruction update program is run; the multiple address information stored in the multiple address registers is updated through the instruction update program, so that the updated multiple address information respectively points to the storage addresses of the multiple instruction fragments of the current composite program instruction to be processed. For example, when the nth composite program instruction is processed, a pre-configured instruction update program is run; the multiple address information stored in the multiple address registers is updated through the instruction update program, so that the updated multiple address information respectively points to the storage addresses of the multiple instruction fragments of the current composite program instruction to be processed, where n is a natural number. Through the instruction update program, the values ​​of the multiple address registers can be dynamically updated so that the values ​​of the multiple address registers always point to the multiple instruction fragments of the current composite program instruction to be processed.

[0041] In an optional implementation, the target program includes a plurality of composite program instructions, and the instruction update program includes a plurality of groups of update instructions corresponding to the plurality of composite program instructions; wherein each group of update instructions is used to update the storage addresses of the plurality of instruction fragments of the corresponding composite program instruction. For example, a plurality of address registers may correspond to the plurality of instruction fragments of each composite program instruction on a one-to-one basis, and each group of update instructions may further include: a plurality of address update instructions corresponding to the plurality of address registers on a one-to-one basis, each address update instruction being used to update the corresponding address register so that the address information in the address register points to the storage address of the instruction fragment corresponding to the address register in the composite program instruction currently to be processed.

[0042] It can be seen that the instruction update program is specifically configured according to the number of compound program instructions in the target program. For example, in the case where the target program includes N compound program instructions, the instruction update program includes N groups of update instructions corresponding to the N compound program instructions. Among them, the specific number of each group of update instructions can be set according to the number of multiple address registers. For example, in the case where the number of multiple address registers is M, each group of update instructions contains M address update instructions, which are respectively used to update the values ​​of the M address registers. Accordingly, the number of instruction fragments contained in each compound program instruction is not greater than M.

[0043] In an optional implementation, the number of multiple address registers is M, and the instruction update program can be generated in the following manner: split the target program into multiple non-repeating instruction fragments, and store the multiple non-repeating instruction fragments in a preset address space. For example, the instruction fragments in the target program can be deduplicated and then stored in the preset address space. For the i-th compound program instruction in the target program, the storage address of the M instruction fragments of the i-th compound program instruction in the preset address space is determined; and, based on the positional relationship between the storage address of the M instruction fragments of the i-1-th compound program instruction in the preset address space and the storage address of the M instruction fragments of the i-th compound program instruction in the preset address space, the i-th group of update instructions corresponding to the i-th compound program instruction in the instruction update program is generated.

[0044] For example, the instruction content of the i-th group of update instructions corresponding to the i-th compound program instruction in the instruction update program can be determined based on the relative position relationship between the i-th storage address of the M instruction fragments of the i-th compound program instruction in the preset address space and the i-th storage address of the M instruction fragments of the i-th compound program instruction in the preset address space. Specifically, the i-th group of update instructions includes M address update instructions, so the relative position relationship between the i-th storage address of each instruction fragment of the i-th compound program instruction in the preset address space and the i-th storage address of the corresponding instruction fragment of the i-th compound program instruction in the preset address space can be determined respectively, thereby generating an address update instruction for the address register corresponding to the instruction fragment in the i-th group of update instructions.

[0045] In an optional implementation, the M instruction fragments contained in each compound program instruction can be allocated to M address registers in order of sequence numbering, for example, the beginning portion of the compound program instruction corresponds to the instruction fragment pointed to by the first address register, and the ending portion of the compound program instruction corresponds to the instruction fragment pointed to by the Mth address register. Therefore, the update logic of the first address register is determined according to the relative position relationship between the storage address of the first instruction fragment of the i-1th compound program instruction in the preset address space and the storage address of the first instruction fragment of the i-th compound program instruction in the preset address space.

[0046] It can be seen that the i-th group of update instructions is used to update the M address information stored in the M address registers from the storage addresses of the M instruction fragments of the i-1-th compound program instruction in the preset address space to the storage addresses of the M instruction fragments of the i-th compound program instruction in the preset address space; where i is a natural number.

[0047] In an optional implementation, when the target program is split into multiple non-repeating instruction fragments and the multiple non-repeating instruction fragments are stored in a preset address space, it can be implemented in the following way: the instruction unit contained in the target program that appears multiple times is stored as a reusable instruction fragment in the first type of storage area in the preset address space; the instruction unit contained in the target program that does not appear multiple times is stored as a non-reusable instruction fragment in the second type of storage area in the preset address space. It can be seen that the target program can be parsed in advance to extract the instruction units that appear multiple times as a reusable instruction fragment, and store this type of instruction fragment in the first type of storage area in the preset address space. In addition, the instruction unit that appears only once is stored as a non-reusable instruction fragment in the second type of storage area in the preset address space. By storing the repeated part and the non-repeating part separately, it is convenient to configure the specific logic of the instruction update program according to different storage locations.

[0048] Among them, the M address registers may further include: a first group of registers for pointing to instruction fragments in the first type of storage area, and a second group of registers for pointing to instruction fragments in the second type of storage area; wherein the update logic of the first group of registers is different from that of the second group of registers. It can be seen that by dividing the M address registers into a first group of registers corresponding to the instruction fragments in the first type of storage area, and a second group of registers corresponding to the instruction fragments in the second type of storage area, it is convenient to configure different address update logics for the first group of registers and the second group of registers according to the difference between the reusable instruction fragments and the non-reusable instruction fragments. Correspondingly, the i-th group of update instructions may further include: a first group of address update instructions for updating the first group of registers, and a second group of address update instructions for updating the second group of registers; wherein the update logic of the first group of address update instructions is different from that of the second group of address update instructions. It can be seen that the M address update instructions contained in each group of update instructions mentioned above are further divided into two groups. In addition, the control types contained in the two groups of address update instructions can be different, which can be flexibly set according to actual conditions.

[0049] In an optional implementation, the i-th group of update instructions includes at least one of the following control type instructions:

[0050] (1) A control type used to control the address information stored in the address register to increase or decrease a preset step size:

[0051] The address information stored in the address register can be controlled to increase or decrease the preset step length by address stepping, or address addition, subtraction, multiplication, etc. This control type is applicable to control according to the address offset before and after the update, and can be applicable to the first group of address update instructions mentioned above, so as to update the information in the first group of registers for indicating the storage address of the non-reusable instruction fragment.

[0052] For example, the control type can be implemented by "+ / -step", where step represents the step length, and step can be a constant, or step can also be an increasing or decreasing variable. In addition, the control type can also be implemented by address addition, subtraction, and multiplication operations.

[0053] (2) Control type used to control the address information stored in the address register to be updated according to a preset cycle strategy:

[0054] Among them, the preset loop strategy can be controlled by means of a "for loop" statement, etc. This control type is suitable for instruction fragments that appear in multiple loops, and can be applied to the second group of address update instructions mentioned above to update the information in the second group of registers used to indicate the storage address of reusable instruction fragments.

[0055] (3) Control type used to control the address information stored in the address register to be updated according to preset judgment conditions:

[0056] The address information stored in the address register can be controlled to be updated by means of if branch judgment, etc. This control type is applicable to instruction fragments that appear multiple times under specified conditions, and can be applied to the second group of address update instructions mentioned above to update the information in the second group of registers for indicating the storage address of the reusable instruction fragment.

[0057] In summary, those skilled in the art can flexibly configure the specific control type of the update instruction. Among them, for the second group of address update instructions, since the instruction fragments pointed to by them are usually not reusable and only appear once, it can be implemented by the above-mentioned control type (1) for controlling the address information stored in the address register to increase or decrease the preset step size. For example, the address offset of the corresponding instruction fragment in the address register before and after the update can be calculated in advance, so as to configure the update logic according to the numerical value of the address offset. In addition, for the first group of address update instructions, since the instruction fragments pointed to by them are reusable, that is, they appear repeatedly, therefore, according to the repetition rule of the recurring instruction fragments, such as appearing sequentially according to certain loop conditions, or appearing multiple times according to certain judgment conditions, the corresponding control type can be flexibly configured. Therefore, it can be implemented by the above-mentioned control type (2) for controlling the address information stored in the address register to be updated according to the preset loop strategy and the control type (3) for controlling the address information stored in the address register to be updated according to the preset judgment condition.

[0058] In an optional implementation, the preset step size can be determined based on the instruction length of the instruction fragment. In addition, considering that the logic complexity and execution time of the instruction update program itself will affect the instruction processing time, therefore, in the present application, the storage method of the instruction length of the instruction fragment can be flexibly configured according to the program processing time (or logic complexity) of the instruction update program. For example, when the program processing time of the instruction update program is less than the preset time, it means that the logic complexity of the instruction update program itself is not high, and it will basically not affect the instruction processing process. Therefore, the instruction length of the instruction fragment can be stored as a program parameter of the instruction update program to facilitate the instruction update program to read. For another example, when the program processing time of the instruction update program is greater than the preset time, it means that the logic complexity of the instruction update program itself is high. In order to avoid affecting the instruction processing process, the instruction length of the instruction fragment and the instruction fragment can be associated and stored in the preset address space, thereby avoiding increasing the storage overhead and logic complexity of the instruction update program.

[0059] In an optional implementation, when the previous composite program instruction has been processed, the pre-configured instruction update program can be run in the following manner: First, the program address stored in the instruction register is read through a preset instruction control unit. The program address stored in the instruction register is dynamically determined according to the storage address of a group of update instructions corresponding to the composite program instruction to be processed currently in the instruction update program. It can be seen that the program address stored in the instruction register is used to characterize the storage address of a group of update instructions corresponding to the composite program instruction to be processed currently in the instruction update program. Then, according to the read program address, a group of update instructions corresponding to the composite program instruction to be processed currently in the instruction update program are obtained and run to update multiple address information stored in multiple address registers. In this method, on the one hand, the storage address of a group of update instructions corresponding to the composite program instruction to be processed currently in the instruction update program is specially stored through the instruction register; on the other hand, the instruction update program is run through the instruction control unit.

[0060] It can be seen that this method can ensure the efficient operation of the instruction update program by providing a dedicated instruction register and a dedicated hardware computing unit (i.e., an instruction control unit). Among them, the instruction control unit can also be called an instruction controller. As a medium for executing the instruction update program, it has at least the following advantages: in scenarios such as neural networks, there is a lack of hardware units specifically used to execute the instruction update program. Therefore, if the instruction update program is run directly through the operator, the resources of the operator will be occupied, thereby affecting the execution efficiency of the operator. Therefore, the present application can improve the instruction processing efficiency by adding an instruction control unit dedicated to executing the instruction update program. Among them, the instruction control unit can be implemented by a general computing unit.

[0061] For ease of understanding, an example is taken below to introduce the implementation of the instruction processing method provided in an embodiment of the present disclosure.

[0062] This example can be applied to neural network acceleration chips (also called neural network accelerators). With the rapid development of artificial intelligence technology, neural network acceleration chips have also emerged. Generally, neural network acceleration chips execute coarse-grained instructions. The so-called coarse-grained instructions refer to instructions with relatively large operation and data granularity, which can be used to process data structures such as two-dimensional and three-dimensional vectors and tensors. In other words, coarse-grained instructions refer to instructions with a large amount of information contained in the instructions, high complexity of instruction execution, and long instruction processing time. Correspondingly, each coarse-grained instruction usually occupies a large storage space, for example, more than 64 bits of storage space. These coarse-grained instructions not only include a complete Tensor calculation process, but also cover detailed information on memory access operations and data flows, as well as related parameters of many hardware parallel computing devices. Therefore, neural network acceleration chips often require a large storage space to store these instructions. However, due to the limited storage space inside the chip, the number of instructions that can be processed by the neural network acceleration chip is also limited due to the upper limit of the chip storage space, which seriously affects the processing power of the neural network acceleration chip.

[0063] For example, in the existing neural network instruction set architecture, an operator or fusion operator is usually mapped to a hardware instruction. For example, a convolution instruction may include: instruction type, instruction ID, size of each dimension of the convolution, padding / stride / dilation parameters, calculation accuracy, parallel expansion strategy, data read and write address, and address stepping during the calculation process. When a neural network contains multiple convolution operations, the program executed by the hardware contains multiple such convolution instructions. However, there are often repeated operations of several operators in the neural network, especially in large models, where not only the operators contained in each layer are the same, but also the shapes of the operators are the same. In addition, there is a lot of repetitive information in the instruction content of the hardware instructions, and the existing memory access is redundant for the storage of repetitive information in the instruction content. Although for some network structures, instructions can be reused in the form of loop instruction segments, different instructions of the same type often have some different parameters (such as different addresses for reading and writing data). At this time, the above optimization method cannot be used.

[0064] In order to solve the above problems, the instruction storage redundancy can be reduced by means of a hierarchical instruction format, and the storage space required for the instruction can be effectively reduced. For example, in one implementation, a preset target program of a specified type (also called a target program of the first type) can be processed into a plurality of hierarchical composite program instructions (also called a composite program instruction of the first type). Among them, some or all areas in the target program of the specified type meet the preset arrangement conditions. It can be seen that the target program of the specified type can be a complete program or a local area in the program. Among them, the preset arrangement conditions may include: multiple recurring instruction fragments contained in the target program are arranged in a tree structure, a linear structure, a loop nested structure, etc., and appear multiple times in a certain regular pattern. Accordingly, this type of composite program instruction can be processed in the following manner:

[0065] First, according to the first address information stored in the first register, the shared instruction data contained in the composite program instruction is obtained. Wherein, the composite program instruction refers to: an instruction or instruction sequence composed of multiple simple instructions for realizing a more complex function. Wherein, the simple instruction can be in various forms such as an instruction fragment, an instruction local data, etc., and the present application does not limit the specific form of the composite program instruction. The shared instruction data contained in the composite program instruction refers to: an instruction content that can be reused by at least two instruction fragments in the composite program instruction. Specifically, the shared instruction data can also be the instruction content that appears repeatedly in the composite program instruction. The first register can also be called an address register, a program counter, etc. The first register is used to store the storage address of the shared instruction data contained in the composite program instruction in a storage space (such as a memory space). Accordingly, according to the first address information stored in the first register, the storage address of the shared instruction data contained in the composite program instruction can be determined, and then the shared instruction data contained in the composite program instruction can be obtained according to the storage address.

[0066] Then, according to the second address information stored in the second register, multiple sub-instruction data contained in the compound program instruction are obtained in sequence; wherein the second address information stored in the second register can be dynamically updated to represent the storage address of the sub-instruction data to be obtained currently. wherein, the sub-instruction data contained in the compound program instruction generally refers to: instruction content that does not appear repeatedly or appears less frequently. usually, a compound program instruction contains multiple sub-instruction data, and the multiple sub-instruction data reuse the above-mentioned shared instruction data. wherein, the second register can also be called an address register, a program counter, etc. the second register is used to store the storage address of the sub-instruction data contained in the compound program instruction in a storage space (such as a memory space). accordingly, according to the second address information stored in the second register, the storage address of the sub-instruction data contained in the compound program instruction can be determined, and then the sub-instruction data contained in the compound program instruction can be obtained according to the storage address. since the number of sub-instruction data contained in the compound program instruction is multiple, therefore, during the processing of the compound program instruction to be processed currently, the second address information in the second register will be updated multiple times, so that the second register can accurately represent the storage address of the sub-instruction data to be obtained currently.

[0067] Finally, for each acquired sub-instruction data, the sub-instruction data and the shared instruction data are combined into an executable instruction, and multiple executable instructions corresponding to the multiple sub-instruction data contained in the composite program instruction are obtained. Among them, each sub-instruction data and the shared instruction data are respectively combined into an executable instruction, thereby obtaining multiple executable instructions corresponding to the multiple sub-instruction data one by one. Accordingly, by running multiple executable instructions, the function of the above-mentioned composite program instruction can be realized.

[0068] According to the composite program instruction of the hierarchical structure mentioned above, the shared instruction data contained in the composite program instruction can be obtained through the first register; and the multiple sub-instruction data contained in the composite program instruction can be obtained in sequence through the second register; wherein the second address information stored in the second register can be dynamically updated to represent the storage address of the sub-instruction data to be currently obtained. Accordingly, for each sub-instruction data obtained, the sub-instruction data is combined with the shared instruction data into an executable instruction, thereby obtaining multiple executable instructions corresponding to the multiple sub-instruction data contained in the composite program instruction. It can be seen that this method enables multiple sub-instruction data in the composite program instruction to reuse the same shared instruction data, so that the shared instruction data only needs to be stored in one copy, without the need for repeated storage multiple times, thereby reducing storage space and saving storage overhead.

[0069] In an optional implementation, when multiple sub-instruction data contained in the composite program instruction are sequentially obtained according to the second address information stored in the second register; for each sub-instruction data obtained, when the sub-instruction data is combined with the shared instruction data into an executable instruction, it can be implemented in the following manner: determining the instruction length of the sub-instruction data contained in the composite program instruction and the total number of instructions of the sub-instruction data. In order to improve the reuse rate of the shared instruction data, under normal circumstances, the total number of instructions of the sub-instruction data contained in the composite program instruction is multiple. In addition, in order to facilitate determining the address change amount of the second register after each acquisition of a sub-instruction data, the instruction length of the sub-instruction data contained in the composite program instruction can be predetermined, so that the second register dynamically updates the specific value of the second address information stored in the second register according to the instruction length. Among them, the instruction length of the sub-instruction data contained in the composite program instruction and the total number of instructions of the sub-instruction data can be used as instruction parameters related to the shared instruction data and stored together with the shared instruction data. Accordingly, when reading the shared instruction data, the instruction length of the sub-instruction data associated with the shared instruction data and the total number of instructions of the sub-instruction data are read together. Of course, the instruction length of the sub-instruction data contained in the composite program instruction and the total number of instructions of the sub-instruction data can also be stored in other ways, and the present application does not limit this. According to the second address information stored in the second register, the i-th sub-instruction data corresponding to the shared instruction data is obtained, and the i-th sub-instruction data and the shared instruction data are combined into the i-th executable instruction, wherein i is a natural number not greater than the total number of instructions. Specifically, the i-th sub-instruction data can be any sub-instruction data contained in the composite program instruction. For example, the i-th sub-instruction data can be understood as the sub-instruction data currently being processed. Since the second register is dynamically updated, therefore, according to the second address information stored in the second register, the storage address of the sub-instruction data currently being processed contained in the composite program instruction can be obtained, and then the i-th sub-instruction data and the shared instruction data are combined into the i-th executable instruction. When the value of i is less than the total number of instructions, it is determined that the i-th sub-instruction data is not the last sub-instruction data in the composite program instruction. Accordingly, the second address information stored in the second register is updated according to the instruction length of the sub-instruction, the i+1th sub-instruction data corresponding to the shared instruction data is obtained according to the updated second address information, and the i+1th sub-instruction data and the shared instruction data are combined into the i+1th executable instruction. Usually, the instruction lengths of multiple sub-instruction data in the same composite program instruction are the same, so each time a sub-instruction data is obtained, the second address information stored in the second register is offset by a preset value according to the instruction length.Of course, if the instruction lengths of multiple sub-instruction data in the same compound program instruction are different, it is necessary to update the second address information stored in the second register according to the instruction length of the i-th sub-instruction, so as to obtain the i+1-th sub-instruction data corresponding to the shared instruction data according to the updated second address information.

[0070] In an optional implementation, the number of compound program instructions is multiple, and the first address information stored in the first register can be dynamically updated to represent the storage address of the shared instruction data contained in the compound program instruction to be processed currently. Accordingly, the method in the present application further includes the following operations: when the value of i is equal to the total number of instructions, it is determined that the i-th sub-instruction data is the last sub-instruction data in the compound program instruction, that is, the current compound program instruction has been processed and the next compound program instruction needs to be processed. Therefore, the first address information stored in the first register is updated to obtain the shared instruction data contained in the next compound program instruction to be processed according to the first address information stored in the updated first register.

[0071] In an optional implementation, after the first address information stored in the first register is updated, the following operation is further performed: based on the first address information stored in the updated first register, the address base of the second address information stored in the second register is updated; wherein the updated address base is used to determine the storage address of the first sub-instruction data contained in the next compound program instruction to be processed. Specifically, before the first address information stored in the first register is updated, the address base of the second address information stored in the second register is determined based on the storage address of the first sub-instruction data contained in the compound program instruction currently being processed. After the first address information stored in the first register is updated, the address base of the second address information stored in the second register is determined based on the storage address of the first sub-instruction data contained in the next compound program instruction to be processed. It can be seen that the address base of the second address information refers to: the address offset based on the starting stage of processing a compound program instruction.

[0072] In an optional implementation, in order to facilitate the addressing operation of shared instruction data and sub-instruction data, the shared instruction data and the sub-instruction data can be stored in different storage spaces. Accordingly, the first address information stored in the first register is used to represent the address information in the first storage space, and the first storage space is used to store the shared instruction data contained in multiple compound program instructions; the second address information stored in the second register is used to represent the address information in the second storage space, and the second storage space is used to store the sub-instruction data contained in multiple compound program instructions. By storing the shared instruction data and the sub-instruction data separately, the first register and the second register can be updated independently. In this way, after updating the first address information stored in the first register, it is not necessary to update the address base of the second address information stored in the second register, thereby simplifying the update processing logic of the second register and improving processing efficiency.

[0073] In an optional implementation, before obtaining the shared instruction data contained in the composite program instruction based on the first address information stored in the first register, the following operations are performed in advance: when it is determined that multiple recurring instruction fragments contained in the target program meet a preset arrangement condition, a composite program instruction corresponding to the recurring instruction fragment is generated based on the number of occurrences of each recurring instruction fragment and the instruction information associated with the recurring instruction fragment.

[0074] Optionally, the shared instruction data contained in the compound program instruction is determined based on the repeatedly occurring instruction fragment, the total number of instructions of the sub-instruction data contained in the compound program instruction is determined based on the number of occurrences of the repeatedly occurring instruction fragment, and the data content of the sub-instruction data contained in the compound program instruction is determined based on the instruction information associated with the repeatedly occurring instruction fragment. For example, the shared instruction data in a compound program instruction can be obtained based on each repeatedly occurring instruction fragment, and the total number of instructions of the sub-instruction data contained in the compound program instruction is determined based on the number of occurrences of the repeatedly occurring instruction fragment. Wherein, each sub-instruction data is determined based on the instruction information associated with the repeatedly occurring instruction fragment.

[0075] In an optional implementation, a composite program instruction can be applied to a neural network; and the shared instruction data contained in the composite program instruction may include: instruction data for characterizing an operator operation type; the sub-instruction data contained in the composite program instruction may include: instruction data for characterizing an operation parameter corresponding to the operator operation type. Among them, the operator operation type may include: a convolution type; the operation parameters corresponding to the operator operation type may include: a parameter for characterizing the convolution size, and / or a parameter for characterizing the convolution input data. It can be seen that the instruction code corresponding to the operator operation type of the convolution type can be used as shared instruction data, and the data information for characterizing the specific parameters of the convolution can be used as sub-instruction data. Accordingly, the multiple sub-instruction data within the composite program instruction are used to rely on different convolution parameters and implement multiple convolution processing based on the same convolution operation mode.

[0076] In an optional implementation, the compound program instruction is an m-th level compound program instruction, and the m-th level compound program instruction is any sub-instruction in the m-1-th level compound program instruction; wherein, the shared instruction data contained in the m-th level compound program instruction can be determined according to the m-th level first register, and the sub-instruction data contained in the m-th level compound program instruction can be determined according to the m-th level second register. Moreover, in the case where any sub-instruction data contained in the m-th level compound program instruction is an m+1-th level compound program instruction, the shared instruction data contained in the m+1-th level compound program instruction is determined according to the m+1-th level first register, and the sub-instruction data contained in the m+1-th level compound program instruction is determined according to the m+1-th level second register; wherein, m is a natural number. It can be seen from this that the compound program instruction can be designed in the form of loop nesting, further nesting a layer of compound program instructions inside a sub-instruction. This method is particularly suitable for scenarios where multiple recurring instruction fragments contained in the target program are arranged in accordance with the arrangement of a loop nesting structure.

[0077] However, the hierarchical composite program instructions mentioned above (i.e., the first type of composite program instructions) can only be applied to programs that meet specific arrangement conditions (i.e., the first type of target programs). For example, it is only applicable to special scenarios where the reusable instruction parts in the program are arranged in a tree form. However, most parallel programs do not meet the above arrangement conditions. For example, general branch programs or multi-layer loop programs may also find it difficult to achieve sufficient instruction sharing by modifying the instruction format. Accordingly, the present application can be applied to the first type of target programs and the second type of target programs. Among them, the first type of target programs include the above-mentioned tree structure and / or hierarchical structure programs, and the second type of target programs include parallel structures and / or non-hierarchical structures.

[0078] Therefore, in order to improve the versatility of the composite program instruction and enable it to be flexibly adapted to various types of target programs, this example provides a program pointer structured stepping method to be applied to instruction storage in a more general parallel computing scenario. Specifically, this example provides a composite program instruction (also called the composite program instruction of the second type) of a non-hierarchical structure, and the composite program instruction of this non-hierarchical structure can be applicable to the target program of the second type. Wherein, the target program of the second type does not usually meet the preset arrangement conditions mentioned above. Similar to the target program of the first type, the target program of the second type can also be a complete program, or a local area in a program.

[0079] Accordingly, in this example, the following operations can be performed in advance: determine the program type of the target program to be processed, and when it is determined that the program type of the target program to be processed is the first type, execute the processing flow corresponding to the first type of target program mentioned above; when it is determined that the program type of the target program to be processed is the second type, execute the processing flow corresponding to the second type of target program described below.

[0080] Among them, the instructions of the target program can be coarse-grained instructions, and the instruction characteristics of the coarse-grained instructions may include at least one of the following: the amount of information contained in the instructions is greater than a preset information amount threshold; the instruction processing time is greater than a preset time threshold; the instruction storage space is greater than a preset space threshold; the number of operators contained in the instructions is greater than a preset number threshold (for example, the more types and numbers of operators, the more complex the instructions).

[0081] Figure 2 FIG. 2 shows a schematic diagram of instruction processing when the target program is of the second type. Figure 2 As shown, the second type of target program is pre-divided into a plurality of non-repeating instruction fragments and stored in a designated storage space, such as a memory (corresponding to Figure 2 In the Memory in , each instruction fragment has a unique storage address. In addition, m sub-instruction pointers are set, such as Figure 2 PC1, PC2, …, PC m The m sub-instruction pointers may be stored in m address registers, and the specific values ​​may be dynamically updated as the composite program instruction is switched, so that m instruction fragments corresponding to the composite program instruction to be processed are extracted from the storage space through the values ​​of the m sub-instruction pointers.

[0082] like Figure 2As shown, according to the value of the first sub-instruction pointer PC1 (specifically, it can be read through the first address register), the first instruction fragment S1 in the current compound program instruction to be processed can be obtained from the memory, and the length of the instruction fragment S1 is L1; according to the value of the second sub-instruction pointer PC2 (specifically, it can be read through the second address register), the second instruction fragment S2 in the current compound program instruction to be processed can be obtained from the memory, and the length of the instruction fragment S2 is L2... According to the value of the mth sub-instruction pointer PCm (specifically, it can be read through the mth address register), the mth instruction fragment Sm in the current compound program instruction to be processed can be obtained from the memory, and the length of the instruction fragment Sm is Lm.

[0083] After the current composite program instruction to be processed is processed, the m sub-instruction pointers are dynamically updated to point to each instruction fragment in the next composite program instruction to be processed.

[0084] It can be seen that by presetting m sub-instruction pointers and m sub-instruction lengths L1, L2, ..., L m , so that these sub-instruction pointers dynamically point to different storage addresses, and can achieve the purpose of multiple composite program instructions reusing the same instruction fragment when each instruction fragment is only stored once. It should be noted that the sub-instructions here are different from the sub-instructions mentioned in the hierarchical composite program instructions, but refer to the instruction fragments mentioned above.

[0085] In this example, in addition to the program that the chip is supposed to execute, it also includes a PC update program (i.e., the instruction update program mentioned above), which is used to dynamically update the values ​​of the m sub-instruction pointers. Accordingly, each time the processor executes a composite program instruction, the PC update program updates PC1, PC2, ..., PC m and L1,L2,…,L m , so that the updated PC1, PC2, …, PC m Point to the location, read L1, L2, ..., L m length of instruction fragments and combine them into a new compound program instruction, such as Figure 2 A complete compound program instruction is shown in .

[0086] For traditional computers, m=1, that is, only one address register and instruction pointer are set, and the PC update program is usually a simple next PC=PC+1 plus jump implementation logic. This example does not limit the specific implementation details of the PC update program, which can be implemented by combining various basic control flows. For example, the PC update program may include the following control logic:

[0087] (1)+step, step is a constant;

[0088] (2) +step, step is an increasing variable;

[0089] (3) for loop;

[0090] (4) if branch judgment;

[0091] (5)Addition, subtraction, and multiplication of addresses.

[0092] The combination of the above logic can realize more flexible PC control. Of course, in order to improve the efficiency of instruction processing, the complexity of the PC update program can be reduced as much as possible.

[0093] In this example, during the program compilation phase, the compiler can analyze the reuse relationship between instructions, separate the repeated instruction segments, store them in the memory, and finally generate the instruction update program based on the instruction segmentation and the arrangement in the memory. The segmentation method during the segmentation process needs to ensure that the number of instruction fragments contained in each composite program instruction does not exceed m.

[0094] In addition, the instruction update program itself usually needs to be executed by the processor, that is, the instruction update program also needs to be stored as a series of instructions (such as the address update instructions mentioned above). However, these instructions are mostly scalar calculation instructions or control instructions, which are completely different from the coarse-grained parallel calculation instructions contained in the main load of the AI ​​processor (often an instruction is longer than 100 bits), so it will not affect the performance. For example, the instruction length of the instruction update program can be very short, such as 16bit or 32bit. The instruction update program can have its own instruction pointer, denoted as PPC, and PPC can use the basic PPC+1 plus jump stepping method. It can be seen that the address update instructions contained in the instruction update program may include various types such as scalar calculation instructions and / or control instructions. In addition, the instruction pointer corresponding to the instruction update program can be updated in a stepping manner. Among them, the instruction pointer corresponding to the instruction update program is used to point to the program address stored in the instruction register.

[0095] In other optional implementations, the sub-instruction lengths L1, L2, ..., L may not be specified separately. m , but directly record the length of each instruction fragment itself at the starting position of the instruction fragment, such as Figure 3 As shown, the length of each instruction fragment is directly recorded at the starting position of the corresponding instruction fragment without being stored through the instruction update program, thereby reducing the complexity of the instruction update program.

[0096] In some optional implementations, in order to facilitate the execution of the instruction update program, a dedicated instruction controller may be provided to improve instruction execution efficiency. Figure 4 A hardware architecture diagram for implementing the above instruction processing method is shown. Figure 4 , as shown in step S1, the instruction controller reads the instruction pointer of the instruction update program from the PPC.

[0097] As shown in step S2, the instruction controller obtains the next address update instruction of the instruction update program to be executed from the instruction storage through the value of the PPC pointer, and executes the address update instruction.

[0098] As shown in step S3, after executing multiple address update instructions, it is determined that all address registers in the address register group, ie, PC1 to PCm, have been updated, and the instruction controller writes the updated values ​​into the PC1 to PCm registers.

[0099] As shown in step S4, according to the updated values ​​of PC1-PCm, the corresponding instruction fragments are taken out from the corresponding positions in the instruction storage and sent to the instruction assembler. Step S4 may be executed by a global controller (not shown in the figure).

[0100] As shown in step S5, the instruction assembler assembles the above instruction fragments into a complete composite program instruction in sequence, and issues it to the computing unit so that the computing unit executes the composite program instruction.

[0101] In the above process, one or more registers among PC1-PCm may also be null values ​​or illegal values. In this case, it means that the number of instruction fragments contained in the currently processed composite program instruction is less than m, so it is not necessary to use all address registers.

[0102] Through the above method, with the help of the instruction update program, multiple instruction fragments in each compound program instruction can be flexibly taken from different storage addresses, so that each instruction fragment is only stored once (instruction fragments that appear multiple times do not need to be stored repeatedly multiple times), and the effect of multiple compound program instructions flexibly reusing different instruction fragments can be achieved, thereby greatly saving instruction storage space and improving instruction processing efficiency. In addition, this method can be flexibly applied to various types of target programs, without any restrictions on the structure of the target program, and has a wide range of applicable scenarios.

[0103] In addition, the above instruction processing method can be applied to a many-core system including multiple processing cores. Accordingly, instruction processing based on the many-core system can be implemented in the following manner:

[0104] First, the second processing core sends the stored multi-core shared data to the first processing core. Among them, the second processing core can be called the instruction supply core corresponding to the multi-core shared data, and the first processing core can be called the instruction use core corresponding to the multi-core shared data. Specifically, the second processing core sends the stored multi-core shared data to the first processing core for use by the first processing core. Among them, the number of first processing cores can be one or one. And, in the case where there is a direct connection relationship between the first processing core and the second processing core (that is, the first processing core is directly connected to the second processing core), the second processing core directly sends the multi-core shared data to the first processing core. In the case where there is an indirect connection relationship between the first processing core and the second processing core (that is, the first processing core is not directly connected to the second processing core, but is indirectly connected through other processing cores), the second processing core transmits the multi-core shared data to the first processing core through the forwarding of other processing cores. This application does not limit the connection relationship between the first processing core and the second processing core and the data transmission method.

[0105] Then, the first processing core combines the multi-core shared data with the multiple private instruction data stored in the first processing core to obtain multiple compound program instructions, and runs the multiple compound program instructions through the first processing core; wherein the multiple compound program instructions reuse the multi-core shared data. The first processing core has multiple private instruction data stored inside, and these private instruction data can be combined with the multi-core shared data from the second processing core to obtain multiple executable instructions, so that the multiple executable instructions can be run through the first processing core. wherein, since each executable instruction includes at least two parts, the multi-core shared data and the private instruction data, each executable instruction is a compound program instruction.

[0106] Among them, multi-core shared data is usually the instruction content that appears repeatedly in the target program, and the instruction content that appears repeatedly can be reused by multiple processing cores. Therefore, in order to avoid the waste of storage resources caused by repeated storage of the same content by multiple processing cores, in this application, the instruction content reused between multiple processing cores is stored in the second processing core as multi-core shared data to reduce the number of repeated storage times and improve the utilization of storage resources. In addition, private instruction data refers to data that is only used by this processing core and does not need to be shared with other processing cores. Usually, the shared instruction part reused between multiple processing cores can be determined first, and the content other than the shared instruction part is the private instruction data of each processing core. Private instruction data does not need to be reused by other processing cores, so it only needs to be stored in the private storage space inside the processing core.

[0107] Wherein, when the composite program instruction is a hierarchical structure, the multi-core shared data may be the shared instruction data (i.e., the parent instruction data) and the child instruction data mentioned above. When the composite program instruction is a non-hierarchical structure, the multi-core shared data may be the instruction fragment mentioned above. In addition, the private instruction data may be the child instruction or instruction fragment mentioned above.

[0108] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0109] In addition, the present disclosure also provides an instruction processing device, an electronic device, and a computer-readable storage medium, all of which can be used to implement any instruction processing method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0110] Figure 5 A block diagram of an instruction processing device provided in an embodiment of the present disclosure.

[0111] Reference Figure 5 , the embodiment of the present disclosure provides a data processing device, the device comprising: an address register group 51, an instruction control unit 52, an instruction storage unit 53, and an instruction processing unit 54;

[0112] The address register group 51 includes: a plurality of address registers for storing address information of a plurality of instruction fragments of the composite program instruction to be processed currently in the instruction storage unit;

[0113] The instruction control unit 52 is used to obtain multiple instruction fragments of the composite program instruction to be processed currently according to the multiple address information stored in the multiple address registers; wherein the multiple address information stored in the multiple address registers is dynamically updated according to a pre-configured instruction update program;

[0114] The instruction processing unit 54 is used to combine and process the multiple instruction fragments to obtain the current composite program instruction to be processed; wherein the current composite program instruction to be processed is any instruction in the target program, and multiple composite program instructions in the target program reuse the same instruction fragment.

[0115] In an optional implementation, the instruction control unit is used to run the pre-configured instruction update program; and the instruction processing device further includes: an instruction register, which is used to dynamically store the storage address of a group of update instructions in the instruction update program corresponding to the composite program instruction currently to be processed; then the instruction control unit is used to obtain and run a group of update instructions corresponding to the composite program instruction currently to be processed according to the storage address in the instruction register, and the running result of the update instructions is used to update the multiple address information stored in the multiple address registers, so that the updated multiple address information points to the multiple instruction fragments of the composite program instruction currently to be processed;

[0116] In addition, the instruction processing unit further includes: an instruction assembler and an instruction operator; wherein the instruction assembler is used to combine and process the multiple instruction fragments to obtain the current composite program instruction to be processed; and the instruction operator is used to run the composite program instruction.

[0117] In an optional implementation, the device also includes: an update unit, which is used to run the pre-configured instruction update program when the previous compound program instruction is processed; and update the multiple address information stored in the multiple address registers through the instruction update program, so that the updated multiple address information respectively point to the storage addresses of the multiple instruction fragments of the current compound program instruction to be processed.

[0118] In an optional implementation, the target program includes a plurality of compound program instructions, and the instruction update program includes a plurality of groups of update instructions corresponding one-to-one to the plurality of compound program instructions;

[0119] Among them, the multiple address registers correspond one-to-one to the multiple instruction fragments of each compound program instruction, and each group of update instructions further includes: multiple address update instructions corresponding one-to-one to the multiple address registers, each address update instruction is used to update the corresponding address register so that the address information in the address register points to the storage address of the instruction fragment corresponding to the address register in the current compound program instruction to be processed.

[0120] In an optional implementation, the number of the multiple address registers is M, and the instruction update program is generated in the following manner:

[0121] Splitting the target program into a plurality of mutually non-repeating instruction fragments, and storing the plurality of mutually non-repeating instruction fragments into a preset address space;

[0122] For an i-th compound program instruction in the target program, determining storage addresses of M instruction fragments of the i-th compound program instruction in the preset address space;

[0123] generating an i-th group of update instructions corresponding to the i-th compound program instruction in the instruction update program according to a positional relationship between storage addresses of the M instruction fragments of the i-1-th compound program instruction in the preset address space and storage addresses of the M instruction fragments of the i-th compound program instruction in the preset address space;

[0124] Among them, the i-th group of update instructions is used to update the M address information stored in the M address registers from the storage addresses of the M instruction fragments of the i-1-th compound program instruction in the preset address space to the storage addresses of the M instruction fragments of the i-th compound program instruction in the preset address space; wherein i is a natural number.

[0125] In an optional implementation, the target program is split into a plurality of mutually non-repeating instruction fragments, and the plurality of mutually non-repeating instruction fragments are stored in a preset address space in the following manner:

[0126] storing the instruction units contained in the target program and appearing multiple times as a reusable instruction fragment in the first type of storage area in the preset address space;

[0127] storing the instruction units contained in the target program and not appearing multiple times as a non-repeated instruction fragment in the second type of storage area in the preset address space;

[0128] Furthermore, the M address registers further include: a first group of registers for pointing to instruction fragments in a first type of storage area, and a second group of registers for pointing to instruction fragments in a second type of storage area; and the i-th group of update instructions further includes: a first group of address update instructions for updating the first group of registers, and a second group of address update instructions for updating the second group of registers; wherein the update logic of the first group of address update instructions is different from that of the second group of address update instructions.

[0129] In an optional implementation manner, the i-th group of update instructions includes at least one of the following control type instructions:

[0130] A control type for controlling the address information stored in the address register to increase or decrease a preset step size;

[0131] A control type for controlling the address information stored in the address register to be updated according to a preset cycle strategy;

[0132] A control type used to control the address information stored in the address register to be updated according to preset judgment conditions.

[0133] In an optional implementation, the preset step size is determined according to the instruction length of the instruction fragment;

[0134] Wherein, in the case where the program processing time length of the instruction update program is less than the preset time length, the instruction length of the instruction fragment is stored as a program parameter of the instruction update program;

[0135] In a case where the program processing time length of the instruction update program is greater than a preset time length, the instruction length of the instruction fragment is associated with the instruction fragment and stored in the preset address space.

[0136] In an optional implementation, the address update instructions contained in the instruction update program include: scalar calculation instructions, and / or control instructions; and the instruction pointer corresponding to the instruction update program is updated in a step-by-step manner.

[0137] In an optional implementation, the updating unit is specifically configured to:

[0138] The program address stored in the instruction register is read through a preset instruction control unit; wherein the program address stored in the instruction register is dynamically determined according to the storage address of a group of update instructions corresponding to the composite program instruction currently to be processed in the instruction update program;

[0139] According to the program address, a group of update instructions corresponding to the composite program instructions to be processed currently in the instruction update program are obtained and executed to update the multiple address information stored in the multiple address registers.

[0140] In an optional implementation, the target program includes: a first type of target program, and a second type of target program;

[0141] The first type of target programs include programs with tree structures and / or hierarchical structures, and the second type of target programs include programs with parallel structures and / or non-hierarchical structures.

[0142] Figure 6 A block diagram of an electronic device provided in an embodiment of the present disclosure.

[0143] Reference Figure 6 An embodiment of the present disclosure provides an electronic device, which includes: at least one processor 901; at least one memory 902, and one or more I / O interfaces 903, connected between the processor 901 and the memory 902; wherein the memory 902 stores one or more computer programs that can be executed by the at least one processor 901, and the one or more computer programs are executed by the at least one processor 901 so that the at least one processor 901 can execute the above-mentioned instruction processing method.

[0144] In some embodiments, the processing device may be a brain-like chip, which can use vectorized computing and needs to load the weight information and other parameters of the neural network model through an external memory such as a double data rate (DDR) synchronous dynamic random access memory. Therefore, the batch processing used in the embodiments of the present disclosure has a higher computing efficiency.

[0145] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above instruction processing method when executed by a processor / processing core. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0146] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned instruction processing method.

[0147] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0148] As is known to those of ordinary skill in the art, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0149] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0150] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0151] The computer program product described herein may be implemented in hardware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), etc.

[0152] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0153] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0154] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0155] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0156] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for processing an instruction, the method comprising: Acquire multiple instruction fragments of the composite program instruction to be processed currently according to multiple address information stored in multiple address registers; wherein the multiple address information stored in the multiple address registers is dynamically updated according to a pre-configured instruction update program; The multiple instruction fragments are combined and processed to obtain the composite program instruction currently to be processed; wherein the composite program instruction currently to be processed is any instruction in the target program, and multiple composite program instructions in the target program reuse the same instruction fragment.

2. The method according to claim 1, wherein: Before acquiring multiple instruction fragments of the composite program instruction to be processed according to multiple address information stored in multiple address registers, the method further includes: When the last composite program instruction is processed, running the pre-configured instruction update program; The multiple address information stored in the multiple address registers is updated by the instruction updating program, so that the updated multiple address information respectively point to the storage addresses of the multiple instruction fragments of the composite program instruction to be processed currently.

3. The method according to claim 2, wherein: The target program includes a plurality of compound program instructions, and the instruction update program includes a plurality of groups of update instructions corresponding one-to-one to the plurality of compound program instructions; Among them, the multiple address registers correspond one-to-one to the multiple instruction fragments of each compound program instruction, and each group of update instructions further includes: multiple address update instructions corresponding one-to-one to the multiple address registers, each address update instruction is used to update the corresponding address register so that the address information in the address register points to the storage address of the instruction fragment corresponding to the address register in the current compound program instruction to be processed.

4. The method according to claim 3, wherein: The number of the plurality of address registers is M, and the instruction update program is generated in the following manner: Splitting the target program into a plurality of mutually non-repeating instruction fragments, and storing the plurality of mutually non-repeating instruction fragments into a preset address space; For an i-th compound program instruction in the target program, determining storage addresses of M instruction fragments of the i-th compound program instruction in the preset address space; generating an i-th group of update instructions corresponding to the i-th compound program instruction in the instruction update program according to a positional relationship between storage addresses of the M instruction fragments of the i-1-th compound program instruction in the preset address space and storage addresses of the M instruction fragments of the i-th compound program instruction in the preset address space; Among them, the i-th group of update instructions is used to update the M address information stored in the M address registers from the storage addresses of the M instruction fragments of the i-1-th compound program instruction in the preset address space to the storage addresses of the M instruction fragments of the i-th compound program instruction in the preset address space; wherein i is a natural number.

5. The method according to claim 4, wherein: The step of splitting the target program into a plurality of mutually non-repeating instruction fragments and storing the plurality of mutually non-repeating instruction fragments into a preset address space comprises: storing the instruction units contained in the target program and appearing multiple times as a reusable instruction fragment in the first type of storage area in the preset address space; storing the instruction units contained in the target program and not appearing multiple times as a non-repeated instruction fragment in the second type of storage area in the preset address space; Furthermore, the M address registers further include: a first group of registers for pointing to instruction fragments in a first type of storage area, and a second group of registers for pointing to instruction fragments in a second type of storage area; and the i-th group of update instructions further includes: a first group of address update instructions for updating the first group of registers, and a second group of address update instructions for updating the second group of registers; wherein the update logic of the first group of address update instructions is different from that of the second group of address update instructions.

6. The method according to claim 4, wherein: The i-th group of update instructions includes at least one of the following control type instructions: A control type for controlling the address information stored in the address register to increase or decrease a preset step size; A control type for controlling the address information stored in the address register to be updated according to a preset cycle strategy; A control type used to control the address information stored in the address register to be updated according to preset judgment conditions.

7. The method according to claim 6, wherein: The preset step length is determined according to the instruction length of the instruction fragment; Wherein, in the case where the program processing time length of the instruction update program is less than the preset time length, the instruction length of the instruction fragment is stored as a program parameter of the instruction update program; In a case where the program processing time length of the instruction update program is greater than a preset time length, the instruction length of the instruction fragment is associated with the instruction fragment and stored in the preset address space.

8. The method according to claim 6, wherein: The address update instructions contained in the instruction update program include: scalar calculation instructions, and / or control instructions; and the instruction pointer corresponding to the instruction update program is updated in a step-by-step manner.

9. The method according to claim 2, wherein: When the previous composite program instruction is processed, running the pre-configured instruction update program includes: The program address stored in the instruction register is read through a preset instruction control unit; wherein the program address stored in the instruction register is dynamically determined according to the storage address of a group of update instructions corresponding to the composite program instruction currently to be processed in the instruction update program; According to the program address, a group of update instructions corresponding to the composite program instructions to be processed currently in the instruction update program are obtained and executed to update the multiple address information stored in the multiple address registers.

10. The method according to claim 1, wherein: The target programs include: first-category target programs and second-category target programs; The first type of target programs include programs with tree structures and / or hierarchical structures, and the second type of target programs include programs with parallel structures and / or non-hierarchical structures.

11. An instruction processing device, comprising: An address register group, an instruction control unit, an instruction storage unit, and an instruction processing unit; wherein the address register group includes: a plurality of address registers for storing address information of a plurality of instruction fragments of a composite program instruction to be processed currently in the instruction storage unit; The instruction control unit is used to obtain multiple instruction fragments of the composite program instruction to be processed currently according to the multiple address information stored in the multiple address registers; wherein the multiple address information stored in the multiple address registers is dynamically updated according to a pre-configured instruction update program; The instruction processing unit is used to combine and process the multiple instruction fragments to obtain the current composite program instruction to be processed; wherein the current composite program instruction to be processed is any instruction in the target program, and multiple composite program instructions in the target program reuse the same instruction fragment.

12. The device according to claim 11, wherein The instruction control unit is used to run the pre-configured instruction update program; and the instruction processing device further includes: an instruction register, which is used to dynamically store the storage address of a group of update instructions corresponding to the composite program instruction to be processed currently in the instruction update program; the instruction control unit is used to obtain and run a group of update instructions corresponding to the composite program instruction to be processed currently according to the storage address in the instruction register, and the running result of the update instructions is used to update the multiple address information stored in the multiple address registers, so that the updated multiple address information points to the multiple instruction fragments of the composite program instruction to be processed currently; In addition, the instruction processing unit further includes: an instruction assembler and an instruction operator; wherein the instruction assembler is used to combine and process the multiple instruction fragments to obtain the current composite program instruction to be processed; and the instruction operator is used to run the composite program instruction.

13. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 10.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the method according to any one of claims 1 to 10.

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