Computing device, method and equipment based on RISC-V instruction and medium

Abstract

The invention provides a computing device, method and equipment based on an RISC-V instruction and a medium. An instruction fetching unit is set to generate a first instruction address of a current period, and a first instruction of the current period is acquired according to the first instruction address; the first instruction address of the current period is compared with the jump address of the branch instruction in the branch prediction cache, and if branch prediction succeeds, the jump address of the branch instruction serves as the first instruction address of the next period; the decoding unit decodes the first instruction of the current period to obtain a decoded second instruction; the address generation unit generates a data access address of the current period according to the second instruction; the execution unit performs calculation according to the data in the data access address to obtain an execution result of the current period; and the write-back unit writes back the execution result of the current period, the current period is ended, and branch prediction is performed by using the branch prediction cache, so that high-hit-rate branch prediction is realized, delay is reduced, the performance is high, and the cost is low.

Description

Technical Field

[0001] The present invention relates to the field of image processing technology, and in particular to a computing device, method, equipment and medium based on RISC-V instructions. Background Art

[0002] A digital signal processor (DSP) is a microprocessor chip designed for digital signal processing algorithms and is widely used in audio, telecommunications, image processing, radar, sonar, and speech recognition. Its architecture is optimized for digital signal processing operations and is manufactured using MOS integrated circuit technology. It has the characteristics of high energy efficiency and is suitable for real-time processing of continuous signals. DSP can measure, filter or compress continuous analog signals and use a dedicated storage architecture to perform a large number of fast and repetitive mathematical operations. In commercial communication satellites, the application of DSP can significantly reduce weight, power consumption, complexity, manufacturing cost and reliability, and improve operational flexibility. For example, 25% of the chips in the SES-12 and SES-14 satellites manufactured by Airbus are DSPs. However, there are some problems with the digital signal processors currently on the market, such as high cost, difficult programming, and high latency.

[0003] Therefore, there is an urgent need for a computing device, method, equipment and medium based on RISC-V instructions to improve the above problems. Summary of the invention

[0004] The object of the present invention is to provide a computing device, method, apparatus and medium based on RISC-V instructions, which can reduce delay, have high performance and low cost.

[0005] In a first aspect, the present invention provides a computing device based on RISC-V instructions, comprising:

[0006] an instruction fetch unit, configured to generate a first instruction address of a current cycle, and obtain the first instruction of the current cycle according to the first instruction address; and compare the first instruction address of the current cycle with a jump address of a branch instruction in a branch prediction cache, and if the branch prediction is successful, use the jump address of the branch instruction as the first instruction address of the next cycle;

[0007] A decoding unit, used for decoding a first instruction of a current cycle to obtain a decoded second instruction;

[0008] An address generating unit, configured to generate a data access memory address of a current cycle according to the second instruction;

[0009] An execution unit, used to perform calculations according to the data in the data access memory address to obtain an execution result of the current cycle;

[0010] The write-back unit is used to write back the execution result of the current cycle and end the current cycle.

[0011] The beneficial effects of the present invention are as follows: an instruction fetch unit is set to generate the first instruction address of the current cycle, and the first instruction of the current cycle is obtained according to the first instruction address; and the first instruction address of the current cycle is compared with the jump address of the branch instruction in the branch prediction cache. If the branch prediction is successful, the jump address of the branch instruction is used as the first instruction address of the next cycle; a decoding unit is used to decode the first instruction of the current cycle to obtain the decoded second instruction; an address generation unit is used to generate the data access memory address of the current cycle according to the second instruction; an execution unit is used to calculate according to the data in the data access memory address to obtain the execution result of the current cycle; a write-back unit is used to write back the execution result of the current cycle, end the current cycle, and use the jump address of the branch instruction in the branch prediction cache to perform branch prediction on the first instruction address of the current cycle, thereby achieving a branch prediction with a high hit rate, reducing the performance loss per megahertz caused by pipeline flushing, and having low latency, high performance and low cost.

[0012] Optionally, sources of the first instruction address include: the first instruction address of the next cycle, the jump address of the branch instruction when the branch prediction of the current cycle is successful, and the pipeline flush address generated when the current cycle is written back after the branch prediction fails.

[0013] Optionally, generating a first instruction address of a current cycle, and acquiring a first instruction of the current cycle according to the first instruction address includes:

[0014] A comparison is performed between the first instruction address and the instruction address in the instruction tightly coupled memory. If a hit is found, an instruction fetch request is sent to the instruction tightly coupled memory. Otherwise, a comparison is performed between the first instruction address and the instruction address in the local cache. If a hit is found, an instruction fetch request is sent to the local cache. Otherwise, an instruction fetch request is sent to the external memory according to the first instruction address, until the first instruction corresponding to the first instruction address is obtained.

[0015] Optionally, decoding the first instruction of the current cycle to obtain the decoded second instruction includes:

[0016] Partially decode the first instruction of the current cycle to obtain the instruction type;

[0017] Decoding an undecoded portion of the first instruction to obtain a decoded second instruction;

[0018] Wherein, the instruction types include branch instructions, operation instructions, memory access instructions and system instructions;

[0019] The second instruction includes a specific subdivision instruction operation, a source register, and a target register.

[0020] Optionally, generating a data memory access address of a current cycle according to the second instruction includes:

[0021] Accessing the general register file and the future register file of the access address according to the second instruction to obtain the source operand required for calculating the data access address;

[0022] The data access memory address of the current cycle is calculated and generated according to the source operand; and the data access memory address of the next cycle is generated according to the set offset.

[0023] Optionally, performing calculation according to the data in the data access memory address to obtain the execution result of the current cycle includes:

[0024] Initiate memory access according to the data memory access address, compare whether the data memory access address hits the first-level tightly coupled on-chip storage of the instruction tightly coupled memory, and if so, obtain data from the first-level tightly coupled on-chip storage in the next cycle; otherwise, compare whether the data memory access address hits the first-level data cache of the local cache, and if so, obtain data from the first-level data cache in the next cycle; otherwise, keep the second instruction corresponding to the data memory access address until the next cycle until the corresponding data is obtained; and update the future register file for subsequent instruction access;

[0025] Selecting the data hit in the first-level data cache returned in the first-level tightly coupled on-chip storage / local cache;

[0026] Initiate a read source operand request for a general register;

[0027] Align / sign-extend the data returned from memory access;

[0028] Select the data required for the operation in the general register readback and bypass transfer;

[0029] Calculate based on the acquired data to get the execution result of the current cycle.

[0030] Optionally, write back the execution result of the current cycle. Ending the current cycle includes:

[0031] Write the execution result of the current cycle back to the register;

[0032] Update the branch prediction cache according to the final branch instruction calculation result;

[0033] Write out the data memory access address of the current cycle.

[0034] In a second aspect, the present invention provides a computing method based on RISC-V instructions, based on the computing device described in the first aspect, comprising the steps of:

[0035] Generate a first instruction address of the current cycle, and obtain the first instruction of the current cycle according to the first instruction address; and compare the first instruction address of the current cycle with the jump address of the branch instruction in the branch prediction cache, and if the branch prediction is successful, use the jump address of the branch instruction as the first instruction address of the next cycle;

[0036] Decoding the first instruction of the current cycle to obtain a decoded second instruction;

[0037] According to the second instruction, generating a data access memory address of the current cycle;

[0038] Calculating according to the data in the data access memory address to obtain the execution result of the current cycle;

[0039] Write back the execution result of the current cycle and end the current cycle.

[0040] The beneficial effects of the method of the present invention are as follows: by generating the first instruction address of the current cycle, and obtaining the first instruction of the current cycle according to the first instruction address; and comparing the first instruction address of the current cycle with the jump address of the branch instruction in the branch prediction cache, if the branch prediction is successful, the jump address of the branch instruction is used as the first instruction address of the next cycle; decoding the first instruction of the current cycle to obtain the decoded second instruction; generating the data access memory address of the current cycle according to the second instruction; calculating according to the data in the data access memory address to obtain the execution result of the current cycle; writing back the execution result of the current cycle, ending the current cycle, and using the jump address of the branch instruction in the branch prediction cache to perform branch prediction on the first instruction address of the current cycle, thereby achieving branch prediction with a high hit rate, reducing the performance loss per megahertz caused by pipeline flushing, and having low latency, high performance and low cost.

[0041] In a third aspect, the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a program that can be run on the processor, and when the program is executed by the processor, the electronic device implements a method for executing any possible design of any of the above aspects.

[0042] In a fourth aspect, the present invention provides a readable storage medium, wherein the readable storage medium stores a program, and when the program is executed, it implements any possible design method of any of the above aspects.

[0043] For the beneficial effects of the third and fourth aspects, reference may be made to the description of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the structure of a computing device based on RISC-V instructions provided by the present invention;

[0045] Figure 2 A schematic diagram of a flow chart of a computing method based on RISC-V instructions provided by the present invention;

[0046] Figure 3 A schematic diagram of the principle of a computing device based on RISC-V instructions provided by the present invention;

[0047] Figure 4 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0049] like Figure 1 As shown, the present invention provides a computing device based on RISC-V instructions, comprising:

[0050] The instruction fetch unit is used to generate the first instruction address of the current cycle and obtain the first instruction of the current cycle according to the first instruction address; and compare the first instruction address of the current cycle with the jump address of the branch instruction in the branch prediction cache. If the branch prediction is successful, the jump address of the branch instruction is used as the first instruction address of the next cycle.

[0051] In some embodiments, sources of the first instruction address include: the first instruction address of the next cycle, the jump address of the branch instruction when the branch prediction of the current cycle is successful, and the pipeline flush address generated when the current cycle is written back after the branch prediction fails.

[0052] In other embodiments, generating the first instruction address of the current cycle, and obtaining the first instruction of the current cycle according to the first instruction address includes: comparing the first instruction address with the instruction address in the instruction tightly coupled memory, and if there is a hit, sending an instruction fetch request to the instruction tightly coupled memory; otherwise, comparing the first instruction address with the instruction address in the local cache, and if there is a hit, sending an instruction fetch request to the local cache; otherwise, sending an instruction fetch request to the external memory according to the first instruction address; until the first instruction corresponding to the first instruction address is obtained.

[0053] The decoding unit is used to decode the first instruction of the current cycle to obtain a decoded second instruction.

[0054] In some embodiments, decoding the first instruction of the current cycle to obtain the decoded second instruction includes: partially decoding the first instruction of the current cycle to obtain the instruction type; decoding the undecoded portion of the first instruction to obtain the decoded second instruction; wherein the instruction type includes branch instructions, operation instructions, memory access instructions and system instructions; the second instruction includes specific subdivision instruction operations, source registers and target registers.

[0055] The address generation unit is used to generate a data memory access address of the current cycle according to the second instruction.

[0056] In some embodiments, according to the second instruction, generating the data access memory address of the current cycle includes: accessing the general register file and the future register file of the access address according to the second instruction to obtain the source operand required to calculate the data access memory address; calculating and generating the data access memory address of the current cycle according to the source operand; and generating the data access memory address of the next cycle according to the set offset.

[0057] The execution unit is used to perform calculations according to the data in the data access memory address to obtain the execution result of the current cycle.

[0058] Calculation is performed based on the data in the data access memory address to obtain the execution result of the current cycle, including: initiating memory access based on the data access memory address, comparing whether the data access memory address hits the first-level tightly coupled on-chip storage of the instruction tightly coupled memory, and if so, obtaining data from the first-level tightly coupled on-chip storage in the next cycle; otherwise, comparing whether the data access memory address hits the first-level data cache of the local cache, and if so, obtaining data from the first-level data cache in the next cycle; otherwise, keeping the second instruction corresponding to the data access memory address until the next cycle until the corresponding data is obtained; and updating the future register file for subsequent instruction access; selecting and returning the data that hits in the first-level tightly coupled on-chip storage / the first-level data cache of the local cache; initiating a read source operand request for a general register; aligning / sign-extending the memory access return data; selecting the data required for the preparation operation in the general register read back and bypass transfer; and calculating based on the obtained data to obtain the execution result of the current cycle. It is worth noting that the data required for the operation comes from the processor's internal register read back and bypass transmission; the bypass transmission can come from the bypass of the calculation results of other operation units, or from the bypass of the memory access return data. The memory access return data can be the data returned by the cache hit, or the data obtained from the next level of storage if the cache does not hit.

[0059] The write-back unit is used to write back the execution result of the current cycle and end the current cycle.

[0060] In some embodiments, writing back the execution result of the current cycle and ending the current cycle include: writing the execution result of the current cycle back to the register; updating the branch prediction cache according to the final branch instruction calculation result; writing out the data access address of the current cycle. It is worth noting that the branch instruction is an instruction that can "jump" to other addresses to execute in the next program, or it can not "jump" and continue to execute the next instruction in sequence. Whether to jump and where to jump needs to be calculated based on the source operand of the instruction. Branch prediction refers to predicting whether to jump and what address to jump to before the above calculation results come out (if the prediction is correct, the processor performance can be improved). The final branch instruction calculation result, that is, whether to jump and where to jump, this information can help improve the accuracy of the prediction when this instruction is executed in the future.

[0061] like Figure 2 As shown, the present invention also provides a calculation method based on RISC-V instructions, which is used in the above-mentioned calculation device, comprising the steps of:

[0062] S201, generate the first instruction address of the current cycle, and obtain the first instruction of the current cycle according to the first instruction address; and compare the first instruction address of the current cycle with the jump address of the branch instruction in the branch prediction cache. If the branch prediction is successful, the jump address of the branch instruction is used as the first instruction address of the next cycle.

[0063] S202, decoding the first instruction of the current cycle to obtain a decoded second instruction.

[0064] S203: Generate a data memory access address for the current cycle according to the second instruction.

[0065] S204, performing calculation according to the data in the data access memory address to obtain the execution result of the current cycle.

[0066] S205, write back the execution result of the current cycle, and end the current cycle.

[0067] For ease of understanding, this embodiment further describes the specific implementation method of the above method in combination with a specific application scenario system, such as Figure 3 As shown, this embodiment uses a digital signal processor as a computing device, and its functional characteristics and working principle are as follows:

[0068] 11-stage pipeline, targeting 800MHz / 1.2GHz at nominal on 40nm / 28nm process nodes.

[0069] The pipeline architecture of Pipeline Stages is as follows:

[0070] The IF instruction fetch stage is divided into 2 pipeline cycles: IF1 and IF2.

[0071] The ID instruction decoding stage is divided into 2 pipeline cycles: ID1 and ID2.

[0072] The AG address generation stage is divided into two pipeline cycles: AG1 and AG2.

[0073] The EX execution phase consists of four pipeline cycles: EX1, EX2, EX3, and EX4. Memory access also occurs in these four pipeline cycles.

[0074] WB Write Back, the last stage to write the result back to the architectural register file.

[0075] IF1

[0076] PC value (first instruction address) is generated

[0077] Generated by the Fetch PC Gen module, the PC value of the current cycle comes from:

[0078] 1) The address of the first instruction in the next cycle, that is, the current instruction + 2 (16-bit instruction) or 4 (32-bit instruction);

[0079] 2) The jump address of the branch instruction when the branch prediction (BTB) of the current cycle succeeds, that is, the result read out by the BTB hit in the previous cycle;

[0080] 3) After the BTB branch prediction fails, the pipeline flush address generated when the current cycle is written back.

[0081] Instruction fetch

[0082] After the 32-bit PC value is generated in the IF1 stage, it is compared with the address range of ITCM (instruction tightly coupled memory) based on the PC value. If it hits, an instruction fetch request is sent to the first-level tightly coupled on-chip storage of ITCM, and the corresponding first instruction is received in the IF2 cycle. If ITCM is not hit, the first instruction address is compared with the instruction address in ICACHE (local cache). If it hits, an instruction request is initiated to the first-level data cache of ICACHE, and the corresponding first instruction is received in the IF2 cycle. If neither ITCM / ICACHE hits, an instruction fetch request is initiated to the processor's external memory, and the IF1 and IF2 stages will pause until the instruction is returned from the Fill Buffer after the corresponding first instruction is received. The instruction fetch width of the above operations is 128 bits, and multiple instructions can be fetched at a time (the instruction width is 16 bits or 32 bits).

[0083] BTB (branch prediction cache) query

[0084] BTB stands for Branch Target Buffer, which has a total of 64 storage units. Each storage unit includes the PC value of the branch instruction and the corresponding jump address. When indexing, the PC values ​​of the 64 storage units are queried for indexing. If the PC value of the current cycle and the PC value of the branch instruction are successfully compared, the jump address of the corresponding storage unit will become the new PC value in the next cycle (that is, the first instruction address of the next cycle), achieving the effect of 0-delay branch prediction. The initial value and update value of each storage unit of BTB are written in the WB cycle, so the branch prediction of BTB requires a warm-up process. Only branch instructions that are not run for the first time can be predicted by BTB.

[0085] IF2

[0086] As described in the IF1 cycle, the IF2 cycle returns the first instruction that the ITCM / ICACHE value hits, or the first instruction returned by the external storage.

[0087] ID1

[0088] Instruction alignment and strobing

[0089] The 128-bit instruction data returned by IF2 contains multiple instructions. These instruction data will enter the buffer queue of size 128*4 in the align module in ID1. As long as the buffer queue is not empty in the ID1 cycle, the next 16-bit or 32-bit instruction will be selected from the 128-bit storage unit at the top of the queue.

[0090] Instruction pre-decoding

[0091] For processor performance (timing) considerations, instruction decoding is split into two cycles, ID1 / ID2, to increase processor frequency. In the ID1 cycle, instructions are partially decoded, and the instruction types are decoded: branch instructions, operation instructions, memory access instructions, and system instructions.

[0092] ID2

[0093] Instruction decoding

[0094] Complete the decoding of the unfinished instruction of ID1 and obtain the decoded second instruction. The second instruction includes the specific subdivision instruction operation, source register, target register and immediate value (if any). This information will flow along the pipeline until the cycle it needs to be used.

[0095] AG1

[0096] In the AG1 cycle, the general register file (Reg File) and the future register file (FutureFile) of the memory access address are accessed to obtain the source operands required for calculating the data memory access address, and prepare data for AG2 to calculate the data memory access address.

[0097] AG2

[0098] The AG2 stage uses the source operand read by AG1 to calculate the data access address (addition / shift operation). In addition, to enhance performance, the post-address modification function (i.e., after generating a data access address, immediately add an offset to generate the next data access address. This operation can improve performance during continuous data access) is also executed at this stage.

[0099] EX1

[0100] Accessing Data Stores

[0101] In the EX1 cycle, the data memory access address calculated by AG2 is used to initiate a memory access. First, the data memory access address is compared to see if it hits the DTCM first-level tightly coupled on-chip storage. If it hits, the memory access data can be obtained in the next cycle. If it does not hit DTCM, the data memory access address will be compared to see if it hits the DCACHE first-level data cache. If it hits, the return data will be received in the next cycle. If neither DTCM nor DCACHE hits, the data needs to be obtained from the next level of data storage, but the first instruction of the current cycle will continue to flow to the next cycle and will not be blocked in EX1 waiting for data to return. If the data has not returned until EX4, the pipeline will be blocked. If the processor has a high-speed second-level cache with a clock rate that is usually 1 / 2 of the processor, there will be no blocking if the second-level cache is hit.

[0102] Future register file writeback

[0103] This cycle also completes the update of the future register file so that subsequent instructions can obtain the latest memory access address source register.

[0104] EX2

[0105] The strobe returns the hit data in the first level tightly coupled on-chip storage of DTCM / DCACHE.

[0106] The arithmetic unit (ALU / MUL) initiates a read source operand request to the general register (Reg File).

[0107] EX3

[0108] The memory access return data is aligned / sign extended in the EX3 stage. In order to speed up the performance from load to use, the EX3 stage implements the memory access return data to bypass the transfer path directly to the execution unit.

[0109] Select the data required for the operation in the general register readback and bypass transfer. Implement multiple bypass transfer paths to improve performance:

[0110] Pass the loaded return data to MUL in the EX3 stage;

[0111] Pass the loaded return data into the ALU, in the EX4 stage;

[0112] MUL result goes to ALU, in EX4 stage;

[0113] ALU result goes to MUL, in the EX3 stage;

[0114] In the EX3 stage, the multiplication / division unit (MUL) operations begin calculations and become available in the EX4 stage.

[0115] EX4

[0116] ALU operations complete all calculations in the EX4 stage.

[0117] Get the calculation result of MUL.

[0118] WB

[0119] The instruction is submitted and the final result is written back to the register;

[0120] Update BTB based on the final branch instruction calculation result information;

[0121] Write data access and write instructions out of the processor from the store buffer;

[0122] Scalar Register File

[0123] The current register file is divided into two parts: 1) 32 32-bit registers defined in the RISC-V specification, 2) extended independent registers, such as loop registers. Since the present invention uses the RISC-V general register file as the basic data address (different from the traditional DSP processor which usually uses an independent pointer register file), the register access port and its timing impact should be carefully considered.

[0124] The register file can be speculatively updated (currently mainly by post-increment load / store instructions). If flushed from the WB stage, those entries that were speculatively updated are restored.

[0125] Address Register Future File

[0126] In order to improve performance, the present invention uses a future file of 8 entries to access load / store addresses in advance. As shown above, each entry of the future file includes a 1-bit valid bit, a 5-bit register index and a 32-bit register content. Access is based on index matching.

[0127] The future file is read in the AG1 stage. If there is a hit and there is no forwarding in the AG2 stage, then the content read out will be selected to calculate the data address. In the AG2 stage, if there is a post-increment operation on the address, then the updated value will be updated in the future file. If there is no valid entry for that register, a new entry will be allocated. The valid entry will be released in two cases. The first case is when the updated register is written back to the architectural register file in the WB stage and there are no new updates to this register, then the register will be released. The second is when the pipeline from the WB stage is flushed, all entries in the future file will be released.

[0128] Since there are only two load / store pipelines and 4 stages (EX1-4) before the WB stage, the 8 entries will never overflow, so no culling is required for future files.

[0129] BTB cache jump target address cache

[0130] For the unconditional jump instructions commonly used in digital signal processing, the present invention designs a 0-delay BTB to improve performance. Specifically, the BTB will query the BTB in the IF stage where the PC address is generated. If a hit is found, the next PC value will be directly rewritten in the IF1 cycle, thereby achieving a 0-delay prediction effect. If the address prediction is wrong, it will be corrected and flushed in the WB stage. In the actual operation process, the jump address is basically a fixed value in most cases, so the probability of prediction error is extremely low.

[0131] This embodiment provides a high-performance, low-cost, and software-friendly digital signal processor design by using a deep pipeline (11 stages) but limited-issue out-of-order execution architecture designed based on the RISC-V instruction set architecture. By introducing a zero-latency branch prediction cache and a loop buffer, a high-hit-rate branch prediction capability is provided for digital signal processing applications, effectively reducing the "per-MHz" performance loss caused by pipeline flushing. By adding a future register file mechanism, blocking due to data dependencies is reduced, greatly improving the throughput of the pipeline without consuming too many hardware resources (compared to the out-of-order execution cache mechanism of general high-performance processors.

[0132] In some other embodiments of the present invention, an electronic device 400 is disclosed. Figure 4 As shown, it may include: one or more processors 401; memory 402; display 403; one or more applications (not shown); and one or more computer programs 404. The above-mentioned components may be connected via one or more communication buses 405. The one or more computer programs 404 are stored in the above-mentioned memory 402 and configured to be executed by the one or more processors 401. The one or more computer programs 404 include instructions, which can be used to execute the following instructions: Figure 2 The various steps in the corresponding embodiments.

[0133] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A computing device based on RISC-V instructions, characterized in that: include: An instruction fetch unit, configured to generate a first instruction address of a current cycle, and obtain a first instruction of the current cycle according to the first instruction address; and comparing the first instruction address of the current cycle with the jump address of the branch instruction in the branch prediction cache, and if the branch prediction is successful, using the jump address of the branch instruction as the first instruction address of the next cycle; A decoding unit, used for decoding a first instruction of a current cycle to obtain a decoded second instruction; An address generating unit, configured to generate a data access memory address of a current cycle according to the second instruction; An execution unit, used to perform calculations according to the data in the data access memory address to obtain an execution result of the current cycle; The write-back unit is used to write back the execution result of the current cycle and end the current cycle.

2. The computing device according to claim 1, wherein: Sources of the first instruction address include: the first instruction address of the next cycle, the jump address of the branch instruction when the branch prediction of the current cycle is successful, and the pipeline flush address generated when the current cycle is written back after the branch prediction fails.

3. The computing device according to claim 1, wherein: Generating a first instruction address of a current cycle, and acquiring a first instruction of the current cycle according to the first instruction address includes: A comparison is performed between the first instruction address and the instruction address in the instruction tightly coupled memory. If a hit is found, an instruction fetch request is sent to the instruction tightly coupled memory. Otherwise, a comparison is performed between the first instruction address and the instruction address in the local cache. If a hit is found, an instruction fetch request is sent to the local cache. Otherwise, an instruction fetch request is sent to the external memory according to the first instruction address, until the first instruction corresponding to the first instruction address is obtained.

4. The computing device according to claim 1, wherein: The first instruction of the current cycle is decoded to obtain the decoded second instruction including: Partially decode the first instruction of the current cycle to obtain the instruction type; Decoding an undecoded portion of the first instruction to obtain a decoded second instruction; Wherein, the instruction types include branch instructions, operation instructions, memory access instructions and system instructions; The second instruction includes a specific subdivision instruction operation, a source register, and a target register.

5. The computing device according to claim 1, wherein: According to the second instruction, generating the data access address of the current cycle includes: Access the general register file and the future register file of the access address according to the second instruction to obtain the source operand required for calculating the data access address; The data access memory address of the current cycle is calculated and generated according to the source operand; and the data access memory address of the next cycle is generated according to the set offset.

6. The computing device according to claim 5, characterized in that: Calculating according to the data in the data access memory address to obtain the execution result of the current cycle includes: Initiate memory access according to the data memory access address, compare whether the data memory access address hits the first-level tightly coupled on-chip storage of the instruction tightly coupled memory, and if so, obtain data from the first-level tightly coupled on-chip storage in the next cycle; otherwise, compare whether the data memory access address hits the first-level data cache of the local cache, and if so, obtain data from the first-level data cache in the next cycle; otherwise, keep the second instruction corresponding to the data memory access address until the next cycle until the corresponding data is obtained; and update the future register file for subsequent instruction access; Strobe returns the hit data in the L1 data cache of the L1 tightly coupled on-chip storage / local cache; Initiate a read source operand request for a general register; Align / sign-extend the data returned from memory access; Select the data required for the operation in the general register readback and bypass transfer; Calculate based on the acquired data to get the execution result of the current cycle.

7. The computing device according to claim 5, characterized in that Write back the execution result of the current cycle. Ending the current cycle includes: Write the execution result of the current cycle back to the register; Update the branch prediction cache according to the final branch instruction calculation result; Write out the data memory access address of the current cycle.

8. A computing method based on RISC-V instructions, used in the computing device according to any one of claims 1 to 7, characterized in that: Includes steps: Generate a first instruction address of the current cycle, and obtain the first instruction of the current cycle according to the first instruction address; and compare the first instruction address of the current cycle with the jump address of the branch instruction in the branch prediction cache, and if the branch prediction is successful, use the jump address of the branch instruction as the first instruction address of the next cycle; Decoding the first instruction of the current cycle to obtain a decoded second instruction; According to the second instruction, generating a data access memory address of the current cycle; Calculating according to the data in the data access memory address to obtain the execution result of the current cycle; Write back the execution result of the current cycle and end the current cycle.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory stores a program that can be run on the processor, and when the program is executed by the processor, the electronic device implements the method described in claim 8.

10. A readable storage medium, wherein a program is stored in the readable storage medium, characterized in that: When the program is executed, the method described in claim 8 is implemented.

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