Chip power consumption attack detection method and system based on voltage comparison, and chip

Abstract

The application provides a chip power consumption attack detection method and system based on voltage comparison, and a chip. The method comprises the following steps: deploying an analog voltage comparator between power grid nodes of an integrated circuit, and using the analog voltage comparator to compare voltages between the power grid nodes in real time to detect voltage changes caused by power consumption analysis attacks; extracting features of the power grid nodes based on voltage comparison results, and training the extracted features using a linear support vector machine model to obtain a trained machine learning model; and finally embedding the trained machine learning model into the integrated circuit for power consumption analysis attack detection. The application detects voltage differences between adjacent power grid nodes through the analog voltage comparator, and compensates for the influence of voltage noise through multiple voltage comparisons; the linear support vector machine model is selected as the power consumption analysis attack detection model, which can detect power consumption analysis attacks in real time and ensure the security of the hardware system.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit security technology, and in particular to a chip power consumption attack detection method and system based on voltage comparison, as well as a chip. Background Art

[0002] Advances in integrated circuit design and manufacturing have significantly improved the performance of modern electronic devices, but this has also brought security challenges. Power Analysis Attack (PAA), a side-channel attack method, poses a serious threat to hardware security. PAA analyzes the power consumption of chips when performing sensitive operations (such as encryption and decryption). PAA can use this power side-channel information to extract sensitive data, allowing non-invasive access to sensitive data within the chip.

[0003] In a typical PAA, an attacker uses a malicious probe (often simulated as a resistor) connected to the chip's power pads to sense voltage and current changes on the chip. The attacker then uses the collected power side-channel information for statistical analysis to infer sensitive information. Existing countermeasures primarily focus on increasing system unpredictability or proactively detecting voltage drops caused by malicious probes.

[0004] However, the reliability of these PAA detection methods is often affected by the presence of noise in the power-side channel information. For example, when the power-side channel information is mixed with voltage noise, the detection accuracy of most PAA countermeasures decreases significantly. In many circuits, the power-side channel information acquired by sensors always contains some circuit noise, with noise levels reaching up to 20% of the supply voltage (Vdd). Therefore, a PAA detection technology with noise immunity is needed. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of this application is to provide a chip power consumption attack detection method and system based on voltage comparison and a chip to solve the technical problems existing in the prior art.

[0006] To achieve the above objectives and other related objectives, the present application provides a chip power consumption attack detection method and system based on voltage comparison, and a chip, comprising the following steps:

[0007] Deploy analog voltage comparators between power grid nodes of the integrated circuit, and use the analog voltage comparators to compare voltages between the power grid nodes in real time to detect voltage changes caused by power analysis attacks;

[0008] Extracting features of power grid nodes based on voltage comparison results;

[0009] The extracted features are trained using a linear support vector machine model to obtain a trained machine learning model;

[0010] The trained machine learning model is embedded into integrated circuits for power analysis attack detection.

[0011] Optionally, before extracting the features of the power grid nodes based on the voltage comparison results, the method further includes:

[0012] Counting the number of winning results after voltage comparison for each pair of power grid nodes in a predetermined time period; wherein each pair of power grid nodes includes adjacent power grid nodes; and

[0013] Counting the winning probability of each pair of power grid nodes after voltage comparison within a predetermined time period; and,

[0014] Counting the ratio of the number of winning times after voltage comparison between each pair of power grid nodes in a predetermined time period to the total number of comparisons;

[0015] The number of winning times after voltage comparison, the probability of winning after voltage comparison, and the ratio of the number of winning times to the total number of comparisons are used as features of the power grid node.

[0016] Optionally, the method further includes:

[0017] accumulating the voltage comparison results using an accumulator; and,

[0018] Storing the voltage comparison result in a random access memory; and

[0019] Storing linear support vector machine model parameters using a read-only memory; and,

[0020] The voltage comparison results are classified using a linear classifier according to the linear support vector machine model parameters.

[0021] Optionally, the linear classifier is obtained by offline training using the voltage comparison result as training data.

[0022] The present application also provides a chip power consumption attack detection system based on voltage comparison, the system comprising:

[0023] a voltage comparison unit, configured to deploy analog voltage comparators between power grid nodes of the integrated circuit and use the analog voltage comparators to perform real-time comparisons of voltages between power grid nodes to detect voltage changes caused by power analysis attacks;

[0024] a feature extraction unit, configured to extract features of power grid nodes based on voltage comparison results;

[0025] A machine learning unit, used to train the extracted features using a linear support vector machine model to obtain a trained machine learning model;

[0026] The attack detection unit is used to embed the trained machine learning model into the integrated circuit to perform power consumption analysis attack detection.

[0027] Optionally, before extracting the features of the power grid node according to the voltage comparison result, the feature extraction unit further includes:

[0028] Counting the number of winning results after voltage comparison for each pair of power grid nodes in a predetermined time period; wherein each pair of power grid nodes includes adjacent power grid nodes; and

[0029] Counting the winning probability of each pair of power grid nodes after voltage comparison within a predetermined time period; and,

[0030] Counting the ratio of the number of winning times after voltage comparison between each pair of power grid nodes in a predetermined time period to the total number of comparisons;

[0031] The number of winning times after voltage comparison, the probability of winning after voltage comparison, and the ratio of the number of winning times to the total number of comparisons are used as features of the power grid node.

[0032] Optionally, the system further includes:

[0033] An accumulator, used for accumulating voltage comparison results;

[0034] A random access memory, used for storing voltage comparison results;

[0035] A read-only memory, used for storing linear support vector machine model parameters;

[0036] A linear classifier is used to classify the voltage comparison results based on the linear support vector machine model parameters.

[0037] Optionally, the linear classifier is obtained by offline training using the voltage comparison result as training data.

[0038] The present application also provides a chip, characterized in that the chip is applied to the chip power consumption attack detection method based on voltage comparison as described in any one of the above, or the chip is applied to the chip power consumption attack detection system based on voltage comparison as described in any one of the above.

[0039] Optionally, the chip is configured with an integrated circuit.

[0040] As described above, the present application provides a method and system for detecting chip power consumption attacks based on voltage comparison, as well as a chip. These methods have the following beneficial effects: Analog voltage comparators are deployed between power grid nodes of an integrated circuit, and the voltages between these nodes are compared in real time using the analog voltage comparators to detect voltage changes caused by power analysis attacks. Features of the power grid nodes are then extracted based on the voltage comparison results, and the extracted features are trained using a linear support vector machine model to obtain a trained machine learning model. Finally, the trained machine learning model is embedded in the integrated circuit for power analysis attack detection. As can be seen, the present application uses analog voltage comparators to detect voltage differences between adjacent power grid nodes and compensates for the effects of voltage noise through multiple voltage comparisons. A machine learning method is then used to analyze the voltage comparison results and select a linear support vector machine model as the power analysis attack detection model. This method can detect power analysis attacks in real time, ensuring the security of the hardware system. Furthermore, the linear support vector machine model in the present application can be embedded in a nanoscale CMOS process. Compared to existing power analysis attack detection technologies based on voltage sensors and analog-to-digital converters, the present application can reduce circuit area and power consumption. Therefore, the present application can achieve high detection accuracy even in the case of large voltage noise, thereby effectively responding to the threat of power consumption analysis attacks to hardware security. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a flow chart of a chip power consumption attack detection method based on voltage comparison provided in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of a training and generation linear support vector machine model provided in one embodiment of the present application;

[0043] Figure 3 A schematic diagram of the collection and labeling of a training data set provided in one embodiment of the present application;

[0044] Figure 4 A schematic diagram of deploying a linear support vector machine model provided in one embodiment of the present application;

[0045] Figure 5 This is a hardware structure diagram of a chip power consumption attack detection system based on voltage comparison provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0047] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0048] In actual chips, the external voltage must be distributed as evenly as possible across the various internal load circuits. To achieve this, a power supply voltage grid has emerged. This grid connects to a high voltage at specific nodes and then transmits this voltage to the various load circuits via wires. In this way, the power profiles of each load circuit are coupled to the voltage profiles on the power supply grid. This means that by monitoring the voltage changes at the externally exposed nodes in the power supply voltage grid, sensitive information can be further inferred. Monitoring these externally exposed nodes often involves attaching a malicious probe circuit to them, which can be simply simulated as a resistor. The above process is a typical PAA model.

[0049] In order to deal with the impact of voltage noise on PAA detection accuracy, Figure 1 A schematic flow chart of a chip power consumption attack detection method based on voltage comparison is shown. Specifically, in an exemplary embodiment, as Figure 1 As shown, this embodiment provides a chip power consumption attack detection method based on voltage comparison, which includes the following steps:

[0050] S110, deploy analog voltage comparators between the power grid nodes (Power Grid, referred to as PG) of the integrated circuit, and use the analog voltage comparators to compare the voltages between the power grid nodes in real time to detect voltage changes caused by power analysis attacks. As an example, in this embodiment or other embodiments, multiple voltage monitoring points can be first arranged inside the integrated circuit to monitor the voltage changes of the integrated circuit in real time when performing specific operations; these monitoring points are generally directly connected to the power supply of the integrated circuit to ensure that the captured voltage fluctuations are the largest. Then, analog voltage comparators are deployed between the power grid nodes of the integrated circuit, and the analog voltage comparators are used to compare the voltage values ​​of different monitoring points at the same time point to obtain voltage differences.

[0051] S120: Extracting features of the power grid node based on the voltage comparison results. For example, in this embodiment or other embodiments, the features can be extracted by counting the number of winning comparisons for each pair of power grid nodes within a predetermined time period, wherein each pair of power grid nodes comprises adjacent power grid nodes; counting the winning probability for each pair of power grid nodes within the predetermined time period; and counting the ratio of the number of winning comparisons for each pair of power grid nodes within the predetermined time period to the total number of comparisons; and finally, the number of winning comparisons, the winning probability, and the ratio of the number of winning comparisons to the total number of comparisons are used as features of the power grid node.

[0052] S130, using a linear support vector machine model to train the extracted features to obtain a trained machine learning model. As an example, in this embodiment or other embodiments, the process of using a linear support vector machine model to train the extracted features to obtain a trained machine learning model is as follows: Figure 2 Specifically, we can first establish the attack detection model architecture with a linear support vector machine model, then collect data from safe and compromised power grid nodes, determine the detection window length, and label the dataset formed by the features of the power grid nodes. The collection and labeling process of the training dataset is as follows: Figure 3 As shown in the figure, the dataset is split into training, validation, and test sets. Offline model training is then performed, and the trained machine learning model is deployed on the chip for performance evaluation. Finally, the adjacent node comparison results are saved and evaluated using the model. This demonstrates that this embodiment can utilize the collected feature dataset to train a lightweight linear support vector machine model for PAA classification. This model can accurately identify PG nodes affected by PAA with high detection accuracy.

[0053] S140, embedding the trained machine learning model into the integrated circuit to perform power analysis attack detection. As an example, in this embodiment or other embodiments, the process of embedding the trained machine learning model into the integrated circuit to perform power analysis attack detection is as follows: Figure 4 As shown. Figure 4 As shown, this embodiment can also utilize an accumulator to accumulate voltage comparison results, utilize random access memory to store voltage comparison results, utilize read-only memory to store linear support vector machine model parameters, and utilize a linear classifier to classify voltage comparison results based on the linear support vector machine model parameters. The linear classifier is trained offline using the voltage comparison results as training data. This demonstrates that this embodiment designs a real-time PAA detection solution based on a trained linear SVM model. This solution includes offline linear classifier training and on-chip PAA classifier design. The effectiveness of power analysis attack detection was verified by simulating the IBM Power Grid benchmark, and detection accuracy and resource consumption were evaluated.

[0054] According to the above description, in one specific embodiment, the process of voltage difference assessment can include detecting the voltage difference between adjacent PG nodes using a voltage comparator and performing multiple voltage comparisons to eliminate noise errors. This embodiment utilizes the Gaussian distribution characteristics of noise to calculate the probability of voltage comparison results, thereby more accurately assessing voltage differences. For example, there is a pair of power supply voltage grid nodes, node i and node j. At a certain moment, the noise-free voltage values ​​of these two nodes are Vi and Vj, respectively. If one node (for example, node i) is hacked and a malicious probe causes a voltage drop at that node, the voltage value Vj of the other, safe node j will be significantly greater than Vi. By continuously accumulating the comparison results, the voltage drop caused by the malicious probe will eventually become sufficiently significant. However, due to the complexity of the power supply voltage grid nodes, Vi may still be lower than Vj under normal circumstances. In this case, no matter how the comparison is performed, it is difficult to determine whether a voltage drop has occurred at node i. The introduction of noise can provide new information. Since circuit noise can be simply modeled as a Gaussian distribution, the probability that the voltage of the hacked node i is higher than the voltage of the safe node j is much lower. As an example, there are currently three nodes with voltage values ​​of 1v, 1.1v, and 2v respectively. In the absence of noise, the first node will always be smaller than the next two nodes. But when noise that obeys a Gaussian distribution is introduced, the situation changes. The possibility that the second node is larger than the first node should be significantly smaller than the possibility that the third node is larger than the first node. This brings more information to the subsequent machine learning stage while also making the distribution of data more linear. It can be seen that this embodiment improves the detection accuracy of PAA by evaluating the voltage drop of certain nodes caused by PAA and using a series of voltage comparisons to eliminate the errors caused by noise. Specifically, this embodiment uses an analog voltage comparator to detect the voltage difference between adjacent PG nodes, and performs multiple voltage comparisons to accurately identify the voltage changes caused by PAA.

[0055] According to the above description, in another specific embodiment, the specific process for extracting power grid node features can be: preparing features for each PG node, including voltage comparison results of its four neighboring nodes: top, bottom, left, and right. These features are used as input to a machine learning model to identify "victim nodes" affected by PAA. For boundary nodes, this embodiment uses a symmetric padding method to ensure that all nodes have four features. Symmetric padding ensures the integrity of the four-dimensional features by copying the data of the neighbors symmetrical to the missing neighbors to the missing positions. For example, if the first node only has bottom and right neighbors but no top and left neighbors, symmetric padding will copy the data of the node's bottom neighbor to the missing top neighbor position and the data of the right neighbor to the missing left neighbor position. Specific features are generated by accumulating the results of each comparison. For example, for node i, the feature is generated after a fixed number of comparisons. Specifically, if node i is smaller than its neighboring nodes, the accumulated result is subtracted by one. Otherwise, the accumulated result is greater than one. This continues until the number of comparisons reaches the set number, at which point the accumulated value is extracted. This step can be considered a probabilistic convergence method.

[0056] According to the above records, in an exemplary embodiment of the present application, the embodiment provides a chip power consumption attack detection method based on voltage comparison, comprising the following steps:

[0057] Step 1: Voltage monitoring and acquisition.

[0058] First, multiple voltage monitoring points are placed inside the integrated circuit to monitor voltage changes in real time when the integrated circuit performs specific operations. These monitoring points are generally directly connected to the power supply of the integrated circuit to ensure that the voltage fluctuations captured are maximized.

[0059] Step 2: Confirm the voltage comparison window length and the upper limit of the comparison times.

[0060] The ratio of the voltage comparison window length to the upper limit of the number of comparisons determines the frequency of the two voltage comparisons. The selection principle is as follows: The voltage comparison window length should be long enough to allow the voltage comparison to cover more voltage curves in time. However, an excessively long window length will result in excessive detection delays in the PAA detection system, so an appropriate window length should be selected through experimentation. Regarding the number of comparisons, while an excessively large number of comparisons will further converge the probability, it will also result in excessive consumption of storage space. For example, when the number of comparisons is 1000, the required storage space is 10 bits. As a rule of thumb, the number of comparisons should be set to 125, which means the required storage space is 7 bits.

[0061] Step 3: Voltage comparison and feature extraction.

[0062] This embodiment can use a voltage comparator to compare the monitored voltage data. Specifically, the voltage values ​​of different monitoring points at the same time point are compared to obtain voltage differences. These voltage differences are used as feature data for subsequent machine learning model analysis. For example, if the number of comparisons is set to 100 times, the comparison results will be completed and saved after 100 comparisons. When the voltage of node i is greater than that of node j, then for node i, the comparison result is plus one, and for node j, the comparison result is minus one. Of course, the relevant operations can also be interchanged, as long as the comparison results can produce sufficient differences in the size of the values. The comparison result of a pair of nodes can generate one-dimensional data for a single node in it. This embodiment adopts a four-dimensional data extraction method, that is, the voltages of the four neighboring nodes above, below, left and right of the node are compared. For edge nodes, that is, there are no four neighbors, and the missing dimensions will be filled in a mirror-symmetrical manner, such as Figure 3 Finally, depending on whether the current node has been hacked, it is labeled as safe or hacked, which facilitates the subsequent training of the machine learning algorithm.

[0063] Step 4: Machine learning model training and classification.

[0064] To improve detection accuracy and efficiency, this embodiment uses a linear kernel support vector machine (SVM) to classify feature data. First, training is performed using the extracted training set. During training, the model's parameters and structure are adjusted to accurately distinguish between attack data and normal data. After training, the machine learning model can classify new voltage difference feature data to determine whether the IC is experiencing PAA. It's worth noting that a SVM using a linear kernel function isn't the only option; any linear kernel function that can generate a decision hyperplane, such as logistic regression, can be used for binary classification.

[0065] Step 5: Real-time detection and early warning.

[0066] The trained machine learning model is embedded in the integrated circuit's monitoring system to enable real-time detection. When a potential PAA is detected, the monitoring system immediately issues an early warning signal, allowing system administrators to take appropriate defensive measures. The main components used are voltage comparators, random access memory (RAM), and read-only memory (ROM).

[0067] In summary, the present application provides a voltage comparison-based chip power analysis attack detection method. This method deploys analog voltage comparators between power grid nodes of an integrated circuit and uses them to perform real-time voltage comparisons between the power grid nodes, detecting voltage changes caused by power analysis attacks. Features of the power grid nodes are then extracted based on the voltage comparison results, and the extracted features are trained using a linear support vector machine model to obtain a trained machine learning model. Finally, the trained machine learning model is embedded in the integrated circuit for power analysis attack detection. As can be seen, this method uses analog voltage comparators to detect voltage differences between adjacent power grid nodes and compensates for the effects of voltage noise through multiple voltage comparisons. A machine learning method is then used to analyze the voltage comparison results and select a linear support vector machine model as the power analysis attack detection model. This method can detect power analysis attacks in real time, ensuring the security of the hardware system. Furthermore, the linear support vector machine model in this method can be embedded in a nanoscale CMOS process. Compared to existing power analysis attack detection technologies based on voltage sensors and analog-to-digital converters, this method can reduce circuit area and power consumption. Therefore, this method can achieve high detection accuracy even in the presence of high voltage noise, effectively addressing the threat posed by power analysis attacks to hardware security.

[0068] In another exemplary embodiment of the present application, Figure 5 As shown, this embodiment also provides a chip power consumption attack detection system based on voltage comparison, including:

[0069] The voltage comparison unit 510 is used to deploy analog voltage comparators between the power grid nodes of the integrated circuit and use the analog voltage comparators to perform real-time comparisons of the voltages between the power grid nodes to detect voltage changes caused by power analysis attacks. As an example, in this embodiment or other embodiments, multiple voltage monitoring points can be first arranged within the integrated circuit to monitor the voltage changes of the integrated circuit in real time when performing specific operations; these monitoring points are generally directly connected to the power supply of the integrated circuit to ensure that the captured voltage fluctuations are maximized. Then, analog voltage comparators are deployed between the power grid nodes of the integrated circuit and used to compare the voltage values ​​of different monitoring points at the same time to obtain voltage differences.

[0070] Feature extraction unit 520 is configured to extract features of the power grid node based on the voltage comparison results. For example, in this or other embodiments, feature extraction unit 520 may calculate the features by counting the number of winning comparisons for each pair of power grid nodes within a predetermined time period, where each pair of power grid nodes comprises adjacent power grid nodes; calculating the probability of winning comparisons for each pair of power grid nodes within the predetermined time period; and calculating the ratio of the number of winning comparisons for each pair of power grid nodes within the predetermined time period to the total number of comparisons; and finally, using the number of winning comparisons, the probability of winning comparisons, and the ratio of the number of winning comparisons to the total number of comparisons as features of the power grid node.

[0071] The machine learning unit 530 is used to train the extracted features using a linear support vector machine model to obtain a trained machine learning model. As an example, in this embodiment or other embodiments, the process of training the extracted features using a linear support vector machine model to obtain a trained machine learning model is as follows: Figure 2 Specifically, we can first establish the attack detection model architecture with a linear support vector machine model, then collect data from safe and compromised power grid nodes, determine the detection window length, and label the dataset formed by the features of the power grid nodes. The collection and labeling process of the training dataset is as follows: Figure 3 As shown in the figure, the dataset is split into training, validation, and test sets. Offline model training is then performed, and the trained machine learning model is deployed on the chip for performance evaluation. Finally, the adjacent node comparison results are saved and evaluated using the model. This demonstrates that this embodiment can utilize the collected feature dataset to train a lightweight linear support vector machine model for PAA classification. This model can accurately identify PG nodes affected by PAA with high detection accuracy.

[0072] The attack detection unit 540 is configured to embed the trained machine learning model into the integrated circuit to perform power analysis attack detection. As an example, in this embodiment or other embodiments, the process of embedding the trained machine learning model into the integrated circuit to perform power analysis attack detection is as follows: Figure 4 As shown. Figure 4As shown, this embodiment can also utilize an accumulator to accumulate voltage comparison results, utilize random access memory to store voltage comparison results, utilize read-only memory to store linear support vector machine model parameters, and utilize a linear classifier to classify voltage comparison results based on the linear support vector machine model parameters. The linear classifier is trained offline using the voltage comparison results as training data. This demonstrates that this embodiment designs a real-time PAA detection solution based on a trained linear SVM model. This solution includes offline linear classifier training and on-chip PAA classifier design. The effectiveness of power analysis attack detection was verified by simulating the IBM Power Grid benchmark, and detection accuracy and resource consumption were evaluated.

[0073] According to the above description, in one specific embodiment, the process of voltage difference assessment can include detecting the voltage difference between adjacent PG nodes using a voltage comparator and performing multiple voltage comparisons to eliminate noise errors. This embodiment utilizes the Gaussian distribution characteristics of noise to calculate the probability of voltage comparison results, thereby more accurately assessing voltage differences. For example, there is a pair of power supply voltage grid nodes, node i and node j. At a certain moment, the noise-free voltage values ​​of these two nodes are Vi and Vj, respectively. If one node (for example, node i) is hacked and a malicious probe causes a voltage drop at that node, the voltage value Vj of the other, safe node j will be significantly greater than Vi. By continuously accumulating the comparison results, the voltage drop caused by the malicious probe will eventually become sufficiently significant. However, due to the complexity of the power supply voltage grid nodes, Vi may still be lower than Vj under normal circumstances. In this case, no matter how the comparison is performed, it is difficult to determine whether a voltage drop has occurred at node i. The introduction of noise can provide new information. Since circuit noise can be simply modeled as a Gaussian distribution, the probability that the voltage of the hacked node i is higher than the voltage of the safe node j is much lower. As an example, there are currently three nodes with voltage values ​​of 1v, 1.1v, and 2v respectively. In the absence of noise, the first node will always be smaller than the next two nodes. But when noise that obeys a Gaussian distribution is introduced, the situation changes. The possibility that the second node is larger than the first node should be significantly smaller than the possibility that the third node is larger than the first node. This brings more information to the subsequent machine learning stage while also making the distribution of data more linear. It can be seen that this embodiment improves the detection accuracy of PAA by evaluating the voltage drop of certain nodes caused by PAA and using a series of voltage comparisons to eliminate the errors caused by noise. Specifically, this embodiment uses an analog voltage comparator to detect the voltage difference between adjacent PG nodes, and performs multiple voltage comparisons to accurately identify the voltage changes caused by PAA.

[0074] According to the above description, in another specific embodiment, the specific process for extracting power grid node features can be: preparing features for each PG node, including voltage comparison results of its four neighboring nodes: top, bottom, left, and right. These features are used as input to a machine learning model to identify "victim nodes" affected by PAA. For boundary nodes, this embodiment uses a symmetric padding method to ensure that all nodes have four features. Symmetric padding ensures the integrity of the four-dimensional features by copying the data of the neighbors symmetrical to the missing neighbors to the missing positions. For example, if the first node only has bottom and right neighbors but no top and left neighbors, symmetric padding will copy the data of the node's bottom neighbor to the missing top neighbor position and the data of the right neighbor to the missing left neighbor position. Specific features are generated by accumulating the results of each comparison. For example, for node i, the feature is generated after a fixed number of comparisons. Specifically, if node i is smaller than its neighboring nodes, the accumulated result is subtracted by one. Otherwise, the accumulated result is greater than one. This continues until the number of comparisons reaches the set number, at which point the accumulated value is extracted. This step can be considered a probabilistic convergence method.

[0075] In summary, the present application provides a chip power analysis attack detection system based on voltage comparison. This system deploys analog voltage comparators between power grid nodes of an integrated circuit and uses them to perform real-time voltage comparisons between the nodes to detect voltage changes caused by power analysis attacks. Based on the voltage comparison results, the system extracts features from the power grid nodes and trains the extracted features using a linear support vector machine model to obtain a trained machine learning model. Finally, the trained machine learning model is embedded in the integrated circuit to detect power analysis attacks. As can be seen, the system detects voltage differences between adjacent power grid nodes using analog voltage comparators and compensates for the effects of voltage noise through multiple voltage comparisons. Machine learning methods are then used to analyze the voltage comparison results and select a linear support vector machine model as the power analysis attack detection model. This system can detect power analysis attacks in real time, ensuring the security of the hardware system. Furthermore, the linear support vector machine model in this system can be embedded in a nanoscale CMOS process. Compared to existing power analysis attack detection technologies based on voltage sensors and analog-to-digital converters, this system can reduce circuit area and power consumption. Therefore, even in the presence of high voltage noise, this system can achieve high detection accuracy, effectively addressing the threat posed by power analysis attacks to hardware security.

[0076] It should be noted that the chip power consumption attack detection system based on voltage comparison provided in the above embodiment and the chip power consumption attack detection method based on voltage comparison provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs operations has been described in detail in the method embodiment and will not be repeated here. In actual applications, the chip power consumption attack detection system based on voltage comparison provided in the above embodiment can allocate the above functions to different functional modules as needed, that is, divide the internal structure of the system into different functional modules to complete all or part of the functions described above, which is not limited here. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0077] In another exemplary embodiment of the present application, the embodiment further provides a chip, which includes an integrated circuit, and is applied to the chip power consumption attack detection system based on voltage comparison as described in the above embodiment, or to the chip power consumption attack detection method based on voltage comparison as described in the above embodiment. It is understandable that since the specific manner in which the chip power consumption attack detection system and the chip power consumption attack detection method perform operations has been described in detail in the embodiments, the technical functions and effects of the chip provided in this embodiment can be referred to in the above embodiments and will not be repeated here.

[0078] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

[0079] The structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by those familiar with this technology. They are not intended to limit the conditions for implementation of this application and therefore have no substantial technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size should still fall within the scope of the technical contents disclosed in this application without affecting the effects and objectives that can be achieved by this application. At the same time, terms such as "upper," "lower," "left," "right," "center," and "one" cited in this specification are only for the convenience of description and are not intended to limit the scope of implementation of this application. Changes or adjustments in their relative relationships should also be considered as the scope of implementation of this application without substantially changing the technical contents.

Claims

1. A chip power consumption attack detection method based on voltage comparison, characterized in that: The method comprises the following steps: Deploy analog voltage comparators between power grid nodes of the integrated circuit, and use the analog voltage comparators to compare voltages between the power grid nodes in real time to detect voltage changes caused by power analysis attacks; Extracting features of power grid nodes based on voltage comparison results; The extracted features are trained using a linear support vector machine model to obtain a trained machine learning model; Embed the trained machine learning model into integrated circuits for power analysis attack detection; Before extracting the features of the power grid nodes based on the voltage comparison results, the method further includes: Counting the number of winning results after voltage comparison for each pair of power grid nodes in a predetermined time period; wherein each pair of power grid nodes includes adjacent power grid nodes; and Counting the winning probability of each pair of power grid nodes after voltage comparison within a predetermined time period; and, Counting the ratio of the number of winning times after voltage comparison between each pair of power grid nodes in a predetermined time period to the total number of comparisons; The number of winning times after voltage comparison, the probability of winning after voltage comparison, and the ratio of the number of winning times to the total number of comparisons are used as the characteristics of the power grid node; The method further comprises: accumulating the voltage comparison results using an accumulator; and, Storing the voltage comparison result in a random access memory; and Storing linear support vector machine model parameters using a read-only memory; and, The voltage comparison results are classified using a linear classifier according to the linear support vector machine model parameters.

2. The chip power consumption attack detection method based on voltage comparison according to claim 1 is characterized in that: The linear classifier is obtained by offline training using the voltage comparison result as training data.

3. A chip power consumption attack detection system based on voltage comparison, characterized in that: The system includes: a voltage comparison unit, configured to deploy analog voltage comparators between power grid nodes of the integrated circuit and use the analog voltage comparators to perform real-time comparisons of voltages between power grid nodes to detect voltage changes caused by power analysis attacks; a feature extraction unit, configured to extract features of power grid nodes based on voltage comparison results; A machine learning unit, used to train the extracted features using a linear support vector machine model to obtain a trained machine learning model; An attack detection unit, configured to embed the trained machine learning model into the integrated circuit for power analysis attack detection; Before extracting the features of the power grid nodes according to the voltage comparison results, the feature extraction unit further includes: Counting the number of winning results after voltage comparison for each pair of power grid nodes in a predetermined time period; wherein each pair of power grid nodes includes adjacent power grid nodes; and Counting the winning probability of each pair of power grid nodes after voltage comparison within a predetermined time period; and, Counting the ratio of the number of winning times after voltage comparison between each pair of power grid nodes in a predetermined time period to the total number of comparisons; The number of winning times after voltage comparison, the probability of winning after voltage comparison, and the ratio of the number of winning times to the total number of comparisons are used as the characteristics of the power grid node; The system also includes: An accumulator, used for accumulating voltage comparison results; A random access memory, used for storing voltage comparison results; A read-only memory, used for storing linear support vector machine model parameters; A linear classifier is used to classify the voltage comparison results based on the linear support vector machine model parameters.

4. The chip power consumption attack detection system based on voltage comparison according to claim 3 is characterized in that: The linear classifier is obtained by offline training using the voltage comparison result as training data.

5. A chip, characterized in that: The chip is applied to the chip power consumption attack detection method based on voltage comparison as described in claim 1 or 2, or the chip is applied to the chip power consumption attack detection system based on voltage comparison as described in claim 3 or 4. The chip according to claim 5 , wherein the chip is provided with an integrated circuit.

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