A Thermoelectric Coupling Modeling Method for Devices Based on TDTR Technology

Abstract

The present invention provides a method for thermoelectric coupling modeling of a device based on the TDTR technology, which relates to the technical field of semiconductor power devices. The method includes: when the thickness of the preset dielectric layer of the second preset material is less than a preset value, preparing a plurality of samples with different thicknesses; when the upper material layer is a test sensing layer suitable for TDTR testing, determining a target thermal resistance value through TDTR testing and samples with different preset dielectric layer thicknesses; using simulation software, physical models, measured electrical characteristic data, known thermophysical property parameters, and the target thermal resistance value to fit and construct an initial device thermoelectric model; performing a target test on the preset semiconductor device under a preset power density to obtain a preset surface temperature rise and a preset temperature distribution; at the same power density, fitting the surface temperature rise and the target temperature distribution of the initial device thermoelectric model with the preset surface temperature rise and the preset temperature distribution of the target test, so as to accurately construct a self-consistent semiconductor device thermoelectric coupling model.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular, to a device thermoelectric coupling modeling method based on TDTR technology. Background Art

[0002] With the increasing maturity and popularity of the (ultra) wide bandgap semiconductor power device industry, device-level thermoelectric co-optimization design based on the device thermoelectric model can actively exploit its thermoelectric performance advantages and create many new application scenarios that silicon devices cannot achieve, which has become an inevitable trend in the development of the energy industry. Device thermophysical parameters are an important prerequisite for constructing a self-consistent thermoelectric coupling model of (ultra) wide bandgap semiconductor power devices, conducting thermoelectric numerical simulation research based on this model, and device-level thermoelectric co-optimization design. Device thermophysical parameters include: the thermal resistance, specific heat capacity, and thermal expansion coefficient of the device material, as well as the interfacial thermal resistance between different materials. However, the research on the thermophysical parameters of the metal-oxide-semiconductor (MOS) structure part of (ultra) wide bandgap semiconductor power devices has just started, and the research on the thermal resistance of different gate dielectrics, the interfacial thermal resistance between different gate dielectrics and (ultra) wide bandgap semiconductor materials, and the interfacial thermal resistance between different gate dielectrics and gate metals based on the actual device structure is almost blank, which brings serious obstacles to thermoelectric modeling based on the actual device structure.

[0003] Currently, realizing time-domain thermoreflectance (TDTR) based on an ultrafast laser is a general technique for measuring the thermal performance of various bulk, thin film materials, and interfaces between different materials. Its principle is to rely on a test transducer layer to obtain the thermophysical parameters of the material to be measured. The transducer is usually a metal material such as aluminum, nickel, palladium, gold, etc. To eliminate the error influence of the interfacial thermal resistance between the transducer and the thin film in TDTR testing, it is generally required that the thickness of the thin film sample (including the thickness of the gate dielectric) tested by TDTR is at least greater than or equal to 100 nm. However, the gate dielectric of the MOS structure is realized by atomic layer deposition (ALD), and the thickness of the gate dielectric is less than 50 nm. The thickness of the thin film grown by ALD in a single time generally does not exceed 10 nm. If an MOS structure test unit that meets the TDTR test thickness requirement is prepared using the ALD method, first, the process time is too long to meet the thickness requirement; second, as the growth thickness increases, the single deposition time increases significantly, and the film quality difference between different growth batches and the interfacial problems between them will make the TDTR test results unable to reflect the thermophysical characteristics of the actual device MOS gate dielectric structure, and thus it is impossible to accurately construct a self-consistent thermoelectric coupling model of (ultra) wide bandgap semiconductor devices. Summary of the Invention

[0004] An object of an embodiment of the present invention is to provide a method for modeling the thermoelectric coupling of a device based on the TDTR technology, so as to solve the problem that it is impossible to accurately construct a self-consistent thermoelectric coupling model for (ultra) wide-bandgap semiconductor devices.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] The present invention provides a method for modeling the thermoelectric coupling of a device based on the TDTR technology, and the method includes:

[0007] Determine the known thermophysical property parameters of the first preset material and the unknown thermophysical property parameters of the second preset material of the preset semiconductor device. The known thermophysical property parameters are the thermophysical property parameters of the first preset material in the preset semiconductor device recorded in the record file, and the unknown thermophysical property parameters are the thermophysical property parameters of the second preset material in the preset semiconductor device not recorded in the record file;

[0008] When the thickness of the preset dielectric layer of the second preset material is less than a preset value, prepare a plurality of samples with different thicknesses. The thicknesses of the target dielectric layers in the second target materials in each sample are different, and each sample includes an upper material layer adjacent to the target dielectric layer in the second target material;

[0009] When the upper material layer is a test sensing layer applicable to TDTR testing, determine the target thermal resistance value in the unknown thermophysical property parameters through TDTR testing and the thickness of the preset dielectric layer in the preset semiconductor device;

[0010] Utilize simulation software, physical models, measured electrical characteristic data, known thermophysical property parameters, and the target thermal resistance value to construct an initial device thermoelectric model based on the thermophysical property parameters;

[0011] Conduct a target test on the preset semiconductor device under a preset power density for thermal steady state to obtain a preset surface temperature rise and a preset temperature distribution;

[0012] At the same power density, fit the target surface temperature rise and the target temperature distribution of the initial device thermoelectric model with the preset surface temperature rise and the preset temperature distribution to construct a thermoelectric coupling model for the semiconductor device.

[0013] In some embodiments, when the upper material layer is a test sensing layer applicable to TDTR testing, determining the target thermal resistance value in the unknown thermophysical property parameters through TDTR testing and the thickness of the preset dielectric layer in the preset semiconductor device includes:

[0014] When the upper material layer is a test sensing layer applicable to TDTR testing, obtain the preset thermal resistance values corresponding to each sample through TDTR testing;

[0015] Fit the preset thermal resistance values corresponding to each sample to obtain a fitting line;

[0016] Determine the target thermal resistance value according to the fitting line and the thickness of the preset dielectric layer.

[0017] In some embodiments, using a simulation software, a physical model, measured electrical property data, known thermal property parameters, and a target thermal resistance value, fit and construct an initial device thermoelectric model, including:

[0018] Use the simulation software, the physical model, and the measured electrical property data to fit the electrical property device model corresponding to the preset semiconductor device;

[0019] Input the known thermal property parameters and the target thermal resistance value into the electrical property device model to construct an initial device thermoelectric model based on the thermal property parameters.

[0020] In some embodiments, the electrical property device model includes a first electrical property device model and a second electrical property device model, and the initial device thermoelectric model includes a first initial device thermoelectric model and a second initial device thermoelectric model;

[0021] Use the simulation software, the physical model, and the measured electrical property data to fit the electrical property device model corresponding to the preset semiconductor device, including:

[0022] According to the structure editor in the simulation software, construct a two-dimensional structure model and a three-dimensional structure model corresponding to the preset semiconductor device, and generate grids in the two-dimensional structure model and the three-dimensional structure model;

[0023] For the two-dimensional structure model after generating grids and the three-dimensional structure model after generating grids, sequentially add physical models and perform local grid optimization to obtain a preset two-dimensional structure model and a preset three-dimensional structure model. The physical models include a carrier transport model, a mobility model, a generation-recombination model, a lattice self-heating model, and an energy balance model, etc.;

[0024] Fit the preset two-dimensional structure model and the preset three-dimensional structure model according to the measured electrical property data to obtain a first electrical property device model corresponding to the preset two-dimensional structure model and a second electrical property device model corresponding to the preset three-dimensional structure model;

[0025] Correspondingly, input the known thermal property parameters and the target thermal resistance value into the electrical property device model to construct an initial device thermoelectric model based on the thermal property parameters, including:

[0026] Input both the known thermal property parameters and the target thermal resistance value into the first electrical property device model and the second electrical property device model to construct a first initial device thermoelectric model based on the thermal property parameters corresponding to the preset two-dimensional structure model and a second initial device thermoelectric model corresponding to the preset three-dimensional structure model.

[0027] In some embodiments, the target surface temperature rise includes a first target surface temperature rise and a second target surface temperature rise, and the target temperature distribution includes a first target temperature distribution and a second target temperature distribution;

[0028] At the same power density, fitting the target surface temperature rise and the target temperature distribution of the initial device thermoelectric model to the preset surface temperature rise and the preset temperature distribution to construct a thermoelectric coupling model of the semiconductor device, including:

[0029] According to the preset surface temperature rise and the preset temperature distribution, fitting the simulation software so that the first target surface temperature rise corresponding to the first initial device thermoelectric model is the same as the preset surface temperature rise, and the first target temperature distribution is the same as the preset temperature distribution;

[0030] According to the first target surface temperature rise and the first target temperature distribution, determining the heating profile of the first device model based on thermal property parameters;

[0031] Importing the heating profile into the second initial device thermoelectric model to obtain the second target surface temperature rise and the second target temperature distribution corresponding to the second initial device thermoelectric model, and fitting the second target surface temperature rise and the second target temperature distribution to the preset surface temperature rise and the preset temperature distribution to construct a thermoelectric coupling model of the semiconductor device.

[0032] In some embodiments, after determining the known thermal property parameters of the first preset material and the unknown thermal property parameters of the second preset material of the preset semiconductor device, the method further includes:

[0033] Determining the thickness of the preset dielectric layer of the second preset material through the preset semiconductor device design drawing, where the preset semiconductor device design drawing is used to record the thickness of the material corresponding to the unknown thermal property parameters;

[0034] When the thickness of the second preset material is not less than the set value, obtaining the target thermal resistance value through the TDTR test.

[0035] In some embodiments, when the thickness of the preset dielectric layer of the second preset material is less than the preset value, after preparing a plurality of samples with different thicknesses, the method further includes:

[0036] According to the electromigration test, the thermal conductivity test, and the coating analysis, determining whether the upper material layer is a test sensing layer suitable for the TDTR test or a test sensing layer not suitable for the TDTR test.

[0037] In some embodiments, after determining whether the upper material layer is a test sensing layer suitable for the TDTR test or a test sensing layer not suitable for the TDTR test according to the electromigration test, the thermal conductivity test, and the coating analysis, the method further includes:

[0038] When the upper material layer is not applicable to the test sensing layer of the TDTR test, a preset metal layer is deposited on the upper material layer, and the preset metal layer is a metal layer suitable for the TDTR test.

[0039] In some embodiments, the number of multiple samples is greater than or equal to 5.

[0040] In some embodiments, the target tests include infrared thermal imaging test, thermal reflection thermal imaging test, and microparticle Raman test.

[0041] Compared with the prior art, for the device thermoelectric coupling modeling method based on the TDTR technology provided by the present invention, when the thickness of the preset dielectric layer of the second preset material is less than a preset value, unknown thermophysical parameters of the second preset material in the preset semiconductor device are indirectly obtained through TDTR tests and multiple groups of sample tests, and combined with the known thermophysical parameters of the first preset material, an initial device thermoelectric model is fitted and constructed by using simulation software, physical models, and measured electrical characteristic data; at the same time, a target test of the thermal steady state under a preset power density is performed on the preset semiconductor device to obtain the preset surface temperature rise and preset temperature distribution of the device; and at the same power density, the target surface temperature rise and target temperature distribution of the constructed initial device thermoelectric model are fitted with the preset surface temperature rise and preset temperature distribution of the actual target test under this power thermal steady state. When the temperatures are the same, a precise and self-consistent thermoelectric coupling model of the semiconductor device is established. For the finally constructed thermoelectric coupling model of the semiconductor device, all the physical parameters related to heat and electricity come from the results of actual measurement and calculation, and it is more precise and self-consistent than the device model established only based on semiconductor process simulation and the built-in model of the device simulation tool (Technology Computer Aided Design, TCAD). This model provides an important prerequisite for carrying out thermoelectric numerical simulation research and device-level thermoelectric co-optimization design based on this model. Description of the Drawings

[0042] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present invention will become easily understood. In the drawings, several embodiments of the present invention are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0043] Figure 1 Schematically shows a flowchart of a device thermoelectric coupling modeling method based on the TDTR technology;

[0044] Figure 2 Schematically shows the structure diagram of the preset semiconductor device in Embodiment 1;

[0045] Figure 3Schematically shows the structural diagram of the preset semiconductor device of the second embodiment;

[0046] Figure 4 Schematically shows the structural diagrams of multiple samples of the first embodiment;

[0047] Figure 5 Schematically shows the structural diagram of the test sensing layer where the upper material layer is not suitable for TDTR testing;

[0048] Figure 6 Schematically shows the schematic diagram of the fitting line of the first embodiment;

[0049] Figure 7 Schematically shows the output characteristic curves of the preset semiconductor device and the electrical characteristic device model;

[0050] Figure 8 Schematically shows the flow chart for constructing the thermoelectric coupling model of the semiconductor device. Detailed implementation manners

[0051] Hereinafter, the exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention can be fully conveyed to those skilled in the art.

[0052] It should be noted that: Unless otherwise specified, the technical terms or scientific terms used in the present invention should have the ordinary meanings understood by those skilled in the art to which the present invention belongs.

[0053] The methods in the embodiments of the present invention will be described in detail below.

[0054] Figure 1 Schematically shows the flow chart of the method for thermoelectric coupling modeling of the device based on TDTR technology in the embodiment of the present invention. Refer to Figure 1 As shown, the method may include:

[0055] S101. Determine the known thermophysical property parameters of the first preset material and the unknown thermophysical property parameters of the second preset material of the preset semiconductor device.

[0056] Among them, the known thermophysical property parameters are the thermophysical property parameters of the first preset material in the preset semiconductor device recorded in the record file, and the unknown thermophysical property parameters are the thermophysical property parameters of the second preset material in the preset semiconductor device not recorded in the record file. The first preset material is different from the second preset material.

[0057] The second preset material corresponding to the unknown thermal property parameter may be the material corresponding to the preset dielectric layer, or the material corresponding to the preset dielectric layer and the material layer.

[0058] By means of the record file, the known thermal property parameters and unknown thermal property parameters of the materials corresponding to the preset semiconductor device are determined, and the record file is used to record the thermal property parameters of all the materials corresponding to the semiconductor devices.

[0059] The preset semiconductor device of the present invention is applicable to all semiconductor devices, such as Figure 2 and Figure 3 the semiconductor devices in. Among them, Figure 2 Schematically shows the structure diagram of the preset semiconductor device of Embodiment 1. The preset semiconductor device includes a plurality of preset material layers and a preset dielectric layer. Specifically: the preset semiconductor device sequentially includes a Fe-doped Ga2O3 preset material layer, a Si-doped Ga2O3 preset material layer, an Al2O3 preset dielectric layer, a Ni preset material layer from bottom to top. There are 3 Au preset material layers. Among them, 2 Au preset material layers are respectively arranged on both sides of the Al2O3 preset dielectric layer and are adjacent to the Al2O3 preset dielectric layer and not adjacent to the Ni preset material layer; 1 Au preset material layer is arranged on the Ni preset material layer, and the Ni preset material layer is located on the Al2O3 preset dielectric.

[0060] Figure 3 Schematically shows the structure diagram of the preset semiconductor device of Embodiment 2. The preset semiconductor device includes a plurality of preset material layers and a preset dielectric layer. Specifically: the preset semiconductor device sequentially includes a Fe-doped Ga2O3 preset material layer, a Si-doped Ga2O3 preset material layer, a lead zirconate titanate (PZT) preset dielectric layer, a SiO2 preset dielectric layer, a Ni preset material layer from bottom to top. There are 3 Au preset material layers. Among them, 2 Au preset material layers are respectively arranged on both sides of the PZT preset dielectric layer and the SiO2 preset dielectric layer and are adjacent to the PZT preset dielectric layer and the SiO2 preset dielectric layer and not adjacent to the Ni preset material layer. 1 Au preset material layer is arranged on the Ni preset material layer, and the Ni preset material layer is located on the Al2O3 preset dielectric.

[0061] For the preset semiconductor device of Embodiment 1, the known thermal property parameters corresponding to the first preset material are the material thermal resistances of Au, Ni and Ga2O3, and the interfacial thermal resistance between Au and Ni. The unknown thermal property parameters corresponding to the second preset material are the thermal resistance of Al2O3, the interfacial thermal resistance between Ni and Al2O3, the interfacial thermal resistance between Al2O3 and Ga2O3, and the interfacial thermal resistance between Au and Ga2O3.

[0062] Specifically, after determining the known thermal property parameters and unknown thermal property parameters of the materials corresponding to the preset semiconductor device, the method further includes:

[0063] Step A1: Determine the thickness of the preset dielectric layer of the second preset material through the design drawing of the preset semiconductor device.

[0064] The design drawing of the preset semiconductor device is used to record the thickness of the material corresponding to the unknown thermal property parameter and the thickness of the material corresponding to the known thermal property parameter.

[0065] It is determined that the thickness of the Al2O3 preset dielectric layer in the preset semiconductor device of Example 1 is 30 nm.

[0066] Step A2: When the thickness of the second preset material is not less than the preset value, directly obtain the target thermal resistance through TDTR testing.

[0067] The unknown thermal property parameter is the interfacial thermal resistance between Au and Ga2O3. Since the thickness of Ga2O3 is greater than 100 nm, the interfacial thermal resistance between Au and Ga2O3 can be directly obtained through TDTR testing.

[0068] S102. When the thickness of the preset dielectric layer of the second preset material is less than the preset value, prepare multiple samples with different thicknesses.

[0069] Among them, the thicknesses of the target dielectric layers in the second target materials of the samples are different. Each sample includes an upper material layer and a lower material layer adjacent to the target dielectric layer in the second target material.

[0070] The thickness of the second target material in each sample is the same as the thickness of the first preset material in the preset semiconductor device.

[0071] Each sample includes a target dielectric layer and multiple target material layers adjacent to the target dielectric layer. The multiple target material layers adjacent to the target dielectric layer include an upper material layer adjacent to the target dielectric layer in the second target material and a lower material layer adjacent to the target dielectric layer in the second target material.

[0072] In Example 1, since the thickness of the material corresponding to the 30-nm Al2O3 preset dielectric layer in the second preset material is less than the preset value of 100 nm, the thermal resistance cannot be directly measured, and multiple samples corresponding to the preset material unit need to be prepared.

[0073] Among them, the number of multiple samples is greater than or equal to 5.

[0074] The thermal resistance of each prepared sample is the same as the known thermal property parameters of the preset semiconductor device. To further eliminate the test error of the interface thermal resistance caused by the thickness of the Al2O3 target dielectric layer in the TDTR test, taking the 30-nm Al2O3 target dielectric layer as the lower reference, several samples with the thickness of the Al2O3 target dielectric layer increased by 10 nm at uniform intervals are additionally prepared.

[0075] The structure of each sample is a part of the preset semiconductor device structure. Figure 4 The structural diagrams of 5 samples in the first embodiment are schematically shown. Refer to Figure 4 As shown, the 5 samples in the first embodiment all include multiple target material layers, specifically: each sample successively includes a Fe-doped Ga2O3 target material layer, a Si-doped Ga2O3 target material layer, an Al2O3 target dielectric layer, and a Ni target material layer from bottom to top. The thicknesses of the Al2O3 target dielectric layers in the 5 samples are different. Since the single growth thickness of the ALD film generally does not exceed 10 nm, the thicknesses of the Al2O3 target dielectric layers in the 5 samples are 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm in sequence. The thicknesses of the Fe-doped Ga2O3 target material layers in the 5 samples are the same as those of the Fe-doped Ga2O3 preset material layers in the preset semiconductor device, the thicknesses of the Si-doped Ga2O3 target material layers in the 5 samples are the same as those of the Si-doped Ga2O3 preset material layers in the preset semiconductor device, and the thicknesses of the Ni target material layers in the 5 samples are the same as those of the Ni preset material layers in the preset semiconductor device.

[0076] Specifically, when the thickness of the preset dielectric layer of the second preset material is less than the preset value, after preparing multiple samples with different thicknesses, the method further includes:

[0077] Step B1: Determine whether the upper material layer is a test sensing layer suitable for the TDTR test or a test sensing layer not suitable for the TDTR test according to the electromigration test, the thermal conductivity test, and the coating analysis.

[0078] According to the electromigration test, the thermal conductivity test, and the coating analysis, if it is analyzed that the upper material layer has high thermal conductivity, low laser transmittance, and good thermal stability, then the upper material layer is a test sensing layer suitable for the TDTR test; if it is analyzed that the upper material layer does not have any one of high thermal conductivity, low laser transmittance, and good thermal stability, then the upper material layer is a test sensing layer not suitable for the TDTR test.

[0079] The upper material layer in the first embodiment is the Ni target material layer.

[0080] Step B2: When the upper material layer is not suitable for the test sensing layer of TDTR testing, a preset metal layer is grown on the upper material layer, and the preset metal layer is a metal layer that meets the preset conditions.

[0081] Among them, the preset conditions are conditions that meet high thermal conductivity, low laser transmittance, and good thermal stability.

[0082] Figure 5 The structural diagram of the test sensing layer where the upper material layer is not suitable for TDTR testing is schematically shown. This structure includes a Ga2O3 target material layer (Fe-doped Ga2O3 target material layer and Si-doped Ga2O3 target material layer), an Al2O3 target dielectric layer, a Ti target material layer, and an Al preset metal layer from bottom to top. The upper material layer of the Al2O3 target dielectric layer in this structure is the Ti target material layer. Since the Ti reflection signal is not good and it cannot be used as the test sensing layer, a layer of Al preset metal layer is grown as the test sensing layer. Among them, the overall thermal resistance of this structure is the Al-Ti interface thermal resistance, the thermal resistance of Ti, the Ti-Al2O3 interface thermal resistance, the Al2O3 thermal resistance, and the Al2O3-Ga2O3 interface thermal resistance. Among them, the Ti-Al2O3 interface thermal resistance and the Al2O3-Ga2O3 interface thermal resistance are unknown thermophysical parameters.

[0083] S103: When the upper material layer is suitable for the test sensing layer of TDTR testing, determine the target thermal resistance value in the unknown thermophysical parameters through TDTR testing and the thickness of the preset dielectric layer in the preset semiconductor device.

[0084] Specifically, when the upper material layer is suitable for the test sensing layer of TDTR testing, indirectly determine the target thermal resistance value in the unknown thermophysical parameters through TDTR testing and the thickness of the preset dielectric layer in the preset semiconductor device, including:

[0085] Step C1: When the upper material layer is suitable for the test sensing layer of TDTR testing, obtain the preset thermal resistance values corresponding to each sample through TDTR testing.

[0086] When the upper material layer is suitable for the test sensing layer of TDTR testing, for example, the Ni target material layer in Example 1 can be directly used as the test sensing layer of TDTR testing. Under the same TDTR testing conditions, obtain the preset thermal resistance values of each sample with different thicknesses of the Al2O3 target dielectric layer. Each time TDTR testing is performed, adjust the laser angular frequency of the instrument used for TDTR testing so that the probe receives the signal when the thermal penetration depth reaches the Al2O3-Ga2O3 interface. The preset thermal resistance values of each sample all include: the interface thermal resistance between Ni and Al2O3, the thermal resistance of Al2O3, and the interface thermal resistance between Al2O3 and Ga2O3.

[0087] Step C2: Fit the preset thermal resistance values corresponding to each sample to obtain a fitting line.

[0088] Fit the preset thermal resistance values of each sample with five groups of spaced Al2O3 target dielectric layer thicknesses obtained in Step C1 to obtain a fitting line. If the value of the coefficient of determination of the preset thermal resistance values corresponding to each sample is close to 1, it indicates that the fitting linearity of the fitting line is good, which proves the accuracy of the thermal resistance test of each sample with different Al2O3 target dielectric layer thicknesses.

[0089] Figure 6 Schematically shows the fitting line schematic diagram of Embodiment 1. The abscissa is the thickness of the Al2O3 target dielectric layer (thin film), the ordinate is the thermal resistance, and the 5 circles respectively correspond to the preset thermal resistance values of 5 samples. The line in the figure is the fitting line.

[0090] Step C3: Determine the target thermal resistance according to the fitting line and the thickness of the preset dielectric layer.

[0091] Extract the target thermal resistance value corresponding to the thickness of the Al2O3 target dielectric layer with an abscissa of 30 nm in Embodiment 1 on the fitting line. The target thermal resistance value is the overall thermal resistance value of the Ni-Al2O3 interface thermal resistance, the 30 nm Al2O3 thermal resistance, and the Al2O3-Ga2O3 interface thermal resistance.

[0092] S104. Use simulation software, physical models, measured electrical property data, known thermal property parameters, and the target thermal resistance value to fit and construct an initial device thermoelectric model.

[0093] Specifically, using simulation software, physical models, measured electrical property data, known thermal property parameters, and the target thermal resistance value to fit and construct an initial device thermoelectric model includes:

[0094] Step D1: Use simulation software, physical models, and measured electrical property data to fit the electrical property device model corresponding to the preset semiconductor device.

[0095] Among them, the electrical property device model includes a first electrical property device model and a second electrical property device model, and the device model based on thermal property parameters includes a first device model based on thermal property parameters and a second device model based on thermal property parameters.

[0096] The simulation software includes Sentaurus TCAD simulation software, COMSOL, and Workbench.

[0097] Figure 7 Schematically shows the output characteristic curve of the preset semiconductor device and the electrical property device model. Figure 7The abscissa is the drain-source voltage, and the ordinate is the drain-source current. The solid green line is the measured output characteristic curve of the preset semiconductor device (actual device) under the condition that the gate voltage is 14V. The dashed green line is the output characteristic curve fitted by the simulated electrical characteristic device model under the same condition. If the two are almost the same, it is considered that the fitting is completed. The solid blue line is the measured output characteristic curve of the preset semiconductor device (actual device) under the condition that the gate voltage is -2V. The dashed blue line is the output characteristic curve fitted by the simulated electrical characteristic device model under the same condition. If the two are almost the same, it is considered that the fitting is completed.

[0098] Specifically, using simulation software, physical models, and measured electrical characteristic data, fitting the electrical characteristic device model corresponding to the preset semiconductor device, including:

[0099] Step D11: According to the structure editor in the simulation software, construct the two-dimensional structure model and three-dimensional structure model corresponding to the preset semiconductor device, and generate grids in the two-dimensional structure model and three-dimensional structure model.

[0100] Both the two-dimensional structure model and the three-dimensional structure model are the same as the structure of the preset semiconductor device.

[0101] Step D12: For the two-dimensional structure model after generating grids and the three-dimensional structure model after generating grids, sequentially add physical models and optimize local grids to obtain the preset two-dimensional structure model and the preset three-dimensional structure model.

[0102] Among them, the physical models include carrier transport models, mobility models, generation-recombination models, lattice self-heating models, and energy balance models, etc.

[0103] The carrier transport model can be a thermodynamic model, the mobility model can be a high-field velocity saturation model and an ionized impurity scattering model, and the generation-recombination model can be an indirect recombination model.

[0104] The grid is used to indicate the calculation area of the simulation software.

[0105] Step D13: Fit the preset two-dimensional structure model and the preset three-dimensional structure model according to the measured electrical characteristic data to obtain the first electrical characteristic device model corresponding to the preset two-dimensional structure model and the second electrical characteristic device model corresponding to the preset three-dimensional structure model.

[0106] The electrical input conditions of the first electrical characteristic device model and the second electrical characteristic device model are the same, and the same measured electrical characteristic data are used.

[0107] Step D2: Input the known thermal property parameters and the target thermal resistance value into the electrical characteristic device model to construct an initial device thermoelectric model based on the thermal property parameters.

[0108] Specifically, input the known thermal property parameters and the target thermal resistance value into the electrical property device model to construct an initial device thermoelectric model based on the thermal property parameters, including:

[0109] Input both the known thermal property parameters and the target thermal resistance value into the first electrical property device model and the second electrical property device model to construct a first device model based on the thermal property parameters corresponding to the preset two-dimensional structure model and a second device model based on the thermal property parameters corresponding to the preset three-dimensional structure model.

[0110] S105. Conduct a target test on the preset semiconductor device under thermal steady state at a preset power density to obtain a preset surface temperature rise and a preset temperature distribution.

[0111] Among them, the target test on the thermal steady state at the preset power density can be an infrared thermal imaging test, a thermal reflection thermal imaging test, or a microparticle Raman test.

[0112] The preset surface temperature rise and the preset temperature distribution are used as the evaluation basis for the thermoelectric coupling fitting modeling of the semiconductor device.

[0113] The preset power density range of the preset semiconductor device is from 0.25 W / mm to 1.5 W / mm.

[0114] S106. At the same power density, fit the target surface temperature rise and the target temperature distribution of the initial device thermoelectric model with the preset surface temperature rise and the preset temperature distribution to construct a thermoelectric coupling model of the semiconductor device.

[0115] Among them, the target surface temperature rise is the same as the preset surface temperature rise, and the target temperature distribution is the same as the preset temperature distribution.

[0116] Among them, the target surface temperature rise includes a first target surface temperature rise and a second target surface temperature rise, and the target temperature distribution includes a first target temperature distribution and a second target temperature distribution.

[0117] Specifically, in the simulation software, set the same infrared test temperature boundary conditions and electrical stress conditions for the device model based on the thermal property parameters, and simulate and couple the solution of the electron, hole, temperature, and Poisson equations to obtain the temperature distributions of the device two-dimensional model and three-dimensional model. Based on the preset surface temperature rise and the preset temperature distribution under this power thermal steady state, fit until the temperature distributions of the two-dimensional model and three-dimensional model are consistent with the temperature distribution during the actual measurement imaging. So far, the thermal and electrical property fittings of the device model are both self-consistent, and the accurate thermoelectric coupling model of the above device is established.

[0118] Specifically, at the same power density, fit the target surface temperature rise and the target temperature distribution of the initial device thermoelectric model with the preset surface temperature rise and the preset temperature distribution to construct a thermoelectric coupling model of the semiconductor device, including:

[0119] Step E1: According to the preset surface temperature rise and the preset temperature distribution, fit the simulation software so that the first target surface temperature rise corresponding to the first initial device thermoelectric model is the same as the preset surface temperature rise, and the first target temperature distribution is the same as the preset temperature distribution.

[0120] Step E2: Determine the heat generation profile of the first device model based on thermal physical parameters according to the first target surface temperature rise and the first target temperature distribution.

[0121] Step E3: Import the heat generation profile into the second initial device thermoelectric model to obtain the second target surface temperature rise and the second target temperature distribution corresponding to the second initial device thermoelectric model, and fit the second target surface temperature rise and the second target temperature distribution with the preset surface temperature rise and the preset temperature distribution to construct a thermoelectric coupling model of the semiconductor device.

[0122] Figure 8 Schematically shows a flowchart for constructing a thermoelectric coupling model of a semiconductor device. Refer to Figure 8 As shown, temperature boundary conditions have been added to both the first initial device thermoelectric model and the second initial device thermoelectric model, the heat dissipation surface between the device and the outside is defined, and according to the TDTR test and known thermal physical parameters, the thermal resistance (R th ) of each layer (including dielectric layers and material layers) of the device is defined, and the interfacial thermal resistance (R th.int); In the simulation software, for both the first initial device thermoelectric model and the second initial device thermoelectric model, set the temperature boundary conditions and apply the electrical stress conditions according to the ambient temperature during the actual thermal imaging and the power density of the device. Define the initial step size, minimum step size, and maximum step size during the solution process to ensure the convergence and accuracy of the simulation results. Couple and solve the electron, hole, temperature, and Poisson equations to obtain the first target surface temperature rise and the first target temperature distribution of the first initial device thermoelectric model corresponding to the two-dimensional model. Adjust other parameters except the input parameters actually measured and calculated for the device fitting modeling, such as the local grid size, solution step size, etc., until the first target surface temperature rise and the first target temperature distribution of the first initial device thermoelectric model corresponding to the two-dimensional model are the same as the preset surface temperature rise and temperature distribution; According to the first target surface temperature rise and the first target temperature distribution, determine the heating profile of the first initial device thermoelectric model; Import the heating profile into the second initial device thermoelectric model to obtain the second target surface temperature rise and the second target temperature distribution of the second initial device thermoelectric model corresponding to the three-dimensional model. Adjust other parameters except the input parameters obtained by actual measurement and calculation for the device fitting modeling, such as the local grid size, solution step size, etc., until the second target surface temperature rise and the second target temperature distribution of the second initial device thermoelectric model corresponding to the three-dimensional model are the same as the preset surface temperature rise and temperature distribution. Thus, the establishment of the accurate self-consistent thermoelectric coupling model for semiconductor devices is completed.

[0123] The device thermoelectric coupling modeling method based on the TDTR technology of the present invention includes determining the known thermal physical properties parameters of the first preset material and the unknown thermal physical properties parameters of the second preset material of the preset semiconductor device. When the thickness of the preset dielectric layer of the second preset material is less than the preset value, prepare multiple samples with different thicknesses; When the upper material layer is the test sensing layer suitable for TDTR testing, indirectly determine the target thermal resistance value of the unknown thermal physical properties material through TDTR testing and samples with preset different dielectric layer thicknesses; Use the simulation software, physical model, measured electrical characteristic data, known thermal physical properties parameters, and target thermal resistance value to fit and construct the initial device thermoelectric model; Conduct the target test of the thermal steady state under the preset power density for the preset semiconductor device to obtain the preset surface temperature rise and the preset temperature distribution; At the same power density, fit the surface temperature rise and the target temperature distribution of the constructed initial device thermoelectric model with the preset surface temperature rise and the preset temperature distribution of the target test. When the temperatures are the same, the accurate self-consistent thermoelectric coupling model of the semiconductor device is established. For the finally constructed semiconductor device thermoelectric coupling model, all the physical parameters related to heat and electricity come from the results of actual measurement and calculation, which is more accurate and self-consistent than the device model established only based on the TCAD own model. This model provides an important prerequisite for carrying out thermoelectric numerical simulation research and device-level thermoelectric co-optimization design based on this model.

[0124] The above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A device thermoelectric coupling modeling method based on the TDTR technology, characterized in that, The device thermoelectric coupling modeling method based on the TDTR technology includes: Determine the known thermal property parameters of the first preset material and the unknown thermal property parameters of the second preset material of the preset semiconductor device. The known thermal property parameters are the thermal property parameters of the first preset material in the preset semiconductor device recorded in the record file, and the unknown thermal property parameters are the thermal property parameters of the second preset material in the preset semiconductor device not recorded in the record file; When the thickness of the preset dielectric layer of the second preset material is less than the preset value, prepare a plurality of samples with different thicknesses. The thicknesses of the target dielectric layers in the second target materials of the samples are different. Each sample includes an upper material layer adjacent to the target dielectric layer in the second target material; When the upper material layer is a test sensing layer applicable to the TDTR test, determine the target thermal resistance value in the unknown thermal property parameters through the TDTR test and the thickness of the preset dielectric layer in the preset semiconductor device; Use simulation software, physical models, measured electrical characteristic data, the known thermal property parameters, and the target thermal resistance value to fit and construct an initial device thermoelectric model; Conduct a target test on the preset semiconductor device under a preset power density for thermal steady state to obtain a preset surface temperature rise and a preset temperature distribution; Under the same power density, fit the target surface temperature rise and the target temperature distribution of the initial device thermoelectric model with the preset surface temperature rise and the preset temperature distribution to construct a thermoelectric coupling model of the semiconductor device.

2. The method for device thermoelectric coupling modeling based on the TDTR technology according to claim 1, wherein The step of determining the target thermal resistance value in the unknown thermal property parameters through the TDTR test and the thickness of the preset dielectric layer in the preset semiconductor device when the upper material layer is a test sensing layer applicable to the TDTR test includes: When the upper material layer is a test sensing layer applicable to the TDTR test, obtain the preset thermal resistance values corresponding to the samples through the TDTR test; Fit the preset thermal resistance values corresponding to the samples to obtain a fitting straight line; Determine the target thermal resistance value according to the fitting straight line and the thickness of the preset dielectric layer.

3. The device thermoelectric coupling modeling method based on the TDTR technology according to claim 1, wherein The step of using simulation software, physical models, measured electrical characteristic data, the known thermal property parameters, and the target thermal resistance value to fit and construct an initial device thermoelectric model includes: Use the simulation software, the physical models, and the measured electrical characteristic data to fit the electrical characteristic device model corresponding to the preset semiconductor device; Input the known thermal property parameters and the target thermal resistance value into the electrical characteristic device model to construct the initial device thermoelectric model.

4. The device thermoelectric coupling modeling method based on the TDTR technology according to claim 3, characterized in that The electrical characteristic device model includes a first electrical characteristic device model and a second electrical characteristic device model, and the initial device thermoelectric model includes a first initial device thermoelectric model and a second initial device thermoelectric model; The step of using the simulation software, the physical models, and the measured electrical characteristic data to fit the electrical characteristic device model corresponding to the preset semiconductor device includes: According to the structure editor in the simulation software, construct the two-dimensional structure model and three-dimensional structure model corresponding to the preset semiconductor device, and generate grids in the two-dimensional structure model and three-dimensional structure model; For the two-dimensional structure model with grids generated and the three-dimensional structure model with grids generated, sequentially add the physical models and perform local grid optimization to obtain the preset two-dimensional structure model and preset three-dimensional structure model. The physical models include carrier transport model, mobility model, generation-recombination model, lattice self-heating model, and energy balance model; Fit the preset two-dimensional structure model and the preset three-dimensional structure model according to the measured electrical characteristic data to obtain the first electrical characteristic device model corresponding to the preset two-dimensional structure model and the second electrical characteristic device model corresponding to the preset three-dimensional structure model; Correspondingly, input the known thermal property parameters and the target thermal resistance value into the electrical characteristic device model to construct the initial device thermoelectric model, including: Input both the known thermal property parameters and the target thermal resistance value into the first electrical characteristic device model and the second electrical characteristic device model to construct the first initial device thermoelectric model corresponding to the preset two-dimensional structure model and the second initial device thermoelectric model corresponding to the preset three-dimensional structure model.

5. The method for device thermoelectric coupling modeling based on the TDTR technology according to claim 4, characterized in that The target surface temperature rise includes a first target surface temperature rise and a second target surface temperature rise, and the target temperature distribution includes a first target temperature distribution and a second target temperature distribution; At the same power density, fit the target surface temperature rise and target temperature distribution of the initial device thermoelectric model with the preset surface temperature rise and the preset temperature distribution to construct the thermoelectric coupling model of the semiconductor device, including: According to the preset surface temperature rise and the preset temperature distribution, fit the simulation software to make the first target surface temperature rise corresponding to the first initial device thermoelectric model the same as the preset surface temperature rise, and the first target temperature distribution the same as the preset temperature distribution; Determine the heating profile of the first initial device thermoelectric model according to the first target surface temperature rise and the first target temperature distribution; Import the heating profile into the second initial device thermoelectric model to obtain the second target surface temperature rise and the second target temperature distribution corresponding to the second initial device thermoelectric model, and fit the second target surface temperature rise and the second target temperature distribution with the preset surface temperature rise and the preset temperature distribution to construct the thermoelectric coupling model of the semiconductor device.

6. The method for device thermoelectric coupling modeling based on the TDTR technology according to claim 1, characterized in that After determining the known thermal property parameters of the first preset material and the unknown thermal property parameters of the second preset material of the preset semiconductor device, the method further includes: Determine the thickness of the preset dielectric layer of the second preset material through the preset semiconductor device design drawing, and the preset semiconductor device design drawing is used to record the thickness of the material corresponding to the unknown thermal property parameters; When the thickness of the second preset material is not less than the preset value, obtain the target thermal resistance value through the TDTR test.

7. The method for device thermoelectric coupling modeling based on the TDTR technology according to claim 1, characterized in that, When the preset dielectric layer thickness of the second preset material is less than a preset value, after preparing a plurality of samples with different thicknesses, the method further includes: Based on electromigration testing, thermal conductivity testing, and plating analysis, determine whether the upper material layer is suitable for the test sensing layer of the TDTR test or the upper material layer is not suitable for the test sensing layer of the TDTR test.

8. The method for device thermoelectric coupling modeling based on the TDTR technology according to claim 7, characterized in that After determining whether the upper material layer is suitable for the test sensing layer of the TDTR test or the upper material layer is not suitable for the test sensing layer of the TDTR test based on electromigration testing, thermal conductivity testing, and plating analysis, the method further includes: When the upper material layer is not suitable for the test sensing layer of the TDTR test, deposit a preset metal layer on the upper material layer, and the preset metal layer is a metal layer suitable for the TDTR test.

9. The method for thermoelectric coupling modeling of a device based on the TDTR technology according to claim 1, wherein The number of the plurality of samples is greater than or equal to 5.

10. The method for device thermoelectric coupling modeling based on the TDTR technology according to claim 1, wherein The target tests include infrared thermal imaging test, thermal reflection thermal imaging test, and microparticle Raman test.

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