Interface layout method and device for 3D chip, 3D chip, device and medium

Abstract

The invention discloses an interface layout method and device for a 3D chip, the 3D chip, a device and a medium. The interface layout method for the 3D chips comprises the steps that a signal interface area on a first chip in the 3D chips and a combinational logic area which corresponds to the signal interface area and is adjacently arranged in the first direction are determined, and the signal interface area is divided into a plurality of sub-signal areas at least in the first direction relative to the combinational logic area; obtaining a function parameter of each of a plurality of signal interfaces of the first chip and a construction parameter related to the combinational logic area; and determining a sub-signal area corresponding to each of the plurality of signal interfaces and the position in the corresponding sub-signal area based on the function parameters and the construction parameters of the plurality of signal interfaces. According to the interface layout method for the 3D chip, the interface layout efficiency and accuracy can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an interface layout method and device for a 3D chip, a 3D chip, a device, and a medium. Background Art

[0002] As chip technology develops, the industry has higher and higher requirements for the effective use of chip area and the reduction of power consumption. Although 3D packaging technology can double the number of transistors accommodated per unit chip area in three-dimensional space, since the signal communication between various modules of the chip is complex and dense, it is very important to strategically layout the various interface modules on the chip. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an interface layout method for a 3D chip, the interface layout method for a 3D chip comprising: determining a signal interface area on a first chip in the 3D chip and a combinational logic area corresponding to the signal interface area and adjacently arranged in a first direction, wherein the signal interface area is divided into a plurality of sub-signal areas relative to the combinational logic area at least in the first direction; obtaining functional parameters of each of the plurality of signal interfaces of the first chip and construction parameters related to the combinational logic area; and determining the sub-signal area corresponding to each of the plurality of signal interfaces and the position in the corresponding sub-signal area based on the respective functional parameters and construction parameters of the plurality of signal interfaces.

[0004] For example, in the interface layout method for a 3D chip provided in at least some embodiments of the present disclosure, the multiple signal interfaces include multiple input interfaces and multiple output interfaces; each of the multiple sub-signal areas includes an input interface unit and an output interface unit, the input interface unit is used to accommodate the input interface to be placed, and the output interface unit is used to accommodate the output interface to be placed.

[0005] For example, in the interface layout method for a 3D chip provided in at least some embodiments of the present disclosure, the corresponding sub-signal area of ​​each of the multiple signal interfaces and the position in the corresponding sub-signal area are determined based on the functional parameters and construction parameters of each of the multiple signal interfaces, including: in response to the signal transmitted by the first interface among the multiple signal interfaces being a timing relaxation signal, the first interface is placed in the third sub-signal area farthest from the combinational logic area in the first direction.

[0006] For example, in the interface layout method for a 3D chip provided by at least some embodiments of the present disclosure, the timing relaxation signal includes a multi-cycle signal or a non-timing signal.

[0007] For example, in the interface layout method for a 3D chip provided in at least some embodiments of the present disclosure, the corresponding sub-signal area of ​​each of the multiple signal interfaces and the position in the corresponding sub-signal area are determined based on the functional parameters and construction parameters of each of the multiple signal interfaces, and the method also includes: in response to the fan-out number or fan-in number of the first-level register corresponding to the second interface among the multiple signal interfaces being greater than a first preset value, placing the second interface in the first sub-signal area closest to the combinational logic area in the first direction, wherein the first-level register is located in the combinational logic area.

[0008] For example, in the interface layout method for a 3D chip provided by at least some embodiments of the present disclosure, the first preset value is set by a process library.

[0009] For example, in the interface layout method for a 3D chip provided in at least some embodiments of the present disclosure, the corresponding sub-signal area of ​​each of the multiple signal interfaces and the position in the corresponding sub-signal area are determined based on the functional parameters and construction parameters of each of the multiple signal interfaces, and the method also includes: in response to a first displacement parameter of a fan-out register or a fan-in register of a first-level register corresponding to a third interface among the multiple signal interfaces being greater than a second preset value in a second direction intersecting the first direction, the third interface is placed in a second sub-signal area or a first sub-signal area located between the third sub-signal area and the first sub-signal area in the first direction, wherein the fan-out register or the fan-in register is located in a combinational logic area.

[0010] For example, in the interface layout method for a 3D chip provided by at least some embodiments of the present disclosure, the second preset value is an average coordinate value of a fan-out register or a fan-in register of a first-level register corresponding to the third interface in the second direction.

[0011] For example, in the interface layout method for a 3D chip provided in at least some embodiments of the present disclosure, the corresponding sub-signal area of ​​each of the multiple signal interfaces and the position in the corresponding sub-signal area are determined based on the functional parameters and construction parameters of each of the multiple signal interfaces, and the method also includes: determining the position of the object interface in the corresponding object sub-signal area based on the interface evaluation coefficient and the coordinates of the fan-in register or the fan-out register corresponding to the object interface in the second direction, wherein the interface evaluation coefficient is determined based at least on the logical depth of the first-level register and the adjacent-level register and the displacement from the first-level register to the adjacent-level register in the first direction.

[0012] For example, in the interface layout method for a 3D chip provided in at least some embodiments of the present disclosure, the position of the object interface in the corresponding object sub-signal area is determined based on the interface evaluation coefficient and the coordinates of the fan-in register or the fan-out register corresponding to the object interface in the second direction, including: in response to the average coordinate value of the fan-in register or the fan-out register corresponding to the object interface in the second direction being greater than half of the height of the signal interface area in the second direction, the object interfaces are sorted according to the size of the interface evaluation coefficient and placed in a part of the object sub-signal area with a larger coordinate value in the second direction; in response to the average coordinate value of the fan-in register or the fan-out register corresponding to the object interface in the second direction being less than half of the height of the signal interface area in the second direction, the object interfaces are sorted according to the size of the interface evaluation coefficient and placed in a part of the object sub-signal area with a smaller coordinate value in the second direction.

[0013] For example, in the interface layout method for a 3D chip provided by at least some embodiments of the present disclosure, the interface evaluation coefficient is calculated according to the relation: Determine, where X m is the displacement from the first level register to the adjacent level register in the first direction, Q m is the logic depth between the first-level register and the adjacent-level register, and d is the buffer driving distance of the corresponding process of the first chip.

[0014] For example, in the interface layout method for a 3D chip provided in at least some embodiments of the present disclosure, the interface evaluation coefficients are sorted from small to large and the corresponding positions are placed from near to far from the center of the signal interface area.

[0015] For example, in the interface layout method for a 3D chip provided in at least some embodiments of the present disclosure, the 3D chip also includes a second chip stacked with the first chip, wherein at least some of the multiple signal interfaces of the first chip are used to communicate with the multiple signal interfaces in the second chip.

[0016] At least some embodiments of the present disclosure also provide an interface layout device for a 3D chip, the interface layout device for a 3D chip comprising a first determination module, an acquisition module, and a second determination module, the first determination module being configured to determine a signal interface area on a first chip under design and a combinational logic area corresponding to the signal interface area and adjacently arranged in a first direction, wherein the signal interface area is divided into a plurality of sub-signal areas relative to the combinational logic area at least in the first direction; the acquisition module being configured to acquire functional parameters of each of the plurality of signal interfaces of the first chip and construction parameters associated with the combinational logic area; the second determination module being configured to determine the corresponding sub-signal area of ​​each of the plurality of signal interfaces and the position in the corresponding sub-signal area based on the respective functional parameters and construction parameters of the plurality of signal interfaces.

[0017] At least one embodiment of the present disclosure further provides an electronic device, which includes at least one memory and at least one processor, wherein the at least one memory stores computer-executable instructions; and the at least one processor is configured to execute the computer-executable instructions. When the computer-executable instructions are executed by the at least one processor, the interface layout method for the 3D chip described in any of the above embodiments is implemented.

[0018] At least one embodiment of the present disclosure further provides a 3D chip, which includes a plurality of stacked chips, wherein an interface layout of a first chip among the plurality of stacked chips is determined according to the interface layout method for a 3D chip as described in any of the above embodiments.

[0019] At least some embodiments of the present disclosure also provide a non-transitory storage medium that non-transitory stores computer executable instructions, wherein when the computer executable instructions are executed by at least one processor, the interface layout method for a 3D chip provided in any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0021] Figure 1 A schematic diagram showing the interface layout of a chip.

[0022] Figure 2 A flow chart of an interface layout for a 3D chip provided by at least one embodiment of the present disclosure is shown.

[0023] Figure 3 A schematic diagram of an interface layout of a first chip provided by at least one embodiment of the present disclosure is shown.

[0024] Figure 4 A schematic diagram of an interface layout of a first chip provided by at least one embodiment of the present disclosure is shown.

[0025] Figure 5 An exemplary flow chart of an interface layout of a first chip provided by at least one embodiment of the present disclosure is shown.

[0026] Figure 6 A schematic structural diagram of a 3D chip provided by at least one embodiment of the present disclosure is shown.

[0027] Figure 7 A block diagram of an interface layout device for a 3D chip provided by at least one embodiment of the present disclosure is shown.

[0028] Figure 8 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0029] Fig. 9 A schematic structural diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0030] Fig.10 A schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0034] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0035] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0036] 3D chip technology can meet the needs of chip miniaturization and integration, and because 3D chip technology can also achieve interconnection and functional integration between different chips (dies) through through-silicon vias (TSV) in silicon wafers, it can significantly reduce the capacitance and inductance between different chips (dies). Therefore, the demand for chip combinations with cross-die interconnection is increasing, especially in the field of high-performance computing.

[0037] When a large number of signal lines need to be connected across chips, the layout distribution and layout strategy of the interface is a very important issue in chip design. In the cross-chip interconnection link of 3D chip technology, how to effectively layout the silicon through-hole or bond pad via (BPV) interface and how to optimize the layout distribution of the chip have become important operations to reduce the power consumption and latency of each chip (die).

[0038] For example, in the scenario of cross-chip (die) interconnection between stacked chips, since the upper and lower chips of the cross-chip interconnection need to interconnect power supply, clock signal and data signal, etc., the upper and lower chips of the interconnection need to have corresponding sending interfaces and receiving interfaces. For example, the upper chip is the main chip and the lower chip is the slave chip. For example, in order to interconnect data signals during preparation, the receiving interface on the main chip needs to be connected to the sending interface on the slave chip, and the sending interface on the main chip needs to be connected to the receiving interface on the slave chip.

[0039] Figure 1 A schematic diagram showing the interface layout of a chip.

[0040] like Figure 1As shown, the chip 510 includes an interface area 50 and a logic area 51. The interface area 50 is used to receive signals in the chip, and the logic area 51 is used to respond to and process the signals after receiving the signals from the interface area 50, for example, including digital circuit elements such as registers.

[0041] For example, the transmitting interface and receiving interface on the chip can be classified and combined according to the requirements of the process manufacturer. For example, the chip has multiple signal interface groups, where each a receiving interface is a group and each b transmitting interface is a group, where a and b are positive integers greater than 1. Figure 1 The interface area 50 includes a plurality of receiving interface groups 90 shown in dashed boxes and a plurality of transmitting interface groups 91 shown in solid boxes, each a receiving interface is divided into a receiving interface group 90, and each b transmitting interface is divided into a transmitting interface group 91. For example, these interface groups can be placed in the interface area where the upper chip and the lower chip are aligned.

[0042] Although the above layout can divide the interface area and the logic area into zones according to the receiving signal and the response signal, in the cross-chip (die) interconnection, the types of signals transmitted in the interface area are complicated and there are many response modules in the logic area. Therefore, there is still a problem that the signals transmitted in the interface area cannot be responded to in time by the logic area due to the unreasonable interface layout of the interface area, which in turn causes the delay and power consumption of the 3D chip to increase.

[0043] To address the above issues, all interfaces in the 3D chip can be repositioned based on timing requirements, or the positions can be adjusted by making some pre-judgments based on the different uses of receiving or transmitting signals by different interface groups.

[0044] However, the number of signals sent and received by each interface in the entire 3D chip is huge, and the relationship between each interface in the interface area and each module in the logic area is intricate. When laying out each interface in the interface area, only one-sided factors are considered to adjust the position, resulting in loss of focus and poor accuracy of the interface layout in the interface area. Moreover, if all factors are considered, the layout of each interface in the interface area needs to be repeatedly adjusted, resulting in low layout efficiency.

[0045] For example, when making layout adjustments, you need to consider whether the setup time of the first-level register (First-level Register) corresponding to the signal transmitted by a certain interface is met. "Setup time" is the minimum time that the signal needs to remain stable at the data input end of the first-level register. The first-level register is the register used to receive data first and ensure the data is correct. If the signal transmitted by a certain interface does not stabilize within the setup time (before the clock cycle arrives), the first-level register cannot correctly latch the data corresponding to the signal.

[0046] Therefore, in the 3D chip layout design, if the setup time of the first-level register cannot be met and it is difficult to optimize the situation through timing adjustment, then the interface area of ​​the upper chip and the lower chip in the 3D chip corresponds to the vertical transmission signal. It is necessary to reconsider the stacking method of the upper chip and the lower chip, the number and position of the interface, and the timing to optimize the layout. For example, all TSV or BPV interfaces in the interface area need to be reordered. The above method will cause the interface layout design in the interface area to have too many iterations and be unstable, making the layout inefficient.

[0047] For example, when performing layout adjustment, for interface groups that have been divided into groups, if some of the signals transmitted by the interfaces have setup time redundancy, for example, there is still enough timing margin after the latching is completed, the signals transmitted by other interfaces have setup time violations, for example, data latching or transmission cannot be completed within the specified timing requirements. Even if the interfaces corresponding to the setup time redundancy and the interfaces corresponding to the setup time violation are considered to be replaced, since the interface groups have been divided, it is still necessary to consider whether the interfaces in the original interface groups can be split out. For example, if multiple signal interfaces in a certain interface group all pass a single sequence signal, then any of the multiple signal interfaces in the interface group cannot be split. If the above factors are not considered during layout adjustment, the layout accuracy will be poor; however, if the above factors are considered during layout adjustment, the layout efficiency will be low due to the increase in judgment conditions.

[0048] For example, when performing layout adjustment, if the fan-out number (Fan-out) or fan-in number (Fan-in) of the first-level register of the signal transmitted by a certain interface is greater than 1, that is, the first-level register corresponds to multiple fan-out registers or multiple fan-in registers. If the multiple fan-out registers or multiple fan-in registers are far apart or set in the opposite direction relative to the interface, only adjusting the position of the interface cannot achieve a good effect, and additional adjustment measures for the number of TSV or BPV interfaces are required. If the above factors are not considered during layout adjustment, the layout accuracy will be poor, but if the above factors are considered during layout adjustment, the layout efficiency will be low due to the increase in judgment conditions.

[0049] Poor layout accuracy of the interface area in 3D chips can also lead to the ineffective use of chip area. For example, there will be some filling structures (Dummy Structures) in the chip that do not participate in the actual circuit function. Although these filling structures can improve the manufacturability and reliability of the chip, they also occupy the area of ​​the chip. For example, some interfaces in the TSV or BPV interface occupy a good position on the chip, resulting in restrictions on the layout of other important circuits. In order to maintain the reliability of the chip, there will be a problem of adding filling structures, which leads to a waste of chip area and affects the performance of the chip.

[0050] In response to at least one of the above problems, the present disclosure provides an interface layout method for a 3D chip, the interface layout method for a 3D chip comprising: determining a signal interface area on a first chip in the 3D chip and a combinational logic area corresponding to the signal interface area and adjacently arranged in a first direction, wherein the signal interface area is divided into a plurality of sub-signal areas relative to the combinational logic area at least in the first direction; obtaining functional parameters of each of the plurality of signal interfaces of the first chip and construction parameters related to the combinational logic area; and determining the sub-signal area corresponding to each of the plurality of signal interfaces and the position in the corresponding sub-signal area based on the respective functional parameters and construction parameters of the plurality of signal interfaces.

[0051] In the interface layout method for a 3D chip of the above-mentioned embodiment of the present disclosure, by acquiring the functional parameters of each of the multiple signal interfaces of the first chip and the construction parameters related to the combinational logic area, based on the functional parameters and construction parameters of the multiple signal interfaces, the sub-signal area corresponding to each of the multiple signal interfaces and the position in the corresponding sub-signal area are determined, and by, for example, pre-judgment of whether the signals in the multiple signal interfaces meet the timing requirements, the layout efficiency and accuracy of the interface layout design of the 3D chip are improved.

[0052] In at least one embodiment, resource allocation of signal interface locations is comprehensively considered based on functional parameters and structural parameters of each of the plurality of signal interfaces, so that the accuracy of interface layout design is improved and no signal interface is neglected.

[0053] Various embodiments of the present disclosure will be described below with reference to specific examples.

[0054] Figure 2 A flow chart of an interface layout for a 3D chip provided by at least one embodiment of the present disclosure is shown.

[0055] like Figure 2 As shown, in some embodiments of the present disclosure, the interface layout method for a 3D chip includes steps S30-S32.

[0056] Step S30: determining a signal interface region on a first chip in the 3D chip and a combinational logic region corresponding to the signal interface region and adjacent to the signal interface region in a first direction.

[0057] The first chip (die) can be any chip in the 3D chip. The first chip includes a signal interface area, which is used for data transmission and communication between the first chip and other chips on the 3D chip or other modules other than the 3D chip. The first chip also includes a combination logic area corresponding to the signal interface area and adjacently arranged in the first direction, and the combination logic area is used to perform a logical response to the signal transmitted in the signal interface area. The first direction is the direction in which the signal interface area is adjacent to the combination logic area. For example, if the signal interface area is adjacent to the combination logic area in the X-axis direction, the first direction is the X-axis direction; if the signal interface area is adjacent to the combination logic area in the Y-axis direction, the first direction is the Y-axis direction.

[0058] In some embodiments of the present disclosure, the signal interface region is divided into a plurality of sub-signal regions relative to the combinational logic region at least in a first direction.

[0059] For example, the signal interface area can be divided into a plurality of sub-signal areas in the first direction according to the different distance ranges between different areas in the signal interface area and the combination logic area. For example, an area in the signal interface area whose distance from the combination logic area is less than or equal to a first preset distance is divided into a first sub-signal area, for example, an area in the signal interface area whose distance from the combination logic area is greater than the first preset distance and less than or equal to a second preset distance is divided into a second sub-signal area, for example, an area in the signal interface area whose distance from the combination logic area is greater than the second preset distance is divided into a third sub-signal area.

[0060] It should be noted that, although the above description is based on dividing the signal interface area into three sub-signal areas, it does not limit the number of sub-signal areas that the signal interface area can be divided into. The above-mentioned first preset distance and second preset distance can be preset in any manner, and the present disclosure does not limit this. For example, the signal interface area can be divided into multiple sub-signal areas according to other factors or methods, and the specific division method is not limited in the present disclosure.

[0061] Step S31: Acquire functional parameters of each of the plurality of signal interfaces of the first chip and construction parameters related to the combinational logic area.

[0062] Functional parameters of each signal interface and construction parameters associated with the combinatorial logic area are parameters associated with the chip design of the first chip.

[0063] The functional parameters of each interface are used to reflect the relevant parameters of the interface and the signals transmitted by the interface. For example, the functional parameters can reflect the timing of the signals transmitted by the interface. For example, the functional parameters can also include the fan-in number or fan-out number of the first-level register corresponding to the interface in the combinational logic area.

[0064] The construction parameters associated with each interface and the combinational logic area reflect the relevant parameters of the interface and the signals transmitted by the interface in the combinational logic area. For example, the construction parameters may include the number and position of fan-in registers or the number and position of fan-out registers corresponding to the first-level register of the interface. For example, the construction parameters may include the displacement of the first-level register to the adjacent-level register in the first direction. For example, the construction parameters may include the logic depth (the meaning is described below) of the first-level register and the adjacent-level register.

[0065] It should be noted that the above lists only some possible examples of functional parameters and construction parameters, which does not represent a limitation on the parameters referred to by the functional parameters and construction parameters. The functional parameters and construction parameters of the present disclosure may also include more parameters and are not limited to the parameters listed above.

[0066] Step S32: Based on the functional parameters and construction parameters of the plurality of signal interfaces, determine the sub-signal area corresponding to each of the plurality of signal interfaces and the position in the corresponding sub-signal area.

[0067] For example, for multiple signal interfaces to be placed on the first chip, the sub-signal area corresponding to each signal interface is determined according to the functional parameters and construction parameters of each signal interface, and, in the corresponding sub-signal area, the position of the signal interface in the sub-signal area is determined, and the position includes, for example, XY coordinates in the sub-signal area.

[0068] It should be noted that, although the above embodiments point out the functional parameters and construction parameters corresponding to each of the multiple signal interfaces, the present disclosure does not limit the consideration of other parameters on this basis, for example, it is further based on the process parameters of the first chip, for example, the buffer drive distance of the corresponding process of the first chip.

[0069] In some embodiments of the present disclosure, for example, in the design process of a 3D chip, multiple signal interfaces can be grouped according to grouping conditions, and multiple signal interfaces that meet the same grouping conditions can be placed in the same unit or the same units. For example, multiple signal interfaces with the same transmission direction can be placed in the same unit, for example, multiple signal interfaces with completely consistent functions can be placed in the same unit, for example, multiple signal interfaces that transmit large bit width data can be placed in the same unit, for example, multiple signal interfaces that transmit single bit width data can be placed in the same unit, etc.

[0070] It should be noted that the grouping conditions can be arbitrarily designed according to the design requirements of the chip, and the present disclosure does not limit this.

[0071] In some embodiments of the present disclosure, in the above-mentioned interface layout method for a 3D chip, the multiple signal interfaces include multiple input interfaces and multiple output interfaces; each of the multiple sub-signal areas includes an input interface unit and an output interface unit, the input interface unit is used to accommodate multiple input interfaces to be placed, and the output interface unit is used to accommodate multiple output interfaces to be placed.

[0072] For example, the interface layout method according to at least one embodiment of the present disclosure may be implemented by software, for example, by electronic design automation software.

[0073] Figure 3 A schematic diagram of an interface layout of a first chip provided by at least one embodiment of the present disclosure is shown.

[0074] like Figure 3 As shown, the first chip 410 includes a signal interface area 11 and a combinational logic area 12 adjacent to the signal interface area 11 in a first direction X, the signal interface area 11 includes a plurality of output interface units 20 and a plurality of input interface units 21; each output interface unit 20 is used to accommodate an output interface to be placed, and each input interface unit 21 is used to accommodate an input interface to be placed, where the output interface and the input interface are divided according to the transmission direction of the transmitted signal with respect to the first chip 410.

[0075] The signal interface area 11 is divided into a first sub-signal area 100, a second sub-signal area 200 and a third sub-signal area 300. The first sub-signal area 100, the second sub-signal area 200 and the third sub-signal area 300 are divided according to the different distance ranges between different areas in the signal interface area and the combinational logic area 12.

[0076] In some embodiments of the present disclosure, step S32 in the above-mentioned interface layout method for a 3D chip includes step S320.

[0077] Step S320: In response to the signal transmitted by the first interface among the plurality of signal interfaces being a timing relaxation signal, placing the first interface in a third sub-signal region farthest from the combinational logic region in the first direction.

[0078] In some embodiments of the present disclosure, in the above-mentioned interface layout method for a 3D chip, the timing relaxation signal includes a multi-cycle signal or a non-timing signal.

[0079] The first interface may be any one of a plurality of signal interfaces for transmitting a timing relaxation signal.

[0080] like Figure 3 As shown, the third signal sub-area 300 is the area in the signal interface area 11 that is the farthest from the combinational logic area 01 in the first direction. For example, the third signal sub-area is the area in the signal interface area that is farther from the combinational logic area than the second preset distance.

[0081] A timing-relaxed signal is a signal that does not need to be transmitted within one timing cycle, for example, a multi-cycle path signal or a false path signal. A multi-cycle signal is a signal that requires multiple timing cycles to complete transmission from one module to another, and a false path signal is a signal that does not need to meet any timing requirements.

[0082] The timing cycle is also called the clock cycle. In the signal transmission of the chip, it refers to the basic time unit required to complete a complete signal transmission cycle.

[0083] By setting the signal interface for transmitting the timing relaxation signal in the third sub-signal area farthest from the combinational logic area, the area in the signal interface area farthest from the combinational logic area can be fully utilized without affecting the function of the signal transmitted by the signal interface, making the layout of the signal interface more accurate.

[0084] In some embodiments of the present disclosure, step S32 in the above-mentioned interface layout method for a 3D chip further includes step S321 .

[0085] Step S321: In response to a fan-out number or a fan-in number of a first-level register corresponding to a second interface among the plurality of signal interfaces being greater than a first preset value, placing the second interface in a first sub-signal region closest to the combinational logic region in a first direction.

[0086] The second interface is any signal interface among the plurality of signal interfaces whose fan-out number or fan-in number corresponding to the first-level register in the combinational logic area is greater than the first preset value. The first preset value may be a preset value or value ratio, which is not limited in the present disclosure.

[0087] In some embodiments of the present disclosure, the first level register is located in the combinatorial logic area.

[0088] The first-level register is the register that the signal passes through first in the data path. For example, it is a register directly connected to the input interface unit or the output interface unit in the combinational logic area, which is used to capture and temporarily store data for subsequent processing or transmission. Depending on whether the interface unit functions as an input interface unit or an output interface unit, the first-level register can be an input register or an output register.

[0089] like Figure 3 As shown, the first sub-signal area 100 is the area in the signal interface area 11 that is the shortest distance from the combinational logic area 12 in the first direction. For example, the first sub-signal area 100 is the area in the signal interface area 11 that is less than or equal to the first preset distance from the combinational logic area 12. The first sub-signal area 100 is provided with a plurality of output interface units 20 and a plurality of input interface units 21.

[0090] For example, a signal transmitted by any output interface unit 20 is correspondingly output to the first-level register 30 , and the first-level register 30 obtains the fan-in number (Fan-in) of the output interface unit 20 , wherein the first-level register 30 is also called an output register.

[0091] For example, a signal transmitted by any input interface unit 21 is output to the first-level register 31, and the first-level register 31 obtains the fan-out number (Fan-out) of the input interface unit 21, wherein the first-level register 31 is also called an input register.

[0092] In chip design, the fan-in number usually refers to the number of input signals that a logic gate or register can receive, and the fan-out number refers to the number of next-level logic gates or registers that a logic gate or register can drive.

[0093] The corresponding second interface for the first-level register whose fan-out number or fan-in number is greater than the first preset value is set in the first sub-signal area, so that the second interfaces logically associated with more modules in the combinational logic area can be placed in the area closest to the combinational logic area, thereby reducing the signal delay of these interfaces and improving the performance of the chip.

[0094] In some embodiments of the present disclosure, in the above-mentioned interface layout method for a 3D chip, the first preset value is set by a process library.

[0095] The process library is a collection of parameters and models used to describe the manufacturing process in the chip design. For example, the process library includes default environment properties and default parameter settings (also called Default values). For example, the default parameter settings of the process library include the default maximum fan-in number of the first-level register or the default maximum fan-out number of the first-level register. For example, the first preset value can be set to the default maximum fan-in number or the default maximum fan-out number. For example, the first preset value can be set to a specific proportion of the default maximum fan-in number or the default maximum fan-out number. For example, the first preset value is 70% of the default maximum fan-in number or 70% of the default maximum fan-out number.

[0096] In some embodiments of the present disclosure, step S32 in the interface layout method for a 3D chip further includes step S322.

[0097] Step S322: In response to the first displacement parameter of the fan-out register or the fan-in register of the first-level register corresponding to the third interface among the multiple signal interfaces being greater than a second preset value in a second direction intersecting the first direction, the third interface is placed in the second sub-signal area or the first sub-signal area located between the third sub-signal area and the first sub-signal area in the first direction.

[0098] As described above, the fan-out register or the fan-in register is located in the combinatorial logic area.

[0099] The fan-out number of the first-level register corresponds to the number of fan-out registers of the first-level register, and the fan-out register is also called the next-level register of the first-level register. The fan-in number of the first-level register corresponds to the number of fan-in registers of the first-level register, and the fan-in register is also called the previous-level register of the first-level register.

[0100] The second direction is a direction intersecting the first direction (for example, a direction intersecting perpendicularly). If the fan-out number or fan-in number of the first-level register corresponding to the third interface is equal to 1, then the number of fan-out registers or fan-in registers corresponding to the third interface is 1. At this time, the first displacement parameter in the second direction is the distance between the fan-out register or fan-in register and the first-level register on the chip in the second direction; if the fan-out number or fan-in number of the first-level register corresponding to the third interface is greater than 1, then the number of fan-out registers or fan-in registers corresponding to the third interface is multiple. At this time, the first displacement parameter in the second direction is the maximum distance between all fan-out registers or all fan-in registers in the second direction.

[0101] like Figure 3 As shown, the second sub-signal area 200 is an area in the signal interface area 11 that is farther from the combinational logic area 12 than the first sub-signal area 100 in the first direction and closer to the combinational logic area 12 than the third sub-signal area 300 in the first direction. For example, the second sub-signal area is an area in the signal interface area 11 that is farther from the combinational logic area 12 than the first preset distance and less than or equal to the second preset distance.

[0102] For example, refer to Figure 3 , with the lower left corner of the first chip as the origin (0,0), the first direction is the X-axis direction, and the second direction is the Y-axis direction. For example, the first-level register 30 is an output register, and its coordinates are (x0, y0).

[0103] For example, when the fan-out number or fan-in number of the first-level register corresponding to the third interface is equal to 1, the first shift parameter Y s is equal to the absolute value of the Y-axis coordinate of the fan-out register or the fan-in register and y0. For example, the coordinates of the first-level register 30 of the output interface unit 20 are (x0, y0), the coordinates of the fan-in register 40 are (x1, y1), and the first displacement parameter Ys =abs(y1-y0).

[0104] When the fan-out number or fan-in number of the first-level register corresponding to the third interface is greater than 1, the first displacement parameter Y s is equal to the maximum value of the distance between all fan-in registers 40 in the Y-axis direction. For example, the fan-in number of the first-level register 30 of the output interface unit 20 is n, where n is a positive integer, and the maximum distance between the n fan-in registers 40 in the Y-axis is yn-y1, then the first displacement parameter Y s =yn-y1.

[0105] The second preset value can be an arbitrarily set value, which is not limited in the present disclosure. When the first displacement parameter is greater than the second preset value, the third interface is placed in the second sub-signal area or the first sub-signal area located between the third sub-signal area and the first sub-signal area in the first direction.

[0106] For example, the first sub-signal area may be placed first, and when the first sub-signal area is full, the second sub-signal area may be placed.

[0107] It should be noted that, although the above embodiments of the present disclosure are Figure 3 The first direction is exemplified as the X-axis direction and the second direction is the Y-axis direction, but it does not limit the specific directions of the first direction and the second direction. For example, the first direction may be the Y-axis direction and the second direction may be the X-axis direction. For example, the first direction may be the X-axis direction and the second direction may be other directions intersecting the first direction.

[0108] In some embodiments of the present disclosure, in the above-mentioned interface layout method for a 3D chip, the second preset value is an average coordinate value of a fan-out register or a fan-in register of a first-level register corresponding to the third interface in the second direction.

[0109] For example, when the fan-out number or fan-in number of the first-level register corresponding to the third interface is equal to 1, the number of fan-out registers or fan-in registers is 1, and the coordinates of the fan-in register 40 are (x1, y1), then the second preset value Y a =y1.

[0110] For example, when the fan-out number or fan-in number of the first-level register corresponding to the third interface is greater than 1, the number of fan-out registers or fan-in registers is multiple, for example, the number of fan-out registers or fan-in registers is n, where n is a positive integer, then the second preset value Y a =(y1+y2+……+yn) / n.

[0111] When the first displacement parameter is greater than the second preset value, that is, Y s >Y aAt this time, the third interface is placed in the second sub-signal area located between the third sub-signal area and the first sub-signal area in the first direction or in the first sub-signal area (if the first sub-signal area still allows continued layout).

[0112] In some embodiments of the present disclosure, step S32 in the above-mentioned interface layout method for a 3D chip further includes step S323.

[0113] Step S323: Determine the position of the object interface in the corresponding object sub-signal area based on the interface evaluation coefficient and the coordinates of the fan-in register or the fan-out register corresponding to the object interface in the second direction.

[0114] The object interface is any one of the second interface and the third interface as the interface describing the object, and the object sub-signal area is any one of the first sub-signal area and the second sub-signal area as the sub-signal area describing the object.

[0115] For example, the interface evaluation coefficient is determined based on at least the logic depth of the first-level register and the adjacent-level register and the displacement from the first-level register to the adjacent-level register in the first direction.

[0116] The adjacent level register is a previous level register of the first level register or a next level register of the first level register. For example, the adjacent level register may be a fan-in register or a fan-out register.

[0117] The logical depth between the first-level register and the adjacent-level register may be the logical depth from the previous-level register (also called the starting register) to the first-level register (also called the ending register); or it may be the logical depth from the first-level register (also called the starting register) to the next-level register (also called the ending register).

[0118] The start register and the end register are determined according to the timing path of the signal within the timing cycle and are related to the transmission direction of the signal.

[0119] Here the logical depth Q m is the number of logic units passed from the start register to the end register. These passed logic units include various logic gate level units, such as AND gates, OR gates, and AND-OR gates, etc. These passed logic units do not include inverters (INV) and buffers (BUF).

[0120] The displacement X in the first direction from the first level register to the adjacent level register m It is the absolute value of the difference between the coordinate values ​​of the fan-in register or the fan-out register and the first-level register in the first direction.

[0121] For example, refer to Figure 3, the coordinates of the fan-in register 40 are (x1, y1), and the coordinates of the first-level register 30 are (x0, y0), then the displacement X m =abs(x1-x0).

[0122] The interface evaluation coefficient f(m) is based on the logic depth Q m and displacement X m Determine. Based on the interface evaluation coefficient f(m) and the coordinates of the fan-in register or fan-out register corresponding to the object interface in the second direction, determine the position of the object interface in the corresponding object sub-signal area. For example, determine the average coordinates of all fan-in registers or all fan-out registers corresponding to the object interface in the second direction.

[0123] For example, the order in which each object interface is placed in the object sub-signal area is determined according to the size of the interface evaluation coefficient, and the coordinates of the placement position of the object interface in the object sub-interface area are determined according to the coordinates of the fan-in register or fan-out register corresponding to the object interface in the second direction.

[0124] In some embodiments of the present disclosure, when there are multiple adjacent level registers to a first level register, the interface evaluation coefficient can be determined based on the maximum logic depth between the first level register and the multiple adjacent level registers and the maximum displacement from the first level register to the multiple adjacent level registers in the first direction.

[0125] In some embodiments of the present disclosure, in the above-mentioned interface layout method for a 3D chip, the interface evaluation coefficient is also determined based on a buffer driving distance of a corresponding process of the first chip.

[0126] For example, in the process corresponding to the first chip, the buffer driving distance d is the maximum transmission distance that the buffer can effectively drive the signal, and this distance refers to the maximum allowable distance from the buffer output to the input of the load (such as the next logic gate or register). The buffer driving distance d is related to the specific corresponding process of the first chip. For example, the buffer driving distance d is the maximum transmission distance that a medium-to-large buffer can effectively drive the signal in the process corresponding to the first chip.

[0127] In some embodiments of the present disclosure, in the above-mentioned interface layout method for a 3D chip, the interface evaluation coefficient is determined according to the following relationship:

[0128]

[0129] Among them, X m is the displacement from the first level register to the adjacent level register in the first direction, Q m is the logic depth between the first-level register and the adjacent-level register, and d is the buffer driving distance of the corresponding process of the first chip.

[0130] For example, the relationship between the interface evaluation coefficients of the object interfaces to be placed can be determined through the relationship formula of the interface evaluation coefficients; according to the relationship between the interface evaluation coefficients of the object interfaces to be placed, the placement order of the object interfaces to be placed can be determined.

[0131] For example, object interfaces with small interface evaluation coefficients may be placed first, and object interfaces with large interface evaluation coefficients may be placed later.

[0132] In some embodiments of the present disclosure, step S323 in the above-mentioned interface layout method for a 3D chip further includes step S3230 and step S3231.

[0133] Step S3230: In response to the average coordinate value of the fan-in register or fan-out register corresponding to the object interface in the second direction being greater than half of the height of the signal interface area in the second direction, the object interfaces are sorted according to the size of the interface evaluation coefficients and placed in the part with larger coordinate values ​​in the second direction of the object sub-signal area.

[0134] Step S3231: In response to the average coordinate value of the fan-in register or fan-out register corresponding to the object interface in the second direction being less than half the height of the signal interface area in the second direction, the object interfaces are sorted according to the size of the interface evaluation coefficients and placed in the part of the object sub-signal area with smaller coordinate values ​​in the second direction.

[0135] For example, Figure 3 As shown, half of the height of the signal interface area 11 in the second direction Y axis is Y m , the average coordinate value of the fan-in register or fan-out register corresponding to the object interface in the second direction is Y a , then compare Y m With Y a The size relationship determines the arrangement position of the object interface in the object sub-signal area.

[0136] For example, when Y a ≥Y m , the object interfaces are sorted according to the size of the interface evaluation coefficients and placed in the part with larger coordinate values ​​in the second direction in the object sub-signal area. Figure 3 As shown, if the object sub-signal area where the object interface is placed is the first sub-signal area 100, then the Y a ≥Y m The object interface is placed in the first signal sub-area 100 and the coordinate value of the Y axis direction is greater than Y m part.

[0137] For example, when Y a <Y m, sort the object interfaces according to the interface evaluation coefficients and place them in the part of the object sub-signal area with smaller coordinate values ​​in the second direction. a <Y m The object interface is placed in the first signal sub-area 100 and the coordinate value of the Y axis direction is less than Y m part.

[0138] In some embodiments of the present disclosure, the interface layout method for a 3D chip further includes step S3232.

[0139] Step S3232: Sort the interface evaluation coefficients from small to large and place them in positions from near to far from the center of the signal interface area.

[0140] like Figure 3 As shown, for example, the center of the signal interface area 11 is point C. After each object interface has determined its corresponding object sub-signal area, the object interfaces can be placed at positions closer to the center point C in the object sub-signal area according to the order of the interface evaluation coefficients of each object interface. Interfaces with smaller interface evaluation coefficients can be placed at positions farther from the center point C in the object sub-signal area, while interfaces with larger interface evaluation coefficients can be placed at positions farther from the center point C in the object sub-signal area.

[0141] After each object interface determines its corresponding object sub-signal area, each object interface can be placed in its own object sub-signal area according to the order of the interface evaluation coefficient from small to large, and from near to far from the center of the signal interface area.

[0142] Figure 4 A schematic diagram of an interface layout of a first chip provided by at least one embodiment of the present disclosure is shown.

[0143] like Figure 4 As shown, the signal interface area 11 can be divided into sub-signal areas in other forms according to the different distance ranges between different areas in the signal interface area and the combinational logic area 12. The signal interface area 11 is divided into a first sub-signal area 100, a second sub-signal area 200 and a third sub-signal area 300, wherein the second sub-signal area 200 can also be divided into a first type of second sub-signal area 200-1, a second type of second sub-signal area 200-2 and a third type of second sub-signal area 200-3 according to the different distance ranges between the second sub-signal area 200 and the combinational logic area 12.

[0144] It should be noted that Figure 4 It is only shown that the second signal sub-area 200 is further divided into three categories, but it does not limit the number of further divisions of the second signal sub-area.

[0145] It should be noted that Figure 4The first-level register 31 and the fan-out register 41 shown in FIG. 1 and the layout method of the corresponding signal interface according to the first-level register 31 and the fan-out register 41 are consistent with the above disclosure of Figure 3 The descriptions of the first-level register 30 and the fan-in register 40 are the same, and are not repeated in this disclosure.

[0146] Figure 5 An exemplary flow chart of an interface layout of a first chip provided by at least one embodiment of the present disclosure is shown.

[0147] like Figure 5 As shown, when performing interface layout on the first chip, simulation can be performed in a software simulation manner.

[0148] For example, the interface model area is Figure 3 and Figure 4 The interface model area corresponds to the signal interface area 11 shown, and the interface model area corresponds to the sub-signal area division of the signal interface area 11.

[0149] For example, the interface models corresponding to the signal interfaces to be placed may be grouped according to the grouping conditions, and then the logic code of the interface model may be generated to simulate and generate the signals transmitted by the signal interfaces to be placed.

[0150] Detect whether the signal transmitted by the interface model contains a timing relaxation signal. If so, determine that these interface models are placed in the third sub-signal area, thereby determining that the corresponding signal interface should be placed in the third sub-signal area; if not, continue to judge.

[0151] Determine whether the fan-out number or fan-in number of the first-level registers of the interface model is greater than 70% of the maximum fan-out number in the process library. If so, place these interface models in the first sub-signal area to determine whether the corresponding signal interface should be placed in the first sub-signal area, where the placement order refers to the interface evaluation coefficient; if not, continue to judge.

[0152] Determine the first displacement parameter Y of the fan-out register or fan-in register of the interface model s Is it greater than half the height of the interface signal area Y m If so, place these interface models in the first sub-signal area; after the first sub-signal area is full, place them in the middle area of ​​the first type of second sub-signal area; then place them in the middle area of ​​the second type of second sub-signal area, so as to determine the placement area of ​​the signal interfaces corresponding to these interface models; if not, further classify them.

[0153] The interface model is the input interface model. The order of input interface models is determined based on the interface evaluation coefficient f(m) of the input interface model, combined with the average coordinate value Y a Determine the coordinates in a certain sub-signal area and place all input interface models into the interface model area.

[0154] The interface model is an output interface model. The output interface model ranking order is determined based on the interface evaluation coefficient f(m) of the output interface model, combined with the average coordinate value Y a Determine the coordinates of a certain sub-signal area and place all output interface models into the interface model area.

[0155] It should be noted that the input interface model and the output interface model are arranged in the order according to the interface evaluation coefficient f(m), and the average coordinate value Y a Determining the coordinates of a certain sub-signal area and placing the input interface model or the output interface model into multiple sub-signal areas divided in the interface model area is the same as the method described in the previous embodiment of the present disclosure, and the technical effect is also the same, so it will not be repeated here.

[0156] For example, in the interface layout method for a 3D chip provided in at least some embodiments of the present disclosure, the 3D chip also includes a second chip stacked with the first chip, wherein at least some of the multiple signal interfaces of the first chip are used to communicate with the multiple signal interfaces in the second chip.

[0157] Figure 6 A schematic structural diagram of a 3D chip provided by at least one embodiment of the present disclosure is shown.

[0158] like Figure 6 As shown, the 3D chip 2000 includes a first chip 410 and a second chip 420 , wherein the second chip 420 is stacked with the first chip 410 , and the first chip 410 and the second chip 420 are any two stacked chips among a plurality of stacked chips in the 3D chip 2000 .

[0159] For example, any output interface unit 20 of the signal interface area 11 in the first chip 410 is stacked with an input interface unit 21 in the second chip, and any input interface unit 21 of the signal interface area 11 in the first chip 410 is stacked with an output interface unit 20 in the second chip.

[0160] At least one embodiment of the present disclosure further provides a 3D chip, which includes multiple stacked chips, and the interface layout of at least one chip (for example, the first chip) among the multiple stacked chips is determined according to the interface layout method for the 3D chip described in any of the above embodiments.

[0161] The 3D chip of the above-mentioned embodiment of the present disclosure is manufactured by an interface layout method for a 3D chip, so that the 3D chip has a reasonably planned interface layout, thereby reducing the filling structure added due to unreasonable interface layout, and improving the interface layout efficiency of any chip in the 3D chip.

[0162] Furthermore, since the 3D chip has a reasonable interface layout determined by the interface layout method for the 3D chip, the performance of the 3D chip is improved and the delay caused by the unreasonable interface layout in the 3D chip is reduced.

[0163] Figure 7 A block diagram of an interface layout device for a 3D chip provided by at least one embodiment of the present disclosure is shown.

[0164] like Figure 7 As shown, at least one embodiment of the present disclosure further provides an interface layout device 800 for a 3D chip, including a first determination module 801 , an acquisition module 802 , and a second determination module 803 .

[0165] The first determination module 801 is configured to determine a signal interface area on a first chip under design and a combinational logic area corresponding to the signal interface area and adjacently arranged in a first direction, wherein the signal interface area is divided into a plurality of sub-signal areas relative to the combinational logic area at least in the first direction.

[0166] The acquisition module 802 is configured to acquire functional parameters of each of the plurality of signal interfaces of the first chip and construction parameters related to the combinational logic region.

[0167] The second determination module 803 is configured to determine the corresponding sub-signal area of ​​each of the plurality of signal interfaces and the position in the corresponding sub-signal area based on the functional parameters and the construction parameters of each of the plurality of signal interfaces.

[0168] The multiple signal interfaces may include multiple input interfaces and multiple output interfaces; each sub-signal area in the multiple sub-signal areas may include an input interface unit and an output interface unit, the input interface unit is configured to accommodate the input interface to be placed, and the output interface unit is configured to accommodate the output interface to be placed.

[0169] The second determination module 803 is further configured to place the first interface among the plurality of signal interfaces in a third signal sub-area farthest from the combinational logic area in the first direction in response to the signal transmitted by the first interface being a timing relaxation signal.

[0170] The timing relaxation signal may include a multi-cycle signal or a non-timing signal.

[0171] The second determination module 803 is also configured to place the second interface in the plurality of signal interfaces into a first sub-signal area closest to the combinational logic area in the first direction in response to the fan-out number or fan-in number of the first-level register corresponding to the second interface being greater than a first preset value, wherein the first-level register is located in the combinational logic area.

[0172] The second determination module 803 is also configured to place the third interface in the second sub-signal area or the first sub-signal area located between the third sub-signal area and the first sub-signal area in the first direction in response to a first displacement parameter of a fan-out register or a fan-in register of a first-level register corresponding to a third interface among the multiple signal interfaces being greater than a second preset value in a second direction intersecting the first direction, wherein the fan-out register or the fan-in register is located in the combinational logic area.

[0173] The first preset value may be set by a process library, and the second preset value may be an average coordinate value of a fan-out register or a fan-in register of a first-level register corresponding to the third interface in the second direction.

[0174] The second determination module 803 is also configured to determine the position of the object interface in the corresponding object sub-signal area based on the interface evaluation coefficient and the coordinates of the fan-in register or the fan-out register corresponding to the object interface in the second direction, wherein the interface evaluation coefficient is determined based at least on the logical depth of the first-level register and the adjacent-level register and the displacement from the first-level register to the adjacent-level register in the first direction.

[0175] The second determination module 803 is further configured to, in response to the average coordinate value of the fan-in register or fan-out register corresponding to the object interface in the second direction being greater than half of the height of the signal interface area in the second direction, sort the object interfaces according to the size of the interface evaluation coefficient and place them in the part of the object sub-signal area with larger coordinate values ​​in the second direction; in response to the average coordinate value of the fan-in register or fan-out register corresponding to the object interface in the second direction being less than half of the height of the signal interface area in the second direction, sort the object interfaces according to the size of the interface evaluation coefficient and place them in the part of the object sub-signal area with smaller coordinate values ​​in the second direction.

[0176] The interface evaluation coefficient can be determined according to the following relationship:

[0177]

[0178] Among them, X m is the displacement from the first level register to the adjacent level register in the first direction, Q m is the logic depth between the first-level register and the adjacent-level register, and d is the buffer driving distance of the corresponding process of the first chip.

[0179] The second determination module 803 is further configured to place the interfaces in a descending order according to the order of the interface evaluation coefficients, corresponding to the positions from near to far from the center of the signal interface area.

[0180] The technical effect of the interface layout device for a 3D chip in the above embodiment of the present disclosure is the same as the technical effect of the interface layout method for a 3D chip, and thus will not be described in detail.

[0181] Figure 8 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0182] like Figure 8 As shown, at least one embodiment of the present disclosure further provides an electronic device 600 , including at least one memory 610 and at least one processor 620 .

[0183] At least one memory 610 is configured to store computer executable instructions. At least one processor 620 is configured to execute computer executable instructions, wherein the computer executable instructions are executed by at least one processor to implement the interface layout method for a 3D chip provided in any embodiment of the present disclosure. The processor can be, for example, any processing circuit with processing capabilities, which can be implemented by hardware or firmware, such as a processor (CPU), etc. The memory can include, for example, a semiconductor memory. The embodiments of the present disclosure do not limit the implementation of the memory 610 and the processor 620.

[0184] The technical effect of the electronic device of the above embodiment of the present disclosure is the same as the technical effect of the above interface layout method for a 3D chip, and thus will not be described in detail.

[0185] At least one embodiment of the present disclosure further provides an electronic device, wherein the electronic device can be used to implement the interface layout method for a 3D chip recorded in at least one of the above embodiments, or includes a 3D chip recorded in at least one of the above embodiments.

[0186] Fig. 9 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0187] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig. 9 The electronic device 1000 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0188] For example, refer to Fig. 9In some examples, the electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processor, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 to a random access memory (RAM) 1003, such as for implementing an interface layout method for a 3D chip as described in at least one of the above embodiments, or for example, the processing device includes a 3D chip as described in at least one of the above embodiments. Various programs and data required for the operation of the computer system are also stored in RAM 1003. The processing device 1001, ROM 1002, and RAM 1003 are connected to each other via an Internet 1004. An input / output (I / O) interface 1005 is also connected to the Internet 1004.

[0189] For example, the following components may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 1010 is also connected to the I / O interface 1005 as needed. Removable media 1011, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1010 as needed, so that the computer program read therefrom can be installed into the storage device 1008 as needed. Although Fig. 9 The electronic device 1000 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0190] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0191] For example, the electronic device 1000 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0192] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer executable instructions. For example, when the computer executable instructions are executed by a processor, the interface layout method for a 3D chip provided by at least one embodiment of the present disclosure is implemented.

[0193] Fig.10 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. Fig.10 As shown, the non-transitory storage medium 900 can store computer executable instructions 910 in a non-transitory manner. When the computer executable instructions 910 are executed by a computer, the interface layout method for a 3D chip provided by any embodiment of the present disclosure is implemented.

[0194] There are a few points to note about this disclosure:

[0195] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0196] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0197] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for layout of interfaces for a 3D chip, comprising: Determine a signal interface area on a first chip in the 3D chip and a combinational logic area corresponding to the signal interface area and adjacent to the combinational logic area in a first direction, wherein the signal interface area is divided into a plurality of sub-signal areas relative to the combinational logic area at least in the first direction; Acquire functional parameters of each of a plurality of signal interfaces of the first chip and construction parameters related to the combinational logic area; Based on the functional parameters and construction parameters of the plurality of signal interfaces respectively, a sub-signal area corresponding to each of the plurality of signal interfaces and a position in the corresponding sub-signal area are determined.

2. The interface layout method for a 3D chip according to claim 1, wherein: The plurality of signal interfaces include a plurality of input interfaces and a plurality of output interfaces; each of the plurality of sub-signal areas includes an input interface unit and an output interface unit, The input interface unit is used to accommodate the input interface to be placed, and the output interface unit is used to accommodate the output interface to be placed.

3. The interface layout method for a 3D chip according to claim 1, wherein: The determining, based on the functional parameters and construction parameters of each of the plurality of signal interfaces, a corresponding sub-signal area of ​​each of the plurality of signal interfaces and a position in the corresponding sub-signal area comprises: In response to a signal transmitted by a first interface among the plurality of signal interfaces being a timing relaxation signal, the first interface is placed in a third sub-signal area farthest from the combinatorial logic area in the first direction.

4. The interface layout method for a 3D chip according to claim 3, wherein: The timing relaxation signal includes a multi-cycle signal or a non-timing signal.

5. The interface layout method for a 3D chip according to claim 3, wherein: The determining, based on the functional parameters and construction parameters of each of the plurality of signal interfaces, a corresponding sub-signal area of ​​each of the plurality of signal interfaces and a position in the corresponding sub-signal area further comprises: In response to a fan-out number or a fan-in number of a first-level register corresponding to a second interface among the plurality of signal interfaces being greater than a first preset value, placing the second interface in a first sub-signal area closest to the combinational logic area in the first direction, Wherein, the first-level register is located in the combinational logic area.

6. The interface layout method for a 3D chip according to claim 5, wherein: The first preset value is set by a process library.

7. The interface layout method for a 3D chip according to claim 5, wherein: The determining, based on the functional parameters and construction parameters of each of the plurality of signal interfaces, a corresponding sub-signal area of ​​each of the plurality of signal interfaces and a position in the corresponding sub-signal area further comprises: In response to a first displacement parameter of a fan-out register or a fan-in register of a first-level register corresponding to a third interface among the plurality of signal interfaces being greater than a second preset value in a second direction intersecting the first direction, placing the third interface in a second sub-signal area or the first sub-signal area located between the third sub-signal area and the first sub-signal area in the first direction, The fan-out register or the fan-in register is located in the combinational logic area.

8. The interface layout method for a 3D chip according to claim 7, wherein: The second preset value is an average coordinate value of a fan-out register or a fan-in register of a first-level register corresponding to the third interface in the second direction.

9. The interface layout method for a 3D chip according to claim 7, wherein: The determining, based on the functional parameters and construction parameters of each of the plurality of signal interfaces, a corresponding sub-signal area of ​​each of the plurality of signal interfaces and a position in the corresponding sub-signal area further comprises: Based on the interface evaluation coefficient and the coordinates of the fan-in register or the fan-out register corresponding to the object interface in the second direction, determining the position of the object interface in the corresponding object sub-signal area, The interface evaluation coefficient is determined based on at least the logic depth of the first-level register and the adjacent-level register and the displacement from the first-level register to the adjacent-level register in the first direction.

10. The interface layout method for a 3D chip according to claim 9, wherein: The determining, based on the interface evaluation coefficient and the coordinates of the fan-in register or the fan-out register corresponding to the object interface in the second direction, the position of the object interface in the corresponding object sub-signal area comprises: In response to the average coordinate value of the fan-in register or the fan-out register corresponding to the object interface in the second direction being greater than half of the height of the signal interface area in the second direction, the object interface is sorted according to the size of the interface evaluation coefficient and placed in a part of the object sub-signal area with a larger coordinate value in the second direction; In response to the average coordinate value of the fan-in register or fan-out register corresponding to the object interface in the second direction being less than half the height of the signal interface area in the second direction, the object interface is sorted according to the size of the interface evaluation coefficient and placed in the part with the smaller coordinate value in the second direction of the object sub-signal area.

11. The interface layout method for a 3D chip according to claim 10, wherein the interface evaluation coefficient is determined according to the following relationship: in, X m is the displacement from the first-level register to the adjacent-level register in the first direction, Q m is the logic depth between the first-level register and the adjacent-level register, and d is the buffer driving distance of the corresponding process of the first chip.

12. The interface layout method for a 3D chip according to claim 10, wherein: The sorting according to the size of the interface evaluation coefficients includes: According to the order of the interface evaluation coefficients from small to large, the corresponding positions are placed from near to far from the center of the signal interface area.

13. The interface layout method for a 3D chip according to claims 1 to 12, wherein: The 3D chip further includes a second chip stacked with the first chip, wherein at least some of the multiple signal interfaces of the first chip are used to communicate with multiple signal interfaces in the second chip.

14. An interface layout device for a 3D chip, comprising: A first determining module is configured to determine a signal interface area on a first chip under design and a combinational logic area corresponding to the signal interface area and arranged adjacent to the combinational logic area in a first direction, wherein the signal interface area is divided into a plurality of sub-signal areas relative to the combinational logic area at least in the first direction; an acquisition module configured to acquire a functional parameter of each of a plurality of signal interfaces of the first chip and a construction parameter related to the combinational logic area; The second determination module is configured to determine a corresponding sub-signal area of ​​each of the plurality of signal interfaces and a position in the corresponding sub-signal area based on the functional parameters and construction parameters of each of the plurality of signal interfaces.

15. An electronic device comprising: at least one storage unit storing computer executable instructions; as well as at least one processing unit configured to execute said computer executable instructions, Wherein, when the computer executable instructions are executed by the at least one processing unit, the interface layout method for a 3D chip according to any one of claims 1-13 is implemented.

16. A 3D chip, comprising a plurality of stacked chips, wherein: The interface layout of the first chip among the plurality of stacked chips is determined according to the interface layout method for a 3D chip according to any one of claims 1-13.

17. A non-transitory storage medium that non-transitory stores computer-executable instructions, wherein: When the computer executable instructions are executed by at least one processor, the interface layout method for a 3D chip according to any one of claims 1 to 13 is implemented.

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