Display device and method for inspecting display device

Abstract

The invention discloses a display device and a method for inspecting the same. The display device includes: a display panel configured to display an image corresponding to an image signal and including a pad; and a driving chip configured to provide a data signal to the pad. The driving chip includes: an analog section configured to convert an input voltage received through an input line into a driving voltage and convert an image data signal into a data signal; and a buffer configured to receive a buffer voltage through a buffer line different from the input line, and output a data signal to the pad.

Description

Technical Field

[0001] The present invention relates to a display device and more particularly to a method for easily judging a defect of the display device and a method for inspecting the display device. Background Art

[0002] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles may include a display device configured to display images.

[0003] In the process of manufacturing a display device, a display device with a defect can be detected in advance through an inspection for determining a defect of the display device. In the inspection for determining a defect of the display device, a test image can be displayed on the display device, and the displayed test image can be analyzed to determine the defect of the display device. Summary of the invention

[0004] The embodiment provides a display device for easily judging a short defect between pads.

[0005] The embodiment provides a method for inspecting a display device for easily judging a short defect between pads.

[0006] The display device according to the embodiment includes: a display panel configured to display an image corresponding to an image signal and including a pad; and a driving chip configured to provide a data signal to the pad. The driving chip includes: an analog part configured to convert an input voltage received through an input line into a driving voltage and convert an image data signal into a data signal; and a buffer configured to receive a buffer voltage through a buffer line different from the input line and output the data signal to the pad.

[0007] In an embodiment, the level of the buffer voltage may be equal to the level of the input voltage.

[0008] In an embodiment, when checking whether there is a short circuit defect between pads, the odd-numbered buffers among the buffers can be configured to output data signals having a first polarity, and the even-numbered buffers among the buffers can be configured to output data signals having a second polarity opposite to the first polarity.

[0009] In an embodiment, a buffer current flowing through the buffer line when a short defect exists between at least two adjacent pads among the pads may be greater than a buffer current flowing through the buffer line when a short defect does not exist between the pads.

[0010] In an embodiment, the driving chip may further include a logic part configured to convert the image signal into an image data signal.

[0011] In an embodiment, the display panel may further include: data lines respectively connected to the pads; and pixels connected to the data lines.

[0012] In an embodiment, the driving voltage may include a first pixel voltage supplied to an anode of a light emitting diode included in each of the pixels, a second pixel voltage supplied to a cathode of the light emitting diode, and an initialization voltage for initializing a gate of a driving transistor included in each of the pixels. The first pixel voltage, the second pixel voltage, and the initialization voltage may be supplied to each of the pixels.

[0013] In an embodiment, the display device may further include: a scanning block configured to provide a scanning signal to the pixel.

[0014] In an embodiment, the driving voltage may include a high gate voltage for turning off a switching transistor included in each of the pixels and a low gate voltage for turning on the switching transistor. The high gate voltage and the low gate voltage may be provided to the scanning block.

[0015] In an embodiment, the display device may further include: a DC-DC converter configured to convert the external voltage into an input voltage and apply the input voltage to the input line.

[0016] In an embodiment, the DC-DC converter may be configured to convert an external voltage into a buffer voltage and apply the buffer voltage to the buffer line.

[0017] According to an embodiment, a method for inspecting a display device (wherein the display device includes a display panel configured to display an image corresponding to an image signal and including a pad and a driving chip including a buffer configured to provide a data signal to the pad) includes: providing a buffer voltage to the buffer through a buffer line; outputting the data signal from the buffer to the pad; measuring a buffer current flowing through the buffer line; and judging whether there is a short circuit defect between the pads based on the buffer current.

[0018] In an embodiment, in output of data signals, odd-numbered buffers among the buffers may be configured to output data signals having a first polarity, and even-numbered buffers among the buffers may be configured to output data signals having a second polarity opposite to the first polarity.

[0019] In an embodiment, a buffer current when a short defect exists between at least two adjacent pads among the pads may be greater than a buffer current when a short defect does not exist between the pads.

[0020] In an embodiment, the method may further include: judging a defect of the driving driver based on a current measured when a driving driver including a driving chip is enabled and a display panel is disabled; and judging a defect of the display panel based on a current measured when the driving driver and the display panel are enabled.

[0021] In an embodiment, when the driving driver is judged to be normal in the judgment of the defect of the driving driver, the judgment of the defect of the display panel may be performed.

[0022] In an embodiment, the driving chip may include an analog part configured to convert an image data signal into a data signal, a logic part configured to convert the image signal into an image data signal, and a data output part including a buffer. The determination of the defect of the driving driver may include: determining the defect of the logic part based on the current measured when the logic part is enabled and the analog part and the data output part are disabled; and determining the defect of the analog part based on the current measured when the logic part and the analog part are enabled and the data output part is disabled.

[0023] In an embodiment, the driving driver may further include a scanning block configured to provide a scanning signal to the display panel. The determination of the defect of the driving driver may further include: determining the defect of the scanning block based on the current measured when the logic part, the analog part and the scanning block are enabled and the data output part is disabled.

[0024] In an embodiment, the determination of the defect of the driving driver may further include determining a defect of the data output part based on currents measured when the logic part, the analog part, the scan block, and the data output part are enabled.

[0025] In an embodiment, the determination of the defect of the data output portion may include providing a buffer voltage, outputting a data signal, measuring a buffer current, and determining whether there is a short defect between pads.

[0026] In the display device and the method for inspecting the display device according to the embodiment, the buffer can receive the buffer voltage through the buffer line different from the input line that transmits the input voltage to the analog part, and the buffer current flowing through the buffer line can be measured, so that the short circuit defect between the pads of the display panel can be accurately judged based on the buffer current. Accordingly, by judging whether a potential defect occurs in the display device, the quality reliability of the display device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a perspective view showing a display device according to an embodiment.

[0029] Figure 2 It is shown Figure 1 An exploded perspective view of a display device.

[0030] Figure 3 is a block diagram showing a display device according to an embodiment.

[0031] Figure 4 is a circuit diagram showing a pixel according to the embodiment.

[0032] Figure 5 is a block diagram showing a display device according to an embodiment.

[0033] Figure 6 Is used to describe Figure 5 FIG. 1 is a view of a display panel and a driving chip included in a display device.

[0034] Figure 7 is a block diagram showing an inspection apparatus according to an embodiment.

[0035] Figure 8 yes Figure 7 A block diagram of a judgment block included in an inspection device.

[0036] Fig. 9 and Fig.10 is a flowchart illustrating a method for inspecting a display device according to an embodiment.

[0037] Fig.11 is a flowchart illustrating a method for judging a defect of a data output part according to an embodiment.

[0038] Figures 12 to 19 is a view for describing a method for inspecting a display device according to an embodiment. DETAILED DESCRIPTION

[0039] The terms used in this article are only used for the purpose of describing specific embodiments, and are not intended to be limiting. As used in this article, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and unless the context clearly indicates otherwise, it is intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "element" has the same meaning as the meaning of "at least one element". "At least one" should not be interpreted as a restrictive "one". "Or" means "and / or". As used in this article, the term "and / or" includes any and all combinations of one or more of the related listed items. It will be further understood that when used in this specification, the term "includes" or "comprising" indicates the existence of stated features, regions, entireties, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or its groups.

[0040] It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or directly connected to the other element, or intervening elements may exist therebetween. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0041] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, the first element, component, region, layer or portion discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings herein.

[0042] Hereinafter, a display device and a method for inspecting a display device according to an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals will be used for the same elements in the drawings.

[0043] Figure 1 is a perspective view showing a display device DD according to the embodiment.

[0044] refer to Figure 1 , the display device DD may be a device activated according to an electrical signal. Figure 1 An embodiment in which the display device DD is a smart phone has been shown, but the present disclosure is not limited thereto. According to another embodiment, the display device DD may be a large display device such as a TV or a monitor or a small or medium-sized display device such as a tablet computer, a notebook computer, a car navigation system, or a game console.

[0045] The display device DD may have a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1 in a plan view, and may have a quadrilateral shape with rounded vertices. However, the shape of the display device DD is not limited thereto, and a display device DD having various shapes may be provided. A display surface IS of the display device DD parallel to the first direction DR1 and the second direction DR2 may display an image IM in a third direction DR3 intersecting the first direction DR1 and the second direction DR2. The display surface IS on which the image IM is displayed may correspond to a front surface of the display device DD.

[0046] The front surface (or top surface) and the rear surface (or bottom surface) of each of the components may be defined based on the direction in which the image IM is displayed. The front surface and the rear surface may face each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3.

[0047] The separation distance between the front surface and the rear surface in the third direction DR3 may correspond to the thickness of the display device DD in the third direction DR3. Directions indicated by the first direction to the third directions DR1, DR2, and DR3 may be relative directions that may be converted into other directions.

[0048] The display device DD may sense an external input TC applied from the outside. The external input TC may include various types of inputs provided from the outside of the display device DD. The external input TC may be one or a combination of various types of external inputs such as a part of the body of the user US, light, heat, and pressure. Figure 1 , an embodiment in which the external input TC of the user US is a touch input applied to the front surface by the hand of the user US is shown, but the present disclosure is not limited thereto. In addition, depending on the structure of the display device DD, the display device DD may sense the external input TC of the user US applied to the side surface or the rear surface of the display device DD. The display device DD may sense the position (e.g., coordinate information, etc.) of the external input TC.

[0049] According to an embodiment, the external input TC may further include an input performed by an input device (eg, a stylus pen, an active pen, a touch pen, an electronic pen, etc.), in addition to the hand of the user US.

[0050] The display surface IS of the display device DD may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area in which the image IM is displayed. The user may visually recognize the image IM through the transmission area TA. The frame area BZA may be adjacent to the transmission area TA. The frame area BZA may have a predetermined color. The frame area BZA may surround the transmission area TA. Accordingly, the shape of the transmission area TA may be substantially defined by the frame area BZA.

[0051] Figure 2 It is shown Figure 1 An exploded perspective view of a display device DD.

[0052] refer to Figure 1 and Figure 2 The display device DD may include a window WM, a display module DM and a housing EDC. The display module DM may include a display panel DP configured to display an image IM according to an electrical signal and an input sensing layer ISP configured to transmit / receive information about an external input TC.

[0053] The window WM may protect the top surface of the display module DM. The window WM may be optically transparent. The window WM may include a transparent material capable of transmitting the image IM. In an embodiment, for example, the window WM may include glass, sapphire and / or plastic, etc.

[0054] The bezel area BZA may be basically provided as an area in which a material having a predetermined color is printed on an area of ​​the window WM. According to an embodiment, the window WM may include a light shielding pattern for defining the bezel area BZA. The light shielding pattern may be a colored organic film and may be formed, for example, by a coating scheme.

[0055] The window WM may be bonded to the display module DM by an adhesive film. According to an embodiment, the adhesive film may include an optically clear adhesive ("OCA") film. However, the adhesive film is not limited thereto, and according to another embodiment, the adhesive film may include a conventional adhesive or adhesive. In an embodiment, for example, the adhesive film may include an optically clear resin ("OCR") or a pressure sensitive adhesive ("PSA") film.

[0056] An anti-reflection layer may be further provided between the window WM and the display module DM. The anti-reflection layer may reduce the reflectivity of external light incident from the upper side of the window WM. According to an embodiment, the anti-reflection layer may include a phase retarder and a polarizer. The phase retarder may be a film-type phase retarder or a liquid crystal coating type phase retarder, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may be a film-type polarizer or a liquid crystal coating type polarizer. The film-type polarizer may include an elongated synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a predetermined arrangement. The phase retarder and the polarizer may be implemented as one polarization film.

[0057] According to an embodiment, the anti-reflection layer may include a color filter. The arrangement of the color filter may be determined in consideration of the color of light generated by the pixels included in the display panel DP. The anti-reflection layer may further include a light shielding pattern.

[0058] The display module DM may display an image IM according to an electrical signal and may send / receive information about an external input TC. The display module DM may be defined by an active area AA and a non-active area NAA. The active area AA may be defined as an area in which an image IM is displayed from the display panel DP. In addition, the active area AA may be defined as an area in which an input sensing layer ISP senses an external input TC.

[0059] The non-active area NAA may be adjacent to the active area AA. In an embodiment, for example, the non-active area NAA may surround the active area AA. According to an embodiment, the active area AA may correspond to at least a portion of the transmissive area TA, and the non-active area NAA may correspond to at least a portion of the bezel area BZA.

[0060] The display panel DP may be a light-emitting display panel. According to an embodiment, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0061] The input sensing layer ISP may be disposed on the display panel DP to sense the external input TC. The input sensing layer ISP may have a multi-layer structure. The input sensing layer ISP may include a single insulating layer or a plurality of insulating layers. According to an embodiment, the input sensing layer ISP may include a single conductive layer or a plurality of conductive layers including a plurality of conductive patterns. According to an embodiment, the conductive pattern may include a plurality of scan electrodes configured to sense the external input TC and a plurality of signal lines connected to the plurality of scan electrodes. According to an embodiment, the input sensing layer ISP may be disposed directly on the display panel DP. According to an embodiment, the input sensing layer ISP may be formed on the display panel DP by a continuous process. When the input sensing layer ISP is disposed directly on the display panel DP, an adhesive film may not be disposed between the input sensing layer ISP and the display panel DP. However, the present disclosure is not limited thereto, and in another embodiment, an adhesive film may be disposed between the input sensing layer ISP and the display panel DP. In this case, the input sensing layer ISP may be manufactured by a process separate from the display panel DP and fixed to the top surface of the display panel DP by the adhesive film, rather than being manufactured by a process continuous with the display panel DP.

[0062] According to an embodiment, the display device DD may further include a driving chip DRC and a flexible circuit film PCB. According to an embodiment, the display panel DP may further include a pad area PP extending from the non-active area NAA.

[0063] Pad( Figure 6 The display panel DP may be electrically connected to the flexible circuit film PCB through the pads PD1 to PDm. However, the present disclosure is not limited thereto, and some of the components included in the driving chip DRC may be mounted on the pad area PP.

[0064] According to an embodiment, the driving chip DRC may be mounted on a flexible circuit film PCB. The flexible circuit film PCB may include a plurality of driving elements. The driving element may include a circuit portion configured to drive the display panel DP. According to an embodiment, the pad area PP may be bent to be disposed on the rear surface of the display panel DP.

[0065] The housing EDC may be coupled to the window WM to define the appearance of the display device DD. The housing EDC may absorb impact applied from the outside and may prevent foreign matter or moisture, etc. from penetrating into the display module DM to protect the components accommodated in the housing EDC. According to an embodiment, the housing EDC may be provided in a form in which a plurality of storage members are coupled to each other.

[0066] According to an embodiment, the display device DD may further include an electronic module including various functional modules configured to operate the display module DM, a power module configured to power the overall operation of the display device DD, and a bracket coupled to the housing EDC to divide the internal space of the display device DD, etc.

[0067] Figure 3 is a block diagram showing a display device DD according to an embodiment. Figure 4 is a circuit diagram showing a pixel according to the embodiment.

[0068] refer to Figure 3 and Figure 4 The display device DD may include a display panel DP and a driving driver DV. The driving driver DV may control the driving of the display panel DP.

[0069] The driving driver DV may include a driving chip DRC and a scanning block SB. The driving chip DRC may receive external signals RGB and CTRL, and may generate a data signal DS and a scanning control signal SCS corresponding to the display panel DP based on the external signals RGB and CTRL. Specifically, the external signals RGB and CTRL may include an image signal RGB and an external control signal CTRL. The driving chip DRC may generate a data signal DS based on the image signal RGB, and may generate a scanning control signal SCS based on the external control signal CTRL. The scanning block SB may generate a data signal DS for displaying an image on the display panel DP ( Figure 1 The display panel DP may display an image IM based on the data signal DS and the scan signal SS. According to an embodiment, the scan signal SS may include write scan signals WSS1 to WSSn+1 and emission scan signals ESS1 to ESSn.

[0070] The driving chip DRC may include a controller CP, a source driving block SDB, and a voltage generating block VGB.

[0071] The controller CP may receive an image signal RGB and an external control signal CTRL. The controller CP may generate an image data signal IMD obtained by converting the data format of the image signal RGB to meet the interface specification with the source driver block SDB. The controller CP may output a scan control signal SCS, a source control signal DCS, and a voltage control signal VCS based on the external control signal CTRL. The scan control signal SCS may include a gate control signal GCS and an emission control signal ECS.

[0072] The source driver block SDB may receive a source control signal DCS and an image data signal IMD from the controller CP. The source driver block SDB may convert the image data signal IMD into a data signal DS and output the data signal DS to the data lines DL1 to DLm, which will be described below. The data signal DS may be each of the analog voltages corresponding to the grayscale value of the image data signal IMD.

[0073] The voltage generation block VGB may generate a driving voltage DRV for the operation of the display panel DP. According to an embodiment, the driving voltage DRV may include a high gate voltage VGH, a low gate voltage VGL, a first pixel voltage VDD, a second pixel voltage VSS, and / or an initialization voltage VINT, etc. The voltage generation block VGB may provide the high gate voltage VGH and the low gate voltage VGL to the scanning block SB, and provide the first pixel voltage VDD, the second pixel voltage VSS, and the initialization voltage VINT to the pixel PX. The voltage generation block VGB may provide the first pixel voltage VDD, the second pixel voltage VSS, and the initialization voltage VINT to a driving voltage line electrically connected to the pixel PX. The pixel PX may generate light based on the data signal DS, the scanning signal SS, the first pixel voltage VDD, the second pixel voltage VSS, and the initialization voltage VINT.

[0074] According to an embodiment, the scanning block SB may include a gate driver block GDB and an emission driver block EDB. The gate driver block GDB may receive a gate control signal GCS from a controller CP. The gate driver block GDB may generate write scan signals WSS1 to WSSn+1 based on the gate control signal GCS, and sequentially output the write scan signals WSS1 to WSSn+1 to a plurality of write scan lines WSL1 to WSLn+1, which will be described below. The emission driver block EDB may receive an emission control signal ECS from the controller CP. The emission driver block EDB may generate emission scan signals ESS1 to ESSn based on the emission control signal ECS, and sequentially output the emission scan signals ESS1 to ESSn to a plurality of emission scan lines ESL1 to ESLn, which will be described below.

[0075] The display panel DP may include a transmissive area ( Figure 1 The display area DA corresponding to the TA) and the frame area ( Figure 1 The non-display area NDA corresponds to the BZA).

[0076] The display panel DP may include a plurality of scan lines SL, a plurality of data lines DL1 to DLm, and a plurality of pixels PX. According to an embodiment, the scan lines SL may include a plurality of write scan lines WSL1 to WSLn+1 and a plurality of emission scan lines ESL1 to ESLn.

[0077] The pixels PX may be arranged in the display area DA. According to an embodiment, the write scan lines WSL1 to WSLn+1 and the emission scan lines ESL1 to ESLn may extend in the second direction DR2. The write scan lines WSL1 to WSLn+1 and the emission scan lines ESL1 to ESLn may be spaced apart from each other in the first direction DR1. The data lines DL1 to DLm may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2.

[0078] Each of the pixels PX can be electrically connected to three write scan lines corresponding to the pixel PX among the write scan lines WSL1 to WSLn+1. In addition, each of the pixels PX can be electrically connected to one emission scan line corresponding to the pixel PX among the emission scan lines ESL1 to ESLn and one data line corresponding to the pixel PX among the data lines DL1 to DLm. However, the connection relationship between the pixel PX and the write scan lines WSL1 to WSLn+1, the emission scan lines ESL1 to ESLn, and the data lines DL1 to DLm can be changed depending on the configuration of the pixel circuit portion of each of the pixels PX.

[0079] Each of the pixels PX may include a light emitting diode LED and a pixel circuit portion configured to control the light emission of the light emitting diode LED. The pixel circuit portion may include a driving transistor T1, a plurality of switching transistors T2, T3, T4, T5, T6 and T7, and a storage capacitor CST. Each of the pixels PX may receive a first pixel voltage VDD, a second pixel voltage VSS and an initialization voltage VINT from a voltage generating block VGB. The first pixel voltage VDD may be provided to the anode of the light emitting diode LED, and the second pixel voltage VSS may be provided to the cathode of the light emitting diode LED. The initialization voltage VINT may initialize the gate of the driving transistor T1. Each of the pixels PX may receive at least one write scan signal WSS from a gate drive block GDB. For example, each of the pixels PX may receive a kth write scan signal WSSk, a k+1th write scan signal WSSk+1 and a k+2th write scan signal WSSk+2. Each of the pixels PX may receive a kth emission scan signal ESSk from an emission drive block EDB.

[0080] The gate driver block GDB and the emission driver block EDB may be disposed in the non-display area NDA of the display panel DP. The gate driver block GDB may sequentially supply write scan signals WSS1 to WSSn+1 to the write scan lines WSL1 to WSLn+1. The emission driver block EDB may sequentially supply emission scan signals ESS1 to ESSn to the emission scan lines ESL1 to ESLn. Each of the gate driver block GDB and the emission driver block EDB may receive a high gate voltage VGH and a low gate voltage VGL from a voltage generation block VGB. The gate driver block GDB may generate the write scan signals WSS1 to WSSn+1 based on the high gate voltage VGH and the low gate voltage VGL, and the emission driver block EDB may generate the emission scan signals ESS1 to ESSn based on the high gate voltage VGH and the low gate voltage VGL. According to an embodiment, the high gate voltage VGH may be a voltage for turning off a switching transistor included in each of the pixels PX, and the low gate voltage VGL may be a voltage for turning on a switching transistor included in each of the pixels PX. However, the present disclosure is not limited thereto, and according to another embodiment, the high gate voltage VGH may be a voltage for turning on a switching transistor included in each of the pixels PX, and the low gate voltage VGL may be a voltage for turning off a switching transistor included in each of the pixels PX.

[0081] According to an embodiment, the display device DD may further include a DC-DC converter DDC. The DC-DC converter DDC may receive an external voltage VBAT. In an embodiment, for example, the external voltage VBAT may be a voltage provided from a battery. The DC-DC converter DDC may generate an input voltage VLI by converting the level of the external voltage VBAT, and transmit the input voltage VLI to the driving chip DRC.

[0082] According to an embodiment, the DC-DC converter DDC may generate a buffer voltage VBF by converting the level of the external voltage VBAT and transmit the buffer voltage VBF to the driving chip DRC. However, the present disclosure is not limited thereto, and according to another embodiment, the driving chip DRC may receive the buffer voltage VBF from the outside.

[0083] Figure 5 is a block diagram showing a display device DD according to an embodiment.

[0084] refer to Figure 3 and Figure 5 The driving chip DRC may include a logic part LGP, an analog part ANP and a data output part DOP.

[0085] Among the controller CP, the source driver block SDB, and the voltage generation block VGB included in the driver chip DRC, a component configured to generate a digital signal to be provided to the display panel DP based on the image signal RGB and the external control signal CTRL may be referred to as a "logic part" LGP. According to an embodiment, the digital signal may include a gate control signal GCS, an emission control signal ECS, a source control signal DCS, a voltage control signal VCS, and an image data signal IMD. Among the controller CP, the source driver block SDB, and the voltage generation block VGB included in the driver chip DRC, a component configured to generate an analog signal to be provided to the display panel DP based on the digital signal generated by the logic part LGP may be referred to as an "analog part" ANP. According to an embodiment, the analog signal may include a data signal DS and a driving voltage DRV. Among the controller CP, the source driver block SDB, and the voltage generation block VGB included in the driver chip DRC, a component configured to transmit the data signal DS generated by the analog part ANP to the display panel DP may be referred to as a "data output part" DOP.

[0086] According to an embodiment, the driving voltage DRV may include a high gate voltage VGH, a low gate voltage VGL, a first pixel voltage VDD, a second pixel voltage VSS, and an initialization voltage VINT. The analog part ANP may transmit the high gate voltage VGH and the low gate voltage VGL to each of the gate driving block GDB and the emission driving block EDB, and may transmit the first pixel voltage VDD, the second pixel voltage VSS, and the initialization voltage VINT to each of the pixels PX.

[0087] The analog part ANP may receive an input voltage VLI from the DC-DC converter DDC through an input line LLI. According to an embodiment, the data output part DOP may receive a buffer voltage VBF from the DC-DC converter DDC through a buffer line LBF. However, the present disclosure is not limited thereto, and according to another embodiment, the data output part DOP may receive a buffer voltage VBF from the outside through a buffer line LBF. The analog part ANP may convert the input voltage VLI received through the input line LLI into a driving voltage DRV, and convert the image data signal IMD into a data signal DS.

[0088] According to an embodiment, the level of the buffer voltage VBF may be equal to the level of the input voltage VLI. In an embodiment, for example, each of the level of the buffer voltage VBF and the level of the input voltage VLI may be about 7.3 volts (V).

[0089] Figure 6 Is used to describe Figure 5 FIG. 5 is a view of a display panel DP and a driving chip DRC included in a display device DD.

[0090] refer to Figure 6 The display panel DP may include a Figure 2 The pads PD1, PD2, PD3, PD4, ... and PDm may be spaced apart from each other in the second direction DR2. The pads PD1, PD2, PD3, PD4, ... and PDm may be connected to the data lines DL1, DL2, DL3, DL4, ... and DLm, respectively.

[0091] The data output part DOP of the driving chip DRC may include buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm. The buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm may be spaced apart from each other in the second direction DR2. The buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm may output data signals DS1, DS2, DS3, DS4, ... and DSm to pads PD1, PD2, PD3, PD4, ... and PDm. The buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm may receive a buffer voltage VBF through a buffer line LBF.

[0092] According to an embodiment, when checking whether there is a short circuit defect between pads PD1, PD2, PD3, PD4, ... and PDm, odd-numbered buffers BUF1, BUF3, ... among buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm may output data signals DS1, DS3, ... having a first polarity, and even-numbered buffers BUF2, BUF4, ... among buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm may output data signals DS2, DS4, ... having a second polarity opposite to the first polarity. In an embodiment, for example, when the first polarity is positive, the second polarity may be negative, and when the first polarity is negative, the second polarity may be positive. Since the polarities of the data signals applied to pads adjacent to each other in the second direction DR2 are different from each other, when there is a short circuit defect between adjacent pads, a potential difference may occur between adjacent pads, and current may flow between short-circuited pads.

[0093] When there is a short circuit defect between at least two adjacent pads among the pads PD1, PD2, PD3, PD4, ... and PDm, the buffer current IBF flowing through the buffer line LBF can be greater than the buffer current IBF flowing through the buffer line LBF when there is no short circuit defect between the pads PD1, PD2, PD3, PD4, ... and PDm. The current flowing between the short-circuited pads can affect the buffer line LBF through the electrical connection between the pads PD1, PD2, PD3, PD4, ... and PDm and the buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm, and the buffer current IBF flowing through the buffer line LBF can be increased by the current flowing between the short-circuited pads. Accordingly, it can be judged whether there is a short circuit defect between the pads PD1, PD2, PD3, PD4, ... and PDm based on the buffer current IBF flowing through the buffer line LBF.

[0094] Figure 7 is a block diagram showing an inspection device ISD according to an embodiment. Figure 8 It is shown Figure 7 A block diagram of a judgment block JDB included in an inspection device ISD.

[0095] refer to Figure 7 and Figure 8 , according to an embodiment, for a display device ( Figure 1 The inspection device ISD of DD) may include an inspection controller ISC and a judgment block JDB. Figure 7 Some of the components of the display device DD (display panel DP, flexible circuit film PCB and driver chip DRC) are shown. In the process of manufacturing the display device DD, after manufacturing the display panel DP, the flexible circuit film PCB and the driver chip DRC, the defects of the display panel DP, the flexible circuit film PCB and the driver chip DRC can be judged by the inspection device ISD. Accordingly, the defects of the display device DD including the display panel DP, the flexible circuit film PCB and the driver chip DRC can be judged. Hereinafter, for the convenience of description, the state in which the display panel DP, the flexible circuit film PCB and the driver chip DRC are manufactured in the process of manufacturing the display device DD will be referred to as the preliminary display device P_DD. In this case, the inspection device ISD can check the defects of the preliminary display device P_DD. The display device DD can be manufactured by using the preliminary display device P_DD that has been judged to be normal by the inspection device ISD. However, the present disclosure is not limited to this, and the defects of the completed display device DD can be judged by using the inspection device ISD.

[0096] The inspection device ISD may provide an inspection signal ISS to the driving chip DRC. The inspection signal ISS may be a signal for enabling the preliminary display device P_DD step by step, and may include first to eighth inspection signals ISS1 to ISS8 (see Figures 12 to 19 ). The inspection device ISD may measure the currents DVC and DPC supplied to the preliminary display device P_DD when the preliminary display device P_DD is enabled step by step by the inspection signal ISS. The inspection device ISD may analyze the measured currents DVC and DPC to generate a determination signal JDS activated at each stage in which the preliminary display device P_DD is enabled and used to determine a defect of each of the components included in the preliminary display device P_DD. Hereinafter, for ease of description, the inspection device ISD will be described as determining a defect of the display panel DP and a driving driver ( Figure 3 The driver DV includes a driver chip DRC and a scanning block ( Figure 3 SB).

[0097] Specifically, the inspection controller ISC may provide the inspection signal ISS to the driver chip DRC. The inspection controller ISC may enable the driver DV and disable the display panel DP by the inspection signal ISS. In addition, the inspection controller ISC may enable the driver DV and the display panel DP by the inspection signal ISS. The inspection controller ISC may measure the current DVC (hereinafter referred to as "driving operation current") provided to the preparatory display device P_DD when the driver DV is enabled and the display panel DP is disabled or the current DPC (hereinafter referred to as "display operation current") provided to the preparatory display device P_DD when both the driver DV and the display panel DP are enabled. The inspection controller ISC may provide the measured driving operation current DVC and the measured display operation current DPC to the judgment block JDB. The judgment block JDB may generate a judgment signal JDS for judging a defect of the driver DV or the display panel DP based on the driving operation current DVC and the display operation current DPC. The inspection device ISD may further include a display portion configured to receive the judgment signal JDS to display a defect of the driver DV or the display panel DP. In addition, the inspection device ISD may further include a separate current measuring part configured to measure the driving operation current DVC and the display operation current DPC supplied to the preliminary display device P_DD.

[0098] The judgment block JDB may include a comparison part CPP, a judgment part JDP, a first memory MM1, and a second memory MM2. According to an embodiment, the pre-measured reference values ​​RFV1 and RFV2 may be stored in the first memory MM1. The reference values ​​RFV1 and RFV2 may include the magnitude of the operating current provided to the preparatory display device P_DD when only the driving driver DV in the normal state is enabled and the magnitude of the operating current provided to the preparatory display device P_DD when the driving driver DV and the display panel DP in the normal state are enabled. The reference values ​​RFV1 and RFV2 may include a first reference value RFV1, which is an average value of the driving operating current DVC provided to the preparatory display device P_DD measured several times in advance when only the driving driver DV in the normal state is enabled. In addition, the reference values ​​RFV1 and RFV2 may include a second reference value RFV2, which is an average value of the display operating current DPC provided to the preparatory display device P_DD measured several times in advance when the driving driver DV and the display panel DP in the normal state are enabled.

[0099] The comparing part CPP may receive the first reference value RFV1 and the second reference value RFV2 from the first memory MM1, and may receive the driving operation current DVC and the display operation current DPC from the inspection controller ISC. The comparing part CPP may generate a first comparison signal CPS1 by comparing the first reference value RFV1 with the driving operation current DVC, and may generate a second comparison signal CPS2 by comparing the second reference value RFV2 with the display operation current DPC. In an embodiment, the comparing part CPP may generate the first comparison signal CPS1 based on the difference between the magnitude of the driving operation current DVC and the first reference value RFV1, and may generate the second comparison signal CPS2 based on the difference between the magnitude of the display operation current DPC and the second reference value RFV2.

[0100] The judging part JDP may receive the first comparison signal CPS1 and the second comparison signal CPS2 from the comparing part CPP. The judging part JDP may judge the defect of the driving driver DV or the display panel DP based on the first comparison signal CPS1 and the second comparison signal CPS2. According to an embodiment, the judging part JDP may judge the defect of the driving driver DV by comparing the size difference between the size of the driving operation current DVC and the first reference value RFV1 with a preset tolerance value based on the first comparison signal CPS1 received when only the driving driver DV is enabled. When the size difference between the size of the driving operation current DVC and the first reference value RFV1 is less than the tolerance value, the judging part JDP may judge that the driving driver DV is normal. When the size difference between the size of the driving operation current DVC and the first reference value RFV1 is greater than or equal to the tolerance value, the judging part JDP may judge that the driving driver DV is defective. According to an embodiment, the judging part JDP may judge the defect of the display panel DP by comparing the size difference between the size of the display operation current DPC and the second reference value RFV2 with a preset tolerance value based on the second comparison signal CPS2 received when the driving driver DV and the display panel DP are enabled. When the difference between the magnitude of the display operation current DPC and the second reference value RFV2 is less than the tolerance value, the judgment part JDP can judge that the display panel DP is normal. When the difference between the magnitude of the display operation current DPC and the second reference value RFV2 is greater than or equal to the tolerance value, the judgment part JDP can judge that the display panel DP is defective.

[0101] According to an embodiment, the tolerance value when only the driving driver DV is enabled may be a value proportional to a standard deviation value of an operating current supplied to the preliminary display device P_DD measured several times in advance when only the driving driver DV in a normal state is enabled. In addition, the tolerance value when the driving driver DV and the display panel DP are enabled may be a value proportional to a standard deviation value of an operating current supplied to the preliminary display device P_DD measured several times in advance when the driving driver DV and the display panel DP in a normal state are enabled.

[0102] According to an embodiment, when the magnitude of the driving operation current DVC is less than the first reference value RFV1 and the magnitude difference between the magnitude of the driving operation current DVC and the first reference value RFV1 is greater than or equal to the tolerance value, the judging part JDP may judge that a part of the circuit included in the driving driver DV has an open circuit defect. When the magnitude of the driving operation current DVC is greater than the first reference value RFV1 and the magnitude difference between the magnitude of the driving operation current DVC and the first reference value RFV1 is greater than or equal to the tolerance value, the judging part JDP may judge that a part of the circuit included in the driving driver DV has a short circuit defect.

[0103] According to an embodiment, when the magnitude of the display operation current DPC is less than the second reference value RFV2 and the magnitude difference between the magnitude of the display operation current DPC and the second reference value RFV2 is greater than or equal to the tolerance value, the judging part JDP may judge that a part of the circuit included in the display panel DP has an open circuit defect. When the magnitude of the display operation current DPC is greater than the second reference value RFV2 and the magnitude difference between the magnitude of the display operation current DPC and the second reference value RFV2 is greater than or equal to the tolerance value, the judging part JDP may judge that a part of the circuit included in the display panel DP has a short circuit defect.

[0104] When judging that the driving driver DV or the display panel DP has a defect, the judging part JDP may provide the defect information signal ERS to the second memory MM2. Accordingly, information about defects that may occur in the driving driver DV or the display panel DP during the process of manufacturing the display device DD may be stored in the second memory MM2.

[0105] The judging part JDP may judge a defect of the preliminary display device P_DD based on the first comparison signal CPS1 and the second comparison signal CPS2 and generate a judging signal JDS.

[0106] Fig. 9 and Fig.10 is a flowchart illustrating a method for inspecting a display device DD according to an embodiment. Fig.11 is a flowchart illustrating a method for determining a defect of a data output part DOP according to an embodiment.

[0107] refer to Figures 5 to 7 and Figures 9 to 11 , the method for inspecting the display device DD may include: measuring the driving operation current DVC supplied to the preliminary display device P_DD by using the inspection device ISD when the driving driver DV is enabled and the display panel DP is disabled, and judging the defect of the driving driver DV based on the measured driving operation current DVC (step S100). In addition, the method for inspecting the display device DD may include: measuring the display operation current DPC supplied to the preliminary display device P_DD by using the inspection device ISD when the driving driver DV and the display panel DP are enabled, and judging the defect of the display panel DP based on the measured display operation current DPC (step S200). According to an embodiment, judging the defect of the display panel DP (step S200) may be performed after judging the defect of the driving driver DV (step S100).

[0108] Determining the defect of the driving driver DV (step S100) may include: determining the defect of the logic part LGP (step S110); determining the defect of the analog part ANP (step S120); determining the defect of the scanning block SB (step S130); and determining the defect of the data output part DOP (step S140). According to an embodiment, determining the defect of the analog part ANP (step S120) may be performed after determining the defect of the logic part LGP (step S110). Determining the defect of the scanning block SB (step S130) may be performed after determining the defect of the analog part ANP (step S120). Determining the defect of the data output part DOP (step S140) may be performed after determining the defect of the scanning block SB (step S130).

[0109] Determining the defect of the display panel DP (step S200) may include: determining the connection state between the pixel PX and the emission scan lines ESL1 to ESLn (step S210); determining the connection state between the pixel PX and the write scan lines WSL1 to WSLn+1 (step S220); determining the connection state between the pixel PX and the drive voltage line (step S230); and determining the defect of the image IM displayed on the display panel DP (step S240). According to an embodiment, determining the connection state between the pixel PX and the write scan lines WSL1 to WSLn+1 (step S220) may be performed after determining the connection state between the pixel PX and the emission scan lines ESL1 to ESLn (step S210). Determining the connection state between the pixel PX and the drive voltage line (step S230) may be performed after determining the connection state between the pixel PX and the write scan lines WSL1 to WSLn+1 (step S220). Determining a defect of the image IM displayed on the display panel DP (step S240 ) may be performed after determining a connection state between the pixel PX and the driving voltage line (step S230 ).

[0110] Determining the defect of the data output part DOP (step S140) may include: providing a buffer voltage VBF to buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm through a buffer line LBF (step S141); outputting data signals DS1, DS2, DS3, DS4, ... and DSm from buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm to pads PD1, PD2, PD3, PD4, ... and PDm (step S142); measuring a buffer current IBF flowing through the buffer line LBF (step S143); and determining whether there is a short circuit defect between pads PD1, PD2, PD3, PD4, ... and PDm based on the buffer current IBF (step S144). According to an embodiment, when data signals DS1, DS2, DS3, DS4, ... and DSm are output from buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm to pads PD1, PD2, PD3, PD4, ... and PDm, the odd-numbered buffers BUF1, BUF3, ... among the buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm can output data signals DS1, DS3, ... having a first polarity, and the even-numbered buffers BUF2, BUF4, ... among the buffers BUF1, BUF2, BUF3, BUF4, ... and BUFm can output data signals DS2, DS4, ... having a second polarity opposite to the first polarity. When there is a short circuit defect between at least two adjacent pads among the pads PD1, PD2, PD3, PD4, ... and PDm, the buffer current IBF flowing through the buffer line LBF can be greater than the buffer current IBF flowing through the buffer line LBF when there is no short circuit defect between the pads PD1, PD2, PD3, PD4, ... and PDm.

[0111] Figures 12 to 19 is a view for describing a method for inspecting a display device according to an embodiment.

[0112] refer to Fig.10 and Fig.12, when judging the defect of the logic part LGP (step S110), when the logic part LGP is enabled and the analog part ANP, the scan block SB, and the data output part DOP are disabled, the current SDRC1 (hereinafter, referred to as "first sub-driving current") supplied to the preliminary display device P_DD may be measured, and the defect of the logic part LGP may be judged based on the first sub-driving current SDRC1. According to an embodiment, the inspection controller ISC may provide the first inspection signal ISS1 for enabling only the logic part LGP to the driving chip DRC when the analog part ANP and the data output part DOP are disabled. Since the defect of the logic part LGP included in the preliminary display device P_DD is judged, a defect may be prevented from occurring in the display device DD manufactured by the preliminary display device P_DD including the defective logic part LGP.

[0113] refer to Fig.10 and Fig.13 , when judging the defect of the analog part ANP (step S120), when the logic part LGP and the analog part ANP are enabled and the scan block SB and the data output part DOP are disabled, the current SDRC2 (hereinafter, referred to as "second sub-driving current") provided to the preliminary display device P_DD can be measured, and the defect of the analog part ANP can be judged based on the second sub-driving current SDRC2. According to an embodiment, the inspection controller ISC can provide the second inspection signal ISS2 for enabling the logic part LGP and the analog part ANP to the driving chip DRC when the data output part DOP is disabled. The logic part LGP can generate a first output signal EN1 for enabling the analog part ANP, and provide the first output signal EN1 to the analog part ANP. Since the defect of the analog part ANP included in the preliminary display device P_DD is judged, it is possible to prevent a defect from occurring in the display device DD manufactured by the preliminary display device P_DD including the defective analog part ANP.

[0114] refer to Fig.10 and Fig.14, when judging the defect of the scanning block SB (step S130), when the logic part LGP, the analog part ANP and the scanning block SB are enabled and the data output part DOP is disabled, the current SDRC3 (hereinafter, referred to as the "third sub-driving current") provided to the preliminary display device P_DD can be measured, and the defect of the scanning block SB can be judged based on the third sub-driving current SDRC3. According to an embodiment, the inspection controller ISC may provide a third inspection signal ISS3 for enabling the scanning block SB to the driving chip DRC. The logic part LGP may generate a first output signal EN1_a for enabling the analog part ANP, and provide the first output signal EN1_a to the analog part ANP. The analog part ANP may generate a second output signal EN2 for enabling the scanning block SB, and provide the second output signal EN2 to the scanning block SB. According to an embodiment, the second output signal EN2 may include a high gate voltage ( Figure 5 VGH) and low gate voltage ( Figure 5 Since the defect of the scanning block SB included in the preliminary display device P_DD is judged, it is possible to prevent a defect from occurring in the display device DD manufactured from the preliminary display device P_DD including the scanning block SB having the defect.

[0115] refer to Fig.10 and Fig.15 , when judging the defect of the data output part DOP (step S140), when the logic part LGP, the analog part ANP, the scan block SB, and the data output part DOP are enabled and the display panel DP is disabled, the current SDRC4 (hereinafter, referred to as "the fourth sub driving current") supplied to the preliminary display device P_DD may be measured, and the defect of the data output part DOP may be judged based on the fourth sub driving current SDRC4. According to an embodiment, the fourth sub driving current SDRC4 may include a buffer current ( Figure 6IBF). According to an embodiment, the inspection controller ISC may provide a fourth inspection signal ISS4 for enabling the data output part DOP to the driving chip DRC. The logic part LGP may generate a first output signal EN1_b for enabling the analog part ANP, and provide the first output signal EN1_b to the analog part ANP. The analog part ANP may generate a second output signal EN2 for enabling the scan block SB and a third output signal EN3 for enabling the data output part DOP. The analog part ANP may provide the second output signal EN2 to the scan block SB, and provide the third output signal EN3 to the data output part DOP. The data output part DOP may provide the data signal DS to the display panel DP. Since the defect of the data output part DOP included in the preliminary display device P_DD is judged, a defect may be prevented from occurring in the display device DD manufactured by the preliminary display device P_DD including the defective data output part DOP.

[0116] refer to Fig.10 and Fig.16 , when judging the connection state between the pixel PX and the emission scan lines ESL1 to ESLn (step S210), when the emission scan signals ESS1 to ESSn are provided to the pixel PX and the write scan signals WSS1 to WSSn+1 are not provided to the pixel PX, the current SDPC1 (hereinafter, referred to as "first sub-display current") provided to the preparatory display device P_DD can be measured, and the connection state between the pixel PX and the emission scan lines ESL1 to ESLn can be judged based on the first sub-display current SDPC1. According to an embodiment, the inspection controller ISC may provide a fifth inspection signal ISS5 for providing the emission scan signals ESS1 to ESSn to the pixel PX to the driving chip DRC. The logic part LGP may generate a first output signal EN1_c for enabling the analog part ANP, and provide the first output signal EN1_c to the analog part ANP. The analog part ANP may generate a second output signal EN2_a for enabling the scan block SB and a third output signal EN3 for enabling the data output part DOP. The analog part ANP may provide the second output signal EN2_a to the scanning block SB, and provide the third output signal EN3 to the data output part DOP. The scanning block SB may provide the emission scanning signals ESS1 to ESSn to the pixels PX. Since the defect of the connection between the pixels PX included in the preliminary display device P_DD and the emission scanning lines ESL1 to ESLn is judged, it is possible to prevent a defect from occurring in the display device DD manufactured by the preliminary display device P_DD including the pixels PX having the connection defect with the emission scanning lines ESL1 to ESLn.

[0117] refer to Fig.10 and Fig.17 , when judging the connection state between the pixel PX and the write scan lines WSL1 to WSLn+1 (step S220), when the write scan signals WSS1 to WSSn+1 are provided to the pixel PX and the first pixel voltage VDD, the second pixel voltage VSS and the initialization voltage VINT are not provided to the pixel PX, the current SDPC2 (hereinafter, referred to as the "second sub-display current") provided to the preparatory display device P_DD can be measured, and the connection state between the pixel PX and the write scan lines WSL1 to WSLn+1 can be judged based on the second sub-display current SDPC2. According to an embodiment, the inspection controller ISC may provide the sixth inspection signal ISS6 for providing the write scan signals WSS1 to WSSn+1 to the pixel PX to the driving chip DRC. The logic part LGP may generate a first output signal EN1_d for enabling the analog part ANP, and provide the first output signal EN1_d to the analog part ANP. The analog part ANP may generate a second output signal EN2_b for enabling the scan block SB and a third output signal EN3 for enabling the data output part DOP. The analog part ANP may provide the second output signal EN2_b to the scanning block SB, and provide the third output signal EN3 to the data output part DOP. The scanning block SB may provide the emission scanning signals ESS1 to ESSn and the writing scanning signals WSS1 to WSSn+1 to the pixels PX. Since the defect of the connection between the pixels PX included in the preliminary display device P_DD and the writing scanning lines WSL1 to WSLn+1 is judged, it is possible to prevent a defect from occurring in the display device DD manufactured by the preliminary display device P_DD including the pixels PX having the connection defect with the writing scanning lines WSL1 to WSLn+1.

[0118] refer to Fig.10 and Fig.18, when judging the connection state between the pixel PX and the driving voltage line (step S230), when the first pixel voltage VDD, the second pixel voltage VSS and the initialization voltage VINT are provided to the pixel PX and the display panel DP does not display the image IM, the current SDPC3 (hereinafter, referred to as the "third sub-display current") provided to the preparatory display device P_DD can be measured, and the connection state between the pixel PX and the driving voltage line can be judged based on the third sub-display current SDPC3. According to an embodiment, the inspection controller ISC may provide the seventh inspection signal ISS7 for providing the first pixel voltage VDD, the second pixel voltage VSS and the initialization voltage VINT to the pixel PX to the driving chip DRC. The logic part LGP may generate a first output signal EN1_e for enabling the analog part ANP, and provide the first output signal EN1_e to the analog part ANP. The analog part ANP may generate a second output signal EN2_b for enabling the scanning block SB, a third output signal EN3 for enabling the data output part DOP, the first pixel voltage VDD, the second pixel voltage VSS and the initialization voltage VINT. The analog part ANP may provide the second output signal EN2_b to the scanning block SB, the third output signal EN3 to the data output part DOP, and the first pixel voltage VDD, the second pixel voltage VSS, and the initialization voltage VINT to the pixel PX. The scanning block SB may provide the emission scanning signals ESS1 to ESSn and the writing scanning signals WSS1 to WSSn+1 to the pixel PX. Since the defect of the connection between the pixel PX included in the preliminary display device P_DD and the driving voltage line is judged, it is possible to prevent a defect from occurring in the display device DD manufactured by the preliminary display device P_DD including the pixel PX having the connection defect with the driving voltage line.

[0119] refer to Fig.10 and Fig.19 , when judging the defect of the image IM displayed on the display panel DP (step S240), the current SDPC4 (hereinafter, referred to as the "fourth sub-display current") provided to the preparatory display device P_DD when the image IM is displayed on the display panel DP can be measured, and the defect of the image IM displayed on the display panel DP can be judged based on the fourth sub-display current SDPC4. According to an embodiment, the inspection controller ISC may provide the eighth inspection signal ISS8 for displaying the image IM on the display panel DP to the driving chip DRC. When the eighth inspection signal ISS8 is provided to the driving chip DRC, the display panel DP may display the image IM. According to an embodiment, the image IM may include a test pattern for judging the defect of the display panel DP, etc.

[0120] The display device according to the embodiment may be applied to a display device included in a computer (eg, a notebook computer), a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, or the like.

[0121] Although the display device and the method for inspecting the display device according to the embodiment have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by a person of ordinary skill in the relevant technical field without departing from the technical spirit described in the claims.

[0122] As used in conjunction with various embodiments of the present disclosure, each of the source driver block SDB, voltage generation block VGB, gate driver block GDB, and emission driver block EDB may be implemented in hardware, software, or firmware, for example, in the form of an application specific integrated circuit (ASIC).

Claims

1. A display device, comprising: A display panel configured to display an image corresponding to an image signal and including a pad; and A driving chip configured to provide a data signal to the pad, Wherein, the driving chip comprises: an analog portion configured to convert an input voltage received through an input line into a driving voltage, and converting the image data signal into said data signal; and The buffer is configured to receive a buffer voltage through a buffer line different from the input line and output the data signal to the pad.

2. The display device according to claim 1, wherein: The level of the buffer voltage is equal to the level of the input voltage.

3. The display device according to claim 1, wherein: When checking whether there is a short circuit defect between the pads, the odd-numbered buffers among the buffers are configured to output the data signal having a first polarity, and the even-numbered buffers among the buffers are configured to output the data signal having a second polarity opposite to the first polarity.

4. The display device according to claim 3, wherein: A buffer current flowing through the buffer line when the short circuit defect exists between at least two adjacent pads among the pads is greater than a buffer current flowing through the buffer line when the short circuit defect does not exist between the pads.

5. The display device according to claim 1, wherein: The driving chip further includes a logic portion configured to convert the image signal into the image data signal.

6. The display device according to any one of claims 1 to 5, further comprising: A DC-DC converter is configured to convert an external voltage into the input voltage and apply the input voltage to the input line.

7. The display device according to claim 6, wherein: The DC-DC converter is configured to convert the external voltage into the buffer voltage and apply the buffer voltage to the buffer line.

8. A method for inspecting a display device, wherein: The display device includes a display panel configured to display an image corresponding to an image signal and including a pad, and a driving chip including a buffer configured to provide a data signal to the pad, the method including: providing a buffer voltage to the buffer via a buffer line; outputting the data signal from the buffer to the pad; measuring a buffer current flowing through the buffer line; and Whether there is a short circuit defect between the pads is determined based on the buffer current.

9. The method according to claim 8, wherein: In the output of the data signal, odd-numbered buffers among the buffers are configured to output the data signal having a first polarity, and even-numbered buffers among the buffers are configured to output the data signal having a second polarity opposite to the first polarity.

10. The method according to claim 8 or 9, further comprising: determining a defect of the driving driver based on a current measured when a driving driver including the driving chip is enabled and the display panel is disabled; as well as A defect of the display panel is determined based on a current measured when the driving driver and the display panel are enabled.

Images