Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a display area, the display area comprises a first area and a second area at least partially surrounding the first area, a gate drive circuit and a pixel circuit electrically connected with the gate drive circuit are arranged in the first area, a trigger wire is arranged in the second area, no pixel circuit exists in the second area, and the trigger wire is electrically connected with the gate drive circuit. According to the display panel and the display device provided by the embodiment of the invention, the frameless effect can be realized, and the stability of the gate drive circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the application of display panels is becoming more and more common, and users have more and more requirements for display panels. Display panels are gradually developing towards thinness, high screen-to-body ratio, and even borderless. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a display device, which can achieve a borderless display and improve the stability of a gate driving circuit.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising a display area, the display area comprising a first area and a second area at least partially surrounding the first area, a gate driving circuit and a pixel circuit electrically connected to the gate driving circuit are provided in the first area, a trigger line is provided in the second area, and there is no pixel circuit in the second area, and the trigger line is electrically connected to the gate driving circuit.

[0005] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel as described in any embodiment of the first aspect.

[0006] In the display panel and display device provided in the embodiments of the present application, the gate drive circuit and the trigger line are both located in the display area, which can achieve a narrow frame or even no frame; in addition, the trigger line is located in the second area of ​​the periphery, and there is no pixel circuit in the second area, so that the trigger line and the pixel circuit and the signal line connected to the pixel circuit can have no overlap, which can reduce the interference of other signals on the signal on the trigger line, thereby improving the stability of the gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0008] Figure 1 A schematic diagram showing the structure of a display panel provided in an embodiment of the present application is shown;

[0009] Figure 2 Another schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown;

[0010] Figure 3 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0011] Figure 4Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0012] Figure 5 Show Figure 4 A schematic diagram of a layout structure in the Q1 area;

[0013] Figure 6 A schematic diagram of a film layer stacking of a display panel provided by an embodiment of the present application is shown;

[0014] Figure 7 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0015] Figure 8 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0016] Fig. 9 A schematic diagram showing a structure of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0017] Fig.10 Another structural schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0018] Fig.11 Another structural schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0019] Fig.12 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0020] Fig.13 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0021] Fig.14 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0022] Fig.15 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0023] Fig.16 Show Fig.13 An enlarged schematic diagram of the middle Q2 region;

[0024] Fig.17 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0025] Fig.18 A schematic diagram showing a structure of an electrostatic protection circuit in a display panel provided in an embodiment of the present application is shown;

[0026] Fig.19Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0027] Fig. 20 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0030] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0031] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0032] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0033] The term "connect" may mean "electrically connected" or "not electrically connected through an intermediate transistor". The term "insulation" may mean "electrically insulating" or "electrically isolated". The term "drive" may mean "control" or "operate". The term "part" may mean "local". The term "pattern" may mean "component". The term "end" may mean "end segment" or "end edge". The display panel may be a display device or a module / part of a display device.

[0034] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0035] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0036] The display panel includes a pixel circuit, a light-emitting device and a gate drive circuit. The gate drive circuit receives a trigger signal through a trigger line. The gate drive circuit is connected to the pixel circuit through a gate line, and a gate control signal output by the gate drive circuit is transmitted to the pixel circuit through the gate line to control the pixel circuit to generate a driving current, thereby driving the light-emitting device to emit light.

[0037] The pixel circuit and the light-emitting device are located in the display area of ​​the display panel. In the related art, the pixel circuit of the edge display area is retracted to make room for the gate drive circuit. This design method can achieve borderless design when the architecture of the gate drive circuit required by the pixel circuit is not complicated (that is, the number of gate drive circuits is not large). However, with the improvement of the driving performance requirements, the number of gate drive circuits will increase, so that the design method that only relies on the retraction of the pixel circuit in the edge display area to make room for the gate drive circuit can no longer meet the architectural design of multiple groups of gate drive circuits. In addition, the gate drive circuit is connected to the trigger signal through the trigger wiring, and the stability of the trigger signal affects the reliability of the gate drive circuit. Therefore, how to achieve borderless design and ensure the reliability of the gate drive circuit is a technical problem faced by those skilled in the art.

[0038] In order to solve the above technical problems, embodiments of the present application provide a display panel and a display device. Embodiments of the display panel and the display device will be described below in conjunction with the accompanying drawings.

[0039] like Figure 1 As shown, the display panel 100 provided in the embodiment of the present application includes a display area AA. It is understandable that the display area AA includes a pixel circuit 20 and a light emitting device ( Figure 1 (not shown in the figure), the display area AA is used to display pictures.

[0040] For example, the display panel in the embodiment of the present application is a narrow-frame or even borderless display panel, that is, the non-display area on the left and right sides of the display area AA in the first direction X is very small, or even non-display area does not exist. The drawings of the present application all take borderless display panels as examples.

[0041] The display area AA includes a first area A1 and a second area A2, and the second area A2 at least partially surrounds the first area A1. For the sake of distinction, the area filled with white in the drawings of the present application represents the first area A1, and the area filled with light gray represents the second area A2. At least part of the peripheral area of ​​the display area AA is the second area A2. Exemplarily, in the first direction X, the second area A2 is disposed on at least one side of the first area A1; in the second direction Y, the second area A2 is disposed on at least one side of the first area A1. Figure 1 In the example shown, the first area A1 is provided with the second area A2 on both sides of the first direction X, and the first area A1 is on the side of the second direction Y and away from the driver chip (ie Figure 1 The second area A2 is disposed on the upper side of the first area A1 in the middle, and the first area A1 is on the side of the second direction Y and close to the driving chip (ie Figure 1 The second area A2 is not provided on the lower side of the first area A1, but this is not intended to limit the present application.

[0042] It is understandable that light-emitting devices are disposed in both the first area A1 and the second area A2, and both the first area A1 and the second area A2 can display images.

[0043] The first area A1 is provided with a gate driving circuit 10 and a pixel circuit 20, and the gate driving circuit 10 and the pixel circuit 20 are electrically connected. The second area A2 is provided with a trigger line 30, and there is no pixel circuit in the second area A2. The trigger line 30 is electrically connected to the gate driving circuit 10.

[0044] Exemplarily, the other end of the trigger line 30 is electrically connected to a driving chip (not shown in the figure), and a trigger signal STV provided by the driving chip is transmitted to the gate driving circuit 10 through the trigger line 30, thereby triggering the gate driving circuit 10 to operate.

[0045] Exemplarily, the plurality of pixel circuits 20 are arranged in an array in a first direction X and a second direction Y. Herein, the first direction X intersects with the second direction Y. For example, the first direction X is a row direction, and the second direction Y is a column direction.

[0046] Exemplarily, in the first direction X, there is at least one column of pixel circuits 20 between the gate drive circuit 10 and the trigger trace 30. In this example, the gate drive circuit is no longer limited to the outermost edge of the display area in the first direction, but the gate drive circuit is arranged toward a position close to the center of the display area in the first direction, so that the distance between the gate drive circuit and the center of the display area can be shortened, thereby shortening the distance for the gate drive circuit to charge the pixel circuit in the center of the display area, thereby improving signal delay and voltage drop, and improving display uniformity.

[0047] There is no pixel circuit in the second area A2 . It can be understood that the trigger wiring 30 and the pixel circuit 20 do not overlap in the thickness direction of the display panel.

[0048] Exemplarily, the gate driving circuit 10 and the pixel circuit 20 are electrically connected via a gate wiring (not shown in the figure), and the gate wiring extends along the first direction X. Usually, the gate wiring is arranged in the area where the pixel circuit 20 is located, that is, the gate wiring is also arranged in the first area A1. It is understandable that the trigger wiring 30 and the gate wiring may not overlap in the thickness direction of the display panel. In this way, the interference of the signal on the gate wiring to the signal on the trigger wiring can be reduced.

[0049] Exemplarily, the pixel circuit 20 is also connected to a data line (not shown in the figure). Usually, the data line is arranged in the area where the pixel circuit 20 is located, and the data line extends along the second direction Y. In other words, the data line is also arranged in the first area A1. It is understandable that the trigger line 30 and the data line may not overlap in the thickness direction of the display panel. In this way, the interference of the signal on the data line to the signal on the trigger line can be reduced.

[0050] The pixel circuit 20 may also be connected to other signal lines, such as a reset signal line, a power signal line, etc., which are not listed here one by one.

[0051] According to the display panel provided by the embodiment of the present application, the gate drive circuit and the trigger wiring are both located in the display area, which can achieve a narrow frame or even a borderless display; in addition, the trigger wiring is located in the second area of ​​the periphery, and there is no pixel circuit in the second area, so that the trigger wiring and the pixel circuit and the signal lines connected to the pixel circuit can have no overlap, which can reduce the interference of other signals on the signals on the trigger wiring, thereby improving the stability of the gate drive circuit.

[0052] With the development of display technology, the requirements for the driving performance of display panels are getting higher and higher. In view of this, the display panel may include multiple gate driving circuits to improve the driving performance of the gate driving circuit. In the case where the gate driving circuit includes multiple ones, the trigger wiring may include multiple ones.

[0053] In some embodiments, the 1st to nth trigger lines are electrically connected to the 1st to nth gate driving circuits respectively in a one-to-one correspondence, n≥2; and there is no crossing between the 1st to nth trigger lines.

[0054] As an example, Figure 2 As shown, the display panel includes four gate drive circuits and four trigger lines. The first gate drive circuit 10 (1) is electrically connected to the first trigger line 30 (1), the second gate drive circuit 10 (2) is electrically connected to the second trigger line 30 (2), the third gate drive circuit 10 (3) is electrically connected to the third trigger line 30 (3), and the fourth gate drive circuit 10 (4) is electrically connected to the fourth trigger line 30 (4). There is no crossing between the first to fourth trigger lines.

[0055] It should be noted that the arrangement of multiple trigger lines in the drawings of the present application is only one implementation method, and other line arrangements that can achieve no crossing between multiple trigger lines are also feasible.

[0056] In this embodiment, by designing multiple trigger lines to have no intersection, parasitic capacitance formed by intersection between the trigger lines can be avoided, and signal interference between the trigger lines can be reduced, thereby ensuring the stability of the signals on each trigger line, and further ensuring the stability of each gate drive circuit.

[0057] In some embodiments, Figure 3 As shown, the trigger line includes a first section 301, a second section 302 and a third section 303 which are interconnected, the second section 302 is electrically connected between the first section 301 and the third section 303, and the first section 301 is electrically connected to a trigger signal terminal (not shown in the figure) of the driving chip, the third section 303 is electrically connected to the gate driving circuit 10, the first section 301 and the third section 303 extend along the second direction Y, and the second section 302 extends along the first direction X.

[0058] Exemplarily, the display panel includes a first center line L1, the first center line L1 extends along the second direction Y, and the first center line L1 is at the same distance from two edges of the display panel in the first direction X. For example, the distance between the first center line L1 and the edge C11 is equal to the distance between the first center line L1 and the edge C12.

[0059] It should be noted that the first center line L1 is located in the display area, and the first center line L1 is parallel or approximately parallel to the first edge C1. The first center line does not represent the actual alignment of the display panel, and can be understood as the position center line of the virtually defined display panel, that is, the first center line is used to indicate the position. The two or more parameters defined in this article as "equal", "equal to", and "=" are not absolutely equal, and a certain error is allowed. It should be noted that the equal distances mentioned in this disclosure refer to distance values ​​being equal within the allowable error range (±5%).

[0060] For the display area on any side of the first center line L1 in the first direction X, in the first direction X, the arrangement order of the first segments 301 of the 1st to nth trigger lines is opposite to the arrangement order of the 1st to nth gate drive circuits; and the arrangement order of the third segments 303 of the 1st to nth trigger lines is the same as the arrangement order of the 1st to nth gate drive circuits. In addition, in the second direction Y, the second segments of the 1st to nth trigger lines can be arranged close to the gate drive circuits in sequence.

[0061] For example, for Figure 3 The left display area of ​​the first midline L1 (i.e. Figure 3 As for the left half screen in the figure, the first gate drive circuit 10(1) to the fourth gate drive circuit 10(4) and the first trigger line 30(1) to the fourth trigger line 30(4) are electrically connected one by one, the first gate drive circuit 10(1) to the fourth gate drive circuit 10(4) are arranged away from the first center line L1 in sequence, the first section 301 of the first trigger line 30(1) to the fourth trigger line 30(4) are arranged close to the first center line L1 in sequence, and the third section 303 of the first trigger line 30(1) to the fourth trigger line 30(4) are arranged away from the first center line L1 in sequence. In addition, in the second direction Y, the second section 302 of the first trigger line 30(1) to the fourth trigger line 30(4) are arranged close to the gate drive circuit in sequence.

[0062] In this embodiment, the arrangement order of the multiple gate driving circuits and the multiple trigger lines can prevent the multiple trigger lines from crossing each other, thereby reducing mutual interference between the trigger lines.

[0063] In some embodiments, Figure 4 As shown, the trigger line 30 includes a first trigger line 31 and a second trigger line 32. In the first direction X, the first trigger line 31 and the second trigger line 32 are located on both sides of the center of the display area. A trigger connection line 40 is also provided in the second area A2. The trigger connection line 40 is electrically connected between the first trigger line 31 and the second trigger line 32.

[0064] It should be noted that, in order to facilitate the distinction between the trigger routing and the trigger connection line, the trigger routing 30 is indicated by a solid line and the trigger connection line 40 is indicated by a dotted line in the drawings herein, and the routing indicated by the dotted line is not used to indicate that the routing is disconnected.

[0065] For example, Figure 4 In the embodiment, the first trigger line 31 is located on the left side of the first center line L1, and the second trigger line 32 is located on the right side of the first center line L1. The first center line L1 is the center line of the display area. Figure 4 In the example, there are four first trigger lines 31 and four second trigger lines 32 on both sides of the first center line L1, and the four first trigger lines 31 and the four second trigger lines 32 can be electrically connected one by one through four trigger connection lines 40. For example, the first trigger connection line 40(1) is connected between the first first trigger line 31(1) and the first second trigger line 32(1), the second trigger connection line 40(2) is connected between the second first trigger line 31(2) and the second second trigger line 32(2), the third trigger connection line 40(3) is connected between the third first trigger line 31(3) and the third second trigger line 32(3), and the fourth trigger connection line 40(4) is connected between the fourth first trigger line 31(4) and the fourth second trigger line 32(4).

[0066] In this embodiment, by setting a trigger connection line, the first trigger line and the second trigger line on both sides in the first direction can be connected, so that when one of the first trigger line and the second trigger line is broken, the trigger signal can be transmitted to the gate drive circuit through the other one, and when the first trigger line and the second trigger line are both well conductive, the trigger signal can be transmitted to the gate drive circuit from both sides, which is beneficial to improving display uniformity.

[0067] It is understandable that the trigger signals on the first trigger trace and the second trigger trace that are electrically connected to each other are the same, and the signals output by the multiple gate drive circuits electrically connected to the first trigger trace and the second trigger trace that are electrically connected to each other are the same. For example, the i-th first trigger trace 31(i) is electrically connected to the gate drive circuit 10a(i), the i-th second trigger trace 32(i) is electrically connected to the gate drive circuit 10b(i), and the i-th first trigger trace 31(i) is electrically connected to the i-th second trigger trace 32(i), and the signals output by the gate drive circuit 10a(i) and the gate drive circuit 10b(i) are the same, where i is any one of 1 to n. For example, Figure 4For example, i is any one from 1 to 4, the signals output by gate drive circuit 10a(1) and gate drive circuit 10b(1) are the same, the signals output by gate drive circuit 10a(2) and gate drive circuit 10b(2) are the same, the signals output by gate drive circuit 10a(3) and gate drive circuit 10b(3) are the same, and the signals output by gate drive circuit 10a(4) and gate drive circuit 10b(4) are the same.

[0068] In some embodiments, Figure 5 As shown, at least one trigger connection line 40 includes a first connection segment 41 and a second connection segment 42 connected to each other, the first connection segment 41 at least partially overlaps with the trigger line 30, and the second connection segment 42 does not overlap with the trigger line 30. The line width of the first connection segment 41 is smaller than the line width of the second connection segment 42. In this embodiment, the line width of the first connection segment 41 is designed to be relatively small, which can avoid an excessively large overlapping area between the first connection segment 41 and the trigger line 30, thereby reducing the interference between the first connection segment 41 and the trigger line 30 that transmit different signals.

[0069] For example, the trigger connection line 40 extends along the first direction X, and the plurality of trigger connection lines 40 are arranged along the second direction Y. The first trigger connection line 40(1) is located at the outermost side, and the first trigger connection line 40(1) does not need to be designed in sections. The second trigger connection line 40(2) to the fourth trigger line 40(4) can all include a first connection segment 41 and a second connection segment 42 electrically connected to each other. For at least one trigger connection line 40, both ends of the first connection segment 41 are electrically connected to the second connection segment 42, and at least one second connection segment 42 is connected to the trigger line 30.

[0070] Exemplarily, the crossing length required for the trigger connection line 40 and the trigger routing line 30 extending along the second direction Y is relatively small. For a trigger connection line 40, the total length of the first connection segment 41 of the trigger connection line 40 is smaller than the total length of the second connection segment 42, so that the thicker second connection segment 42 occupies most of the trigger connection line 40, thereby avoiding excessive increase in the total impedance of the trigger connection line 40.

[0071] In some embodiments, Figure 5 and Figure 6 As shown, the display panel includes a first metal layer M1 and a second metal layer M2, and the first metal layer M1 and the second metal layer M2 are separated by an insulating layer. The materials of the first metal layer M1 and the second metal layer M2 can be different. The square resistance of the second metal layer M2 is smaller than the square resistance of the first metal layer M1.

[0072] Exemplarily, the first connection segment 41 is located on the first metal layer M1 of the display panel, and the second connection segment 42 is located on the second metal layer M2 of the display panel. The first connection segment 41 and the second connection segment 42 are connected through a via.

[0073] For a trigger connection line 40, the total length of the second connection segment 42 of the trigger connection line 40 is greater than the total length of the first connection segment 41. In this embodiment, the second connection segment 42 is arranged on the second metal layer M2 with lower square resistance, so that the impedance of the second connection segment 42 is lower, and thus the total impedance of the trigger connection line 40 is lower, thereby reducing the signal delay caused by the larger impedance.

[0074] In some embodiments, the first trigger trace 31 and the second trigger trace 32 may also be located in the second metal layer M2. In this way, when the first trigger trace 31 and the second trigger trace 32 are connected to the trigger connection line 40, it is not necessary to set a connecting via, and the first trigger trace 31 and the second trigger trace 32 and the second connection section 42 in the trigger connection line 40 can be integrally formed.

[0075] For example, for a trigger connection line that is not designed in segments (e.g. Figure 4 The trigger connection line 40(1)) may also be located in the second metal layer M2.

[0076] In some embodiments, Figure 6 As shown, the display panel includes a substrate 01, a first metal layer M1 is located between a second metal layer M2 and the substrate 01, wherein the gate of the transistor in the gate driving circuit is located on the first metal layer.

[0077] Exemplarily, the display panel further includes a semiconductor layer B and a capacitor metal layer MC, the semiconductor layer B is located between the first metal layer M1 and the substrate 01, and the capacitor metal layer MC is located between the first metal layer M1 and the second metal layer M2. The active layer of the transistor in the gate drive circuit is arranged on the semiconductor layer B. As an example, the material of the semiconductor layer B includes polycrystalline silicon (poly).

[0078] As described in the above embodiments, a light-emitting device is also provided in the area where the trigger wiring is located.

[0079] In some embodiments, Figure 7 As shown, the display area of ​​the display panel includes a plurality of light emitting device columns 50b and a plurality of light emitting device rows 50a. The plurality of light emitting device rows 50a are arranged in the second direction Y, and each light emitting device row 50a includes a plurality of light emitting devices arranged in the first direction X. The plurality of light emitting device columns 50b are arranged in the first direction X, and each light emitting device column 50b includes a plurality of light emitting devices arranged in the second direction Y. Figure 7In the figure, the light emitting device includes a first light emitting device 51, a second light emitting device 52 and a third light emitting device 53, and the light emitting colors of the first light emitting device 51, the second light emitting device 52 and the third light emitting device 53 can be different from each other. Exemplarily, the first light emitting device 51, the second light emitting device 52 and the third light emitting device 53 constitute a light emitting unit for displaying white light. A light emitting device column 50b can include at least one column of first light emitting devices 51, at least one column of second light emitting devices 52 and at least one column of third light emitting devices 53.

[0080] In the thickness direction of the display panel, the trigger trace 30 overlaps with the first light emitting device column 50 b ( 1 ) or the last light emitting device column 50 b (m).

[0081] For example, the first light-emitting device column 50b(1) is located on the first side of the display panel, and the last light-emitting device column 50b(m) is located on the second side of the display panel. Exemplarily, when trigger lines are provided on both sides in the first direction X, the first light-emitting device column 50b(1) overlaps with the trigger line 30 on the first side of the display panel, and the last light-emitting device column 50b(m) overlaps with the trigger line 30 on the second side of the display panel.

[0082] In this embodiment, the trigger line is designed to overlap with the first or last light emitting device column, which can ensure that the trigger line is located at the periphery of the display panel in the first direction, thereby reducing interference of other signal lines on the trigger line.

[0083] In some embodiments, Figure 7 As shown, in the thickness direction of the display panel, the trigger trace 30 at least partially overlaps with the first light-emitting device row 50a(1).

[0084] In the second direction Y, the first light emitting device row 50a(1) is located on the third side of the display panel, and the last light emitting device row 50a(k) is located on the fourth side of the display panel. The third side of the display panel may be a side away from the driver chip, and the fourth side of the display panel may be a side close to the driver chip. In this embodiment, the trigger line is designed to at least partially overlap with the first light emitting device row, which can ensure that the trigger line is located at the periphery of the display panel in the second direction, thereby reducing interference of other signal lines on the trigger line.

[0085] In some embodiments, Figure 8As shown, the display area of ​​the display panel includes a first center line L1, the width of the display panel in the first direction X is D, the first center line L1 extends along the second direction Y, the distance between the first center line L1 and the first edge C1 of the display panel in the first direction X is d1, d1=D / 2, and at least one gate driving circuit 10 is disposed on both sides of the first center line L1 in the first direction X. The first edge C1 is an edge of the display panel extending along the second direction Y, and the display panel includes a first edge C1 on both sides of the first direction X, one of the first edges C1 is a left first edge C11, and the other first edge C1 is a right first edge C12, and the distances between the first center line L1 and the left first edge C11 and the right first edge C12 are both d1.

[0086] The trigger line 30 and the gate drive circuit 10 on the first side of the first center line L1 are respectively the first trigger line 31 and the first group of gate drive circuits 10a, and the first trigger line 31 and the first group of gate drive circuits 10a are electrically connected. The trigger line 30 and the gate drive circuit 10 on the second side of the first center line L1 are respectively the second trigger line 32 and the second group of gate drive circuits 10b, and the second trigger line 32 and the second group of gate drive circuits 10b are electrically connected.

[0087] In this embodiment, it is equivalent to dividing the display panel into two half-screens in the first direction, and a gate driving circuit is arranged in each half-screen, which breaks the conventional design thinking and no longer limits the gate driving circuit to the edge display area. Instead, the gate driving circuit is dispersed on both sides of the first center line. In this way, even if the number of gate driving circuits is large, there is enough display area to accommodate them, thereby realizing a narrow frame or even no frame. In addition, compared with limiting the gate driving circuit to the edge display area, dispersing the gate driving circuit on both sides of the first center line can shorten the distance between at least part of the gate driving circuit and the center of the display area, thereby shortening the distance for the gate driving circuit to charge to the center of the display area, thereby improving signal delay and voltage drop, and improving display uniformity.

[0088] In some embodiments, n gate driving circuits 10 are disposed on both sides of the first center line L1 in the first direction X, and the gate driving circuits 10 on both sides of the first center line L1 are symmetrically disposed.

[0089] As an example, 7 gate drive circuits are arranged on both sides of the first center line L1 in the first direction X, and each side includes a first gate drive circuit 11, a second gate drive circuit 12, a third gate drive circuit 13, a fourth gate drive circuit 14, a fifth gate drive circuit 15, a sixth gate drive circuit 16 and a seventh gate drive circuit 17. The signals output by the two first gate drive circuits 11 are the same, the signals output by the two second gate drive circuits 12 are the same, the signals output by the two third gate drive circuits 13 are the same, the signals output by the two fourth gate drive circuits 14 are the same, the signals output by the two fifth gate drive circuits 15 are the same, the signals output by the two sixth gate drive circuits 16 are the same, and the signals output by the two seventh gate drive circuits 17 are the same.

[0090] The two first gate drive circuits 11 are symmetrical about the first center line L1, the two second gate drive circuits 12 are symmetrical about the first center line L1, the two third gate drive circuits 13 are symmetrical about the first center line L1, the two fourth gate drive circuits 14 are symmetrical about the first center line L1, the two fifth gate drive circuits 15 are symmetrical about the first center line L1, the two sixth gate drive circuits 16 are symmetrical about the first center line L1, and the two seventh gate drive circuits 17 are symmetrical about the first center line L1.

[0091] For example, in order to meet the driving requirements of high-resolution display panels, such as micro LED (Micro Light Emitting Diode) or organic LED (Organic Light Emitting Diode) display panels, a pixel circuit combining pulse amplitude modulation (Pulse Amplitude Modulation, PAM) and pulse width modulation (Pulse Width Modulation, PWM) is used to control the driving current intensity and the duration of the driving current to control the light-emitting state of the light-emitting device.

[0092] In some embodiments, Figures 9 to 11 As shown in any of the figures, the pixel circuit 20 of the display panel includes an amplitude modulation subcircuit 21 and a pulse width modulation subcircuit 22, and the pixel circuit 20 generates a driving current under the control of the amplitude modulation subcircuit 21 and the pulse width modulation subcircuit 22. The amplitude modulation subcircuit 21 can be used to control the amplitude of the driving current, and the pulse width modulation subcircuit 22 can be used to adjust the pulse width of the voltage applied to the first electrode of the light emitting device 50.

[0093] The pulse width modulation subcircuit 22 adjusts the pulse width of the voltage applied to the first electrode of the light-emitting device 50, that is, the pulse width modulation subcircuit 22 adjusts the actual emission period of the driving current applied to the light-emitting device 50, and at the same time, the driving current applied to the light-emitting device is maintained at a constant level to adjust the grayscale or brightness displayed by the light-emitting device, rather than adjusting the grayscale or brightness displayed by the light-emitting device by only adjusting the magnitude of the driving current applied to the light-emitting device. Therefore, the amplitude modulation subcircuit 21 can provide the driving current to the light-emitting device so that the light-emitting device is driven with the best luminous efficiency, and adjust the grayscale or brightness displayed by the light-emitting device by adjusting the light-emitting duty cycle of the light-emitting device (that is, the emission period of the light-emitting device) through the pulse width modulation subcircuit 22.

[0094] It should be noted that Figures 9 to 11 The circuit structure shown is only exemplary and is not intended to limit the present application. Regardless of the specific structures of the amplitude modulation subcircuit and the pulse width modulation subcircuit in the pixel circuit, both of them usually need to write data signals. Therefore, the design concept of the gate drive circuit in the present application can also be applied to Figures 9 to 11 Pixel circuits with other structural forms than the circuit structure shown.

[0095] Exemplarily, the gate signal PAM_S2 output by the first gate driving circuit 11 is used to control the first data signal PAM_data to be written into the amplitude modulation sub-circuit 21, the gate signal PWM_S2 output by the second gate driving circuit 12 is used to control the second data signal PWM_data to be written into the pulse width modulation sub-circuit 22, the gate signal PAM_S1 output by the third gate driving circuit 13 is used to control the reset signal PAM_REF1 to be written into the amplitude modulation sub-circuit 21, and the gate signal PWM_S1 output by the fourth gate driving circuit 14 is used to control the reset signal PWM_REF1 to be written into the pulse width modulation sub-circuit 22. In addition, the fifth gate driving circuit 15 is used to output the first light emission control signal PAM_EM, the sixth gate driving circuit 16 is used to output the second light emission control signal PWM_EM, and the seventh gate driving circuit 17 is used to output the sweep signal SWEEP. The fifth gate driving circuit 15 is electrically connected to the amplitude modulation sub-circuit 21, and the sixth gate driving circuit 16 and the seventh gate driving circuit 17 are electrically connected to the pulse width modulation sub-circuit 22.

[0096] In some embodiments, Figure 8 As shown, the distance between the second center line L2 of the display area and the first center line L1 of the display panel in the first direction X is d2, d2=D / 4, and at least one gate driving circuit 10 is disposed on both sides of the second center line L2 in the first direction X.

[0097] Exemplarily, the second center line L2 includes a first second center line L21 and a second second center line L22, the first second center line L21 and the second second center line L22 are respectively located on both sides of the first center line L1, the distance between the first second center line L21 and the edge C11 is also d2, the distance between the second second center line L22 and the edge C12 is also d2, the first second center line L21, the second second center line L22 and the first center line L1 are equivalent to dividing the display area into four sub-areas, and a gate driving circuit is provided in each sub-area.

[0098] Exemplarily, the plurality of gate driving circuits on the first side of the first center line L1 are distributed close to the first second center line L21, and the plurality of gate driving circuits on the second side of the first center line L1 are distributed close to the second second center line L22. For example, the first gate driving circuit 11 and the second gate driving circuit 12 are arranged close to the second center line L2. In this example, for any first gate driving circuit 11 or any second gate driving circuit 12, the transmission distance of its output signal is only about one-fourth of the width D of the display panel, which can more effectively shorten the distance for the gate driving circuit to transmit the signal to the pixel circuit, thereby improving the signal delay and voltage drop, and improving the display uniformity.

[0099] This technical concept can also be explained by the positional relationship between the gate driving circuit and the pixel.

[0100] In some embodiments, Fig.12 As shown, the display panel 100 includes N pixel circuit columns 201 arranged in a first direction X, where N is an integer, and the pixel circuit column 201 includes a plurality of pixel circuits 20 arranged in the first direction X. At least one gate driving circuit 10 is disposed on both sides of the N / 4th pixel circuit column 201 (1 / 4) in the first direction X, where N / 4 is an integer.

[0101] In other words, the display panel includes N pixel columns arranged in a first direction, N is an integer, and the pixel column includes a plurality of pixel circuits arranged in the first direction. At least one gate driving circuit is disposed on both sides of the N / 4th pixel column in the first direction, wherein N / 4 is an integer.

[0102] like Fig.12 As shown, the pixel circuit columns are marked from left to right, and the N / 4th pixel circuit column 201 (1 / 4) and the 3N / 4th pixel circuit column 201 (3 / 4) are marked respectively. It can be understood that the 3N / 4th pixel circuit column 201 (3 / 4) from left to right is the N / 4th pixel circuit column 201 from right to left.

[0103] The N / 4th pixel circuit column 201 may include the N / 4th pixel circuit column 201 from left to right, and the N / 4th pixel circuit column 201 from right to left.

[0104] Exemplarily, the N / 4th pixel circuit column 201 from left to right is provided with at least one gate driving circuit 10 on both sides in the first direction X, and the N / 4th pixel circuit column 201 from right to left is provided with at least one gate driving circuit 10 on both sides in the first direction X.

[0105] For example, N=240, from left to right, at least one gate driving circuit is provided on both sides of the 60th pixel circuit column in the first direction, and from left to right, at least one gate driving circuit is provided on both sides of the 180th pixel circuit column in the first direction. In other words, N=240, from right to left, at least one gate driving circuit is provided on both sides of the 60th pixel circuit column in the first direction, and from right to left, at least one gate driving circuit is provided on both sides of the 180th pixel circuit column in the first direction.

[0106] This embodiment improves the positional relationship between the gate driving circuit and the pixel circuit column, and no longer limits the gate driving circuit to the edge display area. Instead, the gate driving circuit is dispersed on both sides of the N / 4th pixel circuit column. In this way, even if the number of gate driving circuits is large, there is enough display area to accommodate them, thereby achieving borderless display. In addition, compared with limiting the gate driving circuit to the edge display area, dispersing the gate driving circuit on both sides of the N / 4th pixel circuit column can shorten the distance between at least part of the gate driving circuit and the center of the display area, thereby shortening the distance for the gate driving circuit to charge to the center of the display area, thereby improving signal delay and voltage drop, and improving display uniformity.

[0107] In some embodiments, Fig.13 As shown, the display panel further includes an electrostatic loop line 61, at least part of which is located on a side of the trigger line 30 away from the center O1 of the display panel. The center O1 is located at the midpoint of the first center line L1 in the second direction Y.

[0108] Exemplarily, the electrostatic loop line 61 includes a first protection segment 611 extending along the second direction Y and a second protection segment 612 extending along the first direction X. In the first direction X, the first protection segment 611 is located on the side of the trigger line 30 away from the first center line L1. In the second direction Y, the second protection segment 612 is located on the side of the trigger line 30 away from the center O1. Exemplarily, the second protection segment 612 is also located on the side of the trigger connection line 40 away from the center O1.

[0109] The electrostatic loop 61 is used to access the ground signal (GND signal), and the electrostatic loop 61 can be used to prevent the electrostatic signal from affecting the signal line on the display panel. In this example, the trigger line 30 and the trigger connection line 40 are arranged inside the electrostatic loop 61, so that the electrostatic loop 61 can reverse the influence of the external static electricity on the trigger line 30 and the trigger connection line 40.

[0110] In some embodiments, please refer to Fig.13 The display panel further includes a fixed voltage signal line 62 , at least a portion of the fixed voltage signal line 62 is located on a side of the trigger line 30 close to the center O1 of the display panel.

[0111] For example, in the first direction X, both sides of the first center line L1 are provided with fixed voltage signal lines 62, and the fixed voltage signal lines 62 may include a first fixed voltage signal line 62 (VH) and a second fixed voltage signal line 62 (VL), the first fixed voltage signal line 62 (VH) is used to transmit a high level, and the second fixed voltage signal line 62 (VL) is used to transmit a low level. In the first direction X, the first fixed voltage signal line 62 (VH) and the second fixed voltage signal line 62 (VL) are located on one side of the trigger line 30 close to the first center line L1.

[0112] In this example, since a fixed voltage signal is transmitted on the fixed voltage signal line 62 , the fixed voltage signal line 62 can shield the interference of other signal lines on the trigger line 30 , thereby further ensuring the stability of the signal on the trigger line 30 .

[0113] In some embodiments, Fig.14 As shown, the gate driving circuit 10 includes a first end and a second end opposite to each other in the second direction Y, and the first end of the gate driving circuit 10 is connected to the trigger wiring 30. The display panel also includes a first electrostatic protection circuit 71, which is electrically connected to the trigger wiring 30, and the first electrostatic protection circuit 71 is adjacent to the first end of the gate driving circuit 10.

[0114] Exemplarily, the first electrostatic protection circuit 71 is used to release static electricity on the trigger wiring 30 , thereby providing electrostatic protection for the trigger wiring 30 .

[0115] Exemplarily, the trigger trace 30 includes a first section 301 , a second section 302 and a third section 303 which are connected to each other, the third section 303 is connected to the first end of the gate drive circuit 10 , and the third section 303 is electrically connected to the first electrostatic protection circuit 71 .

[0116] In this example, the first electrostatic protection circuit 71 and the gate driving circuit 10 are designed in a proximity principle, for example Fig.14The first electrostatic protection circuit 71 is distributed above the gate driving circuit 10, breaking the traditional design of designing the electrostatic protection circuit at the left and right corners of the display panel, so as to avoid the trigger line extending inward and being affected by the surrounding electrostatic environment.

[0117] Exemplarily, in the direction from the second section 302 to the first end of the gate drive circuit 10, the third section 303 is first connected to the first electrostatic protection circuit 71, and then connected to the first end of the gate drive circuit 10. In this example, the signal on the trigger trace 30 is first protected by the first electrostatic protection circuit 71, and then transmitted to the gate drive circuit 10, which can avoid the influence of external static electricity on the gate drive circuit as much as possible.

[0118] In some embodiments, Fig.14 As shown, the 1st to nth trigger lines 30 are electrically connected to the 1st to nth gate drive circuits 10 respectively, and the 1st to nth trigger lines 30 are electrically connected to the 1st to nth first electrostatic protection circuits 71 respectively, n≥2; the jth first electrostatic protection circuit is adjacent to the first end of the jth gate drive circuit, and j is any one from 1 to n.

[0119] For example, Fig.14 In the embodiment, the left half screen and the right half screen are both provided with 4 trigger lines 30, 4 gate drive circuits 10 and 4 first electrostatic protection circuits. For the left half screen or the right half screen, the 4 first electrostatic protection circuits 71 are arranged one by one above the 4 gate drive circuits 10. Each trigger line 30 is first connected to the first electrostatic protection circuit 71, and then connected to the gate drive circuit 10. The signals on each trigger line 30 are first protected by the first electrostatic protection circuit 71, and then transmitted to the gate drive circuit 10.

[0120] In this embodiment, multiple first electrostatic protection circuits 71, multiple trigger lines 30 and multiple gate drive circuits 10 are arranged in a one-to-one correspondence, and the first electrostatic protection circuit 71 is arranged close to the gate drive circuit 10 corresponding to the first electrostatic protection circuit 71, so that better electrostatic protection can be performed for each gate drive circuit 10.

[0121] In some embodiments, Fig.14 As shown, the trigger trace 30 includes a first section 301, a second section 302 and a third section 303 which are connected to each other, the second section 302 is electrically connected between the first section 301 and the third section 303, and the first section 301 is electrically connected to the trigger signal terminal (not shown in the figure) of the driver chip, the third section 303 is electrically connected to the gate drive circuit 10, the first section 301 and the third section 303 extend along the second direction Y, and the second section 302 extends along the first direction X. In the second direction Y, the first electrostatic protection circuit 71 is located between the second section 302 and the gate drive circuit 10.

[0122] For the second section 302 and the third section 303 in the same trigger line, the third section 303 is located at a side of the second section 302 close to the gate driving circuit 10 .

[0123] In this embodiment, the first electrostatic protection circuit 71 is disposed between the second section 302 and the gate driving circuit 10, further ensuring that the first electrostatic protection circuit 71 can be disposed close to the gate driving circuit 10 to ensure the electrostatic protection effect.

[0124] In some embodiments, Fig.15 For example, the display area includes a plurality of light emitting device rows 50a, each of which includes a plurality of light emitting devices arranged along a first direction X, and the light emitting devices may include a first light emitting device 51, a second light emitting device 52 and a third light emitting device 53. The plurality of light emitting device rows are arranged along a second direction Y.

[0125] The orthographic projection of the first electrostatic protection circuit 71 on the plane where the display panel is located is located between the orthographic projection of the first light-emitting device row 50a(1) on the plane where the display panel is located and the orthographic projection of the second light-emitting device row 50a(2) on the plane where the display panel is located.

[0126] For example, the sizes of the plurality of pixel circuits in the display panel in the first direction and the second direction may be compressed, and in the first direction X, there is space between adjacent pixel circuits to place the gate driving circuit; and in the first direction X, there is space around the display area to place the trigger wiring. In the second direction Y, there is space around the display area to place the trigger wiring and the first electrostatic protection circuit.

[0127] In some embodiments, please refer to Fig.13 and Fig.16 , the first end of the trigger trace 30 is electrically connected to the trigger signal end 80, in the second direction Y, the trigger signal end 80 is located at one side of the gate drive circuit 10, and in the first direction X, the trigger signal end 80 is located between the gate drive circuit 10 and the trigger trace 30. The trigger signal end 80 is electrically connected to the drive chip, and the trigger signal end 80 is used to transmit the trigger signal provided by the drive chip to the trigger trace 30.

[0128] That is to say, in the first direction X, the trigger signal terminal 80 is arranged close to the first edge C1 of the display panel, which is equivalent to arranging the trigger signal terminal 80 at the lower left corner and / or lower right corner of the display panel, thereby providing trigger signals for the trigger traces on the left and right sides.

[0129] In some embodiments, please refer to Fig.13 and Fig.16The display panel further includes a second electrostatic protection circuit 72, which is electrically connected to the trigger wiring 30, and the second electrostatic protection circuit 72 is adjacent to the trigger signal terminal 80. In other words, the second electrostatic protection circuit 72 is arranged near the trigger signal terminal 80, and the second electrostatic protection circuit 72 is also arranged at the lower left corner and / or lower right corner of the display panel.

[0130] The second electrostatic protection circuit 72 is electrically connected between the trigger signal terminal 80 and the trigger wiring 30. The signal output from the trigger signal terminal 80 is protected by the second electrostatic protection circuit 72 and then transmitted to the trigger wiring 30, thereby ensuring the electrostatic protection effect on the signal passing through the trigger wiring 30.

[0131] In some embodiments, Figures 9 to 11 As shown in any of the figures, the pixel circuit 20 includes an amplitude modulation subcircuit 21 and a pulse width modulation subcircuit 22. Fig.17 As shown, the gate driving circuit includes a first type of gate driving circuit 10c and a second type of gate driving circuit 10d. The first type of gate driving circuit 10c is used to drive the amplitude modulation sub-circuit 21, and the second type of gate driving circuit 10d is used to drive the pulse width modulation sub-circuit 22. For example, the gate signal PAM_S2 output by the first gate driving circuit 11 is used to control the first data signal PAM_data to be written into the amplitude modulation sub-circuit 21, the gate signal PWM_S2 output by the second gate driving circuit 12 is used to control the second data signal PWM_data to be written into the pulse width modulation sub-circuit 22, the gate signal PAM_S1 output by the third gate driving circuit 13 is used to control the reset signal PAM_REF1 to be written into the amplitude modulation sub-circuit 21, and the gate signal PWM_S1 output by the fourth gate driving circuit 14 is used to control the reset signal PWM_REF1 to be written into the pulse width modulation sub-circuit 22. In addition, the fifth gate drive circuit 15 is used to output the first light-emitting control signal PAM_EM, the sixth gate drive circuit 16 is used to output the second light-emitting control signal PWM_EM, the seventh gate drive circuit 17 is used to output the sweep signal SWEEP, the fifth gate drive circuit 15 is electrically connected to the amplitude modulation subcircuit 21, and the sixth gate drive circuit 16 and the seventh gate drive circuit 17 are electrically connected to the pulse width modulation subcircuit 22. The first type of gate drive circuit 10c includes a first gate drive circuit 11, a third gate drive circuit 13, and a fifth gate drive circuit 15. The second type of gate drive circuit 10d includes a second gate drive circuit 12, a fourth gate drive circuit 14, a sixth gate drive circuit 16, and a seventh gate drive circuit 17.

[0132] The fixed voltage signal lines 62 of the display panel include first-type fixed voltage signal lines 62c and second-type fixed voltage signal lines 62d. The first-type fixed voltage signal lines 62c are electrically connected to the first-type gate driving circuit 10c, and the second-type fixed voltage signal lines 62d are electrically connected to the second-type gate driving circuit 10d.

[0133] Exemplarily, the first type of solid voltage signal line 62c includes a first sub-solid voltage signal line 62c1 and a second sub-solid voltage signal line 62c2, the first sub-solid voltage signal line 62c1 is used to transmit a first high level voltage VGH1, and the second sub-solid voltage signal line 62c2 is used to transmit a first low level voltage VGL1.

[0134] The second type of solid voltage signal line 62d includes a third sub-solid voltage signal line 62d1 and a fourth sub-solid voltage signal line 62d2. The third sub-solid voltage signal line 62d1 is used to transmit a second high level voltage VGH2. The fourth sub-solid voltage signal line 62d2 is used to transmit a second low level voltage VGL2.

[0135] Exemplarily, the first high level voltage VGH1 is not equal to the second high level voltage VGH2, and / or the first low level voltage VGL1 is not equal to the second low level voltage VGL2. For example, the first high level voltage VGH1 is 3V, and the first low level voltage VGL1 is -12V. For another example, the second high level voltage VGH2 is 8V, and the second low level voltage VGL2 is -7V.

[0136] In this embodiment, two types of fixed voltage signal lines are designed to supply power to two types of gate drive circuits respectively, and the power supplied by the two types of gate drive circuits is used to drive the amplitude modulation sub-circuit and the pulse width modulation sub-circuit respectively. This facilitates flexible adjustment of the size of the fixed voltage signals on the two types of fixed voltage signal lines according to the respective needs of the amplitude modulation sub-circuit and the pulse width modulation sub-circuit, so as to better meet the source-drain voltage of the transistors in the amplitude modulation sub-circuit and the pulse width modulation sub-circuit, thereby reducing the threshold voltage drift and leakage of the transistors.

[0137] In some embodiments, when the gate driving circuit includes a first type of gate driving circuit and a second type of gate driving circuit, as shown in FIG. Fig.18 As shown, the electrostatic protection circuit of the display panel can be divided into a first type of electrostatic protection circuit 70c and a second type of electrostatic protection circuit 70d, and the trigger line can be divided into a first type of trigger line 30c connected to the first type of gate drive circuit and a second type of trigger line 30d connected to the second type of gate drive circuit. The first type of electrostatic protection circuit 70c is electrically connected to the first type of trigger line 30c, and the second type of electrostatic protection circuit 70d is electrically connected to the second type of trigger line 30d. In addition, the first type of electrostatic protection circuit 70c is electrically connected to the first type of fixed voltage signal line 62c, and the second type of electrostatic protection circuit 70d is electrically connected to the second type of fixed voltage signal line 62d.

[0138] For example, Fig.18 As shown, the first type of electrostatic protection circuit 70c and the second type of electrostatic protection circuit 70d both include a first end 2201 and a second end 2202. The first end 2201 of the first type of electrostatic protection circuit 70c is electrically connected to the first type of trigger wiring 30c, and the second end 2202 of the first type of electrostatic protection circuit 70c is electrically connected to the first type of fixed voltage signal line 62c. The first end 2201 of the second type of electrostatic protection circuit 70d is electrically connected to the second type of trigger wiring 30d, and the second end 2202 of the second type of electrostatic protection circuit 70d is electrically connected to the second type of fixed voltage signal line 62d.

[0139] As an example, the first type of electrostatic protection circuit 70c includes a first transistor T1 and a second transistor T2. The control terminal and the first terminal of the first transistor T1 are both electrically connected to the first sub-solid voltage signal line 62c1, the second terminal of the first transistor T1 is electrically connected to the control terminal and the first terminal of the second transistor T2, and is electrically connected to the first type of trigger wiring 30c as the first terminal 2201; the second terminal of the second transistor T2 is electrically connected to the second sub-solid voltage signal line 62c2.

[0140] The second type of electrostatic protection circuit 70d includes a third transistor T3 and a fourth transistor T4. The control end and the first end of the third transistor T3 are both electrically connected to the third sub-solid voltage signal line 62d1, the second end of the third transistor T3 is electrically connected to the control end and the first end of the fourth transistor T4, and is electrically connected to the second type of trigger wiring 30d as the first end 2201; the second end of the fourth transistor T4 is electrically connected to the fourth sub-solid voltage signal line 62d2.

[0141] The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 can be as follows: Fig.18 The example is an N-channel transistor, and it can also be a P-channel transistor, which is not limited here.

[0142] The following takes the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 as examples where they are all N-type channel transistors to introduce the working principle of the electrostatic protection circuit:

[0143] For the first type of electrostatic protection circuit 70c, when the first type of trigger wiring 30c generates high voltage static electricity, the high voltage static electricity voltage signal of the first type of trigger wiring 30c is input to the first end 2201 of the first type of electrostatic protection circuit 70c. At this time, the first transistor T1 is turned on, and the high voltage static electricity signal is released through the first transistor T1 to the first sub-solid voltage signal line 62c1 that transmits the high level voltage VGH1.

[0144] When the first type of trigger wiring 30c generates low-voltage static electricity, the low-voltage static electricity voltage signal of the first type of trigger wiring 30c is input to the first end 2201 of the first type of static electricity protection circuit 70c. At this time, the second transistor T2 is turned on, and the low-voltage static electricity signal is released through the second transistor T2 to the second sub-solid voltage signal line 62c2 that transmits the low-level voltage VGL1, thereby realizing static electricity release.

[0145] The working principle of the second type of electrostatic protection circuit 70d is the same as the working principle of the first type of electrostatic protection circuit 70c, which will not be repeated here.

[0146] In summary, the first type of electrostatic protection circuit 70c and the second type of electrostatic protection circuit 70d can effectively release the high-voltage static electricity and low-voltage static electricity generated in the display panel, and can avoid static electricity from damaging the internal structure of the panel, thereby ensuring the quality and performance of the display panel.

[0147] certainly, Fig.18 The structure of the electrostatic protection circuit shown is merely an example and is not intended to limit the present application.

[0148] It is understandable that the first protection circuit introduced in the above embodiment can be divided into a first type of electrostatic protection circuit and a second type of electrostatic protection circuit, and the second protection circuit can also be divided into a first type of electrostatic protection circuit and a second type of electrostatic protection circuit, which will not be repeated here.

[0149] For example, Fig.19 As shown, the gate driving circuit includes a plurality of cascaded shift registers VSR, and the plurality of shift registers VSR are arranged in the second direction Y. Exemplarily, the size of the pixel circuit 20 in the second direction Y is compressed so that there is space between the pixel circuits 20 in the second direction Y to set the shift register VSR. Exemplarily, the orthographic projections of the shift register VSR and the pixel circuit 20 on the plane where the display panel is located do not overlap.

[0150] It should be noted that the number of signal lines and the number of gate driving circuits shown in the various drawings of the present application are merely exemplary and are not intended to limit the present application.

[0151] The present application also provides a display device, including the display panel provided by the present application. Fig. 20 , Fig. 20 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig. 20 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Fig. 20The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0152] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: The display area includes a first area and a second area at least partially surrounding the first area, a gate drive circuit and a pixel circuit electrically connected to the gate drive circuit are provided in the first area, a trigger line is provided in the second area, and no pixel circuit is provided in the second area, and the trigger line is electrically connected to the gate drive circuit.

2. The display panel according to claim 1, characterized in that: The first to nth trigger lines are electrically connected to the first to nth gate drive circuits in a one-to-one correspondence, respectively, and n≥2; There is no crossing between the trigger traces described in item 1 to item n.

3. The display panel according to claim 2, characterized in that: The trigger trace comprises a first section, a second section and a third section which are connected to each other, the second section is electrically connected between the first section and the third section, the first section is electrically connected to the trigger signal terminal, the third section is electrically connected to the gate drive circuit, the second section extends along a first direction, the first section and the third section extend along a second direction, and the first direction and the second direction intersect; In the first direction, the arrangement order of the first segments of the 1st to nth trigger lines is opposite to the arrangement order of the 1st to nth gate drive circuits; and the arrangement order of the third segments of the 1st to nth trigger lines is the same as the arrangement order of the 1st to nth gate drive circuits.

4. The display panel according to claim 1, characterized in that: The trigger wiring includes a first trigger wiring and a second trigger wiring, and in a first direction, the first trigger wiring and the second trigger wiring are located on both sides of the center of the display area; A trigger connection line is also provided in the second area, and the trigger connection line is electrically connected between the first trigger wiring and the second trigger wiring.

5. The display panel according to claim 4, characterized in that: At least one of the trigger connection lines comprises a first connection segment and a second connection segment connected to each other, the first connection segment at least partially overlaps with the trigger line, and the second connection segment does not overlap with the trigger line; The line width of the first connecting segment is smaller than the line width of the second connecting segment.

6. The display panel according to claim 5, characterized in that: The first connecting segment is located at a first metal layer of the display panel, and the second connecting segment is located at a second metal layer of the display panel. The sheet resistance of the second metal layer is smaller than that of the first metal layer.

7. The display panel according to claim 6, characterized in that: The first trigger trace and the second trigger trace are located in the second metal layer.

8. The display panel according to claim 6, characterized in that: The display panel includes a substrate, the first metal layer is located between the second metal layer and the substrate, and the gate of the transistor in the gate driving circuit is located in the first metal layer.

9. The display panel according to claim 1, characterized in that: The display area includes a plurality of light emitting device columns, and in the thickness direction of the display panel, the trigger line overlaps with the first light emitting device column or the last light emitting device column.

10. The display panel according to claim 1, characterized in that: The display area includes a plurality of light emitting device rows, and in the thickness direction of the display panel, the trigger wiring at least partially overlaps with the first light emitting device row.

11. The display panel according to claim 1, characterized in that: The display area includes a first center line, the width of the display panel in the first direction is D, the first center line extends along the second direction, the distance between the first center line and the first edge of the display panel in the first direction is d1, d1=D / 2, at least one gate drive circuit is arranged on both sides of the first center line in the second direction, and the first direction and the second direction intersect.

12. The display panel according to claim 11, characterized in that: N gate driving circuits are respectively arranged on both sides of the first center line in the first direction, and the gate driving circuits on both sides of the first center line are symmetrically arranged.

13. The display panel according to claim 11, characterized in that: The distance between the second center line of the display area and the first center line in the first direction is d2, d2=D / 4, and at least one of the first gate driving circuits is disposed on both sides of the second center line in the first direction.

14. The display panel according to claim 11, characterized in that: The display panel includes N pixel circuit columns arranged in the first direction, and the pixel circuit columns include a plurality of pixel circuits arranged in the second direction; At least one gate driving circuit is disposed on both sides of the N / 4th pixel circuit column in the first direction, wherein N / 4 is an integer.

15. The display panel according to claim 1, characterized in that: The display panel further includes an electrostatic loop line, and at least a portion of the electrostatic loop line is located on a side of the trigger line away from the center of the display panel.

16. The display panel according to claim 1, characterized in that: The display panel further includes a fixed voltage signal line, and at least a portion of the fixed voltage signal line is located on a side of the trigger line close to the center of the display panel.

17. The display panel according to claim 1, characterized in that: The gate drive circuit comprises a first end and a second end opposite to each other in a first direction, and the first end of the gate drive circuit is connected to the trigger trace; The display panel further includes a first electrostatic protection circuit, the first electrostatic protection circuit is electrically connected to the trigger wiring, and the first electrostatic protection circuit is adjacent to a first end of the gate driving circuit.

18. The display panel according to claim 17, characterized in that: The display area includes multiple rows of light-emitting devices, and the orthographic projection of the first electrostatic protection circuit on the plane where the display panel is located is located between the orthographic projection of the first row of light-emitting devices on the plane where the display panel is located and the orthographic projection of the second row of light-emitting devices on the plane where the display panel is located.

19. The display panel according to claim 17, characterized in that: The first to nth trigger lines are electrically connected to the first to nth gate drive circuits in a one-to-one correspondence, respectively, and the first to nth trigger lines are electrically connected to the first to nth first electrostatic protection circuits in a one-to-one correspondence, respectively, n≥2; The jth first electrostatic protection circuit is adjacent to the first end of the jth gate driving circuit, where j is any one from 1 to n.

20. The display panel according to claim 19, characterized in that: The trigger trace comprises a first section, a second section and a third section which are connected to each other, the second section is electrically connected between the first section and the third section, the first section is electrically connected to the trigger signal terminal, the third section is electrically connected to the gate drive circuit, the first section and the third section extend along a second direction, the second section extends along a first direction, and the first direction and the second direction intersect; In the second direction, the first electrostatic protection circuit is located between the second segment and the gate driving circuit.

21. The display panel according to claim 1, characterized in that: The first end of the trigger line is electrically connected to the trigger signal end, in the second direction, the trigger signal end is located on one side of the gate drive circuit, and in one direction, the trigger signal end is located between the gate drive circuit and the trigger line.

22. The display panel according to claim 21, characterized in that: The display panel further includes a second electrostatic protection circuit, the second electrostatic protection circuit is electrically connected to the trigger wiring, and the second electrostatic protection circuit is adjacent to the trigger signal terminal.

23. The display panel according to claim 1, characterized in that: The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit, and the gate drive circuit includes a first type of gate drive circuit and a second type of gate drive circuit, the first type of gate drive circuit is used to drive the amplitude modulation subcircuit, and the second type of gate drive circuit is used to drive the pulse width modulation subcircuit; The fixed-voltage signal lines of the display panel include first-type fixed-voltage signal lines and second-type fixed-voltage signal lines. The first-type fixed-voltage signal lines are electrically connected to the first-type gate driving circuits, and the second-type fixed-voltage signal lines are electrically connected to the second-type gate driving circuits.

24. The display panel according to claim 23, characterized in that: The electrostatic protection circuit of the display panel includes a first type of electrostatic protection circuit and a second type of electrostatic protection circuit, the first type of electrostatic protection circuit is electrically connected to the trigger wiring connected to the first type of gate driving circuit, and the second type of electrostatic protection circuit is electrically connected to the trigger wiring connected to the second type of gate driving circuit; The first type of electrostatic protection circuit is electrically connected to the first type of fixed voltage signal line, and the second type of electrostatic protection circuit is electrically connected to the second type of fixed voltage signal line.

25. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1-24.

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