Sensing amplifying circuit and memory device
By introducing an N-type well into the sensing amplification circuit of the memory device and electrically connecting it, the negative bias temperature instability problem of the P-type transistor is solved, and the sensing accuracy is improved.
Patent Information
- Application Number
- CN202311210508.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-19
- Publication Date
- 2025-03-21
AI Technical Summary
The sensing amplifier in the memory device causes the sensing accuracy to be reduced due to the negative bias temperature instability (NBTI) of the P-type transistor.
A sense amplifier circuit is designed to reduce the voltage difference between the gate and the N-well of the P-type transistor by introducing an N-type well into the first P-type transistor and electrically connecting its source to the base, thereby reducing the negative bias temperature instability.
It effectively reduces the negative bias temperature instability of the sensing amplifier and improves the sensing accuracy.
Smart Images
Figure CN119673232A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a sensing amplifier circuit for a memory device. Background Art
[0002] A plurality of sense amplifiers are configured in the memory device to sense and amplify the voltage or signal read from the memory cell to generate a corresponding data signal. Generally speaking, a sense amplifier includes an inverter composed of a group of P-type transistors and N-type transistors. The base of the P-type transistor of the inverter is usually connected to a voltage source so that the N-type well of the P-type transistor has a high voltage of the voltage source. When the input of the inverter is pulled to a low level or 0 volts, the voltage difference between the gate of the P-type transistor and the N-type well is large, which results in a large electric field between the gate of the P-type transistor and the N-type well. Therefore, the P-type transistor has obvious negative bias temperature instabilities (NBTI), which reduces the sensing accuracy of the sense amplifier. Summary of the invention
[0003] In view of this, the present invention proposes a sensing amplifier circuit. The sensing amplifier circuit is coupled to a memory cell through a data line, and includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The first P-type transistor has a gate coupled to the data line at an input node, a source and a base coupled to a first node, and a drain coupled to an output node. The second P-type transistor has a gate coupled to a reverse read trigger signal, a source coupled to a voltage source, and a drain coupled to the first node. The first N-type transistor has a gate coupled to the input node, a drain coupled to the output node, and a source coupled to a ground. The second N-type transistor has a gate for receiving a reverse read trigger signal, a drain coupled to the output node, and a source coupled to the ground. The first P-type transistor further includes an N-type well, and the source and base of the first P-type transistor are electrically connected to the N-type well.
[0004] The present invention provides a memory device. The memory device includes a selection switch, a memory cell, and a sensing amplifier circuit. The selection switch is coupled between a first voltage source and a first node and is controlled by a reverse selection signal, wherein the first node is coupled to a word line. The memory cell is coupled between the first node and a data line and is controlled by a programming signal, a read trigger signal, and a first reverse read trigger signal. The sensing amplifier circuit is coupled to the data line and includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The first P-type transistor has a gate coupled to the data line at an input node, a source and a base coupled to a second node, and a drain coupled to an output node. The second P-type transistor has a gate for receiving a second reverse read trigger signal, a source coupled to a second voltage source, and a drain coupled to the second node. The first N-type transistor has a gate coupled to the input node, a drain coupled to the output node, and a source coupled to a ground. The second N-type transistor has a gate receiving the second reverse read trigger signal, a drain coupled to the output node, and a source coupled to the ground. The first P-type transistor further includes an N-type well, and the source and base of the first P-type transistor are electrically connected to the N-type well. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Figure 1 Schematic diagram of a memory device according to an embodiment of the present invention.
[0006] Figure 2 FIG. 4 shows a memory cell and a sense amplifier circuit according to an embodiment of the present invention.
[0007] Figure 3 FIG. 4 shows a memory cell and a sense amplifier circuit according to another embodiment of the present invention.
[0008] Figure 4 FIG. 4 shows a memory cell and a sense amplifier circuit according to another embodiment of the present invention.
[0009] 1: Memory device
[0010] 10(0)~10(31):Selection switch
[0011] 11(0)~11(31):Sense amplifier (SA) circuit
[0012] 12: Memory Array
[0013] 20: Fuse unit
[0014] 21~23: N-type transistor
[0015] 24: P-type transistor
[0016] 25~26: P-type transistor
[0017] 27~29: N-type transistor
[0018] 30: P-type transistor
[0019] 100(0,0)~100(0,31): memory cell
[0020] D0~D31: data signal
[0021] DL0~DL31: Data line
[0022] GND: Ground
[0023] MRb: Reverse Margin Read Enable Signal
[0024] N20, N21, N23: nodes
[0025] N22: Input node
[0026] N24: Output node
[0027] Read(0,0)~Read(31,31): read trigger signal
[0028] Readb0~Readb31: reverse read trigger signal
[0029] Readb(0,0)~Readb(31,31): Reverse read trigger signal
[0030] PRG(0,0)~PRG(31,31): programming signal
[0031] SELb0~SELb31: Reverse selection signal
[0032] V21~V23: voltage
[0033] VDD, VPP: voltage source
[0034] WL0~WL31: word line DETAILED DESCRIPTION
[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, a preferred embodiment is given below and described in detail with reference to the accompanying drawings.
[0036] Figure 1 denoted as a memory device according to an embodiment of the present invention. Figure 1 As shown, the memory device 1 includes a plurality of word lines, a plurality of data lines, a plurality of selection switches, a plurality of memory cells, and a plurality of sensing amplifier (SA) circuits. Figure 1In the embodiment, 32 word lines WL0~WL31 and 32 data lines DL0~DL31 are used as examples for explanation. Multiple memory cells are configured into a memory array 12 having multiple columns and multiple rows, and each memory cell is coupled to a group of word lines and data lines. Memory cells configured in the same column are coupled to the same word line, and memory cells configured in the same row are coupled to the same data line. For example, memory cells 100(0,0)~100(0,31) configured in the same column are coupled to word line WL0, and are respectively coupled to data lines DL0~DL31; memory cells 100(31,0)~100(31,31) configured in the same column are coupled to word line WL31, and are respectively coupled to data lines DL0~DL31. In other words, the memory cells 100(0,0) to 100(31,0) arranged in the same row are coupled to the data line DL0 and are respectively coupled to the word lines WL0 to WL31; the memory cells 100(0,31) to 100(31,31) arranged in the same row are coupled to the data line DL31 and are respectively coupled to the word lines WL0 to WL31.
[0037] Each memory unit receives and is controlled by a corresponding programming signal, and receives two read trigger signals that are inverted from each other. Figure 1 , memory cells 100(0,0)~100(0,31) receive programming signals PRG(0,0)~PRG(0,31) respectively, and memory cells 100(31,0)~100(31,31) receive programming signals PRG(31,0)~PRG(31,31) respectively. Memory cell 100(0,0) receives a read trigger signal Read(0,0) and an inverted read trigger signal Readb(0,0) which are inverted to each other, memory cell 100(0,1) receives a read trigger signal Read(0,1) and an inverted read trigger signal Readb(0,1) which are inverted to each other, memory cell 100(0,31) receives a read trigger signal Read(0,31) and an inverted read trigger signal Readb(0,31) which are inverted to each other, memory cell 100(31,0) receives a read trigger signal Read(31,0) and an inverted read trigger signal Readb(31,0) which are inverted to each other, memory cell 100(31,1) receives a read trigger signal Read(31,1) and an inverted read trigger signal Readb(31,1) which are inverted to each other, memory cell 100(31,31) receives a read trigger signal Read(0,31) and an inverted read trigger signal Readb(31,31) which are inverted to each other.
[0038] The above-mentioned multiple sense amplifier circuits are coupled to data lines DL0~DL31, and one data line is coupled to one sense amplifier circuit. Therefore, the memory device 1 includes 32 sense amplifier circuits 11(0)~11(31). In this embodiment, the sense amplifier circuits 11(0)~11(31) receive reverse read trigger signals Readb0~Readb31 respectively. When one of the reverse read trigger signals Readb0~Readb31 is disabled, the corresponding sense amplifier circuit performs a sensing operation to generate a corresponding data signal. For example, when the reverse read trigger signal Readb0 is disabled, the sense amplifier circuit 11(0) performs a sensing operation to generate a data signal D0; when the reverse read trigger signal Readb1 is disabled, the sense amplifier circuit 11(1) performs a sensing operation to generate a data signal D1; when the reverse read trigger signal Readb31 is disabled, the sense amplifier circuit 11(31) performs a sensing operation to generate a data signal D31.
[0039] The selection switches 10(0) to 10(31) are implemented by P-type transistors. In the following description, the selection switches 10(0) to 10(31) will be referred to as P-type transistors. Figure 1 As shown, the P-type transistors 10(0)-10(31) are respectively coupled to the word lines WL0-WL31 and are respectively controlled by the reverse selection signals SELb0-SELb31. The P-type transistors 10(0)-10(31) are all coupled to the voltage source VPP. For example, the gate of the P-type transistor 10(0) receives the corresponding reverse selection signal SELb0, the source thereof is coupled to the voltage source VPP, and the drain thereof is coupled to the corresponding word line WL0.
[0040] The memory device 1 can be operated in a write mode, a read mode, or a standby mode. When performing a write or programming operation on at least one memory cell in the write mode, the corresponding one of the P-type transistors 10(0) to 10(31) is turned on by disabling one of the reverse selection signals SELb0 to SELb31, thereby selecting a word line. In this embodiment, based on the conductivity type of the P-type transistors 10(0) to 10(31), the disabled reverse selection signal among the reverse selection signals SELb0 to SELb31 has a low voltage level. For example, when the reverse selection signal SELb0 is disabled and is at a low voltage level, the P-type transistor 10(0) is turned on to select the word line WL0. At this time, at least one of the programming signals PRG(0,0) to PRG(0,31) is enabled to select the corresponding memory cell. In this embodiment, among the programming signals PRG(0,0)-PRG(0,31), the enabled programming signals have a high voltage level. Therefore, it can be known that by controlling the enable or disable state of the reverse selection signals SELb0-SELb31 and the programming signals PRG(0,0)-PRG(31,31), a selection operation of at least one memory cell in the write mode can be implemented.
[0041] In the write mode, the selected memory cell is programmed by the current induced by the voltage source VPP to complete the write operation.
[0042] When a read operation is performed on at least one memory cell in a read mode, the corresponding one of the P-type transistors 10(0)-10(31) is turned on by disabling one of the reverse selection signals SELb0-SELb31, thereby selecting a word line. For example, when the reverse selection signal SELb0 is disabled and is at a low voltage level, the P-type transistor 10(0) is turned on to select the word line WL0. At this time, the read trigger signal and the reverse read trigger signal of at least one of the memory cells 10(0,0)-10(0,31) coupled to the word line WL0 are enabled and disabled, respectively. Therefore, it can be seen that by controlling the enable or disable state of the reverse selection signals SELb0-SELb31 and the read trigger signal and the reverse read trigger signal of each memory cell, a selection operation on at least one memory cell in a read mode can be achieved.
[0043] In the read mode, the read trigger signal and the reverse read trigger signal of the selected memory cell are enabled and disabled respectively to trigger the read operation, and the sense amplifier circuit coupled to the selected memory cell performs a sense operation to generate a corresponding data signal. For example, when the reverse selection signal SELb0 is disabled, when the read trigger signal Read(0,0) and the reverse read trigger signal Readb(0,0) are enabled and disabled respectively, the memory cell 100(0,0) is selected. In this embodiment, the enabled read trigger signal Read(0,0) has a high voltage level, and the disabled reverse read trigger signal Readb(0,0) has a low voltage level. At this time, the reverse read trigger signal Readb0 is disabled, so that the sense amplifier 11(0) circuit coupled to the memory cell 100(0,0) through the data line DL0 performs a sense operation to generate the data signal D0.
[0044] In standby mode, the above-mentioned selection operation of the memory cell is not performed, and the read trigger signal and the reverse read trigger signal of each memory cell are disabled and enabled respectively. For example, the read trigger signal Read(0,0) and the reverse read trigger signal Readb(0,0) of the memory cell 100(0,0) are disabled and enabled respectively. In this embodiment, the disabled read trigger signal Read(0,0) has a low voltage level, and the enabled reverse read trigger signal Readb(0,0) has a high voltage level. At this time, no signal or data is read out from the memory cell. In standby mode, the reverse read trigger signals Readb0~Readb31 are all enabled to reset the sense amplifier circuits 11(0)~11(31) so that the data signals D0~D31 are at a preset low voltage level. In an embodiment, the enabled reverse read trigger signal is at a high voltage level.
[0045] The operation of the memory device 1 will be described below by taking the memory cell 100 ( 0 , 0 ) and the P-type transistor 10 ( 0 ) coupled thereto and the sense amplifier circuit 11 ( 0 ) as an example.
[0046] See also Figure 2 , the memory cell 100(0,0) includes a fuse unit 20, N-type transistors 21-23, and a P-type transistor 24. The first end of the fuse unit 20 is coupled to the drain of the P-type transistor 10(0) at a node N20, and the second end thereof is coupled to a node N21. Figure 1 and Figure 2It can be seen that the memory cell 100 (0, 0) is coupled to the word line WL0 through the node N20. The gate of the N-type transistor 21 receives the programming signal PRG (0, 0), the drain thereof is coupled to the node N21, and the source thereof is coupled to the ground GND. The gate of the N-type transistor 22 receives the read trigger signal Read (0, 0), the drain thereof is coupled to the node N21, and the source thereof is coupled to the ground GND.
[0047] The gate of the N-type transistor 23 receives the read trigger signal Read(0,0), the drain thereof is coupled to the node N21, and the source thereof is coupled to the input node N22. The gate of the P-type transistor 24 receives a gate of the reverse read trigger signal Readb(0,0), the source thereof is coupled to the node N21, and the drain thereof is coupled to the input node N22. Figure 1 and Figure 2 According to the connection structure between the N-type transistor 23 and the P-type transistor 24 and the received read trigger signal Read(0,0) and the reverse read trigger signal Readb(0,0), the N-type transistor 23 and the P-type transistor 24 form a pass gate.
[0048] In this embodiment, the P-type transistor 10 ( 0 ) and the N-type transistor 21 have larger sizes, while the N-type transistor 22 has a smaller size. Therefore, compared with the P-type transistor 10 ( 0 ) and the N-type transistor 21 , the N-type transistor 22 has a larger equivalent resistance.
[0049] The sense amplifier circuit 11(0) includes P-type transistors 25 and 26 and N-type transistors 27 to 29. The gate of the P-type transistor 25 is coupled to the input node N22 to couple to the data line DL0, the source and base thereof are coupled to the node N23, and the drain thereof is coupled to the output node N24. The P-type transistor 25 includes an N-type well, and the source and base of the P-type transistor 25 are electrically connected to the N-type well. The gate of the P-type transistor 26 receives the reverse read trigger signal Readb0, the source thereof is coupled to the voltage source VDD, and the drain thereof is coupled to the node N23. The gate of the N-type transistor 27 is coupled to the input node N22, the drain thereof is coupled to the output node N24, and the source thereof is coupled to the ground GND. The gate of the N-type transistor 28 receives the reverse read trigger signal Readb0, the drain thereof outputs the node N24, and the source thereof is coupled to the ground GND. The gate of the N-type transistor 29 receives the reverse read trigger signal Readb0 , the drain thereof is coupled to the input node N22 , and the source thereof is coupled to the ground GND.
[0050] In one embodiment, the P-type transistor 25 has a double guard ring structure to avoid a latch-up effect in the P-type transistor 25 .
[0051] When the memory device 1 operates in the write mode and is to perform a write or programming operation on the memory cell 100(0,0), the reverse selection signal SELb0 is disabled and has a low voltage level to turn on the P-type transistor 10(0), and the programming signal PRG(0,0) is enabled and has a high voltage level to turn on the N-type transistor 21. At this time, a large current flows from the voltage source VPP through the P-type transistor 10(0), the fuse unit 20, and the N-type transistor 21 to blow the fuse unit 20. The blown fuse unit 20 is in an open circuit state and has a large resistance value.
[0052] When the memory device 1 operates in the read mode and is to perform a read operation on the memory cell 100 (0, 0), the reverse selection signal SELb0 is disabled and has a low voltage level to turn on the P-type transistor 10 (0), and the read trigger signal Read (0, 0) and the reverse read trigger signal Readb (0, 0) are enabled and disabled respectively. The enabled read trigger signal Read (0, 0) has a high voltage level to turn on the N-type transistors 22 and 23, and the disabled reverse read trigger signal Readb (0, 0) has a low voltage level to turn on the P-type transistor 24. In addition, the programming signal PRG (0, 0) is disabled and has a low voltage level to turn off the N-type transistor 21. As described above, the N-type transistor 22 has a larger equivalent resistance value. Therefore, due to the larger equivalent resistance value of the N-type transistor 22, the current flowing from the voltage source VPP through the P-type transistor 10 (0), the fuse unit 20, and the N-type transistor 22 is smaller. As a result, in the read mode, the unblown fuse unit 20 will not be mistakenly blown by the small current. Based on the small current and the resistance value of the fuse unit 20, a voltage V21 is generated on the node N21.
[0053] As described above, both the N-type transistor 23 and the P-type transistor 24 are turned on, so the voltage V22 on the input node N22 is equal to the voltage V21. The voltage V22 is the voltage read from the memory cell 100 (0, 0), which indicates whether the fuse unit 20 is blown, that is, it indicates the data stored in the memory cell 100 (0, 0). When the fuse unit 20 is blown, the voltages V21 and V22 have a lower voltage level (e.g., a voltage level close to the ground GND or 0 volts (V)); when the fuse unit 20 is not blown, the voltages V21 and V22 have a higher voltage level (e.g., a voltage level close to the voltage source VPP).
[0054] In addition, in the read mode, the reverse read trigger signal Readb0 is disabled and has a low voltage level to turn off the N-type transistors 28 and 29 and turn on the P-type transistor 26. At this time, the source of the P-type transistor 25 is coupled to the voltage source VDD, and the P-type transistor 25 and the N-type transistor 27 perform a reverse operation according to the voltage V22 at the input node N22 to generate the data signal D0 at the output node N24. The data signal D0 represents the data stored in the memory cell 100 (0, 0).
[0055] In the standby mode, the reverse selection signal SELb0 is enabled to turn off the P-type transistor 10(0), and the read trigger signal and the reverse read trigger signal of each memory cell are disabled and enabled, respectively. For example, the read trigger signal Read(0,0) and the reverse read trigger signal Readb(0,0) are disabled and enabled, respectively. The disabled read trigger signal Read(0,0) has a low voltage level to turn off the N-type transistors 22 and 23, and the enabled reverse read trigger signal Readb(0,0) has a high voltage level to turn off the P-type transistor 24. Therefore, it can be seen that the memory device 1 does not perform write operations and read operations on the memory cell 100(0,0).
[0056] In addition, in the standby mode, the reverse read trigger signal Readb0 is enabled and has a high voltage level to turn on the N-type transistors 28 and 29 and turn off the P-type transistor 26. Since the N-type transistor 28 is turned on, the voltage on the output node N24 (i.e., the voltage on the drain of the P-type transistor 25) is close to or equal to 0V of the ground GND, that is, the data signal D0 is reset to a preset low voltage level. In addition, since the N-type transistor 29 is turned on, the voltage V22 on the input node N22 (i.e., the voltage on the gate of the P-type transistor 25) is close to or equal to 0V of the ground GND to turn on the P-type transistor 25 and turn off the N-type transistor 27. Since the P-type transistor 26 is turned off, the source and base of the P-type transistor 25 are isolated from the voltage source VDD, so that the node N23 (i.e., the source and base of the P-type transistor 25) is in a floating state. The voltage V23 on the node N23 (i.e., the voltage on the source and the voltage on the base of the P-type transistor 25) starts to discharge from the high voltage level of the parasitic capacitance remaining on the node N23 through the turned-on P-type transistor 25 and the turned-on N-type transistor 28 until the voltage V23 is equal to the threshold voltage (Vtp) of the P-type transistor 25.
[0057] According to the above, the base of the P-type transistor 25 is electrically connected to the N-type well. Therefore, the voltage of the N-type well of the P-type transistor 25 is equal to the threshold voltage (Vtp) of the P-type transistor 25. It can be seen that the voltage difference between the gate and the well of the P-type transistor 25 is equal to the threshold voltage (Vtp), which is about 0.7V of a low level. The vertical electric field between the gate and the well of the P-type transistor 25 is small, which reduces or eliminates the negative bias temperature instabilities (NBTI) of the P-type transistor 25, thereby improving the sensing accuracy of the sense amplifier circuit 11 (0).
[0058] In addition, according to the above, in the standby mode, the voltage V22 on the input node N22 is close to or equal to 0V of the ground GND, and the voltage on the output node N24 is close to or equal to 0V of the ground GND. Therefore, the voltages of the gate, drain, source, and base of the N-type transistor 27 are all close to or equal to 0V of the ground GND, and the positive bias temperature instabilities (PBTI) of the N-type transistor 27 are also reduced or eliminated.
[0059] In other embodiments, the N-type transistor 29 may not be configured. Figure 3 , the sense amplifier circuit 11 (0) does not include the N-type transistor 29. Figure 3 In the embodiment of the present invention, in the write mode and the read mode, the operation of the P-type transistor 10(0), the memory cell 100(0,0), and the sense amplifier circuit 11(0) is the same as Figure 2 For details, please refer to Figure 2 The embodiments of the present invention are omitted here.
[0060] exist Figure 3 In the embodiment of the present invention, in the standby mode, the reverse selection signal SELb0 is enabled to turn off the P-type transistor 10(0), and the read trigger signal and the reverse read trigger signal of each memory cell are disabled and enabled respectively. For example, the read trigger signal Read(0,0) and the reverse read trigger signal Readb(0,0) are disabled and enabled respectively. The disabled read trigger signal Read(0,0) has a low voltage level to turn off the N-type transistors 22 and 23, and the enabled reverse read trigger signal Readb(0,0) has a high voltage level to turn off the P-type transistor 24. Therefore, it can be seen that the memory device 1 does not perform write operations and read operations on the memory cell 100(0,0).
[0061] In addition, in the standby mode, the reverse read signal Readb0 is enabled and has a high voltage level to turn on the N-type transistor 28 and turn off the P-type transistor 26. Since the N-type transistor 28 is turned on, the voltage on the output node N24 (i.e., the voltage on the drain of the P-type transistor 25) is close to or equal to 0V of the ground GND, that is, the data signal D0 is reset to a preset low voltage level. Since the P-type transistor 26 is turned off, the source and base of the P-type transistor 25 are isolated from the voltage source VDD, so that the node N23 (i.e., the source and base of the P-type transistor 25) is in a floating state. However, because the P-type transistor 26 has just been disconnected, the voltage V23 of the node N23 will be floating but close to or equal to the voltage source VDD at the beginning.
[0062] exist Figure 3 In the embodiment of FIG. 1 , in the standby mode, since the memory device 1 does not perform a read operation on the memory cell 100 (0, 0), the voltage V22 on the input node N22 (ie, the voltage on the gate of the P-type transistor 25 ) is also in a floating state.
[0063] Assume that when the voltage V22 on the input node N22 is in a floating state and is close to or equal to 0V of the ground GND, the P-type transistor 25 is turned on and the N-type transistor 27 is turned off. The voltage V23 on the node N23 (i.e., the voltage on the source and the voltage on the base of the P-type transistor 25) begins to discharge through the turned-on P-type transistor 25 and the turned-on N-type transistor 28 until the voltage V23 is equal to the threshold voltage (Vtp) of the P-type transistor 25. According to the above, the base of the P-type transistor 25 is electrically connected to the N-type well. Therefore, the voltage of the N-type well of the P-type transistor 25 is equal to the threshold voltage (Vtp) of the P-type transistor 25. It can be seen that the voltage difference between the gate and the well of the P-type transistor 25 is equal to the threshold voltage (Vtp), which is approximately 0.7V of the low level. The vertical electric field between the gate and the well of the P-type transistor 25 is small, which reduces or eliminates the negative bias temperature instability (NBTI) of the P-type transistor 25, thereby improving the sensing accuracy of the sense amplifier circuit 11 (0).
[0064] Assume that when the voltage V22 on the input node N22 is in a floating state and is close to or equal to the voltage of the voltage source VDD, the P-type transistor 25 is turned off. According to the above, the voltage V23 on the node N23 is initially equal to the voltage of the voltage source VDD. Therefore, the voltage difference between the gate and the well of the P-type transistor 25 is equal to 0V. The absence of a vertical electric field between the gate and the well of the P-type transistor 25 eliminates the negative bias temperature instability (NBTI) of the P-type transistor 25.
[0065] Assume that when the voltage V22 on the input node N22 is in a floating state and is between 0V and the voltage of the voltage source VDD, the P-type transistor 25 and the N-type transistor 27 are both turned on. Therefore, the voltage V23 on the node N23 is equal to (voltage V22+Vpt). Therefore, the voltage difference between the gate and the well of the P-type transistor 25 is equal to the threshold voltage (Vtp), which is about 0.7V of a low level. The vertical electric field between the gate and the well of the P-type transistor 25 is small, which reduces or eliminates the negative bias temperature instability (NBTI) of the P-type transistor 25.
[0066] In other cases, when the memory device 1 performs a write or programming operation on the memory cell 100 (0, 0) to write a predetermined data, the fuse unit 20 may not be completely blown (weakly programmed) and has a smaller resistance value. In the read mode, compared with the voltage V22 on the input node N22 when the fuse unit 20 is completely blown, the voltage V22 on the input node N22 when the fuse unit 20 is not completely blown has a higher voltage level, which will affect the sensing accuracy of the sense amplifier circuit 11 (0), so that the data signal D0 cannot correctly represent the predetermined data stored in the memory cell 100 (0, 0).
[0067] In other embodiments, the voltage V22 can be increased to a specific voltage level, and the amplifier circuit 11(0) can accurately perform a sensing operation to generate a data signal D0 that correctly represents the predetermined data stored in the memory cell 100(0,0). In this way, such fuse cells 20 that may not be completely blown (weakly programmed) can be tested early. Figure 4 , the sense amplifier circuit 11(0) further includes a P-type transistor 30. The gate of the P-type transistor 30 receives the reverse edge read enable signal MRb, the source thereof is coupled to the voltage source VDD, and the drain thereof is coupled to the input node N22. The P-type transistor 30 is used to simulate the level of the voltage V22 when the fuse unit 20 is not completely blown but the data signal D0 can correctly represent the predetermined data stored in the memory cell 100(0,0) (corresponding to the completely blown fuse unit 20).
[0068] In any of the write mode, read mode, and standby mode of the memory device 1, the reverse edge read enable signal MRb is enabled to have a high voltage level to turn off the P-type transistor 30. At this time, the operation of the P-type transistor 10(0), the memory cell 100(0,0), and the sense amplifier circuit 11(0) is the same as Figure 2 For details, please refer to Figure 2 The embodiments of the present invention are omitted here.
[0069] exist Figure 4In the embodiment of the present invention, the memory device 1 can also operate in a marginal read mode. In the marginal read mode, the memory device 1 performs the following operations on the memory cell 100 (0, 0): Figure 2 The read operation described in the embodiment of the present invention generates a voltage V22 on the input node N22, and the operation of the elements 26-29 in the sense amplifier circuit 11(0) is the same as Figure 2 In the embodiment of the present invention, the data signal D0 is generated. In addition, in the marginal read mode, the reverse marginal read enable signal MRb is disabled and has a low voltage level to turn on the P-type transistor 30. According to the voltage of the voltage source VDD and the size of the P-type transistor 30, in the marginal read mode, the voltage V22 on the input node N22 is increased by a specific voltage level. By adjusting the size or parameter setting of the components in the sense amplifier circuit 11 (0), the sense amplifier circuit 11 (0) can generate the data signal D0 that correctly represents the predetermined data stored in the memory cell 100 (0, 0) according to the voltage V22 that is increased by a specific voltage level. In this way, it is ensured that when the fuse unit 20 is completely blown, the data signal D0 can still correctly represent the predetermined data stored in the memory cell 100 (0, 0). When the fuse unit 20 that should be completely blown is actually not completely blown (weak programming), the data signal D0 can still identify the predetermined data stored in the erroneous memory cell 100 (0, 0) in advance.
[0070] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.
Claims
1. A sensing amplifier circuit, characterized in that: A memory unit is coupled via a data line, comprising: a first P-type transistor having a gate coupled to the data line at an input node, a source and a base coupled to a first node, and a drain coupled to an output node; a second P-type transistor having a gate coupled to a reverse read trigger signal, a source coupled to a voltage source, and a drain coupled to the first node; a first N-type transistor having a gate coupled to the input node, a drain coupled to the output node, and a source coupled to a ground; and a second N-type transistor having a gate receiving the reverse read trigger signal, a drain coupled to the output node, and a source coupled to the ground; The first P-type transistor further includes an N-type well, and the source and the base of the first P-type transistor are electrically connected to the N-type well.
2. The sensing amplifier circuit according to claim 1, wherein: Also includes: A third N-type transistor has a gate receiving the reverse read trigger signal, a drain coupled to the input node, and a source coupled to the ground.
3. The sensing amplifier circuit according to claim 1, wherein: Also includes: A third P-type transistor has a gate coupled to a reverse edge read enable signal, a source coupled to the voltage source, and a drain coupled to the input node.
4. The sensing amplifier circuit as claimed in claim 3, wherein: Also includes: When the memory cell operates in one of a write mode, a read mode, and a standby mode, the reverse edge read enable signal is enabled; as well as When the memory cell operates in a marginal read mode, the negative marginal read enable signal is disabled.
5. The sensing amplifier circuit as claimed in claim 1, wherein: Also includes: When the memory unit operates in a standby mode, the reverse read trigger signal is enabled; as well as When the memory cell operates in a read mode, the inverted read trigger signal is disabled.
6. The sensing amplifier circuit according to claim 1, wherein: The first P-type transistor has a double guard ring structure.
7. A memory device, characterized in that: include: a selection switch coupled between a first voltage source and a first node and controlled by a reverse selection signal, wherein the first node is coupled to a word line; a memory unit coupled between the first node and a data line and controlled by a programming signal, a read trigger signal, and a first reverse read trigger signal; and A sensing amplifier circuit is coupled to the data line, wherein the sensing amplifier circuit comprises: A first P-type transistor having a gate coupled to the data line at an input node, a source and a base coupled to a second node, and a drain coupled to an output node; a second P-type transistor having a gate receiving a second reverse read trigger signal, a source coupled to a second voltage source, and a drain coupled to the second node; a first N-type transistor having a gate coupled to the input node, a drain coupled to the output node, and a source coupled to a ground; and a second N-type transistor having a gate receiving the second reverse read trigger signal, a drain coupled to the output node, and a source coupled to the ground; The first P-type transistor further includes an N-type well, and the source and the base of the first P-type transistor are electrically connected to the N-type well.
8. The memory device according to claim 7, wherein: The sense amplifier further comprises: A third N-type transistor has a gate receiving the second reverse read trigger signal, a drain coupled to the input node, and a source coupled to the ground.
9. The memory device according to claim 7, wherein: The sensing amplifier circuit further comprises: A third P-type transistor has a gate coupled to a reverse edge read enable signal, a source coupled to the second voltage source, and a drain coupled to the input node.
10. The memory device according to claim 9, wherein: Also includes: When the memory cell operates in one of a write mode, a read mode, and a standby mode, the reverse edge read enable signal is enabled; as well as When the memory cell operates in a marginal read mode, the negative marginal read enable signal is disabled.
11. The memory device according to claim 7, wherein: Also includes: When the memory unit operates in a standby mode, the second reverse read trigger signal is enabled; and When the memory cell operates in a read mode, the second inverted read trigger signal is disabled.
12. The memory device according to claim 7, wherein: The first P-type transistor has a double guard ring structure.
13. The memory device according to claim 7, wherein: The memory unit comprises: a fuse unit coupled between the first node and a third node; A third N-type transistor has a gate for receiving the programming signal, a drain coupled to the third node, and a source coupled to the ground; A fourth N-type transistor has a gate receiving the read trigger signal, a drain coupled to the third node, and a source coupled to the ground; a fifth N-type transistor having a gate receiving the read trigger signal, a drain coupled to the third node, and a source coupled to the data line; and A third P-type transistor has a gate receiving the first reverse read trigger signal, a source coupled to the third node, and a drain coupled to the data line.
14. The memory device of claim 13, wherein: When the memory cell operates in a read mode, the read trigger signal and the first inverted read trigger signal are enabled and disabled respectively.