Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate which comprises a chip region and a suspension region located around the chip region, and the suspension region plays a role in supporting a part which is to be connected to the substrate and exceeds the chip region on the substrate; a dielectric layer and a wiring layer located in the dielectric layer are formed on the substrate; wherein a first groove is formed in the suspended area before and after the dielectric layer is formed or at the same time, and the height difference between the first groove and the surface of the chip area is within a set specification. According to the invention, the influence on the stability of a photoetching process and a planarization process by a newly added suspended region on the outer side of the chip region can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] For 2.5D packaging technology, the interposer includes not only the chip area, but also an overhang area around the chip area. The overhang area on the interposer is used to expand the chip area. Compared with an interposer without an overhang area, an interposer with an overhang area can carry more chips. The overhang area supports the part of the chip to be connected to the interposer that exceeds the chip area on the interposer.

[0003] Usually, there is no pattern in the suspended area, which causes a higher protrusion to be formed in the area where the suspended area is located due to the load effect of the CMP process during the production of the adapter board, thereby affecting the subsequent photolithography process; and due to the presence of the protrusion, the metal material (such as copper) at the bottom corner of the protrusion is not easily ground away, resulting in residual metal material.

[0004] Therefore, how to prevent the suspended area from affecting the photolithography process and the grinding process is a problem that needs to be solved urgently. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to prevent the newly added suspended area outside the chip area from affecting the stability of the photolithography process and the planarization process.

[0006] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] Provide a substrate, the substrate comprising a chip area and a suspended area located around the chip area, the suspended area plays a supporting role for a portion to be connected to the substrate beyond the chip area on the substrate;

[0008] forming a dielectric layer and a wiring layer located in the dielectric layer on the substrate;

[0009] Wherein, before, during or at the same time as the dielectric layer is formed, a first groove is formed in the suspended area, and a height difference between the first groove and the surface located in the chip area is within a set specification.

[0010] Optionally, before forming the dielectric layer, the first groove is formed in the substrate located in the suspended area, and the first groove extends from the surface of the substrate into the substrate.

[0011] Optionally, the dielectric layer and the wiring layer each have at least two layers;

[0012] After forming any one of the dielectric layers, forming the first groove in any one of the dielectric layers located in the suspended area.

[0013] Optionally, forming a dielectric layer on the substrate and a wiring layer located in the dielectric layer includes:

[0014] forming a dielectric layer on the substrate;

[0015] forming a through hole in the dielectric layer located in the chip area;

[0016] Filling the through hole with a conductive material, wherein the conductive material also extends to cover the surface of the dielectric layer;

[0017] The conductive material on the dielectric layer is removed by a planarization process to form a wiring layer in the through hole.

[0018] Optionally, before forming a dielectric layer and a wiring layer located in the dielectric layer on the substrate, a conductive structure is formed in the substrate located in the chip region, and the wiring layer is electrically connected to the conductive structure.

[0019] Optionally, before forming the conductive structure in the substrate in the chip area, a second groove is formed in the substrate in the chip area, and the second groove is used as an alignment mark.

[0020] The present invention also provides a semiconductor device, comprising:

[0021] A substrate, the substrate comprising a chip area and a suspended area located around the chip area, the suspended area playing a supporting role for a portion to be connected to the substrate beyond the chip area on the substrate;

[0022] A dielectric layer and a wiring layer, wherein the dielectric layer is formed on the substrate, and the wiring layer is formed in the dielectric layer;

[0023] The suspended area is formed with a first groove, so that the height difference between the surface located in the suspended area and the surface located in the chip area is within a set specification.

[0024] Optionally, the first groove is formed in the substrate located in the suspended area, and the first groove extends from the surface of the substrate into the substrate.

[0025] Optionally, the dielectric layer and the wiring layer each have at least two layers; and the first groove is formed in any dielectric layer located in the suspended area.

[0026] Optionally, a conductive structure is formed in the substrate located in the chip area, and the wiring layer is electrically connected to the conductive structure.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] 1. The manufacturing method of the semiconductor device of the present invention comprises: providing a substrate, the substrate comprising a chip area and a suspended area located around the chip area, the suspended area plays a supporting role for the part to be connected to the substrate beyond the chip area on the substrate; forming a dielectric layer and a wiring layer located in the dielectric layer on the substrate; wherein, before or after the dielectric layer is formed, or at the same time, a first groove is formed in the suspended area, and the height difference between the first groove and the surface located in the chip area is within a set specification. This can prevent the newly added suspended area outside the chip area from affecting the stability of the photolithography process and the planarization process.

[0029] 2. The semiconductor device of the present invention comprises: a substrate, the substrate comprises a chip area and a suspended area around the chip area, the suspended area plays a supporting role for the part to be connected to the substrate beyond the chip area on the substrate; a dielectric layer and a wiring layer, the dielectric layer is formed on the substrate, and the wiring layer is formed in the dielectric layer; wherein the suspended area is formed with a first groove, so that the height difference between the surface located in the suspended area and the surface located in the chip area is within the set specification. This can prevent the newly added suspended area outside the chip area from affecting the stability of the photolithography process and the planarization process. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0031] Figure 2a to Figure 2k yes Figure 1 A schematic diagram of a semiconductor device manufacturing method shown;

[0032] Figure 3 is a distribution diagram of a chip area and a suspended area according to an embodiment of the present invention;

[0033] Figure 4 It is a schematic diagram of a protrusion in a suspended area.

[0034] Among them, Figure 1 to Figure 4 The reference numerals are described as follows:

[0035] 101-substrate; 102-first insulating layer; 11-conductive structure; 111-second insulating layer; 121-first groove; 122-second groove; 131-first dielectric layer; 1311-first patterned photoresist layer; 141-first wiring layer; 1411-first through hole; 132-second dielectric layer; 133-third dielectric layer; 142-second wiring layer; 1421-second through hole. DETAILED DESCRIPTION

[0036] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0037] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:

[0038] Step S1, providing a substrate, wherein the substrate comprises a chip area and a suspended area around the chip area, wherein the suspended area plays a supporting role for a portion to be connected to the substrate that exceeds the chip area on the substrate;

[0039] Step S2, forming a dielectric layer and a wiring layer located in the dielectric layer on the substrate; wherein, before or after or simultaneously with the formation of the dielectric layer, a first groove is formed in the suspended area, and the height difference between the first groove and the surface located in the chip area is within a set specification.

[0040] See below Figure 2a to Figure 2k , Figure 3 and Figure 4 The method for manufacturing the semiconductor device provided in this embodiment is described in more detail. Figure 2a to Figure 2k and Figure 4 yes Figure 3 Schematic diagram of the longitudinal section along the AA' direction.

[0041] According to step S1, a substrate is provided, the substrate comprising a chip area A1 and a suspended area A2 located around the chip area A1, the suspended area A2 plays a supporting role for a portion to be connected to the substrate beyond the chip area A1 on the substrate.

[0042] The substrate may be a single-layer structure or a multi-layer stacked structure, and the material of the substrate may be a semiconductor material or a non-semiconductor material.

[0043] In one embodiment, if Figure 2a As shown, the base includes a substrate 101 and a first insulating layer 102 formed on a surface of the substrate 101 .

[0044] The material of the substrate 101 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors, and can also include a layered substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator, and can also include other materials besides semiconductor materials, such as glass.

[0045] The suspended area A2 may be located between some adjacent chip areas A1. Figure 3 As shown, the suspended area A2 is only located at one of the opposite sides of the chip area A1; alternatively, the suspended area A2 may be located between all adjacent chip areas A1, that is, the suspended area A2 may surround the chip area A1.

[0046] The substrate further includes a scribe line region (not shown), which surrounds the chip region A1 and is located between the chip region A1 and the suspension region A2.

[0047] In one embodiment, the object to be connected to the substrate may be a chip.

[0048] According to step S2, a dielectric layer and a wiring layer located in the dielectric layer are formed on the substrate. Before, during or simultaneously with the formation of the dielectric layer, a first groove 121 is formed in the suspended area A2, and the height difference between the first groove 121 and the surface located in the chip area A1 is within a set specification.

[0049] like Figure 2c As shown, before forming a dielectric layer and a wiring layer located in the dielectric layer on the substrate, a conductive structure 11 is formed in the substrate located in the chip area A1, and the wiring layer is electrically connected to the conductive structure 11.

[0050] A second insulating layer 111 may be formed between the conductive structure 11 and the substrate. In one embodiment, the second insulating layer 111 further extends to the surface of the substrate.

[0051] exist Figure 2c In the embodiment shown, the steps of forming the conductive structure 11 include: first, etching the first insulating layer 102 and the substrate 101 to form a through hole; then, forming a second insulating layer 111 on the inner wall of the through hole, and the second insulating layer 111 also extends to the surface of the first insulating layer 102; then, depositing a conductive material in the through hole, and the conductive material also covers the second insulating layer 111 above the first insulating layer 102; then, using a planarization process (such as a chemical mechanical polishing process) to remove the conductive material outside the through hole, and the conductive material in the through hole serves as the conductive structure 11.

[0052] Due to the loading effect of the planarization process, the surface of the suspended area A2 will be higher than the surface of the chip area A1. In one embodiment, before forming the conductive structure 11, the first groove 121 is formed in the substrate of the suspended area A2. Figure 2b As shown, the first groove 121 extends from the surface of the substrate into the substrate. The second insulating layer 111 or the dielectric layer formed subsequently can fill the first groove 121; Figure 2c As shown, when the second insulating layer 111 fills the first groove 121 , the dielectric layer is formed on the second insulating layer 111 ; when the second insulating layer 111 does not fill the first groove 121 , the dielectric layer fills the first groove 121 .

[0053] The surface located in the suspended area A2 and the surface located in the chip area A1 refer to the surface of the dielectric layer located in the suspended area A2 and the surface of the dielectric layer located in the chip area A1, respectively. Alternatively, the surface located in the suspended area A2 and the surface located in the chip area A1 may also refer to the surface of the substrate located in the suspended area A2 and the surface of the substrate located in the chip area A1, respectively.

[0054] The method for manufacturing the semiconductor device further includes: forming a second groove 122 in the substrate of the chip area A1, wherein the second groove 122 is used as an alignment mark.

[0055] Preferably, before forming the conductive structure 11, the first groove 121 and the second groove 122 are made at the same time. The second groove 122 is used as an alignment mark, and its depth is generally tens of nanometers. The first groove 121 and the second groove 122 are made at the same time, so that the depth of the first groove 121 and the depth of the second groove 122 can be the same under the same process. The second insulating layer 111 or the dielectric layer formed subsequently can also fill the first groove 121 and the second groove 122, so that the height difference between the surface located in the suspended area A2 and the surface located in the chip area A1 after the planarization process is within the set specification, so as to simplify the process and save costs. In other embodiments, the first groove 121 and the second groove 122 may not be made at the same time, for example, the second groove 122 is made before forming the conductive structure 11, and the first groove 121 is made after forming the conductive structure 11.

[0056] It should be noted that the height difference between the surface located in the suspension area A2 and the surface located in the chip area A1 is within the set specifications, including: the surface located in the suspension area A2 is flush with the surface located in the chip area A1; or, the surface located in the suspension area A2 is lower than or higher than the surface located in the chip area A1, and the height difference between the surface located in the suspension area A2 and the surface located in the chip area A1 is within the set specifications.

[0057] like Figure 2d to Figure 2k As shown, a dielectric layer and a wiring layer located in the dielectric layer are formed on the substrate. The dielectric material forming the dielectric layer or the conductive material forming the wiring layer is simultaneously formed in the chip area A1 and the suspended area A2 of the substrate; after the wiring layer is formed, part of the conductive material located in the chip area A1 is retained to form the conductive layer and the conductive material located in the suspended area A2 is removed. When the conductive structure 11 is formed on the substrate, the dielectric layer covers the conductive structure 11 and the wiring layer is electrically connected to the conductive structure 11.

[0058] If the dielectric layer and the wiring layer are uniformly formed, the wiring layer is formed in the dielectric layer of the chip area A1 after the dielectric layer is formed. If the surface in the suspended area A2 is higher than the surface in the chip area A1, the first groove 121 is formed in the dielectric layer in the suspended area A2.

[0059] If the dielectric layer and the wiring layer each have at least two layers, after forming each dielectric layer, the wiring layer is formed in the dielectric layer of the chip area A1. If after forming any dielectric layer, the surface located in the suspended area A2 is higher than the surface located in the chip area A1, the first groove 121 is formed in any dielectric layer located in the suspended area A2. Alternatively, the first groove 121 may also be formed in any at least two dielectric layers located in the suspended area A2.

[0060] Taking the dielectric layer as two layers (i.e., the first dielectric layer 131 and the second dielectric layer 132), and the wiring layer as two layers (i.e., the first wiring layer 141 and the second wiring layer 142) as an example, the steps of forming the dielectric layer and the wiring layer located in the dielectric layer on the substrate include:

[0061] The step of forming the first wiring layer 141 in the first dielectric layer 131 of the chip area A1 may include: first, Figure 2dAs shown, a first dielectric layer 131 is formed on the chip area A1 and the suspended area A2 of the substrate, and the first dielectric layer 131 covers the conductive structure 11 and the second insulating layer 111. If the first groove 121 and the second groove 122 are formed in the substrate, the first dielectric layer 131 can also fill the first groove 121 and the second groove 122; a first photoresist layer is formed on the first dielectric layer 131, and the first photoresist layer is patterned to form a first patterned photoresist layer 1311, as shown in FIG. Figure 2e As shown, the first patterned photoresist layer 1311 includes a pattern of the first wiring layer 141 located in the chip area A1; Figure 2f As shown, the first patterned photoresist layer 1311 is used as a mask to etch the first dielectric layer 131 of the chip area A1 to form a first through hole 1411 penetrating the first dielectric layer 131; Figure 2g As shown, the first patterned photoresist layer 1311 is removed; a conductive material is formed in the first through hole 1411, and the conductive material covers the first dielectric layer 131; as shown Figure 2h As shown, a planarization process (such as a chemical mechanical polishing process) is used to remove the conductive material on the first dielectric layer 131 to form a first wiring layer 141 in the first through hole 1411 .

[0062] The step of forming the second wiring layer 142 in the second dielectric layer 132 of the chip area A1 may include: first, Figure 2i As shown, a second dielectric layer 132 is formed on the first dielectric layer 131, and the second dielectric layer 132 covers the first wiring layer 141 located in the chip area A1 and the suspended area A2. If the first groove 121 is formed in the first dielectric layer 131 in the suspended area A2, the second dielectric layer 132 can also fill the first groove 121; a second photoresist layer is formed on the second dielectric layer 132, and the second photoresist layer is patterned to form a second patterned photoresist layer (not shown), and the second patterned photoresist layer includes a pattern of the second wiring layer 142 located in the chip area A1; as shown Figure 2j As shown, the second patterned photoresist layer is used as a mask to etch the second dielectric layer 132 of the chip area A1 to form a second through hole 1421 in the second dielectric layer 132; a conductive material is formed in the second through hole 1421, and the conductive material covers the second dielectric layer 132; as shown Figure 2k As shown, a planarization process (such as a chemical mechanical polishing process) is used to remove the conductive material on the second dielectric layer 132 to form a second wiring layer 142 in the second through hole 1421 .

[0063] The first groove 121 may be formed in the first dielectric layer 131 of the suspended area A2 before, during, or simultaneously with forming the first wiring layer 141 in the first dielectric layer 131 of the chip area A1. For example, the first patterned photoresist layer 1311 may also include a pattern of the first groove 121 located in the suspended area A2. The step of forming a first patterned photoresist layer 1311 including a pattern of a first wiring layer 141 located in the chip area A1 and a pattern of a first groove 121 located in the suspended area A2 may include: shielding the first photoresist layer in the suspended area A2 with a baffle, and performing an exposure process on the first photoresist layer in the chip area A1 with a chip area mask; shielding the first photoresist layer after the exposure process in the chip area A1 with a baffle, and performing an exposure process on the first photoresist layer in the suspended area A2 with a first mask, and performing a development process on the first photoresist layer after the exposure process in the chip area A1 and the suspended area A2 to form the first patterned photoresist layer 1311. The first groove 121 is formed by etching the first dielectric layer 131 in the suspended area A2 with the first patterned photoresist layer 1311. In other embodiments, the pattern of the first wiring layer 141 located in the chip area A1 and the pattern of the first groove 121 located in the suspended area A2 may also be formed in different layers of photoresist.

[0064] And / or, before or after or simultaneously with forming the second wiring layer 142 in the second dielectric layer 132 in the chip area A1, forming the first groove 121 in the second dielectric layer 131 in the suspended area A2. For example, the second patterned photoresist layer may also include a pattern of the first groove 121 located in the suspended area A2. The step of forming the second patterned photoresist layer including the pattern of the second wiring layer 142 located in the chip area A1 and the pattern of the first groove 121 located in the suspended area A2 may include: using a baffle to shield the second photoresist layer in the suspended area A2, and using a chip area mask to perform an exposure process on the second photoresist layer in the chip area A1; using a baffle to shield the second photoresist layer after the exposure process in the chip area A1, and using a first mask to perform an exposure process on the second photoresist layer in the suspended area A2, and performing a development process on the second photoresist layer after the exposure process in the chip area A1 and the suspended area A2 to form the second patterned photoresist layer. The second dielectric layer 132 of the suspended area A2 is etched by the second patterned photoresist layer to form the first groove 121. In other embodiments, the pattern of the second wiring layer 142 in the chip area A1 and the pattern of the first groove 121 in the suspended area A2 can also be formed in different layers of photoresist.

[0065] The chip area mask is designed according to the pattern of the wiring layer to be formed in the chip area. Different wiring layers have different patterns, and the chip area masks for forming corresponding wiring layers may be different.

[0066] Since the chip area A1 is used for carrying the chip and also for realizing conductive interconnection, and the suspended area A2 is used for carrying the chip, the chip area A1 is formed with a conductive interconnection structure (including the conductive structure 11 and the wiring layer, etc.), while the suspended area A2 has fewer conductive interconnection structures. Then, in the process of manufacturing the conductive interconnection structure, when a planarization process (such as a chemical mechanical polishing process) is used to grind the chip area A1 and the suspended area A2 (for example, when manufacturing the conductive structure 11, the conductive material outside the through hole is ground away, when manufacturing the first wiring layer 141, the conductive material on the first dielectric layer 131 is ground away, and when manufacturing the second wiring layer 142, the conductive material on the second dielectric layer 132 is ground away), due to the load effect of the planarization process, when the chip area A1 is ground to the target thickness, the suspended area A2 will produce a bulge; and as the number of layers of the conductive interconnection structure increases and the number of stacked layers of the insulating structure increases, the bulge will become higher and higher.

[0067] And when the development process is performed, the exposed photoresist will be cleaned and removed; if the suspended area A2 is formed with a protrusion, and the height of the protrusion exceeds the set specification (for example, the height difference between the top surface of the dielectric layer in the suspended area A2 and the top surface of the dielectric layer in the chip area A1 exceeds the set specification), the by-products dissolved when the exposed photoresist is cleaned and removed will be blocked by the protrusion and adhere to the vicinity of the protrusion, that is, the development ability is affected, and further affecting the production of the conductive interconnect structure near the protrusion; and due to the presence of the protrusion, when grinding the conductive material, the conductive material at the bottom corner of the protrusion is not easily ground away, resulting in residual conductive material.

[0068] by Figure 4 For example ( Figure 4 For Figure 2kIn the case where the first groove 121 is not formed, after the planarization process when the conductive structure 11 is manufactured, after the planarization process when the first wiring layer 141 is manufactured, and after the planarization process when the second wiring layer 142 is manufactured, the protrusion heights of the suspended area A2 are h1, h2, and h3, respectively, and h1, h2, and h3 increase in sequence. The heights h1 and h2 do not exceed the set specifications, and the height h3 exceeds the set specifications. After the third dielectric layer 133 is subsequently formed on the second dielectric layer 132, the protrusion height of the suspended area A2 is further increased to h4. Then, in the third dielectric layer 133, In the process of forming a third wiring layer (not shown) in the dielectric layer 133, in the process of performing exposure and development processes on the photoresist layer corresponding to the third wiring layer to form a patterned photoresist layer, the byproducts dissolved when cleaning the exposed photoresist will be blocked by the protrusions with a height of h4, resulting in poor quality of the patterned photoresist layer obtained after development, thereby affecting the quality of the third through hole (not shown) etched in the third dielectric layer 133; and, when making the third wiring layer, the conductive material at the bottom corner of the protrusion with a height of h4 is not easily ground away, and there will be conductive material residue.

[0069] In the present invention, before, during or at the same time as the formation of the dielectric layer, if the surface of the suspended area A2 is higher than the surface of the chip area A1, the first groove 121 is formed in the suspended area A2, and the height difference between the first groove 121 and the surface of the chip area A1 is within the set specification, so that the height difference between the surface of the suspended area A2 and the surface of the chip area A1 is within the set specification, that is, no protrusion is formed in the suspended area A2, or, even if a protrusion is formed in the suspended area A2, the height of the protrusion is within the set specification, thereby preventing the byproducts of dissolution generated when the exposed photoresist is cleaned and removed during the development process from being blocked by the protrusion, that is, avoiding affecting the development ability, thereby avoiding affecting the production of the conductive interconnect structure near the protrusion; and, when grinding the conductive material, the conductive material in the suspended area A2 region can be ground away to avoid residual conductive material.

[0070] For example, before forming the dielectric layer, forming the first groove 121 in the substrate of the suspended area A2, as shown in FIG. Figure 2c As shown, after the conductive material outside the through hole is removed by grinding when manufacturing the conductive structure 11, the protrusion in the suspended area A2 is removed because the first groove 121 is formed in the base of the suspended area A2; Figure 2h As shown, after the conductive material on the first dielectric layer 131 is removed by grinding when manufacturing the first wiring layer 141, the first dielectric layer 131 above the first groove 121 has a protrusion with a height of h5; Figure 2iAs shown, after the second dielectric layer 132 is formed, the protrusion height of the second dielectric layer 132 above the first groove 121 increases to h6; Figure 2k As shown, after the conductive material on the second dielectric layer 132 is removed by grinding when manufacturing the second wiring layer 142, the second dielectric layer 132 of the suspended area A2 has a protrusion with a height of h7, and the height h7 is greater than the height h6, and the height h7 is within the set specification. Therefore, since the first groove 121 is formed in the base of the suspended area A2, the suspended area A2 is not formed with a protrusion, or even if the suspended area A2 is formed with a protrusion, the height of the protrusion is within the set specification.

[0071] In addition, the manufacturing method of the semiconductor device may further include: forming a pad (not shown) on the dielectric layer of the chip area A1, the pad being electrically connected to the wiring layer. The metal material forming the pad is formed simultaneously in the chip area A1 and the suspended area A2 of the substrate; after forming the pad, part of the metal material located in the chip area A1 is retained to form the pad and the metal material located in the suspended area A2 is removed.

[0072] The steps of forming the pad may include: depositing metal material on the dielectric layer; forming a third photoresist layer on the metal material; patterning the third photoresist layer to form a third patterned photoresist layer, the third patterned photoresist layer including a pattern located in the chip area A1 for forming the pad and a pattern located in the suspended area A2 for removing the metal material on the same layer as the pad; using the third patterned photoresist layer as a mask, etching the metal material to form a pad in the chip area A1 and remove the metal material located in the suspended area A2 on the same layer as the pad.

[0073] Among them, patterning the third photoresist layer to form the third graphic photoresist layer includes: using a baffle to block the third photoresist layer of the suspended area A2, and performing an exposure process on the third photoresist layer of the chip area A1, and the third photoresist layer of the chip area A1 after exposure includes the pattern of the pad; using a baffle to block the third photoresist layer located in the chip area A1 after the exposure process, and using a first mask to perform an exposure process on the third photoresist layer of the suspended area A2, and the third photoresist layer of the suspended area A2 after exposure includes a pattern for removing the metal material in the same layer as the pad; performing a development process on the third photoresist layer located in the chip area A1 and the suspended area A2 after the exposure process to form the third graphic photoresist layer.

[0074] In the embodiment of the present application, the photomask used to form the first groove 121 and the photomask used to remove the metal material located in the same layer as the pad in the suspended area A2 are the same photomask, both of which are the first photomask. Among them, the metal material located in the same layer as the pad in the suspended area A2 is formed in the suspended area A2 at the same time as the metal material forming the pad when the pad is formed in the chip area A1. In different process stages, the same photomask is used to expose the photoresist of different process stages to respectively form a photoresist layer including the pattern of the first groove 121 and a photoresist layer for removing the metal material pattern located in the same layer as the pad in the suspended area A2, which can save masks. In other embodiments, the photomask used to form the first groove 121 and the photomask used to remove the metal material located in the same layer as the pad in the suspended area A2 can be different masks.

[0075] The method for manufacturing the semiconductor device may further include:

[0076] Thinning the surface of the substrate 101 away from the first insulating layer 102 to expose an end of the conductive structure 11 away from the first insulating layer 102;

[0077] The surface of the substrate 101 away from the first insulating layer 102 is soldered to a base plate (not shown) through an external solder ball (not shown), and the conductive structure 11 is electrically connected to the external solder ball;

[0078] A chip (not shown) is attached to the side of the dielectric layer away from the substrate 101, and the chip is electrically connected to the pad. The chip can be electrically connected to the pad via a hybrid bonding structure or micro bumps (not shown), and the type of the chip is not limited.

[0079] In summary, the manufacturing method of the semiconductor device provided by the present invention includes: providing a substrate, the substrate including a chip area and a suspended area located around the chip area, the suspended area plays a supporting role for the part to be connected to the substrate beyond the chip area on the substrate; forming a dielectric layer and a wiring layer located in the dielectric layer on the substrate; wherein, before or after the dielectric layer is formed, or at the same time, a first groove is formed in the suspended area, and the height difference between the first groove and the surface located in the chip area is within the set specification. The manufacturing method of the semiconductor device of the present invention can prevent the newly added suspended area outside the chip area from affecting the stability of the photolithography process and the planarization process.

[0080] An embodiment of the present invention provides a semiconductor device, which can be manufactured using the above method. The semiconductor device includes: a substrate, the substrate includes a chip area and a suspended area located around the chip area, the suspended area plays a supporting role for a portion to be connected to the substrate that exceeds the chip area on the substrate; a dielectric layer and a wiring layer, the dielectric layer is formed on the substrate, and the wiring layer is formed in the dielectric layer; wherein a first groove is formed in the suspended area, so that the height difference between the surface located in the suspended area and the surface located in the chip area is within a set specification.

[0081] See below Figure 2k , Figure 3 The semiconductor device provided by this embodiment is described in more detail. Figure 2k yes Figure 3 Schematic diagram of the longitudinal section along the AA' direction.

[0082] The substrate includes a chip area A1 and a suspended area A2 located around the chip area A1 , wherein the suspended area A2 supports a portion of the substrate that is to be connected to the substrate and exceeds the chip area A1 on the substrate.

[0083] The substrate may be a single-layer structure or a multi-layer stacked structure, and the material of the substrate may be a semiconductor material or a non-semiconductor material.

[0084] In one embodiment, if Figure 2k As shown, the base includes a substrate 101 and a first insulating layer 102 formed on a surface of the substrate 101 .

[0085] The material of the substrate 101 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors, and can also include a layered substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator, and can also include other materials besides semiconductor materials, such as glass.

[0086] The suspended area A2 may be located between some adjacent chip areas A1. Figure 3 As shown, the suspended area A2 is only located at one of the opposite sides of the chip area A1; alternatively, the suspended area A2 may be located between all adjacent chip areas A1, that is, the suspended area A2 may surround the chip area A1.

[0087] The substrate further includes a scribe line region (not shown), which surrounds the chip region A1 and is located between the chip region A1 and the suspension region A2.

[0088] In one embodiment, the object to be connected to the substrate may be a chip.

[0089] The conductive structure 11 is formed in the substrate of the chip area A1.

[0090] A second insulating layer 111 may be formed between the conductive structure 11 and the substrate. In one embodiment, the second insulating layer 111 further extends to the surface of the substrate.

[0091] exist Figure 2k In the illustrated embodiment, the conductive structure 11 penetrates the first insulating layer 102 and enters the substrate 101 , a second insulating layer 111 is formed between the conductive structure 11 and the first insulating layer 102 and the substrate 101 , and the second insulating layer 111 also extends to the surface of the first insulating layer 102 .

[0092] The dielectric layer is formed on the substrate and covers the conductive structure 11 . The wiring layer is formed in the dielectric layer of the chip area A1 and is electrically connected to the conductive structure 11 .

[0093] The suspended area A2 is formed with a first groove 121 so that the height difference between the surface located at the suspended area A2 and the surface located at the chip area A1 is within a set specification.

[0094] The surface located in the suspended area A2 and the surface located in the chip area A1 refer to the surface of the dielectric layer located in the suspended area A2 and the surface of the dielectric layer located in the chip area A1, respectively. Alternatively, the surface located in the suspended area A2 and the surface located in the chip area A1 may also refer to the surface of the substrate located in the suspended area A2 and the surface of the substrate located in the chip area A1, respectively.

[0095] In the first embodiment, the first groove 121 is formed in the substrate located in the suspended area A2 , and the first groove 121 extends from the surface of the substrate into the substrate. The dielectric layer fills the first groove 121 .

[0096] In the second embodiment, if the dielectric layer and the wiring layer are the same layer, the first groove 121 is formed in the dielectric layer located in the suspended area A2.

[0097] In the third embodiment, if the dielectric layer and the wiring layer each have at least two layers, each wiring layer is formed in the corresponding dielectric layer of the chip area A1, and the first groove 121 is formed in any dielectric layer located in the suspended area A2. Alternatively, the first groove 121 may also be formed in any at least two dielectric layers located in the suspended area A2.

[0098] It should be noted that the height difference between the surface located in the suspension area A2 and the surface located in the chip area A1 is within the set specifications, including: the surface located in the suspension area A2 is flush with the surface located in the chip area A1; or, the surface located in the suspension area A2 is lower than or higher than the surface located in the chip area A1, and the height difference between the surface located in the suspension area A2 and the surface located in the chip area A1 is within the set specifications.

[0099] A second groove (i.e. Figure 2b The dielectric layer fills the second groove 122, and the second groove 122 is used as an alignment mark.

[0100] Preferably, the first groove 121 and the second groove 122 have the same depth, so that the first groove 121 and the second groove 122 can be made at the same time to simplify the process and save costs. In other embodiments, the depths of the first groove 121 and the second groove 122 can be different, and the first groove 121 and the second groove 122 can be made at different times.

[0101] In one embodiment, if the first groove 121 and the second groove 122 are both made before forming the conductive structure 11 , when forming the second insulating layer 111 , the second insulating layer 111 may also fill the first groove 121 and the second groove 122 .

[0102] The first groove 121 and the second groove 122 may be formed only in the first insulating layer 102 , or the first groove 121 and the second groove 122 may penetrate the first insulating layer 102 and enter the substrate 101 .

[0103] Preferably, the first groove 121 has the same area as the suspended area A2.

[0104] like Figure 2k As shown, taking the case where the dielectric layer is two layers (i.e., the first dielectric layer 131 and the second dielectric layer 132) and the wiring layer is two layers (i.e., the first wiring layer 141 and the second wiring layer 142) as an example, the first groove 121 can be formed in the substrate of the suspended area A2, and / or the first groove 121 can be formed in the first dielectric layer 131 of the suspended area A2, and / or the first groove 121 can be formed in the second dielectric layer 132 of the suspended area A2.

[0105] In addition, the semiconductor device may further include: a pad (not shown) formed on the dielectric layer of the chip area A1, wherein the pad is electrically connected to the wiring layer.

[0106] In addition, the end of the conductive structure 11 away from the first insulating layer 102 can penetrate the substrate 101, and the surface of the substrate 101 away from the first insulating layer 102 is soldered to a base plate (not shown) through an external solder ball (not shown), and the conductive structure 11 is electrically connected to the external solder ball; a chip (not shown) is formed on the surface of the dielectric layer away from the substrate 101, and the chip is electrically connected to the pad. The chip can be electrically connected to the pad through a hybrid bonding structure or a micro-bump (not shown), and the type of the chip is not limited.

[0107] In summary, the semiconductor device provided by the present invention comprises: a substrate, the substrate comprising a chip area and a suspended area located around the chip area, the suspended area supporting the portion to be connected to the substrate beyond the chip area on the substrate; a dielectric layer and a wiring layer, the dielectric layer being formed on the substrate, the wiring layer being formed in the dielectric layer; wherein the suspended area is formed with a first groove, so that the height difference between the surface located in the suspended area and the surface located in the chip area is within a set specification. The semiconductor device of the present invention can prevent the newly added suspended area outside the chip area from affecting the stability of the photolithography process and the planarization process.

[0108] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Provide a substrate, the substrate comprising a chip area and a suspended area located around the chip area, the suspended area plays a supporting role for a portion to be connected to the substrate beyond the chip area on the substrate; forming a dielectric layer and a wiring layer located in the dielectric layer on the substrate; Wherein, before, during or at the same time as the dielectric layer is formed, a first groove is formed in the suspended area, and a height difference between the first groove and the surface located in the chip area is within a set specification.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the dielectric layer, the first groove is formed on the substrate located in the suspended area, and the first groove extends from the surface of the substrate into the substrate.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The dielectric layer and the wiring layer both have at least two layers; After forming any one of the dielectric layers, forming the first groove in any one of the dielectric layers located in the suspended area.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a dielectric layer on the substrate and a wiring layer located in the dielectric layer comprises: forming a dielectric layer on the substrate; forming a through hole in the dielectric layer located in the chip area; Filling the through hole with a conductive material, wherein the conductive material also extends to cover the surface of the dielectric layer; The conductive material on the dielectric layer is removed by a planarization process to form a wiring layer in the through hole.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming a dielectric layer and a wiring layer located in the dielectric layer on the substrate, a conductive structure is formed in the substrate located in the chip region, and the wiring layer is electrically connected to the conductive structure.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Before forming the conductive structure in the substrate in the chip area, a second groove is formed in the substrate in the chip area, and the second groove is used as an alignment mark.

7. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a chip area and a suspended area located around the chip area, the suspended area playing a supporting role for a portion to be connected to the substrate beyond the chip area on the substrate; A dielectric layer and a wiring layer, wherein the dielectric layer is formed on the substrate, and the wiring layer is formed in the dielectric layer; The suspended area is formed with a first groove, so that the height difference between the surface located in the suspended area and the surface located in the chip area is within a set specification.

8. The semiconductor device according to claim 7, wherein: The first groove is formed in the substrate located in the suspended area, and the first groove extends from the surface of the substrate into the substrate.

9. The semiconductor device according to claim 7, wherein: The dielectric layer and the wiring layer each have at least two layers; the first groove is formed in any dielectric layer located in the suspended area.

10. The semiconductor device according to claim 7, wherein: A conductive structure is formed in the substrate located in the chip area, and the wiring layer is electrically connected to the conductive structure.

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