A bonding pad lead-out MOS chip structure and packaging method thereof

Abstract

The invention discloses a bonding pad lead-out MOS chip structure and a packaging method thereof. The process comprises the following steps: wiring layer electroplating: respectively electroplating wiring layers on the source and gate connection ports exposed on the surface of a bare chip after encapsulation, and electrically leading out the electrical property horizontally; A-side electrical leading: electroplating a connection column on the wiring layer of the source, and encapsulating and grinding to expose the top of the connection column, and electrically leading out the source to the A-side of a package; exposing the conductive glue flush with the encapsulation material, electrically leading out the drain of the bare chip to the B-side of the package, drilling a hole on the B-side until the wiring layer of the gate is exposed; electroplating metal on the B-side to cover the conductive glue, and at the same time electroplating the inner wall of the hole to connect with the wiring layer, electrically leading out the gate to the B-side of the package, and electroplating metal on the A-side to cover the connection column. The invention electrically leads the gate located on the front side of the bare chip to the back side of the bare chip and out of the package body, the source pin and the gate pin can be mounted normally, and the heat dissipation effect of the packaging structure is good.

Description

Technical Field

[0001] The invention belongs to the technical field of chip packaging, and in particular relates to a bonding pad lead-out MOS chip structure and a packaging method thereof. Background Art

[0002] As integrated circuits and equipment develop in the direction of miniaturization, power semiconductor devices, as one of the core electronics of power integrated circuits, also present the development requirements of high integration, miniaturization, high performance and low cost. Power semiconductor devices can effectively realize circuit output short-circuit protection. MOS tube chip is one of them. It is a metal oxide semiconductor field effect transistor made of silicon material, composed of N-type or P-type MOSFET (metal oxide-semiconductor field effect transistor) devices. The voltage control characteristics of MOS chip make it a very important device. It is usually used in amplification circuits or switching circuits. Each MOS chip is provided with three electrodes: gate, source and drain.

[0003] In the existing commonly used MOS chips, the source and gate are respectively arranged on the same surface of the chip, while the drain is arranged on the other opposite surface of the chip. MOS chips need to be installed in different ways according to different usage scenarios. Some products need to mount the source of MOS on the application circuit board or module to meet working requirements. However, since the source and gate are on the same surface of the chip, and the source occupies a larger surface size and the gate occupies a smaller surface size, the gate cannot be safely mounted when the source is mounted, which leads to obstruction of the electrical connection of the MOS chip, and it cannot be used normally, resulting in defective products. The method of reducing the source size to allow the gate to be safely mounted will directly affect the heat dissipation effect of the overall structure. Summary of the invention

[0004] In order to solve the above problems in the prior art, the present invention provides a bonding pad lead-out MOS chip structure and a packaging method thereof.

[0005] To achieve the above object, the present invention proposes a bonding pad lead-out MOS chip packaging method, comprising the following steps:

[0006] Wiring layer plating: Plating wiring layers on the source and gate connection ports exposed on the surface of the die after encapsulation, and leading out the electrical level;

[0007] Electrical lead-out on the A side: Electroplating connection posts on the wiring layer of the source, encapsulating and polishing to expose the top of the connection posts, and electrically lead the source to the A side of the package;

[0008] Electrical lead-out on the B side: The conductive glue is exposed flush with the encapsulation material, the drain of the bare chip is electrically led out to the B side of the package, and a hole is drilled on the B side until the wiring layer of the gate is exposed;

[0009] Double-sided electroplating: Electroplating metal on the B side covers the conductive glue, while the inner wall of the hole is electroplated to connect with the wiring layer, electrically leading the gate to the B side of the package, and electroplating metal on the A side covers the connecting column.

[0010] Furthermore, in the wiring layer electroplating step, a substrate is provided, the die is mounted toward the substrate and encapsulated and polished to expose the conductive glue covering the drain of the die, the substrate is peeled off and the die is turned upside down, at which time the source and gate of the die are flush with the encapsulation material and exposed.

[0011] Furthermore, in the wiring layer electroplating step, conductive pillars are vertically electroplated on the source and gate exposed on the surface after the bare chip is encapsulated, and the conductive pillars are further encapsulated and polished to expose the tops of the conductive pillars to form connection ports for the source and gate.

[0012] Furthermore, in the A-side electrical lead-out step, the wiring layer and the connecting column are further encapsulated on the basis of the bare chip encapsulation and the conductive column encapsulation in the wiring layer electroplating step, and the top of the connecting column is exposed by horizontal mechanical grinding on the top surface of the encapsulation. At this time, the encapsulation as a whole constitutes a package body.

[0013] Furthermore, in the B-side electrical lead-out step, the wiring layer electrically leads out the gate horizontally, and a hole is drilled in the encapsulation material at a position next to the bare die on the B-side of the package by laser drilling, avoiding the bare die.

[0014] Furthermore, in the double-sided electroplating step, the drain pin plated with metal on the B side is covered with conductive glue, and the metal plated on the inner wall of the hole extends along the B side of the package to form a gate pin, which is arranged on one side of the drain pin.

[0015] Furthermore, in the double-sided electroplating step, the source electrode pins electroplated with metal on the A side cover the connecting pillars.

[0016] A bonding pad lead-out MOS chip structure includes a package body, the package body has an A side and a B side opposite to each other, and the package body encapsulates:

[0017] A bare chip, wherein a source electrode and a gate electrode are arranged on one surface of the bare chip, and a drain electrode is arranged on another opposite surface;

[0018] The wiring layer is electroplated on the source and gate connection ports to lead out the electrical properties horizontally;

[0019] Connecting column: the connecting column is electroplated on the wiring layer of the source electrode to electrically lead the source electrode to the A surface, and the top of the connecting column is flush with the A surface of the package body and exposed;

[0020] Conductive glue, the conductive glue covering the drain electrically leads the drain to the B surface, drills a hole on the B surface until the wiring layer of the gate is exposed, and electroplates in the hole to connect with the wiring layer, electrically leads the gate to the B surface, and the top of the conductive glue is flush with the B surface of the package and exposed.

[0021] Furthermore, conductive pillars are vertically plated on the source and gate of the bare chip to form connection ports for the source and gate.

[0022] Furthermore, the surface where the bare chip source and gate are located is formed into conductive pillars, wiring layers and connecting pillars which are connected in sequence through layer-by-layer electroplating, encapsulation and grinding processes, and finally encapsulated to form a package body.

[0023] Furthermore, the wiring layer electrically leads out the gate horizontally, and a hole is drilled in the encapsulation material at a position next to the die on the B side of the package body by laser drilling, avoiding the die.

[0024] Furthermore, the drain pin of the package body B surface plated with metal is covered with conductive glue.

[0025] Furthermore, the package body B surface is provided with a gate pin formed by metal plated on the inner wall of the hole and extending along the package body B surface, and the gate pin is provided on one side of the drain pin.

[0026] Furthermore, the package body A side is plated with a metal source pin, and the source pin covers the connection column.

[0027] The present invention: 1. The gate located on the front side of the bare chip is electrically led to the back side of the bare chip and then to the outside of the package body, so as to avoid the problem that after the larger-sized source electrode is mounted through the source pin, the smaller-sized gate pin cannot be mounted normally, and the source pin and the gate pin are welded and adhered, resulting in a short circuit;

[0028] 2. Lead the gate electrode to the B side of the package, leaving maximum distribution space for the source pin on the A side of the package, so that the source heat can be dissipated to the maximum extent, and the heat dissipation effect of the entire package structure is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1-Figure 7 It is a cross-sectional view of a wiring layer electroplating step of a bonding pad lead-out MOS chip packaging method of the present invention;

[0030] Figure 8-Figure 10 It is a cross-sectional view of the step of electrically leading out the A side of a bonding pad lead-out MOS chip packaging method of the present invention;

[0031] Figure 11-13 It is a cross-sectional view of the B-side electrical lead-out step of a bonding pad lead-out MOS chip packaging method of the present invention;

[0032] Figure 14-16 It is a cross-sectional view of a double-sided electroplating step of a bonding pad lead-out MOS chip packaging method of the present invention;

[0033] Fig.17 A cross-sectional view of a bonding pad lead-out MOS chip structure of the present invention;

[0034] Fig.18 This is a bottom view of a product of a bonding pad lead-out MOS chip structure of the present invention.

[0035] In the figure: 1. Package body; 2. A side; 3. B side; 4. Wiring layer; 5. Connecting column; 6. Conductive glue; 7. Bare chip; 8. Source pin; 9. Gate pin; 10. Drain pin. DETAILED DESCRIPTION

[0036] The content of the present invention will be explained below in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar numbers throughout represent the same or similar components or components with the same or similar functions.

[0037] The directional terms mentioned in the present invention, such as: up, down, left, right, front, back, inside, outside, front, back, side, etc., are only reference directions of the drawings. The embodiments described below with reference to the drawings and the directional terms used are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention. In addition, the various specific process and material examples provided in the present invention are all examples that ordinary technicians in the field can recognize the application of other processes and / or the use of other materials.

[0038] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a bonding pad lead-out MOS chip packaging method proposed by the present invention in conjunction with the accompanying drawings. The process includes the following steps:

[0039] Wiring layer 4 electroplating: Electroplating wiring layer 4 on the exposed source and gate connection ports on the surface of bare chip 7 after encapsulation, and leading out the electrical level;

[0040] Electrically lead out the A surface 2: Electroplate the connection pillar 5 on the wiring layer 4 of the source electrode, and encapsulate and grind to expose the top of the connection pillar 5, and electrically lead out the source electrode to the A surface 2 of the package body 1;

[0041] Electrical lead-out of the B surface 3: Turn the package body 1 upside down, expose the conductive glue 6 flush with the encapsulation material, electrically lead the drain of the bare chip 7 to the B surface 3 of the package body 1, and drill a hole on the B surface 3 until the wiring layer 4 of the gate is exposed;

[0042] Double-sided electroplating: electroplating metal on the B side 3 to cover the conductive glue 6, while electroplating the inner wall of the hole to connect with the wiring layer 4, electrically leading the gate to the B side 3 of the package 1, and electroplating metal on the A side 2 to cover the connecting column 5.

[0043] Among them, Figure 1-Figure 7 As shown, in the step of electroplating the wiring layer 4, the step of encapsulating the bare chip 7 is included, that is, providing a substrate, mounting the bare chip 7 toward the substrate, and firmly bonding it by adhesive. The surface of the bare chip 7 with the source and the gate is the front side, and the surface with the drain is the back side. The bare chip 7 can be a MOS tube, which is a voltage-controlled element. It can be turned on by simply adding the required voltage to the voltage-controlled element. In general electronic circuits, it is usually used in amplifier circuits or switch circuits. Its structure mainly includes three electrode parts: gate (G), source (S) and drain (D). The gate is the control end of the MOS tube chip. By controlling the change of the gate voltage, the current between the source and the drain is adjusted to control the conduction and cutoff of the MOS tube. The MOS tube mainly has two structural forms: N-channel type and P-channel type. According to different field effect principles, it is divided into depletion type (when the gate voltage is 0, there is a large drain current) and enhancement type (when the gate voltage is 0, the drain current is also 0, and a certain gate voltage must be added before there is a drain current). Therefore, MOS tubes can be made into four types of products: P-channel enhancement type, P-channel depletion type, N-channel enhancement type, and N-channel depletion type. When wiring, the power input of the N-channel is D, and the output is S; the power input of the P-channel is S, and the output is D; and the circuit connection methods of the enhancement type and the depletion type are basically the same, and the present invention does not limit the specific type; mount the bare chip 7 with the front side facing the substrate. According to the area of ​​the substrate, multiple bare chips 7 can be placed evenly spaced on the substrate. This application takes placing one as an example. At this time, the back of the bare chip 7 faces upward, and the conductive glue 6 is mounted on the back of the bare chip 7. The conductive glue 6 covers the drain (such as Figure 1 As shown in FIG. 1 ), the die 7 is completely encapsulated on the substrate using an encapsulation material (as shown in FIG. 1 ). Figure 2 As shown in FIG. 1 ), after the encapsulation material is cured, the conductive glue 6 (as shown in FIG. 1 ) covering the drain of the bare chip 7 is exposed by horizontal mechanical grinding on the top surface of the encapsulation material. Figure 3 shown);

[0044] The encapsulation is peeled off from the substrate and turned upside down. The substrate is peeled off. According to the material of the adhesive colloid, a suitable peeling method can be selected, such as chemical etching, mechanical peeling, etc. At this time, the front side of the bare chip 7 is facing up, and the source and gate are flush with the encapsulation material and exposed (such as Figure 4As shown), and conductive pillars of equal height are vertically plated on the exposed source and gate, respectively. The source occupies a larger area on the surface of the bare chip 7, and the gate occupies a smaller area. The conductive pillars plated on the source cover at least 80% of the area of ​​the source, while electrically leading out the source, and conducting the heat on the source to a greater extent, raising the electrical interface between the source and the gate, and then using the encapsulation material to continue to encapsulate the conductive pillars above the above-mentioned encapsulation as a whole (as shown Figure 5 As shown), and mechanical grinding is performed horizontally on the top surface of the package to expose the top of the conductive column, forming a connection port for the source and the gate (as shown Figure 6 shown);

[0045] The wiring layer 4 is electroplated on the connection ports of the source and gate exposed on the surface of the bare chip 7 after encapsulation, and the wiring layer 4 is horizontally laid and extended along the top surface of the encapsulation to lead out the electrical properties of the source and gate horizontally (such as Figure 7 as shown).

[0046] Among them, Figure 8-Figure 10 As shown, in the step of electrically leading out the A surface 2, a vertical connection column 5 (such as Figure 8 As shown in the figure, the connecting pillar 5 and the conductive pillar below the wiring layer 4 are symmetrically arranged about the horizontal plane where the wiring layer 4 is located, so that the structures and stresses of the upper and lower sides of the wiring layer 4 are symmetrical, and the structure is more stable. The connecting pillar 5 and the conductive pillar have the same size and are symmetrically positioned. The heat of the bare chip 7 is transferred to the connecting pillar 5 through the shortest vertical path, and then dissipated to the outside of the A surface 2 of the package body 1, and the electrical and heat transfer effects are better. The encapsulation material is used again to continue encapsulation on the above-mentioned encapsulation top surface, and the connecting pillar 5 and the wiring layer 4 are completely encapsulated (as shown in the figure). Fig. 9 As shown), and the top of the connection column 5 is exposed by grinding the top surface of the package (as shown Fig.10 As shown), at this time, the encapsulation of the entire process is completed, and the encapsulation material is solidified to form a package body 1 as a whole. The package body 1 has an A side 2 and a B side 3, and the electroplated connecting column 5 electrically leads the source to the A side 2 of the package body 1.

[0047] Among them, Figure 11-13 As shown, in the step of electrically leading out the B side 3, the package body 1 is peeled off from the substrate and turned upside down, at which time the back of the bare chip 7 faces upward, and the conductive glue 6 is flush with the encapsulation material and exposed (as shown in FIG. Fig.12 As shown in FIG. 1 ), the conductive glue 6 electrically leads the drain of the bare chip 7 to the B surface 3 of the package 1, so the source and drain of the bare chip 7 are electrically led out, but the gate of the chip is not electrically led out. The wiring layer 4 has electrically led the gate horizontally. The encapsulation material is drilled by laser drilling at a position next to the bare chip 7 on the surface of the B surface 3 of the package 1, avoiding the bare chip 7, until the drilling reaches the wiring layer 4 on the gate (as shown in FIG. Fig.13 As shown), one end surface of the wiring layer 4 on the gate is exposed in the drilled hole.

[0048] Among them, Figure 14-16 As shown, in the double-sided electroplating step, after drilling the B side 3, a metal drain pin is electroplated on the B side 3 by an electroplating process, and the drain pin is covered with a conductive glue 6 (such as Fig.15 As shown in FIG. 1 ), the metal plated on the inner wall of the hole extends along the B surface 3 of the package body 1 to form a gate pin 9 (as shown in FIG. Fig.14 As shown in FIG. 1 ), the gate pin 9 is arranged on one side of the drain pin 10. The gate pin 9 electrically leads the gate to the B surface 3 through the wiring layer 4, the electroplated metal on the inner wall of the hole, and the metal extending on the B surface 3. The electroplating is only performed on the inner wall of the hole in the drilled hole, and there is no need to completely fill the entire drilled hole, and there is no need to use a sealing material to fill the drilled hole after electroplating. While saving electroplating and sealing materials, the weight of the package 1 is reduced as a whole. The gate pin 9 and the drain pin 10 plated on the B surface 3 of the package 1 are not in contact with each other on the B surface 3 and are at the same height. After the electroplating of the B surface 3 of the package 1 is completed, the package 1 is turned over so that the A surface 2 of the package 1 faces upward, and the source pin 8 plated with metal on the A surface 2 of the package 1 covers the top surface of the connecting column 5 (as shown in FIG. 1 ). Fig.11 As shown in the figure, the source pin 8, the drain pin 10 and the gate pin 9 are respectively used as the electrode electrical ports of the bare chip 7 source, drain and gate located in the package body 1; the gate originally located on the front of the bare chip 7 is electrically led out to the back of the bare chip 7 and then led out to the outside of the package body 1, so as to avoid that the larger source electrode on the front of the bare chip 7 cannot be mounted normally after being mounted through the source pin 8, and the gate pin 9 of the smaller gate electrode cannot be mounted normally, and the source pin 8 and the gate pin 9 are welded and adhered, resulting in a short circuit, affecting the normal function of the product. At the same time, the gate electrode is led out to the B side 3 of the package body 1, leaving a distribution space for the source pin 8 on the A side 2 of the package body 1 to the maximum extent, so that the source heat can be dissipated to the maximum extent, and the heat dissipation effect of the entire packaging structure is better.

[0049] There is no restriction on the order of the above process steps. For example, in the double-sided electroplating step, the A side 2 of the package body 1 is electroplated, and the electroplated metal covers the connecting column 5. The electroplating can be continued directly on the A side 2 after the A side 2 electrical lead-out step.

[0050] After the double-sided electroplating step is completed, the source pin 8 is electroplated on the A side 2 of the package 1, and the drain pin 10 and the gate pin 9 are electroplated on the B side 3 of the package 1, and the surface of the source pin 8, the drain pin 10 and the gate pin 9 is further electroplated with protective materials such as gold (Au), silver (Ag) or tin (Sn), which does not affect the welding effect and ensures the service life of the metal pins.

[0051] Finally, after the entire process is completed, for the production situation where multiple bare chips 7 are evenly spaced and encapsulated on the substrate, the process operations performed on each bare chip 7 are the same, and finally a cutting process is required to cut the encapsulation material in the cutting path reserved in the product design stage to separate each product unit; a bare chip 7 is arranged on the substrate of the present invention, and after the substrate is peeled off, the product unit of the above-mentioned package 1 can be obtained (such as Fig.16 as shown).

[0052] The formed package 1 constitutes a MOS tube power device. In the prior art, MOS tube power devices can be divided into lateral power devices and vertical power devices according to the current flow path. The lateral power device refers to the device whose drain electrode, source electrode and gate are all above the device, and the path of current flowing from the drain to the source is horizontal. The vertical power device refers to the device whose source electrode and gate are above the device, and the drain electrode is below the device, and the path of current flowing from the drain to the source is vertical. In this application, a vertical power MOS tube device is taken as an example, but this is not limited to it.

[0053] A bonding pad lead-out MOS chip structure can be obtained by the above-mentioned bonding pad lead-out MOS chip packaging method. Figure 17-Figure 18 As shown, the package structure includes a package body 1, the package body 1 has an A surface 2 and a B surface 3 opposite to each other, and the package body 1 encloses:

[0054] A bare chip 7, wherein a source electrode and a gate electrode are arranged on one surface of the bare chip 7, and a drain electrode is arranged on another opposite surface;

[0055] The wiring layer 4, the source and gate of the bare chip 7 are respectively plated with conductive pillars vertically to form the connection ports of the source and the gate. The wiring layer 4 is respectively plated on the source and the gate connection ports to lead out the electrical properties horizontally. The wiring layer 4 leads out the gate electrical properties horizontally. The encapsulation material is drilled by laser drilling at the position next to the bare chip 7 on the B surface 3 of the package body 1 to avoid the bare chip 7;

[0056] Connecting pillar 5, the connecting pillar 5 is electroplated on the wiring layer 4 of the source electrode to electrically lead the source electrode to the A surface 2, and the top of the connecting pillar 5 is flush with the A surface of the package body 1 and exposed;

[0057] The surface where the source and gate of the bare chip 7 are located is formed into conductive pillars, wiring layers 4 and connecting pillars 5 connected in sequence through layer-by-layer electroplating, encapsulation and grinding processes, and finally encapsulated to form a package body 1;

[0058] Conductive glue 6, the drain pin of the B side 3 of the package 1 is electroplated with metal and covers the conductive glue 6, the conductive glue 6 covering the drain electrically leads the drain to the B side 3, a hole is drilled on the B side 3 until the wiring layer 4 of the gate is exposed, and the hole is electroplated to connect with the wiring layer 4, the gate is electrically led to the B side 3, and the top of the conductive glue 6 is flush with the B side 3 of the package 1 and exposed.

[0059] The B surface 3 of the package body 1 is provided with a gate pin 9 formed by metal electroplating on the inner wall of the hole and extending along the B surface 3 of the package body 1. The gate pin 9 is arranged on one side of the drain pin 10. The A surface 2 of the package body 1 is electroplated with a source pin 8, and the source pin 8 covers the connecting column 5. Protective materials such as gold (Au), silver (Ag) or tin (Sn) are electroplated on the surface of the source pin 8, the drain pin 10 and the gate pin 9, which does not affect the welding effect and ensures the service life of the metal pins. Among them, the gate pin 9 is as shown in FIG. Fig.18 shown.

[0060] In all the encapsulation steps of the present invention, the encapsulation material used is a plastic encapsulation material, and the specific material can be epoxy resin, cyanate, polyimide, etc., which has low cost and good curing performance. The packaging process plays an important role in the field of semiconductor manufacturing, mainly in terms of protection, connection, support, reliability and promotion of technological progress. The encapsulation method is the commonly used molding and injection molding method in this field.

[0061] All post-encapsulation grinding processes of the present invention use a grinding machine commonly used in the technical field to perform surface treatment on the package body 1, that is, horizontal mechanical grinding is performed on the top surface of the package body 1. Finally, after grinding, the grinding surface is horizontal and flat, and the outer surface of the entire packaging structure is flat and smooth.

[0062] All the steps of the electroplating process of the present invention are to first form electroplating protection on the surface through exposure and development photolithography technology, protect the places that do not need electroplating, expose the areas that need electroplating, and then form a metal seed layer in the area to be electroplated by sputtering or copper deposition or other appropriate methods. The metal seed layer is copper or other metal materials. The metal seed layer is to ensure the bonding force between the metals and metals and between the metals and the encapsulation materials in the subsequent electroplating, and at the same time provide a surface for the electroplating to attach conductive ions, thereby ensuring the electroplating effect. The entire steps in the electroplating process and the materials used are also common technical knowledge in this field. The metals electroplated in all the electroplating processes of the present invention are all made of metallic copper.

[0063] The present invention: the gate located on the front side of the bare chip 7 is electrically led out to the back side of the bare chip 7 and then to the outside of the package 1, so as to avoid that after the larger-sized source electrode is mounted through the source pin 8, the gate pin 9 of the smaller-sized gate electrode cannot be mounted normally, and the source pin 8 and the gate pin 9 are welded and adhered, resulting in a short circuit and affecting the normal function of the product; at the same time, the gate electrode is led out to the B side 3 of the package 1, and the distribution space is left for the source pin 8 on the A side 2 of the package 1 to the maximum extent, so that the source heat can be dissipated to the maximum extent, and the entire package structure The heat dissipation effect is better; the connecting column 5 and the conductive column under the wiring layer 4 are symmetrically arranged about the horizontal plane where the wiring layer 4 is located, so that the structures, stresses and positions of the upper and lower sides of the wiring layer 4 are symmetrical, and the heat of the bare chip 7 is transferred to the connecting column 5 through the shortest vertical path, and then dissipated to the outside of the A surface 2 of the package body 1. The structure is more stable, the connecting column 5 and the conductive column have the same size, and the electrical and heat transfer effects are better; the conductive column electroplated on the source electrode covers at least 80% of the area of ​​the source electrode, which leads out the electrical properties of the source electrode while conducting the heat on the source electrode to a greater extent.

[0064] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are within the scope of protection of the present invention.

Claims

1. A bonding pad lead-out MOS chip packaging method, characterized in that: The following steps are involved: Wiring layer plating: Place the die toward the substrate and encapsulate and grind to expose the conductive glue covering the die drain, peel off the substrate and turn the die upside down. At this time, the source and gate of the die are flush with the encapsulation material and exposed. After the die is encapsulated, the wiring layer is plated on the exposed source and gate connection ports on the surface to lead out the electrical level. Electrical lead-out on the A side: Electroplating connection posts on the wiring layer of the source, encapsulating and polishing to expose the top of the connection posts, and electrically lead the source to the A side of the package; Electrical lead-out on the B side: The conductive glue is exposed flush with the encapsulation material, the drain of the bare chip is electrically led out to the B side of the package, and a hole is drilled on the B side until the wiring layer of the gate is exposed; Double-sided electroplating: Electroplating metal on the B side covers the conductive glue, while the inner wall of the hole is electroplated to connect with the wiring layer, electrically leading the gate to the B side of the package, and electroplating metal on the A side covers the connecting column.

2. The bonding pad lead-out MOS chip packaging method according to claim 1, characterized in that: In the wiring layer electroplating step, conductive pillars are vertically electroplated on the exposed source and gate on the surface of the encapsulated bare chip, and the conductive pillars are further encapsulated and polished to expose the tops of the conductive pillars to form connection ports for the source and gate.

3. The bonding pad lead-out MOS chip packaging method according to claim 2, characterized in that: In the A-side electrical lead-out step, the wiring layer and the connecting column are further encapsulated on the basis of the bare chip encapsulation and the conductive column encapsulation in the wiring layer electroplating step, and the top of the connecting column is exposed by horizontal mechanical grinding on the top surface of the encapsulation. At this time, the encapsulation as a whole constitutes a package.

4. The bonding pad lead-out MOS chip packaging method according to claim 1, characterized in that: In the B-side electrical lead-out step, the wiring layer electrically leads out the gate horizontally, and a hole is drilled in the encapsulation material at a position next to the bare chip on the B-side of the package body by laser drilling, avoiding the bare chip.

5. The bonding pad lead-out MOS chip packaging method according to claim 1, characterized in that: In the double-sided electroplating step, the drain pin plated with metal on the B side is covered with conductive glue, and the metal plated on the inner wall of the hole extends along the B side of the package to form a gate pin, which is arranged on one side of the drain pin.

6. The bonding pad lead-out MOS chip packaging method according to claim 1, characterized in that: In the double-sided electroplating step, the source electrode pins electroplated with metal on the A side cover the connecting pillars.

7. A bonding pad lead-out MOS chip structure, comprising a package body, the package body having opposite A side and B side, characterized in that: The package contains: A bare chip, wherein a source electrode and a gate electrode are arranged on one surface of the bare chip, and a drain electrode is arranged on another opposite surface; The wiring layer is electroplated on the source and gate connection ports to lead out the electrical properties horizontally; Connecting column: the connecting column is electroplated on the wiring layer of the source electrode to electrically lead the source electrode to the A surface, and the top of the connecting column is flush with the A surface of the package body and exposed; Conductive glue, the conductive glue covering the drain electrically leads the drain to the B surface, drills a hole on the B surface until the wiring layer of the gate is exposed, and electroplates in the hole to connect with the wiring layer, electrically leads the gate to the B surface, and the top of the conductive glue is flush with the B surface of the package and exposed.

8. The bonding pad lead-out MOS chip structure according to claim 7, characterized in that: Conductive pillars are vertically plated on the source and gate of the bare chip to form connection ports of the source and gate.

9. The bonding pad lead-out MOS chip structure according to claim 8, characterized in that: The surface where the bare chip source and gate are located is formed into conductive pillars, wiring layers and connecting pillars connected in sequence through layer-by-layer electroplating, encapsulation and grinding processes, and finally encapsulated to form a package body.

10. The bonding pad lead-out MOS chip structure according to claim 7, characterized in that: The wiring layer electrically leads the gate out horizontally, and a hole is drilled in the encapsulation material at a position next to the bare chip on the B side of the package body by laser drilling, avoiding the bare chip.

11. The bonding pad lead-out MOS chip structure according to claim 9, characterized in that: The drain pin of the package body B surface plated with metal is covered with conductive glue.

12. The bonding pad lead-out MOS chip structure according to claim 11, characterized in that: The package body B surface is provided with a gate pin formed by metal electroplating on the inner wall of the hole and extending along the package body B surface, and the gate pin is arranged on one side of the drain pin.

13. The bonding pad lead-out MOS chip structure according to claim 7, characterized in that: The package body A side has a source pin plated with metal, and the source pin covers the connection column.

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