Chip packaging structure, preparation method and electronic equipment

Abstract

The invention discloses a chip packaging structure, a preparation method and electronic equipment. The chip packaging structure comprises a first substrate; the second substrate and the first substrate are arranged up and down in a spaced manner; the plastic package part is used for carrying out plastic package on the first substrate and the second substrate so as to form the chip package structure; and the electric connection layer is arranged on at least one side of the chip packaging structure after plastic packaging, so that the first substrate and the second substrate are mutually conducted. According to the chip packaging structure, the electric connection layers are arranged on the two opposite sides of the plastic-packaged chip packaging structure, and the electric connection layers are used as paths for interconnection of the chip packaging structure up and down, so that narrow-spacing chip packaging is realized, and the chip packaging density is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and more specifically, to a chip packaging structure, a preparation method and an electronic device. Background Art

[0002] Traditional chip packaging products usually use solder balls or copper pillars as upper and lower interconnect structures. However, solder balls (hundreds of microns) or copper pillars (tens of microns) are large in size, occupy a large space, and the packaging density is limited. Summary of the invention

[0003] An object of the present invention is to provide a new technical solution for a chip packaging structure, a preparation method and an electronic device, which can at least solve the problem of limited packaging density in packaging products of the prior art.

[0004] According to a first aspect of the present invention, a chip packaging structure is provided, comprising: a first substrate; a second substrate, the second substrate being spaced apart from the first substrate and arranged up and down; a plastic sealing member, the plastic sealing member being used to seal the first substrate and the second substrate to form the chip packaging structure; and an electrical connection layer, the electrical connection layer being arranged on at least one side of the chip packaging structure after sealing to enable the first substrate and the second substrate to be electrically connected to each other.

[0005] Optionally, the electrical connection layer is a metal layer, and the electrical connection layer is sputtered on two opposite sides of the chip packaging structure after plastic packaging.

[0006] Optionally, the first substrate is a first circuit board, and the second substrate is a second circuit board.

[0007] Optionally, a first chip is disposed on the first substrate, a second chip is disposed on the second substrate, and solder balls are disposed on a side of the first substrate facing away from the first chip.

[0008] Optionally, a portion of the plastic encapsulation member is filled between the first substrate and the second substrate, and another portion of the plastic encapsulation member is filled on a side of the first substrate facing away from the second substrate.

[0009] Optionally, the chip packaging structure also includes: a third circuit board, the area of ​​the second circuit board is larger than the area of ​​the first substrate, a third chip is arranged on the third circuit board, the chip packaging structure with the electrical connection layer is arranged on the third circuit board, and the solder balls on the first substrate are connected to the third circuit board.

[0010] A second aspect of the present invention provides a method for preparing a chip packaging structure, which is used to prepare the chip packaging structure described in the above embodiment, and the preparation method comprises:

[0011] Providing a first substrate, on which a plurality of first chips are arranged, and on which a support member is arranged;

[0012] Planting balls on a side of the first substrate facing away from the support member to form a first structural member;

[0013] Providing a second substrate, and arranging a plurality of second chips on the second substrate to form a second structural member, wherein the supporting member is used to isolate the first substrate and the second substrate;

[0014] stacking the first structural member on the second structural member;

[0015] Performing one-time plastic sealing on the first structural member and the second structural member as a whole;

[0016] Cutting the first and second plastic-sealed structural members, removing the support member, and forming a single chip packaging structure;

[0017] A shielding tape is provided on a single chip packaging structure, and a third structural member having an electrical connection layer is formed on a side of the single chip packaging structure;

[0018] After the electrical connection layer is completed, the shielding tape is removed.

[0019] Optionally, the method for preparing the chip packaging structure further includes:

[0020] Mounting the third structural component on the third circuit board;

[0021] The electrical connection layer on the side of the third structure facing away from the third circuit board is ground.

[0022] Optionally, shielding tapes are respectively pasted on the side walls and the top of the single chip packaging structure, and after sputtering is completed, the shielding tapes are removed.

[0023] A third aspect of the present invention provides an electronic device, comprising the chip packaging structure described in the above embodiment.

[0024] The chip packaging structure of the present invention realizes narrow pitch chip packaging by arranging an electrical connection layer on at least one side of the chip packaging structure after plastic packaging, and uses the electrical connection layer as a path for interconnecting the chip packaging structure from top to bottom, thereby effectively improving the chip packaging density.

[0025] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0027] Figure 1 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present invention;

[0028] Figure 2 is a partial flow chart of a method for preparing a chip packaging structure according to an embodiment of the present invention;

[0029] Figure 3 is another partial flow chart of a method for preparing a chip packaging structure according to an embodiment of the present invention;

[0030] Figure 4 is another partial flow chart of a method for preparing a chip packaging structure according to an embodiment of the present invention;

[0031] Figure 5 is another partial flow chart of a method for preparing a chip packaging structure according to an embodiment of the present invention;

[0032] Figure 6 It is a schematic diagram of sticking shielding tape in the method for preparing a chip packaging structure according to an embodiment of the present invention.

[0033] Reference numerals:

[0034] First substrate 10; support member 11; solder ball 12;

[0035] A second substrate 20;

[0036] Plastic sealing part 30;

[0037] Electrical connection layer 40;

[0038] A first chip 51; a second chip 52; a third chip 53;

[0039] A third circuit board 60;

[0040] Shielding tape 70. DETAILED DESCRIPTION

[0041] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0042] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0043] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0044] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0045] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0046] In the specification and claims of the present invention, if the term "first" or "second" is involved, it may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0047] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present invention.

[0048] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" involved should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] The chip packaging structure according to the embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0050] like Figure 1As shown, the chip packaging structure according to the embodiment of the present invention includes a first substrate 10 , a second substrate 20 , a plastic package 30 and an electrical connection layer 40 .

[0051] Specifically, the second substrate 20 is spaced apart from the first substrate 10 and arranged up and down. The plastic package 30 is used to plastic-package the first substrate 10 and the second substrate 20 to form a chip packaging structure. The electrical connection layer 40 is provided on at least one side of the plastic-packaged chip packaging structure to make the first substrate 10 and the second substrate 20 conduct to each other.

[0052] In other words, see Figure 1 The chip packaging structure according to the embodiment of the present invention is mainly composed of a first substrate 10, a second substrate 20, a plastic package 30 and an electrical connection layer 40. The second substrate 20 is spaced apart from the first substrate 10 and arranged up and down. The plastic package 30 is used to plastic-encapsulate the first substrate 10 and the second substrate 20, and the first substrate 10 and the second substrate 20 are plastic-encapsulated as a whole at one time to form a chip packaging structure. The electrical connection layer 40 is arranged on at least one side of the chip packaging structure after plastic encapsulation. In the present invention, the electrical connection layer 40 can be arranged on one side or both sides of the chip packaging structure after plastic encapsulation. The interconnection width of the electrical connection layer 40 is only about 10μm. The electrical connection layer 40 is used as a path for interconnecting the chip packaging structure up and down, so that the first substrate 10 and the second substrate 20 are vertically connected to each other, and a narrow pitch chip packaging is realized, which effectively improves the chip packaging density. It should be noted that the way in which the first substrate 10 and the second substrate 20 are vertically connected to each other is that the copper layer structure exposed on the side of the first substrate 10 and / or the second substrate 20 is electrically connected to the plating layer (electrical connection layer 40).

[0053] In the prior art, chip packaging products usually use solder balls or copper pillars as upper and lower interconnection structures. However, solder balls (hundreds of microns) or copper pillars (tens of microns) are large in size, occupy a large space, and the packaging density is limited.

[0054] Therefore, according to the chip packaging structure of the embodiment of the present invention, by setting an electrical connection layer 40 on at least one side of the chip packaging structure after plastic packaging, the electrical connection layer 40 is used as a path for interconnecting the upper and lower parts of the chip packaging structure, thereby realizing narrow-pitch chip packaging and effectively improving the chip packaging density.

[0055] According to an embodiment of the present invention, the electrical connection layer 40 is a metal layer, and the electrical connection layer 40 is sputtered on two opposite sides of the chip packaging structure after plastic encapsulation.

[0056] That is to say, Figure 1As shown, the electrical connection layer 40 can be made of a metal layer, such as stainless steel or copper. The electrical connection layer 40 can be made of a magnetron sputtering process, and a layer of electrical connection layer 40 can be sputtered on the opposite sides of the chip packaging structure after plastic sealing or around the chip packaging structure after plastic sealing. The electrical connection layer 40 is used as a path for interconnecting the chip packaging structure up and down to achieve narrow pitch chip packaging, effectively improving the chip packaging density. Of course, in the present invention, before sputtering the metal layer (electrical connection layer 40), the shielding tape 70 can be used to shield the position where the conductive path is connected to the edge electrode of the substrate (circuit board), see Figure 6 After the sputtering is completed, the shielding tape 70 can be removed. The metal layer on the upper layer of the chip packaging structure can also be removed by a grinding process to achieve the purpose of vertical conduction inside the product.

[0057] According to one embodiment of the present invention, Figure 1 As shown, the first substrate 10 is a first circuit board, and the second substrate 20 is a second circuit board. In other words, both the first substrate 10 and the second substrate 20 can be circuit boards, which are directly used as substrates for the chip packaging structure without the need for additional substrates, thereby reducing the overall size and material of the chip packaging structure, and facilitating the miniaturization and lightweight design of the chip packaging structure.

[0058] According to an embodiment of the present invention, a first chip 51 is disposed on the first substrate 10 , a second chip 52 is disposed on the second substrate 20 , and a solder ball 12 is disposed on a side of the first substrate 10 facing away from the first chip 51 .

[0059] That is to say, Figure 1 and Figure 2 As shown, a first chip 51 may be provided on the first substrate 10, and the first chip 51 may be a logic chip. A second chip 52 may be provided on the second substrate 20, and the second chip 52 may be a memory chip. A solder ball 12 may be provided on the side of the first substrate 10 facing away from the first chip 51 through a ball planting process, so as to facilitate mounting the chip packaging structure on a larger circuit board. The types and quantities of the first chip 51 and the second chip 52 may be specifically set according to actual needs, and will not be described in detail in the present invention.

[0060] According to one embodiment of the present invention, a portion of the plastic seal 30 is filled between the first substrate 10 and the second substrate 20, and another portion of the plastic seal 30 is filled on the side of the first substrate facing away from the second substrate 20. The present invention adopts a one-time plastic seal method, meets the technical requirements of double-sided plastic seal, has high efficiency, and saves mold costs.

[0061] According to one embodiment of the present invention, Figure 3As shown, the chip packaging structure also includes: a third circuit board 60, the area of ​​the second circuit board is larger than the area of ​​the first substrate 10, a third chip 53 is arranged on the third circuit board 60, the chip packaging structure provided with an electrical connection layer 40 is mounted on the third circuit board 60, and the solder balls 12 on the first substrate 10 are connected to the third circuit board 60. After the chip packaging structure provided with the electrical connection layer 40 is mounted on the third circuit board 60, plastic sealing of the large board can be achieved.

[0062] In summary, according to the chip packaging structure of the embodiment of the present invention, by setting an electrical connection layer 40 on the opposite sides of the chip packaging structure after plastic packaging, the electrical connection layer 40 is used as a path for upper and lower interconnections of the chip packaging structure to achieve narrow pitch chip packaging and effectively improve the chip packaging density.

[0063] Of course, for those skilled in the art, other structures of the chip packaging structure and its working principles are understandable and achievable, and will not be described in detail in the present invention.

[0064] According to a second aspect of the present invention, Figures 2 to 5 As shown, a method for preparing a chip packaging structure is provided, which is used to prepare the chip packaging structure in the above embodiment, and the preparation method includes:

[0065] A first substrate 10 is provided, a plurality of first chips 51 are arranged on the first substrate 10, and a support member 11 is arranged on the first substrate 10;

[0066] Planting balls on a side of the first substrate 10 facing away from the support member 11 to form a first structural member;

[0067] A second substrate 20 is provided, and a plurality of second chips 52 are arranged on the second substrate 20 to form a second structural member, and the support member 11 is used to isolate the first substrate 10 and the second substrate 20;

[0068] Stacking the first structural member on the second structural member;

[0069] Performing one-time plastic sealing on the first structural member and the second structural member as a whole;

[0070] Cut the first and second plastic-encapsulated structural members, remove the support member 11, and form a single chip packaging structure;

[0071] A shielding tape 70 is provided on the single chip packaging structure, and a third structural member having an electrical connection layer 40 is formed on the side of the single chip packaging structure;

[0072] After the electrical connection layer 40 is completed, the shielding tape 70 is removed.

[0073] In other words, the method for preparing a chip packaging structure according to an embodiment of the present invention is mainly used to prepare the chip packaging structure in the above embodiment. In the preparation method, first, as Figure 2 As shown, a first substrate 10 can be provided, and a plurality of first chips 51 can be mounted on the first substrate 10. A support member 11 is provided on the first substrate 10, and the support member 11 can be pre-set between two adjacent first chips 51. While playing a supporting role, it can also achieve the function of isolating the first substrate 10 and the second substrate 20. The support member 11 and the first substrate 10 can be fixed by bonding, ball planting or soldering. Then, the ball planting can be performed on the side of the first substrate 10 facing away from the support member 11 to form a first structural member. Next, a second substrate 20 can be provided, and a plurality of second chips 52 can be arranged on the second substrate 20 to form a second structural member. The support member 11 is used to isolate the first substrate 10 and the second substrate 20. The first structural member can be stacked on the second structural member. Then, as shown Figure 3 As shown, the first structural member and the second structural member can be plastic-sealed as a whole at one time, and the plastic-sealed first structural member and the second structural member can be cut. During the cutting process, the support member 11 is removed to form a single chip packaging structure.

[0074] Then, a shielding tape 70 is placed on the single chip packaging structure (see Figure 6 ), the shielding tape 70 can be set on the single chip packaging structure by bonding. At the same time, a third structural member with an electrical connection layer 40 is formed on the side of the single chip packaging structure. For example, magnetron sputtering is used to form a third structural member with an electrical connection layer 40 around the plastic package 30. Of course, in the present invention, it can also be formed by deposition, grinding and removal, etc., which will not be described in detail here. Finally, after the electrical connection layer 40 is completed, the shielding tape 70 is removed, and the electrical connection layer 40 is used as a path for interconnecting the upper and lower chip packaging structures to achieve narrow pitch chip packaging, effectively improving the chip packaging density. In the present invention, the electrical connection layer 40 can be set by affixing the shielding tape 70 and sputtering, or by depositing photosensitive glue and depositing metal, or by overall sputtering and then grinding, etc., which will not be described in detail in the present invention.

[0075] According to one embodiment of the present invention, the method for preparing a chip packaging structure further includes:

[0076] Mounting the third structural component on the third circuit board 60;

[0077] The electrical connection layer 40 on the side of the third structure facing away from the third circuit board 60 is ground.

[0078] That is to say, Figure 4 and Figure 5As shown, in the preparation method of the chip packaging structure of the present invention, the third structural member can also be mounted on the third circuit board 60, which can be a large circuit board, and the third chip 53 is mounted on the third circuit board 60. Then, by plastic sealing, the electrical connection layer 40 on the side of the third structural member facing away from the third circuit board 60 is finally ground to form a large package product, and the electrical connection layer 40 is used as a path for interconnecting the chip packaging structure from top to bottom, so as to realize narrow pitch chip packaging and effectively improve the chip packaging density.

[0079] According to one embodiment of the present invention, shielding tape 70 can be respectively pasted on the side walls and top of a single chip packaging structure, and after sputtering is completed, the shielding tape 70 is removed, and the electrical connection layer 40 is used as a path for interconnecting the upper and lower parts of the chip packaging structure to achieve narrow pitch chip packaging and effectively improve the chip packaging density.

[0080] According to a second aspect of the present invention, an electronic device is provided, comprising the chip packaging structure in the above embodiment. Since the chip packaging structure according to the embodiment of the present invention has the above technical effects, the electronic device according to the embodiment of the present invention should also have corresponding technical effects, that is, the electronic device of the present invention adopts the chip packaging structure in the above embodiment, and uses the electrical connection layer 40 as a path for interconnecting the chip packaging structure from top to bottom, so as to realize narrow-pitch chip packaging and effectively improve chip packaging density.

[0081] Of course, for those skilled in the art, other structures and working principles of the electronic device are understandable and achievable, and will not be described in detail in the present invention.

[0082] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A chip packaging structure, characterized in that: include: A first substrate (10); a second substrate (20), the second substrate (20) being spaced apart from the first substrate (10) and arranged up and down; A plastic packaging member (30), the plastic packaging member (30) being used to plastic-package the first substrate (10) and the second substrate (20) to form the chip packaging structure; An electrical connection layer (40), the electrical connection layer (40) being arranged on at least one side of the chip packaging structure after plastic packaging, so as to enable the first substrate (10) and the second substrate (20) to be electrically connected to each other.

2. The chip packaging structure according to claim 1, characterized in that: The electrical connection layer (40) is a metal layer, and the electrical connection layer (40) is sputtered on two opposite sides of the chip packaging structure after plastic packaging.

3. The chip packaging structure according to claim 1, characterized in that: The first substrate (10) is a first circuit board, and the second substrate (20) is a second circuit board.

4. The chip packaging structure according to claim 1, characterized in that: A first chip (51) is provided on the first substrate (10), a second chip (52) is provided on the second substrate (20), and a solder ball (12) is provided on a side of the first substrate (10) facing away from the first chip (51).

5. The chip packaging structure according to claim 1, characterized in that: A portion of the plastic package (30) is filled between the first substrate (10) and the second substrate (20), and another portion of the plastic package (30) is filled on a side of the first substrate facing away from the second substrate (20).

6. The chip packaging structure according to claim 1, characterized in that: Also includes: A third circuit board (60), the area of ​​the second circuit board is larger than the area of ​​the first substrate (10), a third chip (53) is provided on the third circuit board (60), the chip packaging structure provided with the electrical connection layer (40) is provided on the third circuit board (60), and the solder ball (12) on the first substrate (10) is connected to the third circuit board (60).

7. A method for preparing a chip packaging structure, used for preparing the chip packaging structure according to any one of claims 1 to 6, characterized in that: The preparation method comprises: Providing a first substrate (10), wherein a plurality of first chips (51) are arranged on the first substrate (10), and a support member (11) is provided on the first substrate (10); Planting balls on a side of the first substrate (10) facing away from the support member (11) to form a first structural member; Providing a second substrate (20), and arranging a plurality of second chips (52) on the second substrate (20) to form a second structural member, wherein the support member (11) is used to isolate the first substrate (10) and the second substrate (20); stacking the first structural member on the second structural member; Performing one-time plastic sealing on the first structural member and the second structural member as a whole; Cutting the first structural member and the second structural member after plastic packaging, removing the support member (11), and forming a single chip packaging structure; A shielding tape (70) is provided on a single chip packaging structure, and a third structural member having an electrical connection layer (40) is formed on a side surface of the single chip packaging structure; After the electrical connection layer (40) is completed, the shielding tape (70) is removed.

8. The method for preparing a chip packaging structure according to claim 7, characterized in that: Also includes: Mounting the third structural component on a third circuit board (60); The electrical connection layer (40) on the side of the third structural component facing away from the third circuit board (60) is ground.

9. The method for preparing a chip packaging structure according to claim 7, characterized in that: Shielding tapes (70) are respectively pasted on the side walls and the top of the single chip packaging structure, and after sputtering is completed, the shielding tapes (70) are removed.

10. An electronic device, characterized in that: A chip packaging structure comprising any one of claims 1-6.

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