Systems and methods for enhancing die-to-die connections in semiconductor devices

Abstract

The subject technology relates to systems and methods for enhancing die-to-die connections in semiconductor devices. In accordance with an embodiment, the subject technology provides an apparatus comprising a first layer comprising a first block and a second layer comprising a second block. The device further includes a third layer coupled to the first and second layers and positioned between the first and second layers. The first and second layers are aligned at a first region of the first connection based on a set of design strategies. Embodiments of the subject technology enable automatic and efficient routing of signals across dies, accommodating multiple instantiations of circuit blocks with various orientations. This ensures minimum signal path length and high density interconnects by minimizing the physical footprint of the connections and complying with strict design rule checks within the 3D integrated circuit layout. Other embodiments are also present.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 584,092, filed on September 20, 2023, which is commonly owned and incorporated herein by reference for all purposes. Technical Field

[0003] The subject technology relates to systems and methods for die-to-die integration in semiconductor devices. Background Art

[0004] Over the past decade, the semiconductor industry has been very interested in advances in the design of three-dimensional (3D) semiconductor packages. These 3D configurations, which involve stacking multiple semiconductor dies in a vertical arrangement, require reliable die-to-die connections to ensure efficient communication and power distribution across the stacked dies.

[0005] Some methods use hybrid copper bonding (HCB) to establish electrical connections between dies. For example, the term "hybrid copper bonding" may refer to a structure that combines dielectric materials with metal materials to form an interconnect for die-to-die connections in 3D semiconductor packages. In order to establish a stable connection between dies, the HCB must be wired to connect the block pins on one die to the corresponding block pins on another die. However, due to resource constraints in certain areas of the block, it is still a challenging task to efficiently wire the HCB, where existing circuit elements or structures limit the available space for HCB placement. These constraints are further complicated by the integration of multiple instantiation blocks (MIBs) within semiconductor dies. For example, the term "multiple instantiation blocks" may refer to functional units that can be reused multiple times within the same die or across multiple dies. MIBs - different in their orientation and position within the semiconductor stack - require each instantiation of the block to be effectively interconnected, thereby bringing further challenges in achieving consistent and reliable die-to-die connections.

[0006] Various approaches for die-to-die integration have been explored, but have proven to be inadequate. It is important to recognize that new and improved systems and methods are needed for optimizing die-to-die connections in semiconductor devices. Summary of the invention

[0007] In one aspect, the present disclosure provides a device comprising: a first layer comprising a first block, the first block comprising a first pin; a second layer comprising a second block, the second block comprising a second pin; and a third layer coupled to the first layer and the second layer and positioned between the first layer and the second layer, the third layer comprising a first connection coupled to the first pin and the second pin and positioned between the first pin and the second pin, the first pin and the second pin sharing the first connection; wherein the first layer and the second layer are aligned at a first area of ​​the first connection based on a set of design strategies.

[0008] In another aspect, the present disclosure provides a method comprising: receiving a first layout of a first layer, the first layer including a first block, the first block including a first pin; receiving a second layout of a second layer, the second layer including a second block, the second block including a second pin; receiving a third layout of a third layer, the third layer being coupled to the first layer and the second layer and positioned between the first layer and the second layer, the third layer including a first connection configured to couple the first pin to the second pin, the first pin and the second pin sharing the first connection; identifying a first area that can be used to locate the first connection based on a first set of placement constraints; identifying a second area that cannot be used to locate the first connection based on a second set of placement constraints; and determining a third area for locating the first connection based on at least the first area and the second area, the first layer and the second layer being aligned at the third area of ​​the first connection.

[0009] In another aspect, the present disclosure provides a device comprising: a first layer comprising a first block, the first block comprising a first pin; a second layer comprising a second block, the second block comprising a second pin; and a third layer coupled to the first layer and the second layer and positioned between the first layer and the second layer, the third layer comprising a first connection coupled to the first pin and the second pin and positioned between the first pin and the second pin; wherein the first layer and the second layer are aligned at a first area of ​​the first connection, and the first area is determined by: identifying a second area that can be used to locate the first connection based on a first set of placement constraints; identifying a third area that cannot be used to locate the first connection based on a second set of placement constraints; and determining the third area based at least on the first area and the second area. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a simplified diagram illustrating a semiconductor device having a 3D interconnect structure according to an embodiment of the subject technology.

[0011] Figure 2is a simplified diagram illustrating a semiconductor device having a 3D interconnect structure according to an embodiment of the subject technology.

[0012] Figure 3 is a simplified diagram illustrating same-die and cross-die connections within a semiconductor device according to an embodiment of the subject technology.

[0013] Figure 4 is a simplified diagram illustrating a method for identifying available areas for establishing die-to-die connections within a semiconductor device in accordance with an embodiment of the subject technology.

[0014] Figure 5 is a simplified diagram illustrating a method for identifying unusable areas for establishing die-to-die connections within a semiconductor device in accordance with an embodiment of the subject technology.

[0015] Figure 6 is a simplified diagram illustrating a method for determining an area for establishing a die-to-die connection within a semiconductor device in accordance with an embodiment of the subject technology.

[0016] Figure 7 is a simplified diagram illustrating a method for determining HCB placement across multiply instantiated blocks within a semiconductor device in accordance with an embodiment of the subject technology.

[0017] Figure 8 is a simplified diagram illustrating a method for determining pin placement across multiply instantiated blocks within a semiconductor device in accordance with an embodiment of the subject technology.

[0018] Fig. 9 is a simplified flow chart illustrating a method for determining die-to-die connections within a semiconductor device according to an embodiment of the subject technology. DETAILED DESCRIPTION

[0019] The subject technology relates to systems and methods for enhancing die-to-die connections in semiconductor devices. According to an embodiment, the subject technology provides a device comprising a first layer including a first block and a second layer including a second block. The device further comprises a third layer, the third layer being coupled to the first and second layers and positioned between the first and second layers. Based on a set of design strategies, the first and second layers are aligned at a first region of the first connection. Embodiments of the subject technology enable automatic and efficient routing of signals across dies, accommodating multiple instantiations of circuit blocks with various orientations. This ensures minimum signal path length and high-density interconnection by minimizing the physical footprint of the connection and complying with strict design rule checks in 3D integrated circuit layouts. Other embodiments also exist.

[0020] A 3D integrated circuit (IC) may refer to a semiconductor circuit manufactured by vertically stacking two or more semiconductor dies. For example, a die may include one or more logic blocks, which are functional units configured to perform certain computing or storage tasks. In some cases, a die may include a multi-instantiated block (MIB), which may be reused multiple times within the same die or design. These blocks have the same or similar functions, but may be instantiated in different contexts or locations. The interconnection between semiconductor dies may be achieved using various technologies, such as through silicon vias (TSVs) and hybrid copper bonding (HCBs). HCBs may include bonding between copper or other metals (e.g., gold, etc.) and dielectric materials, which may be organic (e.g., small molecules or monomers, etc.) or inorganic (e.g., silicon oxide, other metal oxides, etc.).

[0021] The integration of 3D IC involves aligning and connecting HCBs across vertically stacked semiconductor dies to ensure optimal inter-die communication. For efficient operation, the HCBs on the lower semiconductor die (e.g., bottom die) must be aligned with the corresponding HCBs on the upper die (e.g., top die) to achieve the shortest possible wire length to the associated logic block in the upper metal layer. However, the structural density within the die usually leads to limited space for HCB placement because the upper metal layer may be pre-occupied by other circuits or structural elements. Such allocation complexity is further amplified by the presence of multiple instantiation blocks within the die. Although each instantiation of the logic block is functionally equivalent, it may face unique spatial constraints based on its specific position and orientation within the die. These constraints must not only be tracked within a single die, but also must be tracked across the entire die stack to ensure optimal signal routing. As the scale of semiconductor designs continues to increase, maintaining efficient and effective connections across all layers of 3D ICs becomes a challenging task.

[0022] In various embodiments, the subject technology provides methods and systems for improving the connectivity and performance of 3D ICs by optimizing the placement and routing of HCBs across stacked semiconductor dies. Embodiments of the subject technology relate to an algorithmic framework that analyzes the spatial configuration of each die to identify the optimal path for signal routing that minimizes impedance and length. The algorithmic framework facilitates a coordinated approach to signal routing across the entire 3D IC stack, ensuring that all inter-die connections are precisely aligned and optimally configured for signal transmission. This approach also addresses the challenges posed by MIBs by allowing flexible placement and orientation of MIBs across die stacks while ensuring consistent and efficient signal connections. By simplifying the design process, the system reduces the complexity and time involved in the design phase, enabling faster development cycles for semiconductor devices.

[0023] The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it into the context of a particular application. Various modifications and various uses in different applications will be apparent to those skilled in the art, and the general principles defined herein can be applied to a wide range of embodiments. Therefore, the subject technology is not intended to be limited to the embodiments presented, but should be given the widest scope consistent with the principles and novel features disclosed herein.

[0024] In the following detailed description, many specific details are set forth in order to provide a more thorough understanding of the subject technology. However, it will be apparent to those skilled in the art that the subject technology can be practiced without being limited to these specific details. In other examples, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the subject technology.

[0025] The reader's attention is directed to all papers and documents filed simultaneously with this specification and disclosed for public inspection together with this specification, and the contents of all such papers and documents are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any attached claims, abstracts and drawings) can be replaced by alternative features for the same, equivalent or similar purposes. Therefore, unless otherwise expressly stated, each feature disclosed is only an example of a general series of equivalent or similar features.

[0026] Furthermore, any element in a claim that does not explicitly recite a “means” for performing a specified function or a “step” for performing a specific function should not be construed as a “means” or “step” clause as specified in 35 U.S.C. § 112, paragraph 6. In particular, the “step” or “action” used in the claims herein is not intended to invoke the provisions of 35 U.S.C. § 112, paragraph 6.

[0027] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or have an intervening element present between the elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which intervening elements may be present.

[0028] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, arranged below, disposed adjacent, or disposed in some other relative manner), it is understood that the element may be disposed directly relative to another element (e.g., disposed directly on another element) or have intervening elements present between the elements. Conversely, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which intervening elements may be present.

[0029] Similarly, when an element is referred to herein as being "joined" to another element, it is understood that the element may be directly joined to the other element (without any intervening elements), or with an intervening element present between the joined elements. Conversely, when an element is referred to as being "directly joined" to another element, it is understood that there are no intervening elements in the "direct" joining between the elements. However, the presence of direct joining does not exclude other forms of joining in which intervening elements may be present.

[0030] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include multiple different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include multiple dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intermediary element that exists between the coupled or connected layers. Conversely, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intermediary elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which an intermediary element may exist.

[0031] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0032] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context indicates otherwise, intermediary processes may occur before and / or after any portion of the described processes, and various other processes may be reordered, added, and / or omitted according to various embodiments.

[0033] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, unless otherwise expressly stated, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "including" and "having" as well as other forms (such as includes, included, has, have and had) should be considered non-exclusive. In addition, terms such as "element" or "component" cover both elements and components comprising one unit and elements or components comprising more than one unit, unless otherwise expressly stated.

[0034] As used herein, the phrase "at least one" preceding a series of items using the terms "and" or "or" to separate any of the items modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one" does not require the selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any of the items, and / or at least one of any combination of items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In examples where the selection is intended to be "at least one of each of A, B, and C," or alternatively "at least one of A, at least one of B, and at least one of C," it is explicitly described as such.

[0035] One general aspect includes a device comprising a first layer, the first layer comprising a first block, the first block comprising a first pin. The device further comprises a second layer, the second layer comprising a second block, the second block comprising a second pin. The device further comprises a third layer, the third layer coupled to the first layer and the second layer and positioned between the first layer and the second layer, the third layer comprising a first connection coupled to the first pin and the second pin and positioned between the first pin and the second pin, the first pin and the second pin sharing a first connection. The first layer and the second layer are aligned at a first area of ​​the first connection based on a set of design strategies.

[0036] Embodiments may include one or more of the following features. The first connection includes a mixed copper bond. The distance between the first pin and the first connection is less than or equal to 30um. The first block includes a multi-instantiated block. The set of design strategies includes a first set of placement constraints and a second set of placement constraints. The first set of placement constraints is associated with a second area that can be used to locate the first connection. The second set of placement constraints is associated with a third area that cannot be used to locate the first connection. The first area is determined based on at least the second area and the third area. The first layer further includes a third block, the third block includes a third pin, and the first pin and the third pin share a second connection.

[0037] According to another embodiment, the subject technology provides a method that includes receiving a first layout of a first layer, the first layer including a first block, the first block including a first pin. The method further includes receiving a second layout of a second layer, the second layer including a second block, the second block including a second pin. The method further includes receiving a third layout of a third layer, the third layer coupled to the first layer and the second layer and positioned between the first layer and the second layer, the third layer including a first connection configured to couple the first pin to the second pin, the first pin and the second pin sharing the first connection. The method further includes identifying a first area that can be used to locate the first connection based on a first set of placement constraints. The method further includes identifying a second area that cannot be used to locate the first connection based on a second set of placement constraints. The method further includes determining a third area for locating the first connection based on at least the first area and the second area, the first layer and the second layer being aligned at the third area of ​​the first connection.

[0038] Embodiments may include one or more of the following features. The first layer further includes a third block, the first block being characterized by a first orientation, the third block being characterized by a second orientation, the first orientation being different from the second orientation. The third block includes a third pin, the third pin being configured to couple to a second connection of the third layer. The first pin shares a second connection with the third pin. The method further includes determining a fourth region for locating the second connection. The method further includes determining an association between the first connection and the second connection by mapping the third region and the fourth region onto a reference block. The method further includes determining a first pin configuration characterizing the first pin and the second pin based on the mapping of the third region and the fourth region onto the reference block. The first block includes a multi-instantiated block. The first set of placement constraints is associated with the first layout and the second layout and the third layout.

[0039] According to yet another embodiment, the subject technology provides a device that includes a first layer, the first layer including a first block, the first block including a first pin. The device further includes a second layer, the second layer including a second block, the second block including a second pin. The device further includes a third layer, the third layer coupled to the first layer and the second layer and positioned between the first layer and the second layer, the third layer including a first connection coupled to the first pin and the second pin and positioned between the first pin and the second pin. The first layer and the second layer are aligned at a first area of ​​the first connection, and the first area is determined by: identifying a second area that can be used to locate the first connection based on a first set of placement constraints; identifying a third area that cannot be used to locate the first connection based on a second set of placement constraints; and determining the third area based on at least the first area and the second area.

[0040] Embodiments may include one or more of the following features. The first block includes a multi-instantiated block. A distance between the first pin and the first connection is less than or equal to 30 um. The first connection includes a mixed copper bond. The first layer further includes a third block, the third block includes a third pin, and the third pin is configured to couple to a second connection of the third layer. The first connection is associated with the second connection.

[0041] Figure 1 1 is a simplified diagram illustrating a semiconductor device 100 having a 3D interconnect structure according to an embodiment of the subject technology. This figure is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. As shown, the semiconductor device 100 includes a substrate 102. The term "substrate" may refer to a circuit board on which an integrated circuit and other electrical connections are mounted. The substrate may provide a stable platform for the components, as well as the necessary electrical connections to enable them to interact and function as a complete system. For example, the substrate 102 provides the semiconductor device 100 with a connection to a printed circuit board (PCB) (not shown) to facilitate electrical communication and power transfer.

[0042] The semiconductor device 100 may further include an interposer 106 coupled to the substrate 102 via ball connections 104. The term "interposer" may refer to an intermediate substrate or layer utilized in a 2.5D or 3D IC circuit to facilitate electrical connections between stacked dies or between a die and a substrate (e.g., substrate 102). The interposer may include both silicon and organic materials. As an example, multiple circuits may be placed side-by-side on the interposer 106 to achieve better interconnect density and performance. Individual circuits may be bonded to the interposer 106 via ball connections 104. The term "ball connection" may refer to a solder ball connection, which is a small round solder joint that electrically and mechanically connects a component or substrate. For example, the ball connection 104 may be utilized in a ball grid array (BGA) configuration to attach the interposer 106 to the substrate 102.

[0043] In certain embodiments, semiconductor device 100 may be configured as a 3D stacked configuration and include a first die 114 and a second die 110 coupled via an interconnect 112. For example, the term "die" or "semiconductor die" may refer to a piece or section of semiconductor material (e.g., silicon) containing an integrated circuit system. Such an integrated circuit system may include various electronic components, such as transistors, capacitors, resistors, and other microelectronic structures, which together perform specific electronic functions. A die may include, but is not limited to, a processing unit, a memory array, a dedicated computing module, and / or the like.

[0044] In some embodiments, the first die 114 may be coupled to the second die 110. Thus, the first die 114 may also be referred to as the "top die" and the second die 110 may be referred to as the "bottom die". It should be understood that the terms "top" and "bottom" represent a relative positional relationship and are not intended to imply a strict vertical orientation. The interconnect 112 may include a hybrid copper bond, which may include a fusion of a copper-based material that facilitates electrical connection and thermal performance between semiconductor modules (e.g., the first die 114 and the second die 110). The hybrid copper bond may provide a robust circuit path while providing excellent heat dissipation characteristics in high-performance applications.

[0045] In a 3D stacked configuration, the second die 110 may be coupled to the interposer 106 via backside bumps 108. The term "backside bump" may refer to a protrusion on the back side of a semiconductor module (e.g., a circuit, a die, a chip module, etc.). Backside bumps may be used to connect stacked dies and facilitate dense and reliable interconnections. Backside bumps 108 may include, but are not limited to, controlled collapse chip connections (C4), copper pillar (CuP) connections, and / or the like. These structures enhance mechanical robustness and facilitate power and signal delivery across semiconductor devices.

[0046] Figure 22 is a simplified diagram illustrating a semiconductor device 200 with a 3D interconnect structure according to an embodiment of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions, and modifications.

[0047] As shown, the semiconductor device 200 may include a first circuit 220 and a second circuit 230. For example, the first circuit 220 includes a first block, the first block including a first pin 222. The term "pin" may refer to an electrical contact designed to connect a circuit to an external component or other circuit. The second circuit 230 includes a second pin 232. Pins such as the first pin 222 and the second pin 232 facilitate the transmission of signals or power between different layers or modules within the semiconductor device 200. In some embodiments, the layer 216 may be coupled to the first circuit 220 and the second circuit 230 and positioned between the first circuit 220 and the second circuit 230. The layer 216 may include, but is not limited to, a power grid strip, a metal layer, a conductive trace, a micro-wire, and / or the like. For example, the layer 216 includes a first connection 240, the first connection 240 is coupled to the first pin 222 and the second pin 232 and positioned between the first pin 222 and the second pin 232. The first pin 222 and the second pin 232 may share a first connection. In some embodiments, the distance between first pin 222 and first connection 240 may be less than or equal to 30 um. Depending on the implementation, first connection 240 includes a hybrid copper joint that may include a fusion of a copper-based material that facilitates electrical connection and thermal performance between first circuit 220 and second circuit 230.

[0048] In various embodiments, the first circuit 220 and the second circuit 230 can be aligned at the first area by the first connection 240. For example, the first circuit 220 includes a first HCB, and the second circuit 230 includes a second HCB. The first and second HCBs are aligned to form the first connection 240. This alignment is important for ensuring that signal integrity is maintained across the 3D IC stack, minimizing the possibility of signal loss or degradation. The placement of the first connection 240 can be determined based on a set of design strategies. For example, the term "design strategy" can guide a set of principles, methods and considerations for the layout and configuration of the integrated circuit. These strategies consider several considerations, such as space constraints, signal routing optimization, impedance minimization, thermal considerations and mechanical alignment tolerances. In some cases, the design strategy also adapts to the potential changes in the block orientation and position of the MIB to promote consistent connections.

[0049] In some examples, the set of design strategies may include a first set of placement constraints and a second set of placement constraints. The first set of placement constraints may be associated with an area that can be used to locate the first connection. The second set of placement constraints may be associated with an area that cannot be used to locate the first connection. The term "placement constraints" may refer to a set of predetermined rules that govern where components can be located within a semiconductor layout. The placement constraints may take into account various factors, such as electrical performance, manufacturability, thermal management, physical space requirements, and / or the like.

[0050] In various implementations, the second circuit 230 includes a layer 212 configured to be coupled to a first connection 240 to establish an electrical connection between the first circuit 220 and the second circuit 230. In some embodiments, the second circuit 230 further includes a transistor 210. The transistor 210 can be used to create logic gates and various digital circuits, which can be configured for various functional executions (e.g., signal processing, data calculations, etc.) and ensure efficient circuit operation. Depending on the implementation, the second circuit 230 may further include one or more metal layers 214 to establish interconnections between the transistor 210 and the layer 212 and / or among the various circuit elements of the second circuit 230, ensuring uninterrupted signal flow and power distribution. In an example, the metal layer 214 may be made of copper or aluminum and formed by a physical vapor deposition (PVD) process (e.g., sputtering or evaporation).

[0051] In various implementations, the first circuit 220 and the second circuit 230 can be stacked on an interposer 202 that is configured to facilitate stacked circuits (eg, the first circuit 220 and the second circuit 230) and a packaging substrate (eg, Figure 1 For example, the second circuit 230 can be coupled to the interposer 202 via an interconnect 204, which provides a robust physical connection and efficient electrical conduction. As examples, the interconnect 204 can include, but is not limited to, solder bumps, microbumps, controlled collapse chip connections (C4), copper pillar (CuP) connections, and / or the like.

[0052] Depending on the implementation, semiconductor 200 further includes a first through-hole 208. First through-hole 208 can be configured to connect one or more components of semiconductor device 200 for electrical communication and power delivery. For example, the term "through-hole" refers to a structure that facilitates vertical electrical connection between different layers or components within a semiconductor device. The first through-hole can include, but is not limited to, a through-silicon via, a blind via, a thermal via, a buried via, and / or the like. As an example, first through-hole 208 can include a through-silicon via.

[0053] In some cases, first via 208 can be coupled to grid 206 to receive power from interconnect 204 and transmit power to second circuit 230 and first circuit 220. For example, the term "grid" can refer to a system network of interconnect lines or tracks used as a conduit for distributing power, signals, or ground across a semiconductor device. The grid can be implemented in a variety of configurations, ranging from a regular structure with uniform spacing to a custom design tailored for specific wiring or power requirements. Grid 206 can include, but is not limited to, a power distribution grid, a clock grid, a ground grid, and / or the like.

[0054] Figure 3 3 is a simplified diagram illustrating the same die and cross-die connections within a semiconductor device 300 according to an embodiment of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions, and modifications.

[0055] As shown, semiconductor device 300 includes a first layer 302 and a second layer 304. For example, first layer 302 may be Figure 2 The first circuit 220 is a part of the second layer 304, and the second layer 304 may be Figure 2 The first layer 302 may be coupled to the second layer 304 to establish a die-to-die connection. In some embodiments, the first layer 302 includes a block 306a, which includes a pin 308a. Depending on the implementation, the block 306a may include a multi-instantiated block that is utilized across various instances of the first layer 302. For example, the block 306b is also a representation of the block 306a that is a different instantiation within the first layer 302. The block 306b may include a pin 308b. The use of the MIB provides scalability and reusability of design components within a semiconductor layout, enhances design efficiency, and reduces time to market for complex semiconductor devices.

[0056] In some examples, the first layer 302 further includes a block 310, which includes a pin 312 and a pin 314. The second block 310 may include a single instance block. Synchronization within the same die is important for maintaining signal integrity and facilitating coherent communication paths. For example, pin 308a shares connection 318 with pin 308b. The term "connection" may refer to the establishment of communication between two or more components in a semiconductor device. This may include direct or indirect electrical connections that enable signal, power, or data transfer between components. This shared connection allows replicated blocks within the same die to communicate and operate efficiently without signal degradation or delay. The same die coordination between these MIBs ensures that each instance can access the HCB without compromising the connection of other blocks or pins.

[0057] In some embodiments, pins associated with different blocks can be coordinated on the same die. For example, pin 308a shares connection 320 with pin 312. Pin 308b shares connection 314 with pin 314. Connections 320 and 322 can be established through HCBs, which enable signal communication across the z-axis between vertically stacked dies. HCBs provide physical interconnects that facilitate signal transmission between various layers of semiconductor devices, allowing multi-layer communication within a 3D IC structure.

[0058] In various embodiments, the second layer 304 includes a block 314a. The block 314a may include a multi-instantiated block utilized across various instances of the second layer 304. Blocks 314b, 314c, and 314d may be representations of the block 316a in different instantiations within the second layer 304. The block 314a may include a pin 316a. The block 314b may include a pin 316b. The block 314c may include a pin 316c. The block 314d may include a pin 316d. Similar to the blocks 308a and 308b of the first layer 302, each instance of the block 314a may share a connection to establish synchronization with the same die. For example, pins 316a and 316b may share a connection 328. Pins 316a and 316c may share a connection 330. Pins 316b and 316d may share a connection 332. Pins 316c and 316d may share a connection 334.

[0059] In some examples, cross-die synchronization is achieved through inter-layer connections to promote communication between dies. For example, pins 316a and 308b can share connection 324. Pins 316b and 308a can share connection 326. Pins 316d and 312 can share connection 336. Pins 316c and 314 can share connection 338. Cross-die synchronization allows seamless flow of signals across multiple layers of 3D IC, resulting in improvements in the overall speed and efficiency of semiconductor devices. In addition, this synchronization supports the functional and physical integration of MIB across different layers, thereby enhancing overall design scalability and efficiency. Same die synchronization and cross-die synchronization promote parallel design and layout of circuits, enhancing the overall function and efficiency of IC. It should be understood that optimizing die-to-die connections and HCB placement is important for ensuring such synchronization, enabling complex IC designs to meet the growing demand for higher performance and miniaturization in electronic devices.

[0060] Figure 4 4 is a simplified diagram illustrating a method for identifying available areas for die-to-die connections within a semiconductor device 400 according to an embodiment of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications.

[0061] In various implementations, the process of designing a 3D IC includes identifying available areas to place connections (e.g., pins and / or HCBs) that facilitate communication between different layers of the stack. The process involves analysis of the stacked die to ensure that the placement of the pins and HCBs complies with the placement constraints and maintains signal integrity across the semiconductor device 400. For example, pins may be grouped according to their related functions or signals. Subsequent analysis involves evaluating shared connections between these clusters both within a single die and across multiple dies in the semiconductor device 400. This evaluation is used to identify an "effective area" that accommodates the overlap of all involved pins, thus ensuring that their functions and physical interconnection are not hindered.

[0062] In some examples, the first layout of the first layer 402 may be analyzed to identify regions 414 and 416, which represent desired locations for pin placement. The intersection of regions 414 and 416 produces a valid same-die region 418. In other words, region 418 may represent an allowed area where pins and / or HCBs may be legally placed, avoiding areas with routability challenges due to existing structures. Similar identification of valid regions may occur on different layers for cross-die considerations, as shown by region 422 on the second layer 404. For example, region 422 may be identified by analyzing the second layout of the second layer 404. In some embodiments, regions 418 on the first layer 402 and regions 422 on the second layer 404 may be checked for overlapping areas where pins and / or HCBs may be placed. Therefore, the resulting valid region 424 may be identified as an available area for establishing die-to-die connections, ensuring proper alignment and functionality between stacked dies. By integrating considerations of available area on the same die with considerations of cross-die interactions, pin / HCB placement is optimized for inter-die communication while meeting the space and connection requirements of semiconductor device 400 .

[0063] Figure 5 5 is a simplified diagram illustrating a method for identifying unusable areas of die-to-die connections within a semiconductor device 500 according to an embodiment of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications.

[0064] In addition to identifying available areas for locating connections, the process of designing a 3D IC may also include identifying areas where connections cannot be placed due to the presence of existing structures or circuits within the semiconductor device 500 (e.g., which may be referred to as "blocking areas"). Identification of blocking areas helps avoid interference with signal integrity and conform to placement constraints of the semiconductor device 500. For example, pin placement may need to avoid areas occupied by instantiated intellectual property (IP) cells, TSVs, power grids, dummy areas, or areas designated for test structures (such as probe pads).

[0065] In some examples, the first layout of the first layer 502 can be analyzed to identify regions 514 and 516, which represent desired blocking regions based on a set of placement constraints. These placement constraints may include considerations such as the presence of other components, routing of wires, and / or any regions that should be avoided due to other design considerations. In some embodiments, regions 514 and 516 can be grouped together to produce an effective same-die blocking region 518. In other words, region 518 can represent an area on the same die where pins or HCBs should not be placed due to potential interference from existing structures. Similar identification of effective regions may occur on different layers for cross-die considerations, as shown by region 522 on the second layer 504. In various embodiments, region 518 on the first layer 502 and region 522 on the second layer 504 can be grouped together to reach region 524, which can be identified as a cross-die blocking region. By determining these blocking regions, the design and planning of pin and HCB placement can be performed more accurately, avoiding these regions to ensure effective and efficient die-to-die communication.

[0066] Figure 6 6 is a simplified diagram illustrating a method for determining areas for die-to-die connections within a semiconductor device 600 according to an embodiment of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications.

[0067] When identifying available areas for pin placement (e.g., area 608) and blocking areas to be avoided (e.g., area 620), area 612 on first layer 602 can be determined as the resulting effective pin area. Area 612 can represent the allowed area (real estate) on first layer 602 for establishing die-to-die connections. For example, area 612 can be determined by subtracting blocking areas 610 from the initial available area 608. The exclusion of blocking areas ensures that the remaining available area is optimized for die-to-die communication, facilitating efficient and effective operation of the 3D IC stack. It should be appreciated that the combined analysis of both the effective area and the blocking area allows for judicious selection of pin and HCB locations, enhancing the overall performance of the device by minimizing routing complexity and maintaining signal integrity across multiple layers of the semiconductor stack.

[0068] Figure 7 7 is a simplified diagram illustrating a method for determining HCB placement across multi-instantiated blocks within a semiconductor device 700 according to an embodiment of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications.

[0069] In various embodiments, semiconductor device 700 may include one or more MIBs 702, 704, 706, and 708. Depending on the embodiment, these blocks may be examples of the same functional unit or various functional units that require interconnection within semiconductor device 700. In some examples, each block may be coupled to one or more HCBs. For example, block 702 may be coupled to HCB 712. Block 704 may be coupled to HCB 714. Block 706 may be coupled to HCB 716. Block 708 may be coupled to HCB 718. For each example, the projection of the wiring footprint of the corresponding HCB - the path through which the HCB connects different layers - may change. This change is related to the instantiation of each block, considering the different positions and orientations that the block may have in the overall design. For example, block 702 may be characterized by a first orientation, and block 704 may be characterized by a second orientation. The first orientation may be different from the second orientation. It should be understood that although the position of the HCB instantiated by each block is different, the orientation of the HCB wiring footprint remains consistent across different examples of the block.

[0070] In some embodiments, to manage the complexity of different HCB locations, all HCBs (e.g., HCBs 712, 714, 716, and 718) and their associated routing footprints are mapped onto a reference block 710. The reference block 710 can be used as a standard layout from which the placement of all blocks can be compared and aligned. This mapping helps visualize and plan the connections between HCBs within the complex 3D structure of the semiconductor device 700. Depending on the implementation, HCBs that are adjacent or close to each other across different block instances can be associated with each other and assigned to the same signal. This ensures that signals are efficiently routed and can communicate between different blocks within the semiconductor device 700.

[0071] Figure 8 800 is a simplified diagram illustrating a method for determining pin placement across multiple instantiation blocks within a semiconductor device 800 according to an embodiment of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications.

[0072] The efficiency of pin placement is an important consideration in semiconductor design. As shown, semiconductor device 800 includes one or more pins (e.g., pins 802 and 804). Each pin can be connected to one or more HCBs (e.g., HCB806, 808, 810, and 812). These connections ensure the integrity of the signal path across each layer and functional block of the device. In various embodiments, the pin configuration must comply with the design rule check (DRC) standard to ensure manufacturability and functional reliability. In addition, the pin must be of sufficient size to interface with each associated HCB to maintain the integrity and reliability of the electrical connection. Minimizing the pin footprint while meeting the necessary requirements allows for more efficient use of the available space in the semiconductor device. This is particularly beneficial as the device architecture becomes more and more compact and dense due to its functions. It enhances the ability to integrate, achieves a larger number of connections per unit area, and contributes to the overall performance and scalability of semiconductor technology.

[0073] In order to identify the minimized pin footprint, an analysis may be performed on the available pins and their overlap with all HCBs. For example, pins 802 and 804 may be analyzed, where their respective overlap with each HCB (e.g., HCBs 806, 808, 810, and 812) may be calculated and compared. For example, pin 804 may only be able to connect to HCBs 810 and 812, while pin 802 may be connected to all four HCBs. Thus, area 816 may be determined as the minimum pin footprint required to establish connections with all associated HCBs. By constraining the pin footprint to its minimum necessary size, the design allows for more dense packaging of functional components, enhancing the overall capabilities and performance of the semiconductor device. In addition, such minimization may result in improved signal routing with reduced parasitic effects, thereby improving overall electrical performance within semiconductor device 800 and achieving higher operating speeds.

[0074] Fig. 9 9 is a simplified flow chart illustrating a method 900 for determining die-to-die connections within a semiconductor device according to an embodiment of the subject technology. This figure is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. For example, one or more steps may be added, removed, repeated, modified, replaced, overlapped, and / or rearranged, and should not limit the scope of the claims.

[0075] At step 902, a first layout of a first layer is received. For example, the first layer may be a portion of a semiconductor die. The first layout may be a design plan or blueprint detailing placement of components on the first layer. In some examples, the first layer may include a first block. The first block may include a first pin. Depending on the implementation, the first block may include a multi-instantiated block or a single instance block.

[0076] At step 904, a second layout of a second layer is received. For example, the second layer may be a portion of a semiconductor die. The second layout may be a design plan or blueprint detailing the placement of components on the second layer. In some examples, the second layer may include a second block. The second block may include a second pin. Depending on the implementation, the second block may include a multi-instantiated block or a single instance block. In some embodiments, the first pin shares a first connection with the second pin.

[0077] At step 906, a third layout of a third layer is received. In some implementations, the third layer is coupled to the first layer and the second layer and positioned between the first layer and the second layer. The third layer may include a first connection coupled to the first pin and the second pin and positioned between the first pin and the second pin. For example, the first connection includes a hybrid copper bond, which may include a fusion of a copper-based material that facilitates electrical connection and thermal performance between the first layer and the second layer.

[0078] At step 908, a first area that can be used to locate a first connection is identified based on a first set of placement constraints. The first set of placement constraints can be associated with the first layout and the second layout and the third layout. For example, these constraints can include allowable distances for signal integrity, heat dissipation requirements, maximum connection density per unit area, and / or other design considerations. The process may involve considerations of available area on the same die and considerations across dies to ensure that the placement of pins and HCBs meets the placement constraints.

[0079] At step 910, a second area that is not available for positioning the first connection is identified based on a second set of placement constraints. The second set of placement constraints may be associated with the first layout and the second layout and the third layout. For example, pin placement may need to avoid areas occupied by instantiated intellectual property (IP) cells, TSVs, power grids, dummy areas, or areas designated for test structures (such as probe pads). Identification of blocking areas helps avoid interference with signal integrity and meets placement constraints of semiconductor devices.

[0080] At step 912, a third area for locating the first connection is determined based on at least the first area and the second area. The first layer and the second layer can be aligned at the third area by the first connection. For example, the third area can be determined by subtracting the second area from the first area. Exclusion of the second area ensures that the remaining available area is optimized for die-to-die communication, facilitating efficient and effective operation of the 3D IC stack.

[0081] In various embodiments, the first layer may further include a third block. The first block may be characterized by a first orientation. The third block may be characterized by a second orientation. The first orientation may be different from the second orientation. In some examples, the third block includes a third pin. The third pin may be configured to couple to a second connection of the third layer. The first pin and the third pin may share a second connection.

[0082] According to some embodiments, method 900 may further include determining a fourth region for locating the second connection, and determining an association between the first connection and the second connection by mapping the third region and the fourth region onto a reference block. In order to minimize the pin footprint, method 900 may further include determining a first pin configuration characterizing the first pin and the second pin based on the mapping of the third region and the fourth region onto the reference block.

[0083] While the above is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the subject technology as defined by the appended claims.

Claims

1. A device comprising: A first layer, which includes a first block, the The first block includes a first pin; a second layer including a second block, wherein the second block includes a second pin; and a third layer coupled to the first layer and the second layer and positioned between the first layer and the second layer, the third layer comprising a first connection coupled to the first pin and the second pin and positioned between the first pin and the second pin, the first pin and the second pin sharing the first connection; The first layer is aligned with the second layer at a first region of the first connection based on a set of design strategies.

2. The apparatus of claim 1, wherein the first connection comprises a hybrid copper bond. 3 . The device of claim 1 , wherein a distance between the first pin and the first connection is less than or equal to 30 um. The apparatus of claim 1 , wherein the first block comprises a multiply instantiated block.

5. The device according to claim 1, wherein: The set of design strategies includes a first set of placement constraints and a second set of placement constraints; The first set of placement constraints is associated with a second area that can be used to locate the first connection; and The second set of placement constraints is associated with a third region that is not usable for positioning the first connection. The device of claim 5 , wherein the first area is determined based on at least the second area and the third area. 7 . The apparatus of claim 1 , wherein the first layer further comprises a third block, the third block comprising a third pin, the first pin sharing a second connection with the third pin.

8. A method comprising: receiving a first layout of a first layer, the first layer comprising a first block, the first block comprising a first pin; receiving a second layout of a second layer, the second layer including a second block, the second block including a second pin; receiving a third layout of a third layer coupled to the first layer and the second layer and positioned between the first layer and the second layer, the third layer including a first connection configured to couple the first pin to the second pin, the first pin sharing a first connection with the second pin; identifying a first area usable for positioning the first connection based on a first set of placement constraints; identifying a second area that is not available for positioning the first connection based on a second set of placement constraints; and A third area for positioning the first connection is determined based at least on the first area and the second area, and the first layer is aligned with the second layer at the third area of ​​the first connection.

9. The method according to claim 8, wherein: The first layer further includes a third mass, the first mass being characterized by a first orientation, the third mass being characterized by a second orientation, the first orientation being different than the second orientation; and The third block includes a third pin configured to couple to a second connection of the third layer.

10. The method of claim 9, wherein the first pin shares a second connection with the third pin.

11. The method according to claim 9, further comprising: determining a fourth area for locating the second connection; and An association between the first connection and the second connection is determined by mapping the third region and the fourth region onto a reference block. 12 . The method of claim 11 , further comprising determining a first pin configuration characterizing the first pin and the second pin based on the mapping of the third area and the fourth area on the reference block. The method of claim 8 , wherein the first block comprises a multiply instantiated block. The method of claim 8 , wherein the first set of placement constraints is associated with the first layout and the second layout and the third layout.

15. An apparatus comprising: A first layer, which includes a first block, the The first block includes a first pin; a second layer including a second block, wherein the second block includes a second pin; and a third layer coupled to the first layer and the second layer and positioned between the first layer and the second layer, the third layer comprising a first connection coupled to the first pin and the second pin and positioned between the first pin and the second pin; wherein the first layer is aligned with the second layer at a first region of the first connection, and the first region is determined by: identifying a second area usable for positioning the first connection based on the first set of placement constraints; identifying, based on the second set of placement constraints, a third area that is not available for positioning the first connection; and The third area is determined based on at least the first area and the second area. The apparatus of claim 15 , wherein the first block comprises a multiply instantiated block.

17. The apparatus of claim 15, wherein a distance between the first pin and the first connection is less than or equal to 30 um.

18. The apparatus of claim 15, wherein the first connection comprises a hybrid copper bond.

19. The device of claim 15, wherein the first layer further comprises a third block, the third block comprising a third pin, and the third pin is configured to couple to a second connection of the third layer.

20. The apparatus of claim 19, wherein the first connection is associated with the second connection.

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