Alternating current B code design method based on FPGA pulse width modulation

Abstract

The invention discloses an alternating current B code design method based on FPGA pulse width modulation, and relates to the technical field of industrial vehicle control, and the method comprises the steps: S1, monitoring the voltage of a power grid in real time based on a voltage detection circuit, and feeding back the voltage to an FPGA; s2, dynamically adjusting the frequency and the duty ratio of the PWM signal according to the monitored power grid voltage value; s3, an accurate PWM signal is generated through the FPGA and used for controlling an inverter; s4, smoothing the alternating current signal output by the inverter through a filter circuit; s5, synchronizing the AC signal after smoothing processing with a standard B code, generating a final AC B code and outputting the AC B code; according to the AC B code design method based on FPGA pulse width modulation, the problem that modulation precision is reduced due to unstable power supply when power grid voltage fluctuation is large in the prior art is solved.

Description

Technical Field

[0001] The invention relates to the technical field of industrial vehicle control, and in particular to an AC B code design method based on FPGA pulse width modulation. Background Art

[0002] Forklift is a commonly used material handling equipment, widely used in warehousing, logistics, manufacturing and other fields. With the continuous development of industrial automation, electric forklifts have been widely used due to their green, environmentally friendly, high efficiency and energy saving characteristics. The power system of electric forklifts is usually driven by motors, and its power supply depends on the power grid or batteries. However, in actual use, the power grid power supply system may experience large voltage fluctuations due to load fluctuations, equipment failures and other reasons.

[0003] Grid voltage fluctuations have a great impact on the operating performance of electric forklifts. Especially in modulation control systems, modulation accuracy plays a key role in the smoothness and energy efficiency of motor drives. When the power supply of the grid is unstable, the input voltage of the modulation control system may fluctuate greatly, resulting in a decrease in modulation accuracy. This problem may manifest itself in the following points: System response delay: Due to frequent voltage fluctuations, the system needs to be constantly adjusted to maintain the set working state, which increases the delay of the control system; Motor output fluctuations: The decrease in modulation accuracy will directly lead to torque fluctuations in the motor, thereby affecting the smoothness and controllability of the forklift; Reduced energy efficiency: Unstable modulation causes the motor to work in a non-optimal state, increasing energy loss; Increased equipment loss: Long-term voltage fluctuations will shorten the life of motors, batteries and other electrical components, and increase maintenance costs; Although the existing technology alleviates grid fluctuations by adding voltage stabilizers or increasing the response speed of the control system, these methods have the problems of high cost and poor adaptability. Summary of the invention

[0004] The purpose of the present invention is to provide an AC B code design method based on FPGA pulse width modulation to solve the problem of reduced modulation accuracy caused by unstable power supply when the grid voltage fluctuates greatly in the prior art.

[0005] To achieve the above object, the present invention provides the following technical solution: an AC B code design method based on FPGA pulse width modulation, the method comprising:

[0006] S1, monitor the grid voltage in real time based on the voltage detection circuit and feed it back to the FPGA;

[0007] S2, dynamically adjusting the frequency and duty cycle of the PWM signal according to the monitored grid voltage value;

[0008] S3, using FPGA to generate accurate PWM signals for controlling the inverter;

[0009] S4. Smooth the AC signal output by the inverter through the filtering circuit. Specifically, decompose the signal output by the inverter into effective signal components and noise components, describe the dynamic interaction process between the signal and the noise, simulate its time evolution law in the FPGA, implement attenuation control on the noise component, amplify the effective signal component, generate a smoothed AC signal, and describe the dynamic interaction process between the signal and the noise. The specific formula is:

[0010] Wherein, x represents the effective signal component in the inverter output signal, y represents the noise component in the inverter output signal, α represents the natural growth coefficient of the effective signal component x, β represents the weakening effect coefficient of the noise component y on the effective signal x, δ represents the suppression effect coefficient of the effective signal x on the noise component y, γ represents the natural attenuation coefficient of the noise component y, and t represents time;

[0011] S5. Synchronize the smoothed AC signal with the standard B code to generate a final AC B code output.

[0012] Preferably, the voltage detection circuit in S1 includes:

[0013] A voltage sampling module is used to sample the AC voltage signal of the power grid in real time and convert it into an analog electrical signal;

[0014] an analog-to-digital converter, connected to the voltage sampling module, and used to convert an analog electrical signal into a digital electrical signal;

[0015] Low-pass filter, used to filter out noise from digital electrical signals and output stable digital signals;

[0016] The voltage detection control module is implemented based on FPGA and is used to receive the signal output by the low-pass filter and monitor the voltage changes in real time.

[0017] Preferably, S2 includes:

[0018] Predict the voltage fluctuation range based on the voltage change trend;

[0019] Adjust the frequency and duty cycle of the PWM signal to adapt to the voltage fluctuation range;

[0020] Add PID controller to improve modulation accuracy;

[0021] The backup power source is activated when the voltage fluctuation exceeds the preset threshold.

[0022] Preferably, predicting the voltage fluctuation range according to the voltage variation trend includes:

[0023] Collect grid voltage data within a certain period of time;

[0024] Using the formula ΔV=|Vn -V n－1 |Determine whether the change amount between adjacent voltage sampling points exceeds the threshold T1, where ΔV represents the voltage change amount, V n represents the current sampled voltage value, and V n－1 represents the previous sampled voltage value; adjust the fluctuation range according to the result of ΔV>T1.

[0025] Preferably, further refine the ΔV = |V n -V n－1 |, including:

[0026] Calculate the average value of multiple voltage change amounts through a sliding window;

[0027] Use the formula where N is the window length, and ΔV i is the voltage change amount of the i-th sampling;

[0028] Determine whether ΔV avg exceeds the threshold T2;

[0029] Adjust the frequency and duty cycle of the PWM signal according to the result of ΔV avg >T2.

[0030] Preferably, the determination of whether ΔV avg exceeds the threshold T2 includes:

[0031] Define an accumulation factor C and initialize it to 0;

[0032] When ΔV avg >T2, C = C + 1, and when ΔV avg <T2, C = 1;

[0033] Determine whether the accumulation factor C exceeds the threshold T3;

[0034] If C>T3, start the backup power supply, otherwise continue to monitor.

[0035] Preferably, the determination of whether the accumulation factor C exceeds the threshold T3 further includes:

[0036] When C>T3, record the current timestamp t1;

[0037] The next time C>T3, calculate the time difference Δt = t2 - t1, where t2 is the newly recorded timestamp;

[0038] Determine whether Δt exceeds the threshold T4;

[0039] If Δt>T4, then start the backup power supply, otherwise continue to monitor.

[0040] Preferably, the determining whether Δt exceeds a threshold value T4 includes:

[0041] Record a start mark S each time the backup power supply is started;

[0042] After each voltage fluctuation, the start flag S is cleared;

[0043] Start the backup power supply when Δt>T4 and S is false;

[0044] If S is true, the backup power supply is not started and the value of the accumulation factor C is increased.

[0045] Preferably, S3 includes:

[0046] The duty cycle of the PWM signal is dynamically calculated using the following formula: D = V in / V ref ;

[0047] Where D represents the duty cycle, V in is the real-time monitored grid voltage value, V ref Indicates the target reference voltage value.

[0048] Preferably, S5 includes:

[0049] By detecting the phase difference Δφ between the smoothed signal and the standard B-code signal, the phase is adjusted according to the following formula:

[0050] φ new =φ lod +K·Δφ;

[0051] Among them, φ new is the adjusted phase, φ old is the current phase, K is the phase adjustment coefficient, and Δφ represents the phase difference between the smoothed signal and the standard B code signal.

[0052] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0053] The AC B code design method based on FPGA pulse width modulation monitors the grid voltage in real time based on a voltage detection circuit and feeds it back to the FPGA, dynamically adjusts the frequency and duty cycle of the PWM signal according to the monitored grid voltage value, uses the FPGA to generate an accurate PWM signal for controlling the inverter, smoothes the AC signal output by the inverter through a filter circuit, synchronizes the smoothed AC signal with the standard B code, and generates a final AC B code output, which significantly reduces the system delay caused by voltage fluctuations, ensures that the forklift control system can quickly respond to external power supply fluctuations, improves the operating efficiency, significantly improves the stability and controllability of the electric forklift during operation, adapts to complex working environment requirements, effectively reduces energy loss, improves the overall energy efficiency of the electric forklift, saves energy costs, extends the service life of key equipment, reduces maintenance frequency and costs, reduces system transformation costs, has higher adaptability and economy, can be widely applied to the actual application needs of electric forklifts in various industrial scenarios, and solves the problem of reduced modulation accuracy caused by unstable power supply when the grid voltage fluctuates greatly in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 The figure is a flow chart of the method of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] like Figure 1 As shown, the present invention provides a technical solution: an AC B code design method based on FPGA pulse width modulation, the method comprising:

[0057] S1, monitor the grid voltage in real time based on the voltage detection circuit and feed it back to the FPGA;

[0058] S2, dynamically adjusting the frequency and duty cycle of the PWM signal according to the monitored grid voltage value;

[0059] S3, using FPGA to generate accurate PWM signals for controlling the inverter;

[0060] S4. Smooth the AC signal output by the inverter through the filtering circuit. Specifically, decompose the signal output by the inverter into effective signal components and noise components, describe the dynamic interaction process between the signal and the noise, simulate its time evolution law in the FPGA, implement attenuation control on the noise component, amplify the effective signal component, generate a smoothed AC signal, and describe the dynamic interaction process between the signal and the noise. The specific formula is:

[0061] Wherein, x represents the effective signal component in the inverter output signal, y represents the noise component in the inverter output signal, α represents the natural growth coefficient of the effective signal component x, β represents the weakening effect coefficient of the noise component y on the effective signal x, δ represents the suppression effect coefficient of the effective signal x on the noise component y, γ represents the natural attenuation coefficient of the noise component y, and t represents time;

[0062] S5. Synchronize the smoothed AC signal with the standard B code to generate a final AC B code output.

[0063] The above implementation method realizes real-time monitoring and feedback control of the grid voltage through the high-performance computing capability of FPGA. The first step is to monitor the grid voltage fluctuation through the voltage detection circuit and transmit the data to the FPGA module in real time. In the second step, the FPGA dynamically adjusts the frequency and duty cycle of the PWM signal according to the detected grid voltage changes to ensure that the AC signal output by the inverter is consistent with the target signal. In the third step, the FPGA generates a high-precision PWM signal to drive the inverter to work, thereby converting the DC signal into an AC signal. The fourth step is to optimize the inverter output signal through the filtering circuit, separate the effective signal component and the noise component using a dynamic interaction model, and combine the FPGA algorithm to attenuate the noise component, while enhancing the effective signal component, and finally output a smooth AC signal. The last step is to synchronize the optimized AC signal with the standard B code to generate a qualified AC B code signal. Through real-time voltage monitoring and PWM modulation, the system's dynamic response capability is improved and it can effectively adapt to grid fluctuations. An equation-based dynamic noise control model is adopted to effectively suppress noise signals and improve signal quality. By utilizing the parallel computing capability of FPGA, the processing speed and accuracy of the entire system are improved. The final output AC B-code signal has higher smoothness and reliability, meeting the application requirements in the communication and control fields.

[0064] The voltage detection circuit in S1 includes a voltage sampling module, which is used to sample the AC voltage signal of the power grid in real time and convert it into an analog electrical signal; an analog-to-digital converter, which is connected to the voltage sampling module and is used to convert the analog electrical signal into a digital electrical signal; a low-pass filter, which is used to filter the noise of the digital electrical signal and output a stable digital signal; and a voltage detection control module, which is implemented based on FPGA and is used to receive the signal output by the low-pass filter and monitor the voltage change in real time.

[0065] In the embodiment, the voltage detection circuit is a key component of the entire system, which is used to realize real-time monitoring of the grid voltage. First, the voltage sampling module extracts the AC voltage signal from the grid, uses a voltage divider circuit or a voltage transformer to adjust the signal to a suitable input range, and converts it into an analog electrical signal. Then, the analog-to-digital converter digitizes the analog electrical signal and converts the continuous analog signal into a discrete digital signal, thereby facilitating subsequent digital signal processing. Subsequently, the low-pass filter processes the digital signal, filters out the high-frequency noise components therein, and outputs a stable digital signal to ensure the stability and reliability of the signal. Finally, the voltage detection control module is implemented based on FPGA, receives the filtered signal, and monitors and analyzes the changes in the grid voltage in real time through an internal logic algorithm, providing a high-precision real-time voltage reference for subsequent PWM signal modulation. The voltage sampling module can perform high-frequency real-time sampling of the grid voltage signal to ensure a rapid response to grid fluctuations; the analog-to-digital converter accurately converts the analog signal into a digital signal, and combines it with a low-pass filter to effectively remove noise to ensure signal accuracy and stability; the voltage detection control module is based on FPGA and has powerful parallel processing capabilities. It can quickly process multiple input signals and output voltage change data in real time; the introduction of the low-pass filter enhances the system's ability to suppress noise and improves the system's robustness in complex electromagnetic environments; by clarifying the functional division of each module, it facilitates system maintenance, upgrades, and adjustments to different application scenarios.

[0066] S2 includes predicting the voltage fluctuation range according to the voltage change trend; adjusting the frequency and duty cycle of the PWM signal to adapt to the voltage fluctuation range; adding a PID controller to improve the modulation accuracy; and starting the backup power supply when the voltage fluctuation exceeds a preset threshold.

[0067] This embodiment dynamically adjusts the frequency and duty cycle of the PWM signal to adapt to grid voltage fluctuations and improve modulation accuracy. The FPGA continuously collects grid voltage data through the voltage detection control module, and uses a time series analysis method to predict the voltage change trend, such as determining the voltage fluctuation range in the short term based on a moving average or exponentially weighted average algorithm. Through the analysis of the voltage change trend, the PWM parameters are adjusted in advance to reduce the impact of voltage mutations on the output signal quality. Based on the predicted voltage fluctuation range, the frequency and duty cycle of the PWM signal are adjusted accordingly. For example, when the grid voltage decreases, the PWM duty cycle is appropriately increased to compensate for the output voltage; when the grid voltage increases, the PWM duty cycle is reduced to maintain a stable output. The frequency adjustment is achieved by changing the division coefficient of the clock division module inside the FPGA to optimize the operating frequency of the inverter and synchronize the output signal with the target signal. The PID (proportional-integral-differential) controller is embedded in the control logic of the FPGA to adjust the PWM signal in real time. The PID controller receives the deviation between the target voltage and the actual output voltage, and uses the feedback control principle to quickly adjust the PWM parameters to improve the modulation accuracy and dynamic response performance of the system. The proportional term (P) is used to quickly respond to voltage changes, the integral term (I) eliminates steady-state errors, and the differential term (D) suppresses fluctuations. The three work together to optimize the quality of the output signal. When the FPGA detects that the grid voltage fluctuation exceeds the preset threshold (such as a voltage sag or swell exceeding ±10%), the backup power startup logic will be automatically triggered. The backup power supply can be a battery pack, an uninterruptible power supply (UPS) or other power supply system to ensure that the continuity and stability of the output signal can be maintained when the grid fails. Based on the prediction function of the voltage change trend, the PWM parameters are adjusted in advance to reduce the impact of voltage fluctuations on the system output signal; the frequency and duty cycle of the PWM signal are dynamically adjusted to improve the system's real-time response capability to voltage fluctuations; the introduction of the PID controller significantly improves the modulation accuracy of the system and ensures the smoothness and stability of the signal; when the voltage fluctuation exceeds the preset range, the timely startup of the backup power supply ensures the continuity and reliability of the system output; through the precise control of PWM parameters and the introduction of the backup power supply mechanism, this design is suitable for stable AC signal output in complex grid environments.

[0068] Predicting the voltage fluctuation range based on the voltage change trend includes collecting grid voltage value data within a certain period of time; using the formula ΔV=|V n -V n－1 |Judge whether the change between two adjacent voltage sampling points exceeds the threshold T1, where ΔV represents the voltage change, V n Indicates the current sampling voltage value, V n－1Represents the previous sampled voltage value; adjust the fluctuation range according to the result of ΔV>T1. It can calculate the voltage change amount in a timely manner based on the sampled data and adjust the fluctuation range, improving the response speed to grid fluctuations. Dynamically adjust the PWM parameter range according to the voltage change trend, enhancing the adaptability of the system in a complex grid environment. Setting the threshold T1 can effectively filter out small fluctuation signals and avoid negative impacts on system performance. By optimizing the adjustment logic of the voltage fluctuation range, the smoothness and stability of PWM modulation are enhanced, and the quality of the finally output AC B-code signal is higher.

[0069] ΔV = |V n -V n－1 | is further refined, including calculating the average value of multiple voltage change amounts through a sliding window; using the formula where N is the window length, and ΔV i is the voltage change amount of the i-th sampling; judge whether ΔV avg exceeds the threshold T2; adjust the frequency and duty cycle of the PWM signal according to the result of ΔV avg >T2.

[0070] It can effectively suppress the influence of single-point sampling error or noise on fluctuation detection, improving the reliability of the system. By calculating the average change amount of voltage fluctuation in real time, the system can more accurately capture the fluctuation trend of the grid voltage, enhancing the control accuracy of PWM parameter adjustment. The threshold T2 can be adjusted according to the grid characteristics, enabling the system to adapt to different fluctuation environments and avoiding unnecessary responses to small fluctuations. By dynamically adjusting the PWM signal, it ensures that the output AC signal remains stable and smooth in a severely fluctuating environment.

[0071] Judging whether ΔV avg exceeds the threshold T2 includes defining an accumulation factor C, initialized to 0; when ΔV avg >T2, C = C + 1, when ΔV avg <T2, C = 1; judge whether the accumulation factor C exceeds the threshold T3; if C>T3, start the backup power supply, otherwise continue to monitor.

[0072] Using the accumulation factor to record the duration of fluctuations, avoiding misoperations caused by short-term interference or instantaneous fluctuations, and improving the stability of the system. Combining the double-condition judgments of ΔV avg >T2 and C>T3, only start the backup power supply when the voltage fluctuation lasts for a long time and may affect the output, optimizing the use efficiency of the backup power supply. Through the accumulation factor update logic, it is quickly reset when the fluctuation returns to normal, reducing the sensitivity to single fluctuations, while maintaining a high response ability during continuous fluctuations. When the voltage fluctuates violently and cannot recover for a long time, it switches to the backup power supply in a timely manner, ensuring the smoothness and reliability of the system output signal.

[0073] Judging whether the cumulative factor C exceeds the threshold value T3 also includes recording the current timestamp t1 when C>T3; the next time C>T3, calculating the time difference Δt=t2-t1, where t2 is the timestamp of the new record; judging whether Δt exceeds the threshold value T4; if Δt>T4, starting the backup power supply, otherwise continue monitoring. The independence of fluctuations is determined by the time difference Δt, which avoids frequent switching of the backup power supply caused by continuous fluctuations in a short period of time, thereby improving the operating stability of the system. The time difference judgment mechanism can distinguish whether different fluctuation events are related, thereby improving the accuracy of the backup power supply startup, and starting the backup power supply only when the dual conditions of the time difference and the cumulative factor are met, reducing the risk of excessive use of the backup power supply. Combined with the time difference and threshold judgment mechanism, the system can still effectively cope with a variety of fluctuation scenarios even in a complex power grid environment to ensure the high quality of the output signal.

[0074] Determining whether Δt exceeds the threshold value T4 includes recording a start-up flag S each time the backup power supply is started; clearing the start-up flag S after each voltage fluctuation ends; starting the backup power supply when Δt>T4 and S is false; if S is true, the backup power supply is not started, and the value of the cumulative factor C is increased. By recording the start-up flag S, the system can determine whether the backup power supply is already in operation, avoid triggering multiple start-up operations due to repeated fluctuations, and reduce equipment losses. During the operation of the backup power supply, the dynamic update of the cumulative factor C can accurately reflect the intensity and duration of continuous fluctuations, provide data support for subsequent recovery judgments or optimization strategies, and start the backup power supply only when the necessary conditions are met, reduce the frequency of excessive use of the backup power supply, and improve the overall operation efficiency and reliability of the system. By controlling the start-up and switching logic of the backup power supply, it is ensured that the system output signal remains stable and reliable in the case of frequent power grid fluctuations.

[0075] S3 includes the duty cycle of the PWM signal dynamically calculated by the following formula: D = V in / V ref ; Where D represents the duty cycle, V in is the real-time monitored grid voltage value, V ref Indicates the target reference voltage value. The duty cycle is calculated from the voltage value monitored in real time, which can quickly respond to grid voltage fluctuations and ensure the stability of the output signal. When the grid voltage changes, the duty cycle D will be automatically adjusted, which enhances the dynamic adaptability of the system. By adjusting the duty cycle, the inverter output voltage is always close to the target reference voltage V ref , improves the quality and reliability of the output signal, the formula is simple, and the calculation logic is suitable for FPGA implementation, which can meet the needs of real-time control while saving hardware resources.

[0076] S5 includes detecting the phase difference Δφ between the smoothed signal and the standard B code signal, and adjusting the phase according to the following formula:new =φ old +K·Δφ; where φ new is the adjusted phase, φ old is the current phase, K is the phase adjustment coefficient, and Δφ represents the phase difference between the smoothed signal and the standard B code signal.

[0077] By detecting the phase difference in real time and adjusting it dynamically, the smoothed signal is ensured to always remain synchronized with the standard B-code signal, eliminating the error caused by signal asynchrony. The adjustment formula is simple and suitable for the FPGA parallel processing architecture. It can quickly complete the phase adjustment and meet the needs of real-time control. By adjusting the proportional coefficient K, the sensitivity and stability of the phase adjustment can be optimized according to different application scenarios. The formula logic is simple, easy to implement on the FPGA, occupies less hardware resources, and has good engineering practicality.

[0078] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for designing AC B code based on FPGA pulse width modulation, characterized in that: The method comprises: S1, monitor the grid voltage in real time based on the voltage detection circuit and feed it back to the FPGA; S2, dynamically adjusting the frequency and duty cycle of the PWM signal according to the monitored grid voltage value; S3, using FPGA to generate accurate PWM signals for controlling the inverter; S4. Smooth the AC signal output by the inverter through the filtering circuit. Specifically, decompose the signal output by the inverter into effective signal components and noise components, describe the dynamic interaction process between the signal and the noise, simulate its time evolution law in the FPGA, implement attenuation control on the noise component, amplify the effective signal component, generate a smoothed AC signal, and describe the dynamic interaction process between the signal and the noise. The specific formula is: Wherein, x represents the effective signal component in the inverter output signal, y represents the noise component in the inverter output signal, α represents the natural growth coefficient of the effective signal component x, β represents the weakening effect coefficient of the noise component y on the effective signal x, δ represents the suppression effect coefficient of the effective signal x on the noise component y, γ represents the natural attenuation coefficient of the noise component y, and t represents time; S5. Synchronize the smoothed AC signal with the standard B code to generate a final AC B code output.

2. The method for designing an AC B code based on FPGA pulse width modulation according to claim 1, characterized in that: The voltage detection circuit in S1 includes: A voltage sampling module is used to sample the AC voltage signal of the power grid in real time and convert it into an analog electrical signal; an analog-to-digital converter, connected to the voltage sampling module, and used to convert an analog electrical signal into a digital electrical signal; Low-pass filter, used to filter out noise from digital electrical signals and output stable digital signals; The voltage detection control module is implemented based on FPGA and is used to receive the signal output by the low-pass filter and monitor the voltage changes in real time.

3. The AC B code design method based on FPGA pulse width modulation according to claim 1, characterized in that: The S2 includes: Predict the voltage fluctuation range based on the voltage change trend; Adjust the frequency and duty cycle of the PWM signal to adapt to the voltage fluctuation range; Add PID controller to improve modulation accuracy; The backup power source is activated when the voltage fluctuation exceeds the preset threshold.

4. The method for designing an AC B code based on FPGA pulse width modulation according to claim 3, characterized in that: Predicting the voltage fluctuation range according to the voltage variation trend includes: Collect grid voltage data within a certain period of time; Using the formula ΔV=|V n -V n－1 |Judge whether the change between two adjacent voltage sampling points exceeds the threshold T1, where ΔV represents the voltage change, V n Indicates the current sampling voltage value, V n－1 Indicates the previous sampling voltage value; adjust the fluctuation range according to the result of ΔV>T1.

5. The method for designing an AC B code based on FPGA pulse width modulation according to claim 4, characterized in that: The ΔV=|V n -V n－1 | Further refinement, including: Calculate the average value of multiple voltage changes through a sliding window; Using the formula Where N is the window length, ΔV i is the voltage change of the i-th sampling; Determine ΔV avg Whether it exceeds the threshold T2; According to ΔV avg >The result of T2 adjusts the frequency and duty cycle of the PWM signal.

6. The method for designing an AC B code based on FPGA pulse width modulation according to claim 5, characterized in that: The determination ΔV avg Whether the threshold T2 is exceeded includes: Define a cumulative factor C and initialize it to 0; When ΔV avg > T2, C = C + 1. When ΔV avg < T2, C = 1; Determine whether the cumulative factor C exceeds a threshold value T3; If C>T3, start the backup power supply, otherwise continue monitoring.

7. The method for designing an AC B code based on FPGA pulse width modulation according to claim 6, characterized in that: The step of determining whether the cumulative factor C exceeds the threshold value T3 further includes: When C>T3, record the current timestamp t1; The next time C>T3, calculate the time difference Δt=t2-t1, where t2 is the timestamp of the new record; Determine whether Δt exceeds a threshold value T4; If Δt>T4, start the backup power supply, otherwise continue monitoring.

8. The method for designing an AC B code based on FPGA pulse width modulation according to claim 7, characterized in that: The determination of whether Δt exceeds the threshold value T4 includes: Record a start mark S each time the backup power supply is started; After each voltage fluctuation, the start flag S is cleared; Start the backup power supply when Δt>T4 and S is false; If S is true, the backup power supply is not started and the value of the accumulation factor C is increased.

9. The method for designing an AC B code based on FPGA pulse width modulation according to claim 1, characterized in that: The S3 includes: The duty cycle of the PWM signal is dynamically calculated using the following formula: D = V in / V ref ; Where D represents the duty cycle, V in is the real-time monitored grid voltage value, V ref Indicates the target reference voltage value.

10. The method for designing an AC B code based on FPGA pulse width modulation according to claim 1, characterized in that: The S5 includes: By detecting the phase difference Δφ between the smoothed signal and the standard B-code signal, the phase is adjusted according to the following formula: f new =φ old +K·Dφ; Among them, φ new is the adjusted phase, φ old is the current phase, K is the phase adjustment coefficient, and Δφ represents the phase difference between the smoothed signal and the standard B code signal.

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