An Improved Fifth-Order CIFF Sigma-Delta ADC

Abstract

The present invention provides an improved fifth-order CIFF sigma-delta ADC, which relates to the technical field of sigma-delta ADC, including an integration circuit, an analog-to-digital conversion-digital-to-analog conversion module, three feedforward path modules and multiple coefficient modules; the integration circuit includes an adder, 2 subtractors, 5 integrators and 5 coefficient modules; the input ends of the first feedforward path module, the second feedforward path module and the third feedforward path module are respectively connected to different nodes of the integration circuit, the output ends of the first feedforward path module, the second feedforward path module and the third feedforward path module are respectively connected to different input ends of the first adder of the integration circuit, the output end of the first adder is connected to the input end of the analog-to-digital conversion-digital-to-analog conversion module, and other coefficient modules are respectively arranged in the integration circuit. The present invention has the advantages of solving the problem of the offset of the summation coefficient and improving the performance of the sigma-delta ADC.

Description

Technical Field

[0001] The present invention relates to the technical field of sigma-delta ADC, and in particular to an improved fifth-order CIFF sigma-delta ADC. Background Art

[0002] With the rapid development of integrated circuit technology today, especially with the development of MEMS technology, the demand for ADC accuracy is getting higher and higher.

[0003] Among high-precision ADCs, sigma-delta ADCs play a very important role. In high-precision sigma-delta ADC applications, due to the limitations of operational amplifiers and power consumption, a cascaded integrator feedforward structure, i.e., a CIFF structure, is used in most cases, and it also has a higher order. In a high-order CIFF structure, passive adders are used at the summation point for power consumption considerations. At the same time, because the summation coefficient is easily expressed as a capacitor in the actual circuit, it is very susceptible to the influence of parasitic capacitance. In subsequent tests, the influence of parasitic capacitance and other factors will make the actual test value much lower than the originally designed signal-to-noise ratio, that is, the resolution is greatly reduced.

[0004] Therefore, it is necessary to improve the CIFF sigma-delta ADC structure so that the coefficient at the summation point is significantly reduced by the influence of parasitic capacitance, so that the performance obtained in actual testing can be closer to the theoretical performance parameters designed during design. Summary of the invention

[0005] The object of the present invention is to provide an improved fifth-order CIFF sigma-delta ADC, which can significantly reduce the influence of parasitic capacitance on the coefficients at the summation point.

[0006] The present invention is achieved through the following technical solutions:

[0007] An improved fifth-order CIFF sigma-delta ADC comprises an integration circuit, an analog-to-digital conversion-digital-to-analog conversion module and a plurality of coefficient modules; the integration circuit comprises an adder, two subtractors, five integrators and five coefficient modules;

[0008] In the integration circuit, the input end of the first coefficient module is for receiving an input signal, the output end of the first coefficient module is connected to the positive input end of the first subtractor, the output end of the first subtractor is connected to the input end of the first integrator, the output end of the first integrator is connected to the input end of the second coefficient module, the output end of the second coefficient module is connected to the input end of the second integrator, the output end of the second integrator is connected to the input end of the third coefficient module, the output end of the third coefficient module is connected to the input end of the third integrator, the output end of the third integrator is connected to the input end of the fourth coefficient module, the output end of the fourth coefficient module is connected to the positive input end of the second subtractor, the output end of the second subtractor is connected to the input end of the fourth integrator, the output end of the fourth integrator is connected to the third input end of the second adder, the output end of the second adder is connected to the input end of the fifth coefficient module, and the output end of the fifth coefficient module is connected to the input end of the fifth integrator;

[0009] The input ends of the first feedforward path module, the second feedforward path module and the third feedforward path module are respectively connected to different nodes of the integral circuit, the output ends of the first feedforward path module, the second feedforward path module and the third feedforward path module are respectively connected to different input ends of the first adder, and the output end of the first adder is connected to the input end of the analog-to-digital conversion-digital-to-analog conversion module; the ADC output end of the analog-to-digital conversion-digital-to-analog conversion module outputs the final output signal, the DAC output end of the analog-to-digital conversion-digital-to-analog conversion module is connected to the input end of the tenth coefficient module, and the output end of the tenth coefficient module is connected to the negative input end of the first subtractor on the integral circuit; the input end and output end of the ninth coefficient module are respectively connected to a node of the integral circuit and the negative input end of the second subtractor; the input ends of the sixth coefficient module, the second feedforward coefficient module and the seventh coefficient module are respectively connected to different nodes of the integral circuit, and the output ends of the sixth coefficient module, the second feedforward coefficient module and the seventh coefficient module are respectively connected to the input end of the second adder.

[0010] Preferably, an input end of the first feedforward path module is connected to an input end of the first coefficient module, and an output end of the first feedforward path module is connected to a first input end of the first adder.

[0011] Preferably, the input end of the second feedforward path module is connected to the output end of the first integrator, and the output end of the second feedforward path module is connected to the second input end of the first adder;

[0012] Preferably, an input end of the third feedforward path module is connected to an output end of the fifth integrator, and an output end of the third feedforward path module is connected to a third input end of the first adder.

[0013] Preferably, the input end of the sixth coefficient module is connected to the output end of the first integrator, and the output end of the sixth coefficient module is connected to the first input end of the second adder.

[0014] Preferably, the input end of the eighth coefficient module is connected to the output end of the second integrator, and the output end of the eighth coefficient module is connected to the fourth input end of the second adder.

[0015] Preferably, the input end of the seventh coefficient module is connected to the output end of the third integrator, and the output end of the seventh coefficient module is connected to the second input end of the second adder.

[0016] Preferably, the input terminal and the output terminal of the ninth coefficient module are respectively connected to the output terminal of the fifth integrator and the negative input terminal of the second subtractor.

[0017] Preferably, a coefficient module is respectively arranged on the feedforward path modules.

[0018] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0019] Compared with the traditional CIFF sigma-delta ADC, the high-order CIFF sigma-delta ADC structure of the present invention reduces the feedforward path, thereby solving the problem of the offset of the summation coefficient, and ultimately improving the actual performance of the sigma-delta ADC;

[0020] The error between the actual performance of the CIFF sigma-delta ADC and the theoretical performance during design is smaller, the precision and accuracy of the CIFF sigma-delta ADC are improved, and the difficulty of design and debugging is reduced;

[0021] The high-order CIFF sigma-delta ADC of the present invention reduces the coefficient offset while maintaining the low power consumption that the CIFF sigma-delta ADC should have, and has strong reliability;

[0022] The present invention has reasonable design and simple structure, can be realized without complicated circuit change and design, improves the cost performance of CIFF sigma-delta ADC, and is easy to promote and implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of an improved fifth-order CIFF sigma-delta ADC provided in Example 1 of the present invention;

[0024] Figure 2 It is a schematic diagram of the structure of a traditional fifth-order CIFF sigma-delta ADC;

[0025] Figure 3This is a simulated spectrum diagram of the improved fifth-order CIFF sigma-delta ADC provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] Example 1

[0028] This embodiment provides an improved fifth-order CIFF sigma-delta ADC. Figure 1 , including an integration circuit, an analog-to-digital conversion-digital-to-analog conversion module, namely, the ADC-DAC in the figure, three feedforward path modules, three feedforward coefficient modules and two feedback coefficient modules; the integration circuit includes an adder, 2 subtractors, 5 integrators and 5 coefficient modules;

[0029] In the integration circuit, the input end of the first coefficient module is for receiving an input signal, the output end of the first coefficient module is connected to the positive input end of the first subtractor, the output end of the first subtractor is connected to the input end of the first integrator, the output end of the first integrator is connected to the input end of the second coefficient module, the output end of the second coefficient module is connected to the input end of the second integrator, the output end of the second integrator is connected to the input end of the third coefficient module, the output end of the third coefficient module is connected to the input end of the third integrator, the output end of the third integrator is connected to the input end of the fourth coefficient module, the output end of the fourth coefficient module is connected to the positive input end of the second subtractor, the output end of the second subtractor is connected to the input end of the fourth integrator, the output end of the fourth integrator is connected to the third input end of the second adder, the output end of the second adder is connected to the input end of the fifth coefficient module, and the output end of the fifth coefficient module is connected to the input end of the fifth integrator;

[0030] The input ends of the first feedforward path module, the second feedforward path module and the third feedforward path module are respectively connected to different nodes of the integral circuit, the output ends of the first feedforward path module, the second feedforward path module and the third feedforward path module are respectively connected to different input ends of the first adder, and the output end of the first adder is connected to the input end of the analog-to-digital conversion-digital-to-analog conversion module; the ADC output end of the analog-to-digital conversion-digital-to-analog conversion module outputs the final output signal, the DAC output end of the analog-to-digital conversion-digital-to-analog conversion module is connected to the input end of the tenth coefficient module, and the output end of the tenth coefficient module is connected to the negative input end of the first subtractor on the integral circuit; the input end and output end of the ninth coefficient module are respectively connected to a node of the integral circuit and the negative input end of the second subtractor; the input ends of the sixth coefficient module, the second feedforward coefficient module and the seventh coefficient module are respectively connected to different nodes of the integral circuit, and the output ends of the sixth coefficient module, the second feedforward coefficient module and the seventh coefficient module are respectively connected to the input end of the second adder.

[0031] In this embodiment, the input end of the first feedforward path module is connected to the input end of the first coefficient module, and the output end of the first feedforward path module is connected to the first input end of the first adder.

[0032] Further, the input end of the second feedforward path module is connected to the output end of the first integrator, and the output end of the second feedforward path module is connected to the second input end of the first adder;

[0033] On the other hand, an input terminal of the third feedforward path module is connected to an output terminal of the fifth integrator, and an output terminal of the third feedforward path module is connected to a third input terminal of the first adder.

[0034] As a preferred solution of this embodiment, the input end of the sixth coefficient module is connected to the output end of the first integrator, and the output end of the sixth coefficient module is connected to the first input end of the second adder.

[0035] In addition, an input end of the eighth coefficient module is connected to the output end of the second integrator, and an output end of the eighth coefficient module is connected to the fourth input end of the second adder.

[0036] Secondly, the input end of the seventh coefficient module is connected to the output end of the third integrator, and the output end of the seventh coefficient module is connected to the second input end of the second adder.

[0037] Finally, the input terminal and the output terminal of the ninth coefficient module are connected to the output terminal of the fifth integrator and the negative input terminal of the second subtractor respectively.

[0038] As a preferred solution, a coefficient module is respectively provided on the feedforward path modules.

[0039] In the design of sigma-delta ADC, especially when high-precision ADC is required, it is inevitable to use a high-order sigma-delta modulator structure. In particular, in the face of some application scenarios with strict power consumption requirements, high oversampling rates cannot be used to reduce power consumption. At the same time, high oversampling rates will also bring greater pressure to the bandwidth design of the operational amplifier in the integrator. Among the high-order sigma-delta modulator structures, CIFF, i.e., cascaded integrator feedforward structure, is the most widely used one, because this structure performs summation before the final quantizer, which greatly reduces the pressure and design difficulty faced by the swing of the operational amplifier in the loop. The traditional 5th-order CIFF Delta-Sigma ADC has 6 feedforward summation paths. At the same time, because each feedforward summation path has its own corresponding summation coefficient, when the parasitic capacitance has an effect, the summation coefficient will be offset to a greater or lesser extent. Such a change will greatly reduce the final performance compared with the pre-designed performance. This is mainly because the summation part of the traditional CIFF Delta-Sigma ADC often does not add an additional operational amplifier to the existing integrator circuit to build an active adder due to power consumption and area considerations. However, for passive adders, especially high-order sigma-delta modulators, more summation paths will bring a corresponding number of summation coefficients, and these summation coefficients are composed of a series of capacitors in the actual circuit. Such a large number of capacitors will inevitably be forced to deviate from the pre-designed summation coefficients during the production process due to the influence of parasitic capacitance and other factors.

[0040] Therefore, the main design purpose of this embodiment is to reduce this influence, so that the performance of the ADC finally produced is closer to the design value, and at the same time, the CIFF Delta-Sigma ADC structure will not face the error pressure caused by a large number of summing paths. From the traditional structure and the principle of passive adder, it can be known that the passive summing circuit is summed according to the ratio between the capacitors, so too many summing paths will make each summing coefficient very small. The same parasitic capacitance will inevitably have a greater impact on smaller coefficients, so it is necessary to make changes in the traditional circuit structure, and it is preferable to reduce the feedforward path at the passive summation. In the technical solution of this embodiment, there are three feedforward summing paths, which greatly reduces the influence of parasitic capacitance on the feedforward summing coefficient. The transfer function of the system in the structure of this embodiment is consistent with the transfer function of the traditional structure, but the transfer function of the loop filter has changed to a certain extent. In order to design the coefficient of the entire sigma-delta ADC, a new transfer function needs to be obtained. The expression of the integrator is The coefficients of each coefficient module can be found in Figure 1The letters in the triangle boxes of the coefficient modules in the embodiment are represented by L(z). The transfer function of the scheme of this embodiment is represented by L(z) below:

[0041] ;

[0042] exist Figure 1 middle, , , , , , , , , , They are the coefficient parameters of the first to tenth coefficient modules respectively, , and They are coefficient parameters of the first feedforward path module, the second feedforward path module and the third feedforward path module respectively.

[0043] Since the transfer function is consistent with the transfer function of the traditional structure, the structural diagram of the traditional 5th order CIFF Delta-SigmaADC can be found in Figure 2 , its transfer function for:

[0044] ;

[0045] exist Figure 2 middle, , , , , They are the coefficient parameters of several coefficient modules respectively. , , , , and are the coefficient parameters of the conventional 6 feedforward path modules, is the coefficient parameter of the feedback path.

[0046] According to the transmission function of the conventional structure and the transmission function of the present embodiment, a new set of actual values ​​of the coefficients for the new structure is obtained by one-to-one correspondence of the coefficients of each order, that is, The coefficients are calculated one by one, and the actual values ​​of the coefficients of the transfer function based on the traditional structure can be obtained.

[0047] After substituting the final coefficients, we make constraints that can be actually implemented in circuits and then bring them into the entire structure for simulation. Then we perform spectrum analysis on the obtained results. Figure 3That is, the signal spectrum obtained after actual simulation based on the mechanism of this embodiment, Figure 3 The horizontal axis is frequency in Hertz (Hz), and the vertical axis is the amplitude-frequency characteristic, specifically the amplitude in decibels (dB). It can be seen from the figure that when the input signal that meets the coherent sampling frequency is used for simulation (311Hz here), the noise floor at the main frequency signal is -143dBFS, which means that the 23-bit accuracy is guaranteed, and there is no obvious harmonic distortion, showing good noise shaping characteristics.

[0048] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An improved fifth-order CIFF sigma-delta ADC, characterized in that: It includes an integration circuit, an analog-to-digital conversion-digital-to-analog conversion module, three feedforward path modules and multiple coefficient modules; the integration circuit includes an adder, 2 subtractors, 5 integrators and 5 coefficient modules; In the integration circuit, the input end of the first coefficient module is for receiving an input signal, the output end of the first coefficient module is connected to the positive input end of the first subtractor, the output end of the first subtractor is connected to the input end of the first integrator, the output end of the first integrator is connected to the input end of the second coefficient module, the output end of the second coefficient module is connected to the input end of the second integrator, the output end of the second integrator is connected to the input end of the third coefficient module, the output end of the third coefficient module is connected to the input end of the third integrator, the output end of the third integrator is connected to the input end of the fourth coefficient module, the output end of the fourth coefficient module is connected to the positive input end of the second subtractor, the output end of the second subtractor is connected to the input end of the fourth integrator, the output end of the fourth integrator is connected to the third input end of the second adder, the output end of the second adder is connected to the input end of the fifth coefficient module, and the output end of the fifth coefficient module is connected to the input end of the fifth integrator; The input ends of the first feedforward path module, the second feedforward path module and the third feedforward path module are respectively connected to different nodes of the integral circuit, the output ends of the first feedforward path module, the second feedforward path module and the third feedforward path module are respectively connected to different input ends of the first adder, and the output end of the first adder is connected to the input end of the analog-to-digital conversion-digital-to-analog conversion module; the ADC output end of the analog-to-digital conversion-digital-to-analog conversion module outputs the final output signal, the DAC output end of the analog-to-digital conversion-digital-to-analog conversion module is connected to the input end of the tenth coefficient module, and the output end of the tenth coefficient module is connected to the negative input end of the first subtractor on the integral circuit; the input end and output end of the ninth coefficient module are respectively connected to a node of the integral circuit and the negative input end of the second subtractor; the input ends of the sixth coefficient module and the seventh coefficient module are respectively connected to different nodes of the integral circuit, and the output ends of the sixth coefficient module and the seventh coefficient module are respectively connected to the input end of the second adder; An input end of the first feedforward path module is connected to an input end of the first coefficient module, and an output end of the first feedforward path module is connected to a first input end of the first adder; The input end of the second feedforward path module is connected to the output end of the first integrator, and the output end of the second feedforward path module is connected to the second input end of the first adder; The input end of the third feedforward path module is connected to the output end of the fifth integrator, and the output end of the third feedforward path module is connected to the third input end of the first adder; The input end of the sixth coefficient module is connected to the output end of the first integrator, and the output end of the sixth coefficient module is connected to the first input end of the second adder; An input end of the eighth coefficient module is connected to an output end of the second integrator, and an output end of the eighth coefficient module is connected to a fourth input end of the second adder; The input end of the seventh coefficient module is connected to the output end of the third integrator, and the output end of the seventh coefficient module is connected to the second input end of the second adder; The input terminal and the output terminal of the ninth coefficient module are respectively connected to the output terminal of the fifth integrator and the negative input terminal of the second subtractor.

2. An improved fifth-order CIFF sigma-delta ADC according to claim 1, characterized in that: A coefficient module is respectively arranged on the feedforward path modules.

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