Data processing method and electronic equipment

Abstract

The invention provides a data processing method and electronic equipment, the method is applied to a first device, the first device comprises a first memory and a first cache, and the first memory is used for storing a first routing table; the method comprises the following steps: receiving a first routing table item from a second device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device; and updating the first routing table according to the first routing table item, and sending a to-be-forwarded message by using the updated first routing table.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method and an electronic device. Background Art

[0002] With the booming computing field, data processing units (DPUs) are emerging as a key element in redefining the future of data centers and computing architectures. Field-Programmable Gate Arrays (FPGAs) are one of the core technologies for implementing DPUs, which have the ability to be reconfigured at the hardware level, making them suitable for a variety of computing tasks. DPUs can leverage the flexibility of FPGAs to achieve efficient data processing by reconfiguring hardware.

[0003] In the related technology, when the routing table is updated due to changes in the network topology, the FPGA in the DPU generally adopts the I2C (Inter-Integrated Circuit) bus synchronization method or the routing table synchronization method based on special messages. The data transmission delay of the routing table items is high, and the routing table cannot be changed as quickly as possible, which can easily lead to problems such as packet loss and incorrect message routing. Summary of the invention

[0004] According to a first aspect of the present disclosure, a data processing method is provided, the method being applied to a first device, the first device comprising: a first memory and a first cache, the first memory being used to store a first routing table; the method comprising:

[0005] Receiving a first routing table entry from a second device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device;

[0006] The first routing table is updated according to the first routing table entry, and the message to be forwarded is sent using the updated first routing table.

[0007] According to a second aspect of the present disclosure, a data processing device is provided, the device is applied to a first device, the first device comprises: a first memory and a first cache, the first memory is used to store a first routing table; the device comprises:

[0008] A first transmission module, configured to receive a first routing table entry from a second device through a first channel; the first channel is a channel between the first device and the second device based on a high-speed interconnection protocol;

[0009] A first processing module, configured to update the first routing table according to the first routing table entry;

[0010] The first transmission module is further used to send the message to be forwarded by using the updated first routing table.

[0011] According to a third aspect of the present disclosure, a data processing method is provided, the method being applied to a second device, the method comprising:

[0012] Determine a first routing table entry;

[0013] The first routing table entry is sent to the first device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device.

[0014] According to a fourth aspect of the present disclosure, a data processing apparatus is provided, the apparatus being applied to a second device, the apparatus comprising:

[0015] A determination module, used to determine a first routing table item;

[0016] The second transmission module is used to send the first routing table entry to the first device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device.

[0017] According to a fifth aspect of the present disclosure, there is provided an electronic device, including:

[0018] at least one processor; and

[0019] a memory communicatively connected to the at least one processor; wherein,

[0020] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0021] According to a sixth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the method described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:

[0023] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0024] Figure 1 is a schematic diagram of a DPU based on FPGA;

[0025] Figure 2 A flowchart of a data processing method provided by an embodiment of the present disclosure;

[0026] Figure 3 A flowchart of another data processing method provided by an embodiment of the present disclosure;

[0027] Figure 4 A schematic diagram of data transmission in a CXL-based shared cache manner provided in an embodiment of the present disclosure;

[0028] Figure 5 A schematic diagram of a routing table update based on a CXL shared cache method provided in an embodiment of the present disclosure;

[0029] Figure 6 A schematic diagram of a routing table update based on a CXL shared memory method provided in an embodiment of the present disclosure;

[0030] Figure 7 A schematic diagram of a message forwarding based on a CXL shared cache mode provided in an embodiment of the present disclosure;

[0031] Figure 8 A schematic diagram of a Virtio module queue provided in an embodiment of the present disclosure;

[0032] Fig. 9 A schematic diagram of the structure of a data processing device provided in an embodiment of the present disclosure;

[0033] Fig.10 A schematic diagram of the structure of another data processing device provided by an embodiment of the present disclosure;

[0034] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0036] Before further describing the embodiments of the present disclosure in detail, the related technologies involved in the embodiments of the present disclosure are described.

[0037] Figure 1 is a schematic diagram of a DPU based on FPGA; Figure 1As shown, the DPU implemented based on FPGA can be divided into two channels: uplink and downlink. The uplink message passes through the Ethernet (ETH) port, and after being unpacked by the receive multiplexer (RMUX) port selection parser (PA), the message information is processed by the packet processing engine (PPE) for table lookup, and the message is stored through the data path. For the downlink message sent by the host, the operation is reversed. In addition, Figure 1 TXQ in it can stand for transmit queue, Adp for adapter, MUX for multiplexer, DMUX for down multiplexer, QM for queue management, and MODIFY for message modification module. The host is connected to a double rate synchronous dynamic random access memory (DDR) for storing data.

[0038] FPGA needs various table lookups to implement the routing, editing, and processing of network messages. Therefore, FPGA boards must have a large amount of fast storage to save various table data. Currently, with the continuous increase in network bandwidth and network topology, the stored routing table items are getting larger and larger. The storage resources of FPGA (such as BRAM) cannot meet the storage requirements of various table items. It is chosen to use external DDRx memory next to FPGA to store routing tables, such as Figure 1 The FPGA shown has a DDR storing a routing table.

[0039] When the network changes, such as network topology changes, new hosts joining the existing network, or existing hosts leaving the network, the routing table entries need to be relearned and synchronized. The general process is to send the first packet of the newly added host message to the coprocessor for processing. The coprocessor here can be the Extended Central Processing Unit (ECPU), and then flush the routing table entries to the DDRx memory through the FPGA.

[0040] The learning and synchronization of the above routing table items can be synchronized by I2C bus. Specifically, the FPGA and various processors (including ECPU and Host) communicate through I2C bus, including FPGA sending the first packet of the newly added host message to ECPU, ECPU learning the changed routing table items and sending them to FPGA, and FPGA writing the changed routing table items into DDR memory. Since I2C bus is a low-speed bus (usually KB speed) and multiple configuration modules are connected to I2C bus inside FPGA, the I2C bus updates the data of routing table items very slowly, resulting in a large number of network packet losses in the process of updating routing table items, which seriously affects the performance of the application.

[0041] The learning and synchronization of routing table items can also adopt the routing table synchronization method based on special messages, including: packing the changed routing table items into special messages, parsing the messages through the FPGA message parsing module, stripping the payload (updated routing table items), and writing the updated routing table items into the DDRx memory through the FPGA. Compared with the I2C bus synchronization routing table method, the special message method can synchronize the message to the routing table of the DDRx memory as quickly as possible through a high-speed message processing channel (which can reach GB speed). However, the packaging and parsing of routing messages increases the delay of routing synchronization, especially for delay-sensitive fields (such as real-time surgery, financial quantification, real-time high-definition video, etc.), which cannot meet the needs of current applications.

[0042] In summary, the I2C bus synchronization method or the routing table synchronization method based on special messages has a high delay in routing table item data transmission, and the routing table cannot be changed as quickly as possible, which easily leads to problems such as packet loss and incorrect message routing.

[0043] Figure 2 A flowchart of a data processing method provided by an embodiment of the present disclosure; Figure 2 As shown, the method is applied to a first device, the first device includes: a first memory and a first cache, the first memory is used to store a first routing table; the method includes:

[0044] Step 201: receiving a first routing table entry from a second device through a first channel; the first channel is a channel between the first device and the second device based on a high-speed interconnection protocol;

[0045] Step 202: Update the first routing table according to the first routing table entry, and use the updated first routing table to send the message to be forwarded.

[0046] In some embodiments, the first channel is a first-type first channel or a second-type first channel;

[0047] The first type of first channel is a channel based on a high-speed interconnection protocol between the first cache and the cache of the second device;

[0048] The second-type first channel is a channel between the first memory and the second device based on a high-speed interconnection protocol.

[0049] Here, the first device may be an FPGA of the DPU, and the second device may be a coprocessor of the DPU, such as an ECPU. The first cache may be a cache, and the first memory may be a DDR.

[0050] Using the first channel (first type first channel or second type first channel) based on the high-speed interconnection protocol to transmit the routing table items from the ECPU to the FPGA can reduce data transmission delay and increase data transmission rate, so that the FPGA can receive the routing table items in real time, reducing problems such as packet loss and message error routing.

[0051] In some embodiments, the method further comprises:

[0052] Determine device information and / or a first memory size of the first device; the device information is used to indicate a high-speed interconnect protocol version supported by the first device;

[0053] Generate a channel establishment request according to the device information and / or the first memory size; the channel establishment request is used to request to establish a first-category first channel or a second-category first channel;

[0054] The channel establishment request is sent to the second device.

[0055] Here, the high-speed interconnect protocol versions (CXL, Compute Express Link) include: CXL type1 (first type CXL), CXL type2 (second type CXL), and CXL type3 (second type CXL).

[0056] If the device information indicates that the first device supports CXL type 1 based on the device support, then a first channel of the first type may be established;

[0057] If the device information indicates that the first device supports CXL type 3 based on the device support, then a second type first channel may be selected to be established;

[0058] If the device information indicates that the first device supports CXL type 2 based on the device support, the first memory size can be further determined, and it can be determined whether the first memory size exceeds a preset memory threshold. If it exceeds the memory threshold, the second type first channel is selected to be established. If it does not exceed the memory threshold, the first type first channel is selected to be established. The memory threshold can be set based on actual needs, such as 8G, 16G, etc.

[0059] Here, after determining which type of first channel to select according to the device information and / or the first memory size, a corresponding channel establishment request is generated and sent to the second device to establish the corresponding first channel.

[0060] In this way, the appropriate channel type is selected according to the device information and memory size to reduce the delay in the data transmission process, thereby improving the speed and efficiency of data exchange.

[0061] In some embodiments, generating a channel establishment request includes one of the following:

[0062] Determine a starting address, a total length, and an access granularity of a first routing table in the first memory, and generate a channel establishment request according to the starting address, the total length, and the access granularity;

[0063] Determine address information of the first cache, and generate a channel establishment request according to the address information.

[0064] Here, if the first type of first channel needs to be generated, the address information of the first cache is determined, and a channel establishment request is generated according to the address information, so that the second device establishes a channel based on a high-speed interconnection protocol between the first cache and the cache of the second device according to the channel establishment request.

[0065] Here, if it is necessary to generate a second type of first channel, determine the starting address, total length and access granularity of the first routing table in the first memory, and generate a channel establishment request according to the starting address, total length and access granularity. So that the second device can establish a channel based on a high-speed interconnection protocol between the first memory and the second device. Among them, the starting address can be the starting address of the first routing table in the first memory, which is used to indicate the reference point for accessing the first routing table of the first memory. The access granularity is used to indicate the minimum unit of memory access, which can determine the memory size involved each time the routing table entry is updated or accessed. The total length is used to indicate the total length of the first routing table, usually in bytes.

[0066] Of course, according to the application scenario and requirements, the information for generating the channel establishment request may also include other contents, which are not limited here.

[0067] In some embodiments, if the first channel is a first-category first channel, updating the first routing table according to the first routing table entry includes:

[0068] Obtaining a first routing table entry from the first cache;

[0069] The first routing table entry is written into the first routing table in the first memory.

[0070] Here, the first routing table is used to store the path pointing to a specific network address, and can also record the routing metric value of the path, and also contains the topology information around the network, and is mainly used to implement routing protocols and static routing selection.

[0071] A routing table entry in the first routing table is a single entry that can describe the forwarding information required for a specific network destination (such as an IP address or subnet).

[0072] The first routing table entry refers to a newly learned or obtained routing table entry, which is written into the first routing table so that it can be queried and used during subsequent message forwarding.

[0073] Here, considering that the first routing table is saved in the first memory and the first routing table item is received by the first cache, after the first cache receives the first routing table item, the first routing table item needs to be written into the first routing table in the first memory so that the complete routing table item can be obtained immediately when the first routing table is queried subsequently.

[0074] Specifically, after obtaining the first routing table entry from the first cache, it can be first sent to the buffer inside the first device (buffer, such as composed of a memory resource block (BRAM, Block RAM) of a static random access memory (Static Random-Access Memory, SRAM)). Here, the purpose of the device buffer is to serve as an intermediate buffer when the operation timing of the first cache and the first memory does not match, and to obtain data from the first cache as soon as possible to avoid the data in the first cache being replaced in the memory of the host to which the first device is connected. The updated routing table entries in the buffer are synchronously updated and written into the first routing table in the first memory, and the routing table entries that have been updated in the buffer are synchronously removed. If the first device receives a message at this time and does not hit any routing table entry in the first routing table, it can also preferentially search for routing table entries in a small buffer at this time. If it hits, the message is processed according to the hit routing table entry, thereby reducing the large amount of message packet loss caused by untimely updating of routing table entries. The above method can reduce the loss of messages, especially the loss of important message data.

[0075] In some embodiments, the method further comprises one of the following:

[0076] receiving the message to be forwarded through a second channel; the second channel is a channel based on a high-speed interconnection protocol between a first cache of the first device and a last level cache (LLC) of a processor, and the first device and the processor belong to the same device;

[0077] Receive the message to be forwarded from other devices.

[0078] Specifically, the first device may be an FPGA, which serves as an accelerator in the DPU and is used for message forwarding; the second device may be a coprocessor (ECPU) of the DPU, which may be used for routing learning and / or acquiring new routing table entries.

[0079] The first device and the second device belong to the same electronic device, which may further include a host. The host may be a processor, and the first device is connected to the processor.

[0080] In one example, if the electronic device needs to send a message, its processor sends the message to be forwarded to the first device, and the first device forwards it based on the first routing table. Here, a second channel is provided, specifically a channel based on a high-speed interconnection protocol between the first cache of the first device and the last level cache of the processor, and the message to be forwarded is sent through the second channel, so that the first device can quickly and instantly obtain the message to be forwarded.

[0081] In another example, the first device may also receive a message to be forwarded sent by other devices, and as a receiving end or a transfer party, send the message to be forwarded.

[0082] Accordingly, the method may further include:

[0083] The first device determines address information of the first cache, and generates a channel establishment request according to the address information;

[0084] A channel establishment request is sent to the processor; the channel establishment request is used to request the processor to establish a second channel.

[0085] In this way, after receiving the channel establishment request, the processor can establish the second channel based on the channel establishment request. Thus, the first device and the processor can realize fast message transmission through the second channel.

[0086] In some embodiments, sending the message to be forwarded using the updated first routing table includes:

[0087] If it is determined according to the first routing table that the destination address of the message to be forwarded is the device to which the first device belongs, the message to be forwarded is sent to the processor of the device through a second channel; the second channel is a channel based on a high-speed interconnection protocol between the first cache of the first device and the last level cache of the processor.

[0088] Here, if the first device can receive a message to be forwarded sent by other devices, and the destination address of the message to be forwarded is the device to which the first device belongs, the first device can send the message to be forwarded to the processor of the device through the second channel, so that the processor can quickly and instantly obtain the message to be forwarded.

[0089] In some embodiments, the method further comprises one of the following:

[0090] Polling the first cache to determine whether the first cache has received the first routing table entry;

[0091] The flag bit status of the first memory is periodically detected, and whether the first memory receives the first routing table entry is determined according to the flag bit status.

[0092] Here, a query mechanism is provided so that the first device can quickly find that a new routing table entry, namely, the first routing table entry, is obtained in its first cache or first memory.

[0093] If the first channel of the first type is adopted, the first device may poll the first cache to determine whether the first cache has received the first routing table entry, so as to immediately find out whether there is a change in the first cache.

[0094] If the first type second channel is used, the first device can periodically detect the flag bit state of the first memory, and determine whether the first memory has received the first routing table entry according to the flag bit state, so that it is immediately found whether there is a change in the first memory. The flag bit state can be identified in any form to distinguish whether there is a change or not, which is not limited here.

[0095] Of course, in addition to the above method, other methods can also be used, such as an interrupt method, that is, setting an interrupt. If the first memory receives the first routing table entry, an interrupt signal is generated to the processing unit of the first device to inform the first device that a new first routing table entry has been obtained.

[0096] Figure 3 A flowchart of a data processing method provided by an embodiment of the present disclosure; Figure 3 As shown, the data processing method is applied to a second device, and the method includes:

[0097] Step 301: Determine a first routing table entry;

[0098] Step 302: Send the first routing table entry to the first device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device.

[0099] In some embodiments, determining the first routing table entry includes at least one of the following:

[0100] Receiving a new message from a first device; performing route learning according to the new message to obtain a first routing table entry;

[0101] At least one first routing table entry is received from another second device.

[0102] In one example, when the network topology changes, a new host joins the existing network, or an existing host exits, causing the network to change, the overall network changes, and the routing table entries need to be relearned and synchronized. If the first device fails to query the first routing table after receiving a message from the newly joined host, the new message can be sent to the second device, and the second device performs routing learning to obtain the first routing table entry. The routing learning can adopt any routing learning rule or mechanism, and the method for the second device to determine the first routing table entry is not limited here.

[0103] In another example, it is assumed that the device to which the second device belongs belongs to a cluster, and other devices in the cluster determine that there is a new routing table entry, which can be forwarded to each other. For example, the cluster includes server A, server B, server C, and server D; if server A determines a new routing table entry, and the second devices of each server can communicate synchronously, it can be sent to the second devices of other servers, and then sent to the first device by each second device. Here, the new routing table entry is the first routing table entry, and the number of the first routing table entries can be one or more.

[0104] In this way, the first channel (first type first channel or second type first channel) based on the high-speed interconnection protocol is used to reduce delay, enhance data transmission reliability, and increase data transmission rate, so that the first device can receive the first routing table entry instantly.

[0105] In some embodiments, the first channel is a first-type first channel or a second-type first channel;

[0106] The first type of first channel is a channel based on a high-speed interconnection protocol between the first cache and the cache of the second device;

[0107] The second-type first channel is a channel between the first memory and the second device based on a high-speed interconnection protocol.

[0108] Here, a first channel (first type first channel or second type first channel) based on a high-speed interconnection protocol is used to reduce delay, enhance data transmission reliability, and increase data transmission rate, so that the first device can instantly receive the first routing table entry.

[0109] In some embodiments, the method further comprises:

[0110] receiving a channel establishment request; the channel establishment request is used to request to establish a first-category first channel or a second-category first channel;

[0111] A corresponding first-category first channel or a second-category first channel is established according to the channel establishment request.

[0112] Here, the second device can complete the establishment of the corresponding first channel based on the channel establishment request and the information carried by the channel establishment request.

[0113] For example, the information may include: the starting address, total length, access granularity, etc. of the first routing table in the first memory; or the information may include: address information of the first cache, etc.

[0114] Regarding the first channel of the first category and the first channel of the second category, Figure 2 The method is described in detail and will not be repeated here.

[0115] Figure 4 A schematic diagram of data transmission in a CXL-based shared cache manner provided in an embodiment of the present disclosure; Figure 4 In the figure, CORE represents each processor core. A multi-core processor can have multiple processor cores. L1 and L2 represent the first level cache and the second level cache respectively. LLC represents the last level cache. DDR represents the memory. In FPGA, cache represents the first cache of FPGA. AFU represents the Accelerator Functional Unit.

[0116] For the storage hierarchy, the closer the storage is to the processor (such as registers, caches at all levels), the lower the data latency. For example, the data processing latency of the last level cache (LLC) is lower than that of the memory. Therefore, based on the discovery that shared cache (especially LLC) has relatively lower data processing latency, higher performance, and lower power consumption than shared memory, a shared cache method based on CXL is proposed.

[0117] Figure 5 A schematic diagram of a routing table update based on a CXL shared cache method provided in an embodiment of the present disclosure; Figure 5As shown, a shared cache mechanism between FPGA and ECPU is provided to replace the original I2C shared memory mechanism to achieve low-latency routing table synchronization. The physical data update is actually transmitted to the FPGA cache through the CXL protocol-based cache channel (equivalent to the first channel of the first type).

[0118] Specifically, after the ECPU has learned the routing table items, the FPGA quickly obtains the routing table items from the ECPU based on the CXL Cache; then, it sends them to the buffer inside the FPGA; and then the updated routing table items in the buffer are synchronously updated and written into the routing table items in the DDR ( Figure 5 Table0, Table1…TableN represent routing table entries), and the table entries whose buffers have been updated are removed synchronously. If the FPGA hardware receives a message and does not hit the hardware routing table, it can first search the buffer. If it hits, it processes the message according to the routing table entry, reducing the large number of message losses caused by untimely routing table updates. In this way, the loss of messages can be reduced.

[0119] The following provides a routing table update method based on the CXL shared cache mode, including:

[0120] 1. After the FPGA receives the message from the newly added host, the FPGA hardware parses the message and obtains the message information;

[0121] 2. FPGA queries the routing table and determines that there is no matching routing table entry, that is, the FPGA table query fails, and sends the message to the ECPU for processing;

[0122] Here, the sent message may also be sent to the ECPU based on the CXL Cache.

[0123] 3. ECPU parses the message and learns the route to obtain a new routing table entry;

[0124] 4. ECPU writes the new routing table entry into the local soft routing table (TableX) and forwards the message to FPGA;

[0125] Here, the forwarding message may also be sent to the FPGA based on the CXL Cache.

[0126] 5. Based on the CXL shared cache mode, FPGA reads new routing table entries from the local CXL Cache, writes them into the Buffer, and then synchronizes the data of the routing table entries in the Buffer to the DDR. At the same time, the synchronized routing table entries in the Buffer are deleted.

[0127] Figure 6A schematic diagram of a routing table update based on a CXL shared memory method provided in an embodiment of the present disclosure; Figure 6 As shown in the figure, the CXL type3 protocol is used inside the FPGA to map the FPGA's DDR to the ECPU, and the ECPU can directly access the FPGA's DDR through CXL. Specifically, the routing table in the FPGA's DDR is mapped to the ECPU's address space, and the ECPU can update the routing table items on the FPGA side just like updating the local memory. When the ECPU learns the new routing table items, it updates the local routing table items and simultaneously sends the routing table items to the FPGA's memory to update the routing table. The physical data update is actually to directly write the updated routing table items into the routing table of the FPGA memory through the first channel based on the CXL protocol (equivalent to the second type of first channel).

[0128] The following provides a routing table update method based on CXL shared memory, including:

[0129] 1. After the FPGA receives the message from the newly added host, the FPGA hardware parses the message and obtains the message information;

[0130] 2. FPGA queries the routing table and determines that there is no matching routing table entry, that is, the FPGA table query fails, and sends the message to the ECPU for processing;

[0131] 3. ECPU parses the message and learns the route to obtain a new routing table entry;

[0132] 4. ECPU writes the new routing table entry into the local soft routing table (TableX) and forwards the message to FPGA;

[0133] 5. The ECPU sends the new routing table entry to the FPGA. Here, since the routing table in the DDR on the FPGA side has been mapped to the ECPU, the ECPU can directly update the routing table entry; this is equivalent to the ECPU automatically synchronizing the new routing table entry to the routing table on the FPGA side through the CXL protocol.

[0134] Figure 7 A schematic diagram of a message forwarding based on a CXL cache sharing method provided in an embodiment of the present disclosure; Figure 7 As shown, message sending is divided into uplink and downlink directions;

[0135] Uplink direction: After receiving the message, the FPGA receives it through the MAC (media access control layer), and the message is forwarded through the OVS (open virtual switch) hardware table lookup. For messages whose target address is the local machine, the processed message is written into the queue of the Virtio module, and the RSS (load balancing hash) method of the message is supported to write multiple queues for concurrent processing. The current number of Virtio module queues is generally an integer multiple of the processor core. The processed message is written into the CXL Cache of the FPGA, and automatically synchronized to the LLC of the processor based on the Cache consistency protocol. The corresponding bound processor core quickly reads the message data from the shared LLC.

[0136] In this way, the CXL shared cache is used to obtain the message, which has low data latency and high efficiency. If the processor cache is full or replaced, the shared memory method can be used later.

[0137] Downstream direction: The messages processed by the processor are first cached in LLC, and the FPGA obtains the messages sent by the processor using the CXL shared cache method. In this way, the FPGA can quickly obtain the messages.

[0138] Here, the message obtained by FPGA from CXL Cache can be written into the Virtio module queue, and OVS reads the message in the queue for forwarding processing.

[0139] It should be noted that the above Figure 5-Figure 7 In the example, CXL EP Gen5x16 indicates an example of interconnect technology, where CXL indicates the adopted protocol, EP refers to the end port, which is used to connect to FPGA, Gen5 refers to the fifth generation CXL standard, and x16 indicates that the connection can have 16 channels. CXL cache indicates a CXL-based shared cache.

[0140] The DPDK (Data Plane Development Kit) in ECPU represents the accelerated packet processing unit, and OVS (Open vSwitch) represents the multi-layer virtual switch.

[0141] Regarding the Virtio module queue, an example is provided, such as Figure 8 As shown in the figure, in order to adapt to the data being replaced to DDR due to reducing cache data reorganization, a queue form is designed, such as Q0, Q1...QN. The bit width of each entry is the size of a complete cache line, and the data bit width matches the cache, thereby avoiding data reorganization and splitting in CXLCache and reducing data processing delay.

[0142] The disclosed embodiment provides a device mapping method, including: the FPGA board downloads a project containing the CXL protocol and powers on; after the FPGA is powered on, the capabilities and protocol types of CXL can be negotiated with a processor that supports CXL through the CXL.IO protocol. The FPGA can also allocate the starting address, granularity, and length of the routing table in the memory. After the processor negotiates with the FPGA, it can discover and enumerate the FPAG, and at the same time, it can obtain the address space of the FPGA. The routing table in the FPGA memory can also be mapped to the ECPU, and the ECPU can subsequently update the routing table items in the FPGA memory just like directly operating the local memory.

[0143] Fig. 9 A schematic diagram of the structure of a data processing device provided in an embodiment of the present disclosure; Fig. 9 As shown, the device is applied to a first device, the first device includes: a first memory and a first cache, the first memory is used to store a first routing table; the device includes:

[0144] A first transmission module, configured to receive a first routing table entry from a second device through a first channel; the first channel is a channel between the first device and the second device based on a high-speed interconnection protocol;

[0145] A first processing module, configured to update the first routing table according to the first routing table entry;

[0146] The first transmission module is further used to send the message to be forwarded using the updated first routing table.

[0147] In some embodiments, the first channel is a first-type first channel or a second-type first channel;

[0148] The first type of first channel is a channel based on a high-speed interconnection protocol between the first cache and the cache of the second device;

[0149] The second-type first channel is a channel between the first memory and the second device based on a high-speed interconnection protocol.

[0150] In some embodiments, the first processing module is further used to determine device information and / or a first memory size of the first device; the device information is used to indicate a high-speed interconnect protocol version supported by the first device;

[0151] Generate a channel establishment request according to the device information and / or the first memory size; the channel establishment request is used to request to establish a first-category first channel or a second-category first channel;

[0152] The first transmission module is further configured to send the channel establishment request to the second device.

[0153] In some embodiments, the first processing module is used to perform one of the following:

[0154] Determine a starting address, a total length, and an access granularity of a first routing table in the first memory, and generate a channel establishment request according to the starting address, the total length, and the access granularity;

[0155] Determine address information of the first cache, and generate a channel establishment request according to the address information.

[0156] In some embodiments, if the first channel is a first-type first channel, the first processing module is used to obtain a first routing table entry from the first cache;

[0157] The first routing table entry is written into the first routing table in the first memory.

[0158] In some embodiments, the first transmission module is further configured to perform one of the following:

[0159] receiving the message to be forwarded through a second channel; the second channel is a channel based on a high-speed interconnection protocol between a first cache of the first device and a last-level cache of a processor, and the first device and the processor belong to the same device;

[0160] Receive the message to be forwarded from other devices.

[0161] In some embodiments, the first transmission module is used to send the message to be forwarded to the processor of the device through a second channel if it is determined according to the first routing table that the destination address of the message to be forwarded is the device to which the first device belongs; the second channel is a channel based on a high-speed interconnection protocol between the first cache of the first device and the last level cache of the processor.

[0162] In some embodiments, the first processing module is further configured to perform one of the following:

[0163] Polling the first cache to determine whether the first cache has received the first routing table entry;

[0164] The flag bit status of the first memory is periodically detected, and whether the first memory receives the first routing table entry is determined according to the flag bit status.

[0165] It is understandable that, when the data processing device provided in the above embodiment implements the corresponding data processing method, the above processing can be assigned to different program modules as needed to complete all or part of the above-described processing. In addition, the device provided in the above embodiment and the embodiment of the corresponding method belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0166] Fig.10 A structural diagram of another data processing device provided in an embodiment of the present disclosure; Fig.10 As shown, the device is applied to a second device, and the device includes:

[0167] A determination module, configured to determine a first routing table entry;

[0168] The second transmission module is used to send the first routing table entry to the first device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device.

[0169] It is understandable that, when the data processing device provided in the above embodiment implements the corresponding data processing method, the above processing can be assigned to different program modules as needed to complete all or part of the above-described processing. In addition, the device provided in the above embodiment and the embodiment of the corresponding method belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0170] An embodiment of the present disclosure provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be triggered to execute the data processing method provided by the embodiment of the present disclosure.

[0171] In some embodiments, the computer-readable storage medium may be a ferroelectric random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disk, or a CD-ROM; it may also be various devices including one or any combination of the above memories.

[0172] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, model, subroutine or other unit suitable for use in a computing environment.

[0173] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0174] An embodiment of the present disclosure provides a computer program product, which includes a computer program / instructions. When the computer program / instructions are executed by a processor, the data processing method described in the present disclosure is implemented.

[0175] Fig.11 The structure diagram of an electronic device provided by the embodiment of the present disclosure is shown in FIG. Fig.11 As shown, the electronic device 110 includes: a processor 1101 and a memory 1102 for storing a computer program that can be run on the processor; when the processor 1101 is used to run the computer program, it executes any one of the data processing methods provided in the embodiments of the present disclosure.

[0176] In actual application, the electronic device 110 may further include: at least one network interface 1103. The various components in the electronic device 110 are coupled together via a bus system 1104. It is understood that the bus system 1104 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1104 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Fig.11 In the figure, various buses are all labeled as bus system 1104. There may be at least one processor 1101. The network interface 1103 is used for wired or wireless communication between the electronic device 110 and other devices.

[0177] The memory 1102 in the embodiment of the present disclosure is used to store various types of data to support the operation of the electronic device 110 .

[0178] The method disclosed in the above-mentioned embodiment of the present disclosure can be applied to the processor 1101, or implemented by the processor 1101. The processor 1101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above-mentioned method can be completed by the hardware integrated logic circuit in the processor 1101 or the instruction in the form of software. The above-mentioned processor 1101 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 1101 can implement or execute the disclosed methods, steps and logic block diagrams in the embodiment of the present disclosure. The general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present disclosure can be directly embodied as a hardware decoding processor to execute, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a storage medium, and the storage medium is located in the memory 1102. The processor 1101 reads the information in the memory 1102 and completes the steps of the above-mentioned method in combination with its hardware.

[0179] In some embodiments, the electronic device 110 can be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD), field programmable gate array (FPGA), general processor, controller, microcontroller (MCU), microprocessor, or other electronic components to execute the aforementioned method.

[0180] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0181] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0182] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A data processing method, the method being applied to a first device, the first device comprising: a first memory and a first cache, wherein the first memory is used to store a first routing table; The method comprises: Receiving a first routing table entry from a second device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device; The first routing table is updated according to the first routing table entry, and the message to be forwarded is sent using the updated first routing table.

2. The method according to claim 1, wherein the first channel is a first-type first channel or a second-type first channel; The first type of first channel is a channel based on a high-speed interconnection protocol between the first cache and the cache of the second device; The second-type first channel is a channel between the first memory and the second device based on a high-speed interconnection protocol.

3. The method according to claim 1 or 2, further comprising: Determining device information and / or a first memory size of the first device; The device information is used to indicate a high-speed interconnect protocol version supported by the first device; Generate a channel establishment request according to the device information and / or the first memory size; The channel establishment request is used to request to establish a first-category first channel or a second-category first channel; The channel establishment request is sent to the second device.

4. The method according to claim 3, wherein generating a channel establishment request comprises one of the following: Determine a starting address, a total length, and an access granularity of a first routing table in the first memory, and generate a channel establishment request according to the starting address, the total length, and the access granularity; Determine address information of the first cache, and generate a channel establishment request according to the address information.

5. The method according to claim 1, if the first channel is a first-category first channel, updating the first routing table according to the first routing table entry comprises: Obtaining a first routing table entry from the first cache; The first routing table entry is written into the first routing table in the first memory.

6. The method according to claim 1, further comprising one of the following: receiving the message to be forwarded through a second channel; the second channel is a channel based on a high-speed interconnection protocol between a first cache of the first device and a last-level cache of a processor, and the first device and the processor belong to the same device; Receive the message to be forwarded from other devices.

7. The method according to claim 1, sending the message to be forwarded by using the updated first routing table, comprising: If it is determined according to the first routing table that the destination address of the message to be forwarded is the device to which the first device belongs, sending the message to be forwarded to the processor of the device through the second channel; The second channel is a channel based on a high-speed interconnection protocol between the first cache of the first device and the last level cache of the processor.

8. The method according to claim 1, further comprising one of the following: Polling the first cache to determine whether the first cache has received the first routing table entry; The flag bit status of the first memory is periodically detected, and whether the first memory receives the first routing table entry is determined according to the flag bit status.

9. A data processing method, the method being applied to a second device, the method comprising: Determine a first routing table entry; Sending the first routing table entry to the first device through a first channel; The first channel is a channel between the first device and the second device based on a high-speed interconnection protocol.

10. A first device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to execute: Receiving a first routing table entry from a second device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device; The first routing table is updated according to the first routing table entry, and the message to be forwarded is sent using the updated first routing table.

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