Data communication device and method, electronic equipment and storage medium

Abstract

The invention provides a data communication device and method, electronic equipment and a storage medium, the data communication device is applied to a many-core system, the many-core system comprises a plurality of processing cores, each processing core comprises an arbiter, and the data communication device comprises an arbiter network formed by the arbiters in the processing cores. Different arbiters are connected through a connecting unit to realize data communication, and a first arbiter in the arbiter network is used for processing a first data access request accessing a first processing core where the first arbiter is located and sending a second data access request accessing a second processing core to the second arbiter; and the data is sent to a second arbiter corresponding to the second processing core through the connection unit. The arbiter network constructed based on the arbiters is provided in the embodiment of the invention, and more flexible, more efficient and low-delay data communication is realized.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a data communication device, method, electronic device and storage medium. Background Art

[0002] By integrating a large number of processing cores, many-core systems can provide large-scale parallel computing capabilities and have good scalability and flexibility. However, with the increase in the number of processing cores, the data transmission and communication issues within the many-core system are particularly important. Among the related technologies, the network-on-chip (NoC) architecture is mainly used. NoC uses packet switching and multi-hop routing mechanisms. Data needs to pass through multiple routing nodes to reach the destination, which increases the delay of data transmission and requires the use of complex network protocols for data transmission, which reduces transmission efficiency and increases the delay of data processing. Summary of the invention

[0003] The present disclosure provides a data communication device, method, electronic device and storage medium.

[0004] In a first aspect, the present disclosure provides a data communication device, which is applied to a many-core system, wherein the many-core system includes a plurality of processing cores, each of which includes an arbitrator, and the data communication device includes an arbitrator network composed of arbitrators in the plurality of processing cores, wherein different arbitrators are connected to each other through a connection unit to realize data communication, wherein:

[0005] The first arbitrator in the arbitrator network is used to process a first data access request for accessing the first processing core where it is located, and send a second data access request for accessing the second processing core to the second arbitrator corresponding to the second processing core through the connection unit.

[0006] In a second aspect, the present disclosure provides a data communication method, which is applied to the above-mentioned data communication device, and the method includes:

[0007] The first arbitrator obtains a target data access request, wherein the target data access request includes a target access address;

[0008] In a case where the target access address accesses a storage unit in a first processing core where the first arbitrator is located, sending the target data access request to the storage unit in the first processing core;

[0009] When the target access address accesses a storage unit in the second processing core, based on the data communication device, the target data access request is sent to the second arbitrator of the second processing core, so that the second arbitrator sends the target data access request to the storage unit in the second processing core.

[0010] In a third aspect, the present disclosure provides an electronic device, comprising: multiple processing cores; and the above-mentioned data communication device, configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the above-mentioned data communication method.

[0011] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned data communication method when executed by a processing core.

[0012] The data communication device provided by the present disclosure is applied to a many-core system, and the data communication device includes an arbitrator network composed of arbitrators in multiple processing cores. Different arbitrators are connected to each other through a connection unit to realize data communication. In this way, an arbitrator network can be constructed based on the existing arbitrators in the processing cores to transmit data without adding additional hardware devices. In addition, compared with the on-chip network, the arbitrator network reduces data latency and is more efficient and flexible. During specific data communication, the first arbitrator in the arbitrator network is used to process a first data access request for accessing the first processing core where it is located, and sends a second data access request for accessing the second processing core to the corresponding second arbitrator of the second processing core through the connection unit, which can realize data communication within the processing core and between different processing cores, thereby realizing a more efficient and low-latency data communication mechanism.

[0013] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 It is a structural diagram of an arbitrator in an embodiment of the present disclosure;

[0016] Figure 2 It is a structural schematic diagram of a data communication device in an embodiment of the present disclosure;

[0017] Figure 3 A schematic diagram of a connection structure of multiple arbitrators in an embodiment of the present disclosure;

[0018] Figure 4 This is another schematic diagram of a connection structure of multiple arbitrators in an embodiment of the present disclosure;

[0019] Figure 5 is a network connection diagram of a data communication device in an embodiment of the present disclosure;

[0020] Figure 6 A flow chart of a data communication method provided by an embodiment of the present disclosure;

[0021] Figure 7 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0023] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0024] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0027] A many-core system may include one or more many-core chips. It can be understood that a many-core system refers to a computer system built using one or more many-core chips, which usually includes hardware parts (such as processors, storage devices, etc.) and software parts (such as operating systems, scheduling strategies, etc.). In practice, a many-core system can be used to more efficiently utilize many-core chips. A many-core chip includes multiple processing cores. As the number of processing cores increases, data transmission and communication issues within the many-core system are particularly important. In related technologies, network-on-Chip (NoC) is mainly used to achieve communication.

[0028] The basic principle of NoC is to compare the communication network inside the many-core chip to a computer network, and to manage the data transmission inside the many-core chip by introducing the concept of network layer. NoC is usually composed of routing nodes, communication links and routing protocols. Routing nodes are responsible for forwarding data packets and routing decisions. Each routing node is usually connected to one or more processing cores and connected to other routing nodes to form a network topology. The communication link connects the physical channel of the routing node for transmitting data packets. The routing protocol specifies the format of the data packet and cooperates with the routing node to complete the data transmission operation. NoC can realize functions such as path planning and flow control. After the data packet enters the NoC, each routing node can determine the direction to forward the data packet according to the target address and the current network status. NoC can also reduce network congestion and deadlock through virtual channels and buffer management technology.

[0029] However, NoC uses packet switching and multi-hop routing mechanisms. Data packets need to pass through multiple routing nodes to reach the destination. Each routing node needs to perform routing decisions, buffer management and other operations, which increases the delay of data transmission. Especially for applications that require frequent data exchange, this delay may significantly affect performance. In addition, NoC uses complex network protocols for data transmission, which requires adding a large amount of control information (such as source address, destination address, routing information, etc.) to the data packet, which also reduces the transmission efficiency of valid data and increases the delay of data packet processing.

[0030] In the embodiment of the present disclosure, an arbitrator network composed of arbitrators in multiple processing cores is designed based on the existing arbitrators in the processing cores included in the many-core chip. No additional hardware equipment is required, the area size of the existing many-core chip can be guaranteed, and a more efficient and flexible data transmission mechanism can be provided.

[0031] To facilitate understanding of the embodiments of the present disclosure, the arbitrator is briefly described first.

[0032] The arbitrator is a component in a multi-core chip, which is mainly used to manage and coordinate access to shared resources. In related technologies, the arbitrator is usually used to handle storage access conflicts within the core. Figure 1 As shown in FIG. 1 , it is a schematic diagram of the structure of the arbitrator in the embodiment of the present disclosure. Figure 1 As shown, the input of the arbitrator can be connected to various core components, for example, the core component includes a computing component, and the arbitration unit of the arbitrator can be connected to multiple storage units. It should be noted that Figure 1 This is just an example, and there is no limitation on the number of input ports, arbitration units, and storage units. Figure 1 The arbiter in adopts a fully connected structure, that is, each core component can access each storage unit. Of course, a non-fully connected structure can also be adopted. The non-fully connected structure means that the storage units that certain core components can access can be restricted.

[0033] The basic working principle of the arbitrator is as follows: the input port of the arbitrator can receive data access requests from multiple core components; the arbitration unit can send the data access request to the corresponding storage unit according to the address information included in the data access request, and read or write data from the storage unit, wherein the arbitration unit can determine the processing order of data access requests according to a preset arbitration algorithm, such as a fixed priority setting, a polling method, a priority queue, etc., and can process the data request with the highest priority and allow it to access the storage unit. When multiple data access requests want to access the same storage unit, the arbitrator can ensure that only one data access request can access the storage unit at a time to avoid data conflicts; in addition, the arbitrator can also be responsible for simple address conversion, mapping logical addresses to physical storage units.

[0034] The arbitrator is mainly used for accessing storage resources within a single processing core, and has a smaller latency than NoC. However, the access range of the arbitrator in related technologies is limited, and it cannot directly participate in data communication and transmission between processing cores.

[0035] In an embodiment of the present disclosure, a data communication device is provided for a multi-core system. The data communication device includes an arbitrator network composed of arbitrators in multiple processing cores. Figure 2 FIG. 1 is a schematic diagram of the structure of a data communication device in an embodiment of the present disclosure.

[0036] Different arbiters are connected through connection units to achieve data communication, such as Figure 2 As shown, taking the first arbitrator as an example, the core components in the first processing core include computing components, etc. The first arbitrator can be connected to multiple second arbitrators through a connecting unit. The first arbitrator is located in the first processing core, and the second arbitrator is located in the second processing core, so as to realize data communication between the first processing core and the multiple second processing cores.

[0037] Among them, the first arbitrator in the arbiter network is used to process a first data access request for accessing the first processing core where it is located, and sends a second data access request for accessing the second processing core to the second arbitrator corresponding to the second processing core through a connection unit. The structure of the connection unit is not limited, and it can be a connection port of the first arbitrator, or other additional connection structures can be added.

[0038] Furthermore, in the embodiment of the present disclosure, the processing core includes a storage unit, and the storage unit is connected to the arbiter in the processing core where the storage unit is located, for example, Figure 2 As shown, a processing core may include multiple storage units, and each storage unit corresponds to a global address in the many-core system, and different storage units have different global addresses.

[0039] In the disclosed embodiment, the interconnection structure design of multiple arbitrators can realize not only data transmission within a processing core, but also cross-core data transmission between different processing cores.

[0040] Specifically, the data communication device according to the embodiment of the present disclosure is described below.

[0041] Exemplarily, on the one hand, the first arbitrator is mainly used to process the first data access request within the first processing core, such as Figure 2 As shown, the first arbitrator includes a third arbitration unit and a second input port; the second input port is respectively connected to the computing component in the first processing core and the third arbitration unit; the third arbitration unit is respectively connected to the second input port and the storage unit in the first processing core; the first arbitrator is used to send the first data access request to the corresponding storage unit in the first processing core through the third arbitration unit.

[0042] In the case of multiple first data access requests, the third arbitration unit can coordinate processing based on a preset arbitration strategy to avoid data conflicts without restricting the arbitration strategy, thereby realizing processing of data access requests in the processing core.

[0043] Exemplarily, on the other hand, arbiters between different processing cores are connected via a connection unit to implement the second data access request between the processing cores.

[0044] In one possible embodiment, see Figure 3 FIG. 1 is a schematic diagram of a connection structure of multiple arbitrators in an embodiment of the present disclosure.

[0045] The connection unit of the first arbitrator includes multiple first input ports and multiple first arbitration units; the first input port is connected to the first arbitrator and the first arbitration unit respectively; the first arbitration unit is connected to the first input port and the second arbitrator respectively; the first arbitrator is used to send the second data access request to the first arbitration unit through the first input port, and the first arbitration unit sends the second data access request to the corresponding second arbitrator according to the target access address in the second data access request, and the target access address represents the global address of the target storage unit to be accessed.

[0046] The number of the first input port is at least one, and each first input port is connected to at least one first arbitration unit; the number of the first arbitration units is the same as the number of the connected second arbitrators, and each first arbitration unit is connected to a second arbitrator, such as Figure 3 As shown, three first arbitration units and three second arbitrators are taken as an example, each first arbitration unit is connected to a second arbitrator. It should be noted that the multiple second arbitrators here represent different arbitrators, which are only named as examples to distinguish them from the first arbitrators.

[0047] like Figure 3 As shown, taking the case where there are two first input ports as an example, the first input ports and the first arbitration unit can adopt a fully connected structure, that is, each first input port can be connected to each first arbitration unit. Of course, a non-fully connected structure can also be adopted according to needs, and there is no limitation.

[0048] If the computing component in the first processing core wants to access the storage unit of other processing cores, the computing component in the first processing core sends a second data access request, and the first arbitrator in the first processing core determines that it wants to access the target storage unit in the second processing core based on the target access address in the second data access request, and then sends the second data access request to the first input port through the first arbitrator, and then the first arbitration unit sends it to the corresponding second arbitrator based on the target access address, and then the second arbitrator can send the second data access request to the target storage unit.

[0049] Among them, in the embodiment of the present disclosure, the global addresses of all storage units in the many-core system can be pre-configured, and then the target storage unit to be accessed can be determined according to the target access address in the second data access request, so as to send the second data access request to the second arbitrator corresponding to the target storage unit to be accessed.

[0050] Furthermore, if the first arbitrator in the first processing core is connected to the second arbitrator in the second processing core, and the second arbitrator in the second processing core is connected to the third arbitrator in the third processing core, in this case, if the computing component in the first processing core wants to access the storage unit in the third processing core, the data access request can be sent to the second arbitrator through the first arbitrator, and the second arbitrator forwards the data access request to the third arbitrator to achieve access to the storage unit in the third processing core.

[0051] It should be noted that Figure 3 The connection design is only a possible example and should not limit the embodiments of the present disclosure. For example, the number of first input ports, the connection relationship between the first input port and the first arbitration unit, the number of second arbitrators connected to the first arbitrator, etc. are not limited in the embodiments of the present disclosure.

[0052] Thus, in the embodiment of the present disclosure, the first arbitrator and the second arbitrator are connected through the connection unit design of multiple first input ports and multiple first arbitration units, and more refined data transmission control can be performed through the first input port, and the scalability is also stronger and more flexible.

[0053] In one possible embodiment, see Figure 4 FIG. 1 is a schematic diagram of another connection structure of multiple arbitrators in an embodiment of the present disclosure.

[0054] The first arbitrator includes a plurality of second arbitration units, and the connection unit of the first arbitrator includes a second arbitration unit; the first arbitrator is directly connected to the second arbitrator through the output end of the second arbitration unit, wherein the number of the second arbitration units is the same as the number of the connected second arbitrators, and each second arbitration unit is connected to a second arbitrator; the first arbitrator is used to send the second data access request to the second arbitrator corresponding to the target access address in the second data access request through the second arbitration unit, and the target access address represents the global address of the target storage unit to be accessed.

[0055] like Figure 4 As shown, taking three second arbitration units as an example, each second arbitration unit is connected to a second arbitrator, and the second arbitration unit of the first arbitrator can be directly used as a connection unit to realize the direct connection between the first arbitrator and the second arbitrator. Figure 3 The connection unit shown can save additional connection ports, and the arbitrators are directly connected through the ports of the arbitration unit, thereby reducing costs.

[0056] Exemplarily, in an embodiment of the present disclosure, based on the connection structure of the arbitrator, the arbitrators in multiple processing cores are interconnected to build an arbitrator network, and the arbitrator network can coexist with the existing NoC network, that is, the data communication device in the embodiment of the present disclosure may include an arbitrator network and a NoC network, and the NoC network is used for data access requests between different processing cores.

[0057] See also Figure 5 FIG. 1 is a schematic diagram of a network connection of a data communication device in an embodiment of the present disclosure. Figure 5 As shown, the data communication device in the embodiment of the present disclosure may include an arbitrator network (such as Figure 5 The dashed line in the middle) and the NoC network (as shown in Figure 5 The NoC network is composed of various routing nodes. Each processing core includes an arbitrator, computing components, communication components, and private memory (storage unit). The arbitrators in multiple processing cores are interconnected to build an arbitrator network on a many-core system. The NoC network is composed of multiple routing nodes, communication links, and routing protocols.

[0058] Since the arbitrator itself has a limited access range and the arbitrator network does not require complex network protocols, multi-hop routing decisions, etc., the latency is smaller than that of the NoC network. Therefore, the arbitrator network is more suitable for low-latency short-distance data transmission, while the NoC network is more suitable for long-distance flexible data transmission. In addition, the NoC network can also realize more complex data transmission tasks such as dynamic path planning and global load balancing based on multi-hop routing mechanisms.

[0059] Exemplarily, in an embodiment of the present disclosure, the arbitrator network is used to process data access requests that meet a first transmission requirement, and the NoC network is used to process data access requests that meet a second transmission requirement; wherein the transmission parameters in the first transmission requirement include at least a first transmission distance and a first transmission delay, and the transmission parameters in the second transmission requirement include at least a second transmission distance and a second transmission delay, and the first transmission distance is smaller than the second transmission distance, and the first transmission delay is smaller than the second transmission delay.

[0060] Illustratively, in an embodiment of the present disclosure, when data transmission is actually performed in a many-core system, for example, the network used for data of different tasks or different processing cores can be pre-statically configured as an arbitrator network or a NoC network. For another example, the network currently used for data transmission can be determined based on the distance of data transmission, the busyness of network transmission, etc. when the task is running.

[0061] In this way, in the embodiments of the present disclosure, a variety of different communication networks can be provided for application in a multi-core system, so that a more suitable communication network can be used based on different data transmission requirements, which is more flexible and improves data transmission efficiency.

[0062] Based on the data communication device in the embodiment of the present disclosure, refer to Figure 6 As shown, Figure 6 A flowchart of a data communication method provided by an embodiment of the present disclosure. Figure 6 , the method comprising:

[0063] S610: The first arbitrator obtains a target data access request, where the target data access request includes a target access address.

[0064] S620: When the target access address accesses a storage unit in the first processing core where the first arbitrator is located, send a target data access request to the storage unit in the first processing core.

[0065] The target data access request may be received by the first arbitrator from a computing component in the first processing core, and may also be received by the first arbitrator and forwarded from an arbitrator in another processing core.

[0066] S630: When the target access address accesses the storage unit in the second processing core, based on the data communication device, send the target data access request to the second arbitrator of the second processing core, so that the second arbitrator sends the target data access request to the storage unit in the second processing core.

[0067] The specific data communication device is as introduced in the above embodiment and will not be elaborated here. When data is transmitted based on the arbitrator network in the data communication device, the target access request can be sent to the storage unit of the processing core to be accessed by the target access address based on multi-level arbitrator transmission, which is not limited in the embodiments of the present disclosure.

[0068] In the disclosed embodiment, an arbitrator network is constructed based on the interconnection of arbiters in the processing cores, so that data transmission in the many-core system can be realized based on the arbitrator network, and higher-speed and low-latency data access can be achieved.

[0069] Exemplarily, when executing a target task in a many-core system, it is necessary to first allocate hardware resources in the many-core system to the target task, and then execute the target task based on the allocated hardware resources. When allocating resources, the hardware resources of the target task may be located in the same or different processing cores, and there will be a need to access the hardware resources in the processing core or the hardware resources across processing cores. During the execution of the task stage, data communication can be performed based on the data communication device of the many-core system.

[0070] In a possible embodiment, each processing core includes multiple types of hardware resources. To improve resource utilization and resource allocation flexibility, the present disclosure further provides a resource allocation method, including:

[0071] S10: Construct a resource map according to the hardware resources of the many-core system.

[0072] S11: According to the execution process of the target task, the target task is divided into multiple task stages based on resource demand changes, and each task stage has different resource demands for different types of hardware resources.

[0073] Taking various types of hardware resources including computing resources and storage resources as an example, during the calculation process of the target task, the resource requirements for computing resources and storage resources are constantly changing. For this step, the present disclosure provides a possible implementation method, which divides the target task into multiple task stages according to the change in the ratio between the resource requirements for computing resources and the resource requirements for storage resources during the execution of the target task, wherein the ratio of the resource requirements for storage resources and computing resources in each task stage is different.

[0074] S12: Divide the resource graph corresponding to the hardware resources according to the resource demand of each task stage, and determine the resource group allocated to each task stage, where the resource group includes multiple types of hardware resources.

[0075] Exemplarily, the resource requirements of different types of hardware resources corresponding to each task stage have different ratios, and the resource group includes multiple types of hardware resources that meet the required ratios of the corresponding task stage.

[0076] In this way, in the embodiment of the present disclosure, resources can be allocated in units of computing resources and storage resources from the processing core, achieving finer-grained hardware resource management and allocation. The ratio of computing resources and storage resources in the resource group allocated to each task stage can be different, rather than a bound 1:1 relationship, thereby improving the flexibility of resource allocation and resource utilization.

[0077] For example, different resource groups include different hardware resources, or there are overlapping hardware resources between the hardware resources included in different resource groups. In the embodiment of the present disclosure, the hardware resources between multiple resource groups may overlap, and the overlapping hardware resources can be shared during the calculation process of different task stages.

[0078] In one possible embodiment, hardware resources can be uniformly allocated based on the resource demand of the hardware resources corresponding to the task stage, the available amount of hardware resources included in the processing core, etc., to determine the resource group in which shared hardware resources may exist. For example, if the storage resources of a storage unit in a processing core are allocated to both task stage 1 and task stage 2, the storage resources of the storage unit can be used during the calculation process of task stage 1 and task stage 2. In this way, the utilization rate of the hardware resources in the processing core can be further improved.

[0079] Furthermore, in the embodiment of the present disclosure, after determining the resource group allocated to each task stage according to the resource demand of each task stage, the allocated resource group may be further optimized by comprehensively considering the system performance, so as to improve the performance of the many-core system on the basis of meeting the resource demand of the task stage, which specifically includes:

[0080] S21: Determine the resource load of each resource group according to the task execution information of each task stage.

[0081] Among them, resource load refers to the demand for resources by tasks running on a multi-core system or device within a certain period of time. The level of resource load will affect the performance and stability of the system. For example, if the resource load is too high, it may cause the system response to slow down, operation delays to increase, and service unavailability. Therefore, it is very important to reasonably evaluate and control the resource load.

[0082] For example, a resource group includes computing resources and storage resources, and the computing load, storage load, and storage access load in the resource group can be determined separately. The computing load represents the amount of computing tasks completed by the resource group within a certain period of time, and can be determined based on the number of computing operations performed by the resource group during the task execution phase; the storage load represents the usage of the entire storage system, and here we can focus on the amount of data required for tasks stored within a certain period of time; the storage access load represents the number of access requests to the storage within a certain period of time.

[0083] Task execution information refers to relevant information during the execution of the task stage, such as the amount of data, the number of storage access requests to the storage resources in the resource group, the number of computing operations on the computing resources in the resource group, etc. For example, these task execution information can be collected during the compilation process of the target task to perform resource load and resource group optimization analysis.

[0084] S22: Obtain the evaluation performance index corresponding to each resource group according to the resource load and task execution information of each resource group, and determine whether there is an evaluation performance index of each resource group that does not meet the performance requirements.

[0085] In the disclosed embodiment, the evaluation performance indicator represents the system performance information when executing the corresponding task stage based on the resource group. For example, the evaluation performance indicator can be the response time of storage access, system power consumption, task calculation time or speed, throughput, etc. Corresponding performance requirements can be set for different evaluation performance indicators, and there is no restriction on this.

[0086] In this way, in the embodiment of the present disclosure, the resource bottleneck of each resource group can be analyzed through the evaluation performance index corresponding to each resource group, and whether it will affect or cause the system performance to decline can be analyzed.

[0087] S23: In the case where there is a first evaluation performance indicator that does not meet the performance requirement, determine a resource allocation amount of hardware resources of the first evaluation performance indicator.

[0088] For this step, specifically, in an embodiment of the present disclosure, in the presence of a first evaluation performance indicator that does not meet the performance requirements, determine the target type of hardware resources in the resource group corresponding to the first evaluation performance indicator, wherein the target type of hardware resources represents the hardware resources that affect the first evaluation performance indicator; and determine the resource allocation amount corresponding to the target type of hardware resources.

[0089] In the disclosed embodiment, when there is a first evaluation performance indicator that does not meet the requirements, the hardware resources of the target type that affect the first evaluation performance indicator can be analyzed, indicating that there is a resource bottleneck in the hardware resources of the target type. In order to improve system performance, the allocation of the hardware resources of the target type can be optimized.

[0090] S24: According to the resource allocation amount of the hardware resources of the first evaluation performance indicator, the resource allocation amounts of the various types of hardware resources in the resource group are adjusted to determine an adjusted resource group.

[0091] In the disclosed embodiment, in order to further control the global system performance, the global bottleneck can also be determined based on each resource group that has a first evaluation performance indicator that does not meet the performance requirements. For example, based on the first evaluation performance indicator that does not meet the performance requirements, the degree of influence of the hardware resources with the first evaluation performance indicator on the system performance can be determined, and the hardware resources with the highest influence level can be screened out as the global bottleneck, that is, the hardware resources that need to be adjusted.

[0092] For example, if the computing bottleneck of the global bottleneck is the computing bottleneck of resource group 1, computing resources other than resource group 1 can be allocated to resource group 1 to reduce the computing bottleneck of the global bottleneck. One possible way is, for example, to adjust adjacent computing resources to resource group 1. For another example, if the storage access bottleneck of the global bottleneck is the storage access bottleneck of resource group 2, computing or storage resources other than resource group 2 can be adjusted to resource group 2 to reduce the storage access bottleneck of the global bottleneck. In this way, by adjusting and optimizing each resource group, the global bottleneck can be reduced, so that the resource group of each task stage can be determined.

[0093] In a possible embodiment, after determining the resource group allocated to each task stage, during the actual execution of the target task, multiple task stages of the target task can be mapped to the hardware resources corresponding to the corresponding resource groups, and the corresponding task stages can be executed based on the hardware resources corresponding to the resource groups. Furthermore, during the execution of multiple task stages of the target task, a target data access request can be triggered based on the arbitrator network or on-chip network in the embodiment of the present disclosure to access the data stored in different storage resources.

[0094] In the embodiment of the present disclosure, during the actual execution process, task stages based on different resource groups can be executed in parallel, which can improve processing efficiency.

[0095] In the disclosed embodiment, in a many-core system, a resource graph is constructed based on the hardware resources of the many-core system. Based on the changes in the resource requirements of the target task for different types of hardware resources, the target task can be divided into multiple task stages. Then, according to the resource requirements of each task stage, the resource graph corresponding to the hardware resources is divided to determine the resource group allocated to each task stage. In this way, the hardware resources are abstracted into a resource graph, and the target task is divided into multiple task stages. By dividing the resource graph, a resource group is allocated to each task stage to meet the resource requirements of different task stages, thereby improving the flexibility of resource allocation. In addition, different types of hardware resources are matched with the requirements of the task stages, which can achieve finer-grained hardware resource allocation and improve hardware resource utilization, thereby improving the overall performance of the many-core system.

[0096] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0097] In addition, the present disclosure also provides electronic devices, computer-readable storage media and computer program products, all of which can be used to implement any data communication method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0098] Figure 7 A block diagram of an electronic device provided in an embodiment of the present disclosure.

[0099] Reference Figure 7An embodiment of the present disclosure provides an electronic device, which includes multiple processing cores 701 and a data communication device 702, wherein the multiple processing cores 701 are connected to the data communication device 702, and the data communication device 702 is used to exchange data between the multiple processing cores and external data. The data communication device 702 includes the arbitrator network and / or on-chip network in the above-mentioned embodiments.

[0100] One or more instructions are stored in one or more processing cores 701 , and the one or more instructions are executed by one or more processing cores 701 , so that the one or more processing cores 701 can execute the above-mentioned data communication method.

[0101] In some embodiments, the electronic device may be a brain-like chip, which can use vectorized computing and needs to load the weight information and other parameters of the neural network model through an external memory such as a double data rate (DDR) synchronous dynamic random access memory. Therefore, the batch processing used in the embodiments of the present disclosure has a higher computing efficiency.

[0102] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above-mentioned data communication method when executed by a processing core. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0103] The embodiment of the present disclosure also provides a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processing core of an electronic device, the processing core in the electronic device executes the above-mentioned data communication method.

[0104] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0105] As is known to those of ordinary skill in the art, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0106] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0107] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0108] The computer program product described herein may be implemented in hardware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), etc.

[0109] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0110] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0111] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0112] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0113] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A data communication device, characterized in that: Applied to a many-core system, the many-core system includes a plurality of processing cores, each of the processing cores includes an arbitrator, the data communication device includes an arbitrator network composed of the arbitrators in the plurality of processing cores, different arbitrators are connected via a connection unit to achieve data communication, wherein: The first arbitrator in the arbitrator network is used to process a first data access request for accessing the first processing core where it is located, and send a second data access request for accessing the second processing core to the second arbitrator corresponding to the second processing core through the connection unit.

2. The device according to claim 1, characterized in that The processing core includes a storage unit, and the storage unit is connected to an arbiter in the processing core where the storage unit is located. Each storage unit corresponds to a global address in the many-core system, and different storage units have different global addresses.

3. The device according to claim 2, characterized in that The connection unit of the first arbitrator includes a plurality of first input ports and a plurality of first arbitration units; The first input port is connected to the first arbitrator and the first arbitration unit respectively; The first arbitration unit is connected to the first input port and the second arbitrator respectively; The first arbitrator is used to send the second data access request to the first arbitration unit through the first input port, and the first arbitration unit sends the second data access request to the corresponding second arbitrator according to the target access address in the second data access request, where the target access address represents the global address of the target storage unit to be accessed.

4. The device according to claim 3, characterized in that The number of the first input port is at least one, and each of the first input port is connected to at least one first arbitration unit; The number of the first arbitration units is the same as the number of the connected second arbitrators, and each of the first arbitration units is connected to one second arbitrator.

5. The device according to claim 2, characterized in that The first arbitrator includes a plurality of second arbitration units, and the connection unit of the first arbitrator includes the second arbitration unit; The first arbitrator is directly connected to the second arbitrator through the output end of the second arbitration unit, wherein the number of the second arbitration units is the same as the number of the connected second arbitrators, and each second arbitration unit is connected to a second arbitrator; The first arbitrator is used for sending the second data access request to a second arbitrator corresponding to a target access address in the second data access request through the second arbitration unit, where the target access address represents a global address of a target storage unit to be accessed.

6. The device according to any one of claims 1 to 5, characterized in that: The first arbitrator further includes a third arbitration unit and a second input port; The second input port is connected to the computing component in the first processing core and the third arbitration unit respectively; The third arbitration unit is connected to the second input port and the storage unit in the first processing core respectively; The first arbitrator is used to send the first data access request to a corresponding storage unit in the first processing core through the third arbitration unit.

7. The device according to claim 1, characterized in that The data communication device further includes a NoC network, and the NoC network is used for data access requests between different processing cores.

8. The device according to claim 7, characterized in that The arbitrator network is used to process data access requests that meet the first transmission requirement, and the NoC network is used to process data access requests that meet the second transmission requirement; Among them, the transmission parameters in the first transmission requirement include at least a first transmission distance and a first transmission delay, and the transmission parameters in the second transmission requirement include at least a second transmission distance and a second transmission delay, and the first transmission distance is smaller than the second transmission distance, and the first transmission delay is smaller than the second transmission delay.

9. A data communication method, characterized in that: Applied to the data communication device according to any one of claims 1 to 6, the method comprising: The first arbitrator obtains a target data access request, wherein the target data access request includes a target access address; In a case where the target access address accesses a storage unit in the first processing core where the first arbitrator is located, sending the target data access request to the storage unit in the first processing core; When the target access address accesses a storage unit in the second processing core, based on the data communication device, the target data access request is sent to the second arbitrator of the second processing core, so that the second arbitrator sends the target data access request to the storage unit in the second processing core.

10. The method according to claim 9, characterized in that The target data access request is sent during the execution of multiple task stages divided into a target task, and the multiple task stages are mapped to the allocated resource group for execution; Among them, each processing core includes multiple types of hardware resources, and each task stage has different resource requirements for different types of hardware resources. The resource group allocated to each task stage is allocated according to the resource requirements of the task stage, and the resource group includes multiple types of hardware resources.

11. The method according to claim 10, characterized in that The multiple types of hardware resources include computing resources and storage resources, and the method further includes: According to the change in the ratio between the resource requirements of computing resources and storage resources of the target task during the calculation process, the target task is divided into multiple task stages, wherein the ratio of the resource requirements of storage resources and computing resources in each task stage is different.

12. The method according to claim 10 or 11, characterized in that: The method further comprises: Determining the resource load of each resource group according to the task execution information of each task stage; According to the resource load of each resource group and the task execution information, obtaining the evaluation performance index corresponding to each resource group, and determining whether each resource group has an evaluation performance index that does not meet the performance requirements; In the case where there is a first evaluation performance indicator that does not meet the performance requirement, determining a resource allocation amount of a hardware resource of the first evaluation performance indicator; According to the resource allocation amount of the hardware resource of the first evaluation performance indicator, the resource allocation amounts of the multiple types of hardware resources in the resource group are adjusted to determine an adjusted resource group.

13. An electronic device, characterized in that: include: Multiple processing cores; as well as A data communication device, configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the data communication method as described in any one of claims 9-12.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processing core, the computer program implements the data communication method according to any one of claims 9 to 12.

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