Semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device that operates suitably. According to one embodiment, a semiconductor memory device includes: a substrate; a first wiring; a first semiconductor layer provided between the substrate and the first wiring; a plurality of second semiconductor layers provided between the first semiconductor layer and the first wiring; a first via wiring electrically connected to the first semiconductor layer and the plurality of second semiconductor layers; a first memory unit electrically connected to the first semiconductor layer; a first gate electrode facing the first semiconductor layer; a second wiring electrically connected to the first gate electrode; a plurality of connection electrodes provided between the first memory unit and the first wiring and electrically connected to the plurality of second semiconductor layers; a plurality of second gate electrodes provided between the first gate electrode and the first wiring and facing the plurality of second semiconductor layers; a plurality of third wirings provided between the second wirings and the first wirings and electrically connected to the plurality of second gate electrodes; a fourth wiring electrically connected to the first memory unit; a fifth wire commonly electrically connected to the plurality of connection electrodes; and an insulating layer provided between the fourth wiring and the fifth wiring.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] The present application claims the priority of Japanese Patent Application No. 2023-153972 (filing date: September 20, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] As semiconductor memory devices become more highly integrated, research is being conducted on making semiconductor memory devices three-dimensional. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor memory device that operates appropriately.

[0006] A semiconductor memory device according to one embodiment comprises: a substrate; a first wiring, which is arranged on one side of a first direction intersecting with a surface of the substrate relative to the substrate and extends in a second direction intersecting with the first direction; a first semiconductor layer, which is arranged between the substrate and the first wiring; a plurality of second semiconductor layers, which are arranged between the first semiconductor layer and the first wiring and are stacked in the first direction; a first through-hole wiring, which extends in the first direction and is electrically connected to the first semiconductor layer and the plurality of second semiconductor layers; a first memory portion, which is electrically connected to the first semiconductor layer; a first gate electrode, which is opposite to the first semiconductor layer; and a second wiring, which extends in a third direction intersecting with the first direction and the second direction and is connected to the first gate electrode. a plurality of connecting electrodes, which are arranged between the first memory portion and the first wiring, are stacked along the first direction, and are respectively electrically connected to the plurality of second semiconductor layers; a plurality of second gate electrodes, which are arranged between the first gate electrode and the first wiring, are stacked along the first direction, and are respectively opposite to the plurality of second semiconductor layers; a plurality of third wirings, which are arranged between the second wirings and the first wirings, are stacked along the first direction, and extend along the third direction, and are respectively electrically connected to the plurality of second gate electrodes; a fourth wiring, which extends along the first direction, and is electrically connected to the first memory portion; a fifth wiring, which extends along the first direction, and is commonly electrically connected to the plurality of connecting electrodes; and an insulating layer, which is arranged between the fourth wiring and the fifth wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic circuit diagram showing the structure of the semiconductor memory device according to the first embodiment.

[0009] Figure 3 This is a schematic perspective view showing a partial configuration of the semiconductor memory device according to the first embodiment.

[0010] Figure 4 : is a schematic XY cross-sectional view showing a part of the structure of the memory layer ML.

[0011] Figure 5 It is a schematic XY cross-sectional view showing a partial structure of the transistor layer TL.

[0012] Figure 6 : is a schematic XY cross-sectional view showing a part of the structure of the memory layer ML.

[0013] Figure 7 Yes Figure 6 The structure shown is a cross-sectional view taken along line CC' and viewed in the direction of the arrow.

[0014] Figure 8 It is a schematic XY cross-sectional view showing a partial structure of the transistor layer TL.

[0015] Fig. 9 Yes Figure 8 The structure shown is a cross-sectional view taken along line DD' and viewed in the direction of the arrow.

[0016] Fig.10 It is a schematic cross-sectional view showing the structure of the semiconductor memory device according to the first embodiment.

[0017] Fig.11 It is a schematic cross-sectional view showing the structure of the semiconductor memory device according to the first embodiment.

[0018] Fig.12 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0019] Fig.13 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0020] Fig.14 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0021] Fig.15 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0022] Fig.16 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0023] Fig.17This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0024] Fig.18 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0025] Fig.19 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0026] Fig. 20 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0027] Fig.21 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0028] Fig. 22 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0029] Fig.23 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0030] Fig.24 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0031] Fig.25 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0032] Fig.26 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0033] Fig. 27 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0034] Fig.28 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0035] Fig.29 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0036] Fig.30 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0037] Fig.31This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0038] Fig.32 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0039] Fig.33 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0040] Fig.34 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0041] Fig.35 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0042] Fig.36 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0043] Fig.37 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0044] Fig.38 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0045] Fig.39 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0046] Fig.40 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0047] Fig.41 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0048] Fig.42 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0049] Fig.43 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0050] Fig.44 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0051] Fig.45This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0052] Fig.46 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0053] Fig.47 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0054] Fig.48 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0055] Fig.49 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0056] Fig.50 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0057] Fig.51 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0058] Fig.52 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a second embodiment.

[0059] Fig.53 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a second embodiment.

[0060] Fig.54 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a third embodiment.

[0061] Fig.55 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a third embodiment.

[0062] Fig.56 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a third embodiment.

[0063] Fig.57 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0064] Fig.58 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0065] Fig.59This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0066] Fig.60 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fifth embodiment.

[0067] Fig.61 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fifth embodiment.

[0068] Fig.62 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fifth embodiment.

[0069] Fig.63 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION

[0070] Next, the semiconductor memory device of the embodiment is described in detail with reference to the accompanying drawings. In addition, the following embodiment is only an example and is not intended to limit the present invention. In addition, the following drawings are schematic diagrams, and for the convenience of description, a part of the structure is sometimes omitted. In addition, sometimes the same symbols are marked on the common parts of multiple embodiments, and the description is omitted.

[0071] In addition, in this specification, when "semiconductor storage device" is mentioned, it may refer to a memory die, or a memory system including a controller die such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may also refer to a configuration including a host computer such as a smartphone, a tablet terminal, or a personal computer.

[0072] In addition, in this specification, when it is mentioned that the first configuration is "electrically connected to" the second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, semiconductor components, transistors, etc. For example, when three transistors are connected in series, even if the second transistor is in the disconnected (OFF) state, the first transistor is still "electrically connected to" the third transistor.

[0073] In addition, in this specification, when it is mentioned that the first structure is "electrically connected" "between" the second structure and the third structure, it may mean that the first structure, the second structure and the third structure are connected in series, and the second structure is electrically connected to the third structure via the first structure.

[0074] In addition, in this specification, when it is mentioned that a circuit or the like makes two wirings or the like "conduct", for example, it may mean that the circuit or the like includes a transistor or the like, and the transistor or the like is provided on the current path between the two wirings and the transistor or the like is in the ON state.

[0075] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0076] In this specification, a direction intersecting the surface of the substrate is sometimes referred to as a first direction. In addition, a direction along a predetermined surface intersecting the first direction is sometimes referred to as a second direction, and a direction intersecting the second direction along the surface is sometimes referred to as a third direction. The first direction may or may not coincide with the Z direction. In addition, the second direction and the third direction may or may not correspond to any of the X direction and the Y direction.

[0077] In addition, in this specification, when referring to the “center position” of a certain structure, it may refer to, for example, the center position of the circumscribed circle of the structure or the center of gravity of the structure on the image.

[0078] [First embodiment]

[0079] [Structure of memory die MD]

[0080] Figure 1 FIG. 1 is a schematic exploded perspective view showing a configuration example of a semiconductor storage device according to the first embodiment. Figure 1 As shown, the memory die MD has a chip C M and Chip C P . Chip C M Chip C has a memory cell array MCA. P It is provided with peripheral circuits connected to the memory cell array MCA, etc.

[0081] In Chip C M On one side, multiple external pad electrodes P are provided. X In addition, in chip C M On the other side, a plurality of first bonding electrodes P are provided. I1 In addition, in chip C P On one side, a plurality of second bonding electrodes P are provided. I2 . Below, for chip C M , a plurality of first bonding electrodes P are provided I1 The front side is called the front side, where multiple external pad electrodes P are set. X The surface of chip C is called the back surface. P , a plurality of second bonding electrodes P are provided I2 The surface on the opposite side of the front side is called the back side.

[0082] Chip C M and Chip C P Chip CM The front side with chip C P The plurality of first bonding electrodes P are arranged in a manner facing each other. I1 With a plurality of second bonding electrodes P I2 Correspondingly, it is arranged to be able to be bonded with a plurality of second bonding electrodes P I2 The first bonding electrode P I1 The second bonding electrode P I2 As a chip C M With chip C P The bonding electrodes that bond and electrically connect them function.

[0083] In addition, Figure 1 In the example, chip C M The corners a1, a2, a3, and a4 of the chip C are P The corners b1, b2, b3, and b4 correspond to each other.

[0084] [Circuit configuration]

[0085] Figure 2 This is a schematic circuit diagram showing the structure of a semiconductor memory device according to Embodiment 1. A memory cell array MCA includes a plurality of memory layers ML, a plurality of transistor layers TL, a plurality of bit lines BL connected to the plurality of memory layers ML and the plurality of transistor layers TL, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL via the plurality of transistor layers TL, and plate lines PL connected to the plurality of memory layers ML.

[0086] The memory layer ML includes a plurality of word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL"), and a plurality of memory cells MC connected to the plurality of word lines WL0 to WL2. The memory cells MC include a transistor TrC and a capacitor CpC. One electrode of the transistor TrC is connected to the bit line BL. The other electrode of the transistor TrC is connected to the capacitor CpC. In addition, one electrode and the other electrode of the transistor TrC function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrC. The gate electrode of the transistor TrC is connected to any one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the other electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to the plate line PL.

[0087] In addition, each bit line BL is connected to a plurality of memory cells MC corresponding to a plurality of memory layers ML.

[0088] In addition, the memory layer ML includes a plurality of transistors TrLa, TrLb (hereinafter sometimes referred to as "transistor TrL") provided corresponding to the plurality of word lines WL0 to WL2. One electrode of the transistor TrL is connected to any one of the word lines WL0 to WL2. The other electrode of the transistor TrL is connected to the word line selection lines LW0a, LW0b, LW1a, LW1b, LW2a, LW2b (hereinafter sometimes referred to as "word line selection line LW"), respectively. In addition, one electrode and the other electrode of the transistor TrL function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrL. The gate electrode of the transistor TrL is connected to the layer selection lines LLa, LLb (hereinafter sometimes referred to as "layer selection line LL"), respectively.

[0089] In addition, the word line selection line LW is connected to the plurality of transistors TrL corresponding to the plurality of memory layers ML. In addition, the layer selection line LLa is connected in common to all the transistors TrLa corresponding to the plurality of memory layers ML. Similarly, the layer selection line LLb is connected in common to all the transistors TrLb corresponding to the plurality of memory layers ML.

[0090] The transistor layer TL includes a plurality of bit line selection lines LB0 to LB2 (hereinafter, sometimes referred to as "bit line selection lines LB"), and a plurality of transistors TrB connected to the plurality of bit line selection lines LB0 to LB2. One electrode of the transistor TrB is connected to the global bit line GBL via the electrode Cn1. The other electrode of the transistor TrB is connected to the bit line BL. In addition, one electrode and the other electrode of the transistor TrB function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrB. The gate electrode of the transistor TrB is connected to any one of the bit line selection lines LB0 to LB2.

[0091] In addition, among the plurality of transistors TrB, the transistors TrB having one electrode connected to the same bit line BL have the other electrode connected to the same global bit line GBL via the electrode Cn1 . The plurality of transistors TrB are connected in parallel between the bit line BL and the global bit line GBL.

[0092] For example, the plurality of bit line selection lines LB0 to LB2 are connected to the first bonding electrode P I1 and the second bonding electrode P I2 ( Figure 1 ), and set on chip C P The driving circuit and other connections.

[0093] [Chip C P Structure of

[0094] In Chip C P ( Figure 1), a control circuit and a drive circuit for controlling the memory cell array MCA are provided. For example, the control circuit includes a sense amplifier circuit. The sense amplifier circuit is electrically connected to the bit line BL via the global bit line GBL. In a read operation, the sense amplifier circuit can read the data stored in the selected memory cell MC by detecting the voltage change or current of the bit line BL.

[0095] [Chip C M Structure of

[0096] Figure 3 This is a schematic perspective view showing a partial structure of a semiconductor memory device according to this embodiment. Figure 3 The chip C is shown in M A portion of the memory cell array MCA is constructed.

[0097] In the following description, expressions such as "upper" or "lower" are based on the global bit line GBL. For example, the direction away from the global bit line GBL along the Z direction is called lower, and the direction close to the global bit line GBL along the Z direction is called upper. In addition, when the upper surface or upper end is mentioned about a certain structure, it means the surface or end of the structure on the side of the global bit line GBL, and when the lower surface or lower end is mentioned, it means the surface or end of the structure on the opposite side of the global bit line GBL. In addition, the surface intersecting the X direction or the Y direction is called the side surface, etc.

[0098] The memory cell array MCA is, for example, disposed between the global bit line GBL and the substrate Sub. The substrate Sub may be, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B), or a substrate containing other impurities or materials.

[0099] The memory cell array MCA includes a plurality of memory layers ML stacked in the Z direction and a plurality of transistor layers TL provided between the memory layers ML and the global bit lines GBL and stacked in the Z direction. The length of the memory layers ML in the Z direction is approximately the same as the length of the transistor layers TL in the Z direction.

[0100] An insulating layer 103 made of silicon oxide (SiO2) or the like is provided between the plurality of memory layers ML and between the plurality of transistor layers TL. In addition, an insulating layer 203 made of silicon oxide (SiO2) or the like is provided between the first memory layer ML from the top and the first transistor layer TL from the bottom. The length of the insulating layer 203 in the Z direction is greater than the length of the insulating layer 103 in the Z direction.

[0101] [Structure of Memory Layer ML and Transistor Layer TL]

[0102] Next, except Figure 3 In addition, refer to Figures 4 to 11The structures of the memory layer ML and the transistor layer TL will be described.

[0103] Figure 4 : is a schematic XY cross-sectional view showing a part of the structure of the memory layer ML. Figure 5 It is a schematic XY cross-sectional view showing a partial structure of the transistor layer TL. Figure 6 is a schematic XY cross-sectional view showing a part of the structure of the memory layer ML. Figure 4 A portion of is shown enlarged. Figure 7 Show that Figure 6 The structure shown is cut along the CC' line and is a cross section observed in the direction of the arrow. Figure 8 is a schematic XY cross-sectional view showing a part of the structure of the transistor layer TL. Figure 5 A portion of is shown enlarged. Fig. 9 Show that Figure 8 The structure shown is cut along the line DD' and is a cross section observed in the direction of the arrow. Fig.10 and Fig.11 It is a schematic cross-sectional view showing the structure of the semiconductor memory device according to the present embodiment. Fig.10 Show that Figure 4 and Figure 5 The structure shown is cut along line A1-A1' and is a cross section observed in the direction of the arrow. Fig.11 Show that Figure 4 and Figure 5 The structure shown is cut along the line B1-B1' and is a cross section observed in the direction of the arrow.

[0104] like Figure 4 As shown in FIG. 1 , in the memory layer ML, a plurality of insulating layers 101 arranged in the X direction and a conductive layer 102 provided between two adjacent insulating layers 101 in the X direction are provided. The insulating layer 101 and the conductive layer 102 extend in the Y direction and the Z direction, dividing the plurality of memory layers ML in the X direction (see FIG. 1 ). Fig.10 ).

[0105] like Figure 5 As shown in FIG. 1 , in the transistor layer TL, a contact GBLC and an insulating layer 106 such as silicon oxide (SiO2) are provided. These are provided between two insulating layers 101 adjacent to each other in the X direction and are arranged alternately in the Y direction. The contact GBLC and the insulating layer 106 extend in the Z direction, dividing the plurality of transistor layers TL in the X direction (see FIG. 1 ). Fig.10 ).

[0106] The insulating layer 101 includes, for example, silicon oxide (SiO 2 ) or the like.

[0107] The conductive layer 102 may include, for example, a stacked structure of titanium nitride (TiN) and silicon germanium (SiGe). In addition, the conductive layer 102 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W), or a stacked structure of titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W). The conductive layer 102 may be, for example, a plate line PL ( Figure 2 ) to perform its function.

[0108] Between the insulating layer 101 and the conductive layer 102 ( Figure 4 ), and between the insulating layer 101 and the contact GBLC and the insulating layer 106 ( Figure 5 ) area, a plurality of through-hole wirings 104 are provided. The plurality of through-hole wirings 104 are arranged along the Y direction, for example Figure 3 and Fig.10 As shown, the transistor layer TL and the memory layer ML are extended along the Z direction.

[0109] like Figure 6 and Figure 8 As shown, the through-hole wiring 104 includes, for example: a conductive oxide film 104b containing a conductive oxide, and a conductive component 104c. The conductive component 104c may be, for example, a laminated structure including titanium nitride (TiN) and tungsten (W). The conductive component 104c has a substantially cylindrical shape extending in the Z direction. The conductive oxide film 104b has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive component 104c. In addition, the through-hole wiring 104 may also include ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide film 104b. In addition, the through-hole wiring 104 may only include a conductive oxide, or only include ruthenium (Ru), iridium (Ir) or other metals.

[0110] In addition, in this specification, "conductive oxide" is set to include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2) or other oxygen-containing conductive materials.

[0111] The via wiring 104 is, for example, a bit line BL ( Figure 2 ) to perform its function. For example, Figure 2 As shown, a plurality of bit lines BL are provided corresponding to the plurality of transistors TrC included in the memory layer ML and the plurality of transistors TrB included in the transistor layer TL.

[0112] The memory layer ML and the transistor layer TL include: a plurality of transistor structures 110 provided corresponding to the plurality of via wirings 104; and a conductive layer 120 provided on the side opposite to the conductive layer 102 with respect to the plurality of transistor structures 110. In addition, the memory layer ML includes a plurality of capacitor structures 130 provided between the plurality of transistor structures 110 and the conductive layer 102. In addition, the transistor layer TL includes a plurality of electrode structures 130c provided between the plurality of transistor structures 110 and the plurality of contacts GBLC.

[0113] For example Figure 6 to Figure 9 As shown, the transistor structure 110 includes: a semiconductor layer 111, which is connected to the outer peripheral surface of the through-hole wiring 104 and extends along the X direction; an insulating layer 112, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction and the side surface on one side of the X direction (the conductive layer 120 side) of the semiconductor layer 111; and a conductive layer 113, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction and the side surface on one side of the X direction (the conductive layer 120 side) of the insulating layer 112.

[0114] In such Figure 6 and Figure 8 In the illustrated XY cross section, the side surface of the semiconductor layer 111 on one side in the X direction (on the conductive layer 120 side) may be formed along a circle centered on the center position of the through-hole wiring 104. In addition, the side surfaces of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 on the other side in the X direction (on the conductive layer 102 side) may be formed in a straight line along the side surface of the conductive layer 102. In addition, both side surfaces of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the Y direction may be formed in a straight line along the side surface of the insulating layer 115.

[0115] The semiconductor layer 111 is used as transistors TrC and TrB ( Figure 2 ) channel region. The semiconductor layer 111 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn) and oxygen (O), or other oxide semiconductors. The plurality of semiconductor layers 111 arranged along the Z direction are commonly connected to the through-hole wiring 104 extending along the Z direction.

[0116] For example Figure 6 and Figure 7 As shown, the semiconductor layer 111 includes a first portion 111a and a second portion 111b in the memory layer ML. The first portion 111a extends in the Z direction and is connected to the outer peripheral surface of the through-hole wiring 104. The second portion 111b extends in the X direction and is connected to the transistor TrC ( Figure 2 ) is opposite to the conductive layer 113 which functions as a gate electrode.

[0117] For example Figure 8and Fig. 9 As shown, the semiconductor layer 111 is in the transistor layer TL ( Figure 8 and Fig. 9 ) includes a third portion 111c and a fourth portion 111d. The third portion 111c extends in the Z direction and is connected to the outer peripheral surface of the through-hole wiring 104. The fourth portion 111d extends in the X direction and is connected to the transistor TrB ( Figure 2 ) is opposite to the conductive layer 113 which functions as a gate electrode.

[0118] The insulating layer 112 serves as, for example, transistors TrC and TrB ( Figure 2 ) functions as a gate insulating film. The insulating layer 112 includes, for example, silicon oxide (SiO 2 ) or the like.

[0119] The conductive layer 113 is used as transistors TrC and TrB ( Figure 2 ) functions as a gate electrode. The conductive layer 113 includes, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). The plurality of conductive layers 113 arranged along the Y direction are connected in common to a conductive layer 120 extending along the Y direction (see Figure 4 , Figure 5 The conductive layer 113 faces the upper surface, lower surface, both side surfaces in the Y direction, and one side surface in the X direction (conductive layer 120 side) of the second portion 111b and the fourth portion 111c included in the semiconductor layer 111 via the insulating layer 112.

[0120] An insulating layer 115 made of silicon oxide (SiO2) or the like is provided between two semiconductor layers 111 adjacent to each other in the Y direction. The insulating layer 115 extends in the Z direction so as to penetrate through the plurality of transistor layers TL and the plurality of memory layers ML.

[0121] The conductive layer 120 functions as a word line WL in the memory layer ML and as a bit line selection line LB in the transistor layer TL. Figure 2 The conductive layer 120 extends in the Y direction and is connected to the plurality of conductive layers 113 arranged in the Y direction. The conductive layer 120 includes a barrier conductive film 121 made of, for example, titanium nitride (TiN) or the like, and a tungsten (W) conductive film 122.

[0122] For example Figure 6 and Figure 7 As shown, the capacitor structure 130 includes: a conductive layer 131; an insulating layer 132, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side of the X direction (the transistor structure 110 side) of the conductive layer 131; and a conductive layer 133, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side of the X direction (the transistor structure 110 side) of the insulating layer 132.

[0123] The conductive layer 131 acts as a capacitor CpC ( Figure 2 ) functions as an electrode. The conductive layer 131 includes, for example, a stacked structure of titanium nitride (TiN) and silicon germanium (SiGe). In addition, the conductive layer 131 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W), or a stacked structure of titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W). The conductive layer 131 is continuous with the conductive layer 102.

[0124] The insulating layer 132 serves as a capacitor CpC ( Figure 2 ) functions as an insulating layer. The insulating layer 132 may be, for example, zirconium oxide (ZrO2), aluminum oxide (Al2O3) or other insulating metal oxides. In addition, the insulating layer 132 may be, for example, a laminated film of multiple insulating metal oxides (for example, a laminated film of zirconium oxide and aluminum oxide).

[0125] The conductive layer 133 serves as a capacitor CpC ( Figure 2 ) functions as another electrode. The conductive layer 133 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 is insulated from the conductive layer 131 via the insulating layer 132. The conductive layer 133 is connected to the side surface of the conductor layer 111 in the X direction. The conductive layer 133 is insulated from the conductive layer 102 via the insulating layer 132.

[0126] For example Figure 8 and Fig. 9 As shown, the electrode structure 130c includes: a conductive layer 131c; an insulating layer 132c, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction and the side surface on one side of the X direction (the transistor structure 110 side) of the conductive layer 131c; and a conductive layer 133c, which is arranged on the upper surface, the lower surface, the two side surfaces in the Y direction and the side surface on one side of the X direction (the transistor structure 110 side) of the insulating layer 132c.

[0127] The conductive layer 131c includes the same material as that of the conductive layer 131. One side (contact point GBLC side) in the X direction of the conductive layer 131c is in contact with the contact point GBLC.

[0128] The insulating layer 132c includes the same material as that of the insulating layer 132. One side (contact point GBLC side) of the insulating layer 132c in the X direction is in contact with the contact point GBLC.

[0129] The conductive layer 133c is, for example, an electrode Cn1 ( Figure 2) functions as a conductive component. The conductive layer 133c includes the same material as the conductive layer 133. The side surface of the conductive layer 133c on one side in the X direction (the transistor structure 110 side) is connected to the side surface of the semiconductor layer 111 in the X direction. The side surface of the conductive layer 133c on the other side in the X direction (the contact GBLC side) is connected to the contact GBLC. The conductive layer 133c is electrically connected to the contact GBLC.

[0130] For example Figure 8 to Figure 10 As shown, the contact GBLC includes a barrier conductive film 206 such as titanium nitride (TiN) and a conductive film 207 such as tungsten (W) or indium tin oxide (ITO). In addition, the barrier conductive film 206 and the conductive film 207 may also include a conductive oxide such as indium tin oxide (ITO). The contact GBLC is commonly connected to the conductive layer 133c included in the plurality of electrode structures 130c arranged along the Z direction on both sides in the X direction. In addition, the contact GBLC is connected to the global bit line GBL on the upper surface. The contact GBLC functions as an electrode for connecting the plurality of transistors TrB to the global bit line GBL via the electrode Cn1, for example.

[0131] In addition, regarding the upper part of the contact GBLC, as Fig.10 As shown, the upper portion may include a portion P10 having a larger width in the X direction. A portion of the lower surface of the portion P10 may be in contact with a portion of the upper surface of the conductive layer 133c included in the first electrode structure 130c from above.

[0132] For example Figure 5 As shown, the width of the contact GBLC in the Y direction is approximately the same as the width of the global bit line GBL in the Y direction.

[0133] Between the contact GBLC and the conductive layer 102, such as Fig.10 As shown in FIG. 1 , an insulating layer 205 made of silicon oxide (SiO2) or the like is provided. The contact GBLC is insulated from the conductive layer 102 (PL) via the insulating layer 205.

[0134] like Figure 3 , Figure 5 , Fig.10 and Fig.11 As shown, the global bit line GBL extends in the X direction, and a plurality of global bit lines GBL are arranged in the Y direction. The global bit line GBL includes a barrier conductive film 208 made of, for example, titanium nitride (TiN) or the like, and a conductive film 209 made of tungsten (W).

[0135] For example Figure 5 As shown, the global bit line GBL is provided above the transistor structure 110. The global bit line GBL is arranged in the Y direction at a pitch equal to the pitch of the transistor structure 110 arranged in the Y direction. The width of the global bit line GBL in the Y direction is, for example, about the same as the width of the transistor structure 110 in the Y direction.

[0136] A plurality of global bit lines GBL arranged along the Y direction are respectively connected to a plurality of contacts GBLC arranged along the Y direction.

[0137] [Details of Conductive Layer 102 (PL)]

[0138] Next, refer to Fig.10 , the detailed structure of the conductive layer 102 is described.

[0139] In the following instructions, Fig.10 As shown in the figure, the first and second memory layers ML from the top may be referred to as memory layers ML1 and ML2, respectively. Also, the first and second transistor layers from the bottom may be referred to as transistor layers TL1 and TL2, respectively.

[0140] The conductive layer 102 has a structure in which it is electrically connected to the plurality of capacitor structures 130 but is not electrically connected to the plurality of electrode structures 130 c .

[0141] The conductive layer 102 has a surface SU10 ( Fig.10 ) The conductive layer 102 is provided in such a manner that the surface SU10 is located between the upper surface of the capacitor structure 130 included in the memory layer ML1 and the lower surface of the electrode structure 130 c included in the transistor layer TL1 .

[0142] The capacitor structure 130 included in the memory layer ML1 has a surface SUm1 on the upper surface. The surface SUm1, for example, coincides with the upper surface of the conductive layer 133 included in the memory layer ML1. The electrode structure 130c included in the transistor layer TL1 has a surface SUc1 on the lower surface. The surface SUc1, for example, coincides with the lower surface of the conductive layer 133c included in the transistor layer TL1.

[0143] The plane SU10 is provided above the plane SUm1 and below the plane SUc1. The plane SU10 is closer to the global bit line GBL than the plane SUm1. The plane SU10 is farther from the global bit line GBL than the plane SUc1.

[0144] [Details of contact GBLC and through-hole wiring 104 (BL)]

[0145] Next, refer to Fig.10 , the detailed structure of the connection point GBLC and the through-hole wiring 104 (BL) is described.

[0146] The contact GBLC has a structure that is electrically connected to the plurality of electrode structures 130 c but is not electrically connected to the plurality of capacitor structures 130 .

[0147] The contact GBLC has a surface SU40 ( Fig.10The contact GBLC is provided in such a manner that the surface SU40 is located above the upper surface of the capacitor structure 130 included in the memory layer ML1 and below the upper surface of the electrode structure 130 c included in the transistor layer TL1 .

[0148] The electrode structure 130c included in the transistor layer TL1 has a surface SUc2 on the upper surface. The surface SU40 is closer to the global bit line GBL than the surface SUm1. The surface SU40 is farther from the global bit line GBL than the surface SUc2.

[0149] The through hole wiring 104 (BL) has a surface SU20 ( Fig.10 The contact GBLC has a surface SU30 ( Fig.10 ). The surface SU30 of the contact GBLC is located above the surface SU20 of the via wiring 104. The surface SU30 is closer to the global bit line GBL than the surface SU20.

[0150] [Insulating layer 103 and insulating layer 203]

[0151] The length of the insulating layer 103 in the Z direction provided between the capacitor structure 130 included in the memory layer ML1 and the capacitor structure 130 included in the memory layer ML2 is length T10. The length of the insulating layer 103 in the Z direction provided between the electrode structure 130c included in the transistor layer TL1 and the electrode structure 130c included in the transistor layer TL2 is length T20. The length of the insulating layer 203 in the Z direction provided between the capacitor structure 130 included in the memory layer ML1 and the electrode structure 130c included in the transistor layer TL1 is length T30. The length T30 is greater than the length T10 and greater than the length T20.

[0152] [Manufacturing method]

[0153] Figure 12 to Figure 51 This is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0154] Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 , Fig.26 , Fig.28 , Fig.30 , Fig.32 , Fig.34 , Fig.36 , Fig.38 , Fig.40 Shown with Figure 6 and Figure 8 The corresponding cross section.

[0155] Fig.42 , Fig.44 , Fig.46 , Fig.48 , Fig.50 Shown with Figure 8 The corresponding cross section.

[0156] Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 , Fig.23 , Fig.25 , Fig. 27 , Fig.29 , Fig.31 , Fig.33 , Fig.35 , Fig.37 , Fig.39 , Fig.41 , Fig.43 , Fig.45 , Fig.47 , Fig.49 , Fig.51 Shown with Fig.10 A section corresponding to a portion of .

[0157] In the method for manufacturing a semiconductor memory device according to the first embodiment, for example, Fig.13 As shown, multiple insulating layers 103 and insulating layers 203 and multiple sacrificial layers MLA are alternately formed on the upper surface of the substrate Sub. The substrate Sub may be, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B), or a substrate containing other impurities or materials. The sacrificial layer MLA may include, for example, silicon nitride (Si3N4). This step is performed, for example, by CVD (Chemical Vapor Deposition).

[0158] Next, for example Fig.12 As shown, an insulating layer 115 is formed. In this step, for example, an opening is formed at a position corresponding to the insulating layer 115. The opening extends along the Z direction and penetrates the multiple insulating layers 103, the insulating layer 203 and the multiple sacrificial layers MLA stacked along the Z direction. This step is performed, for example, by RIE (Reactive Ion Etching). After the opening is formed, the insulating layer 115 is formed. This step is performed, for example, by CVD.

[0159] Next, for example Fig.14 and Fig.15 As shown in FIG. 1 , an opening 104A is formed at a position corresponding to the through-hole wiring 104. The opening 104A is Fig.14 and Fig.15The illustrated structure extends in the Z direction and penetrates the plurality of insulating layers 103, insulating layers 203 and sacrificial layers MLA stacked in the Z direction. This step is performed, for example, by RIE.

[0160] Next, for example Fig.16 and Fig.17 As shown, an opening 111A is formed. A portion of the upper surface and a portion of the lower surface of the insulating layers 103 and 203, and a portion of the side surface of the sacrificial layer MLA in the X direction are exposed in the opening 111A. In this step, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 104A. This step is performed, for example, by wet etching or the like.

[0161] Next, for example Fig.18 and Fig.19 As shown, a conductive layer 113' is formed inside the opening 111A, and a sacrificial layer 104Sc' is formed inside the openings 104A and 111A. In this step, for example, a conductive film such as titanium nitride (TiN) is formed inside the openings 104A and 111A. Next, inside the opening 104A, a portion of the conductive film (the portion formed on the side of the insulating layer 103 and 203) is removed, and the conductive film is divided along the Z direction to form a conductive layer 113'. Next, silicon (Si) or the like is embedded in the openings 104A and 111A to form a sacrificial layer 104Sc'. This step is performed, for example, by CVD and RIE.

[0162] Next, for example Fig. 20 and Fig.21 As shown, an opening 101A and an opening 120A are formed at positions corresponding to the insulating layer 101 and the conductive layer 120. A portion of the upper surface and a portion of the lower surface of the insulating layer 103, 203 and the side surface of the conductive layer 113' in the X direction are exposed in the opening 120A. In this step, for example, after the opening 101A is formed, a portion of the sacrificial layer MLA is selectively removed through the opening 101A. This step is performed, for example, by RIE and wet etching.

[0163] Next, for example Fig. 22 and Fig.23 As shown, the conductive layer 120 and the insulating layer 101 are formed inside the opening 120A and the opening 101A. In this step, for example, a conductive film made of the same material as the conductive layer 120 is formed inside the openings 120A and 101A. Next, inside the opening 101A, a portion of the conductive film (the portion formed on the side of the insulating layer 103 and 203) is removed, and the conductive film is divided along the Z direction to form the conductive layer 120. Next, the insulating layer 101 is embedded in the opening 101A. This step is performed by methods such as CVD and RIE, for example.

[0164] Next, for example Fig.24 and Fig.25 As shown, an opening 102A is formed at a position corresponding to the conductive layer 102, the insulating layer 205 and a portion of the contact GBLC. The opening 102A extends in the Z direction and penetrates the plurality of insulating layers 103, the insulating layer 203 and the plurality of sacrificial layers MLA stacked in the Z direction. This step is performed, for example, by RIE or the like.

[0165] In addition, for example Fig.24 and Fig.25 As shown, an opening 130A is formed. A portion of the upper surface and a portion of the lower surface of the insulating layer 103, 203, and a portion of the side surface of the conductive layer 113' in the X direction are exposed in the opening 130A. In this step, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 102A. This step is performed, for example, by wet etching or the like.

[0166] Next, for example Fig.26 and Fig. 27 As shown, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, 203 and a portion of the side surface of the conductive layer 113' in the X direction exposed in the opening 130A are removed. The width of the opening 130A in the Z direction is increased by this step. This step is performed, for example, by wet etching.

[0167] In addition, for example Fig.26 and Fig. 27 As shown, the sacrificial layer 104Sc' is removed to form the openings 104A and 111A. The openings 102A, 104A, 111A, and 130A are connected by this step. This step is performed by, for example, wet etching.

[0168] Next, for example Fig.28 and Fig.29 As shown, an insulating layer 112 is formed inside the openings 102A, 104A, 111A, and 130A. This step is performed by, for example, CVD or the like.

[0169] Next, for example Fig.30 and Fig.31 As shown, a sacrificial layer 111Sc' of silicon nitride (Si3N4) or titanium nitride (TiN) is formed inside the openings 102A, 104A, 111A, and 130A. In this step, the opening 111A is embedded in the sacrificial layer 111Sc', and the openings 102A, 104A, and 130A are not embedded in the sacrificial layer 111Sc'. This step is performed, for example, by CVD.

[0170] Next, for example Fig.32 and Fig.33As shown, a portion of the sacrificial layer 111Sc' is removed through the openings 102A and 104A, and the sacrificial layer 111Sc' is divided along the Z direction to form a sacrificial layer 111Sc of silicon nitride (Si3N4) or titanium nitride (TiN). This step is performed, for example, by wet etching.

[0171] Next, for example Fig.34 and Fig.35 As shown, silicon (Si) or the like is embedded in the opening 104A to form a sacrificial layer 104Sc. In this step, for example, silicon (Si) or the like is embedded in the openings 102A and 104A, and then the silicon (Si) or the like embedded in the opening 102A is removed. This step is performed, for example, by CVD, wet etching, or the like.

[0172] Next, for example Fig.36 and Fig.37 As shown, conductive layers 133 and 133c are formed inside the opening 130A. In this step, for example, a conductive oxide layer such as indium tin oxide (ITO) is formed inside the openings 102A and 130A. Next, inside the opening 102A, a portion of the conductive oxide layer (the portion formed on the side of the insulating layer 103 and 203) is removed, and the conductive oxide layer is divided along the Z direction to form conductive layers 133 and 133c. This step is performed, for example, by CVD and RIE.

[0173] Next, for example Fig.38 and Fig.39 As shown, inside the openings 102A, 130A, and Fig.37 On the upper surface of the structure shown, an insulating layer 132' is formed which is made of the same material as the insulating layer 132. This step is performed by, for example, CVD or the like.

[0174] Next, for example Fig.40 and Fig.41 As shown, a conductive layer 131' made of the same material as the conductive layer 131 is formed inside the openings 102A and 130A, and then a conductive layer 102' made of the same material as the conductive layer 102 is formed inside the opening 102A. In this step, the opening 130A is embedded with the conductive layer 131', while the opening 102A is not embedded with the conductive layer 131'. This step is performed, for example, by CVD or the like.

[0175] Next, for example Fig.42 and Fig.43 As shown, a portion of the conductive layer 102', the conductive layer 131', and the insulating layer 132' are removed to form the conductive layers 131, 131c, the insulating layers 132, 132c, the conductive layer 102, and the opening 205A. This step is performed by, for example, RIE.

[0176] Next, for example Fig.44 and Fig.45 As shown, inside the opening 205A and Fig.43 An insulating layer 106 is formed on the upper surface of the structure shown. Next, the portion of the insulating layer 106 located above the sacrificial layer 104Sc is removed to form an opening 106A, and the sacrificial layers 104Sc and 111Sc are removed through the opening 106A to form openings 104A and 111A. This step is performed, for example, by CVD, RIE, wet etching, etc.

[0177] Next, for example Fig.46 and Fig.47 As shown, the semiconductor layer 111 is formed inside the openings 104A and 111A. The opening 111A is buried by the semiconductor layer 111. On the other hand, the opening 104A is not buried by the semiconductor layer 111. This step is performed by ALD (Atomic Layer Deposition) or the like, for example.

[0178] In addition, for example Fig.46 and Fig.47 As shown, through-hole wiring 104 (conductive oxide film 104b and conductive member 104c) is formed inside openings 104A and 106A, and after the upper surface is flattened, insulating layer 107 is formed on the upper surface of insulating layer 106 and through-hole wiring 104. This step is performed by, for example, CVD, CMP (Chemical Mechanical Polishing), or the like.

[0179] Next, for example Fig.48 and Fig.49 As shown, the portions of the insulating layers 107, 106, and 103 corresponding to the contact GBLC are removed to form the insulating layer 205 and the opening 207A. This step is performed by, for example, RIE.

[0180] In this step, a portion of the insulating layer 112 in contact with the upper surface of the first electrode structure 130c from the top is removed simultaneously, thereby exposing a portion of the upper surface of the conductive layer 133c included in the first electrode structure 130c from the top.

[0181] Next, for example Fig.50 and Fig.51 As shown in FIG. 2 , a contact GBLC (barrier conductive film 206 and conductive film 207) is formed inside the opening 207A. This step is performed by, for example, CVD or CMP.

[0182] Next, in Fig.51A global bit line GBL (blocking conductive film 208 and conductive film 209) is formed on the upper surface of the structure shown. In addition, a structure above the global bit line GBL is formed, and then in chip C M The front side of Figure 1 The plurality of first bonding electrodes P shown I1 .

[0183] Next, the chip C M The wafer and the chip C P The wafer is as follows Figure 1 The relationship shown is then bonded to form a plurality of external pad electrodes P X etc., wherein the chip C M In the above steps, the memory cell array MCA is formed.

[0184] Thus, a reference is formed Figures 1 to 11 The described structure.

[0185] [Effect]

[0186] In the semiconductor memory device of this embodiment, a plurality of transistors TrB are connected in parallel between the bit line BL and the global bit line GBL. The plurality of transistors TrB connected in parallel are turned on at the same time to conduct the bit line BL and the global bit line GBL, thereby increasing the total value of the current flowing from the bit line BL to the global bit line GBL when conducting. According to this configuration, the voltage can be transmitted to the selected bit line BL and the global bit line GBL at a high speed.

[0187] In addition, in this embodiment, the structure in the transistor layer TL is configured in the same manner as the structure in the memory layer ML. Therefore, the semiconductor memory device of this embodiment can be realized at a low price without increasing the number of manufacturing steps.

[0188] [Second embodiment]

[0189] Fig.52 and Fig.53 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a second embodiment. Fig.53 Show that Fig.52 The structure shown is a cross section cut along the line B2-B2' and viewed in the direction of the arrow. In the following description, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof will be omitted.

[0190] The semiconductor memory device of the second embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment, but includes global bit lines GBL2a and GBL2b alternately arranged in the Y direction instead of the global bit line GBL.

[0191] The global bit lines GBL2a and GBL2b are basically configured in the same manner as the global bit line GBL. However, the width of the global bit lines GBL2a and GBL2b in the Y direction is, for example, approximately half the width of the transistor structure 110 in the Y direction.

[0192] The global bit line GBL2a is, for example, provided above the transistor structure 110. The global bit line GBL2b is, for example, provided above the insulating layer 115. The global bit lines GBL2a and GBL2b are alternately arranged along the Y direction, and their pitch is half the pitch of the transistor structure 110 arranged along the Y direction.

[0193] For example, in Fig.52 In the region shown in FIG. 1 , a plurality of global bit lines GBL2a arranged in the Y direction are respectively connected to a plurality of contacts GBLC arranged in the Y direction. Fig.52 In the illustrated region, a plurality of global bit lines GBL2b arranged along the Y direction are not connected to the contact GBLC.

[0194] [Third Embodiment]

[0195] Figure 54 to Figure 56 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a third embodiment. Fig.55 Show that Fig.54 The structure shown is cut along line A3-A3' and is a cross section observed in the direction of the arrow. Fig.56 Show that Fig.54 The structure shown is a cross section taken along the line B3-B3' and viewed in the direction of the arrow. In the following description, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof will be omitted.

[0196] The semiconductor memory device of the third embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the third embodiment includes a contact GBLC3 instead of the contact GBLC, and includes global bit lines GBL3a and GBL3b alternately arranged in the Y direction instead of the global bit line GBL.

[0197] The contact GBLC3 is basically constructed in the same manner as the contact GBLC. However, the width of the contact GBLC3 in the X direction and the Y direction is smaller than that of the contact GBLC. Fig.54 As shown, the width of the contact GBLC3 in the Y direction is approximately half of the width of the transistor structure 110 in the Y direction.

[0198] In addition, for example Fig.54As shown, every other contact GBLC3 is offset to the positive and negative sides of the X direction and arranged in the Y direction. The contact GBLC3 arranged on the negative side of the X direction is arranged on the positive side of the Y direction relative to the through-hole wiring 104, and the contact GBLC3 arranged on the positive side of the X direction is arranged on the negative side of the Y direction relative to the through-hole wiring 104.

[0199] In addition, for example Fig.55 As shown, the contact GBLC3 is connected in common to a plurality of electrode structures 130c arranged in the Y direction on the side surface on one side in the X direction (the side of the through-hole wiring 104).

[0200] The global bit lines GBL3a and GBL3b are basically configured in the same manner as the global bit line GBL.

[0201] However, for example Fig.54 and Fig.56 As shown, the global bit lines GBL3a and GBL3b are arranged over the Y-direction region where the transistor structure 110 and the insulating layer 150 are arranged. The global bit lines GBL3a and GBL3b are arranged alternately along the Y-direction, and their pitch is half of the pitch of the transistor structure 110 arranged along the Y-direction. The width of the global bit lines GBL3a and GBL3b in the Y-direction is, for example, about half of the width of the transistor structure 110 in the Y-direction.

[0202] For example, in Fig.54 In the illustrated region, a plurality of global bit lines GBL3a and GBL3b arranged along the Y direction are respectively connected to a plurality of contacts GBLC3 arranged along the Y direction.

[0203] [Fourth embodiment]

[0204] Figure 57 to Figure 59 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment. Fig.58 Show that Fig.57 The structure shown is cut along line A4-A4' and is a cross section observed in the direction of the arrow. Fig.59 Show that Fig.57 The structure shown is a cross section taken along the line B4-B4' and viewed in the direction of the arrow. In the following description, the same reference numerals are given to the same parts as those in the third embodiment, and the description thereof will be omitted.

[0205] The semiconductor memory device of the fourth embodiment is basically configured in the same manner as the semiconductor memory device of the third embodiment. However, the semiconductor memory device of the fourth embodiment includes a contact GBLC4 instead of the contact GBLC3.

[0206] The contact point GBLC4 is basically constructed in the same manner as the contact point GBLC3.

[0207] However, if Fig.57 and Fig.59 As shown, the contact GBLC4 is provided in the transistor layer TL, inside the insulating layer 115. Fig.59 As shown, the contact GBLC4 is connected to the electrode structure 130c from one side in the Y direction (positive side in the Y direction or negative side in the Y direction).

[0208] In addition, regarding the upper portion of the contact GBLC4, for example Fig.59 As shown, the upper portion may include a portion P14 having a wider width in the Y direction. A portion of the lower surface of the portion P14 may be in contact with a portion of the upper surface of the conductive layer 133c included in the first electrode structure 130c from the top.

[0209] The contact GBLC4 has a surface SU44 ( Fig.59 ). The contact GBLC4 is provided in such a manner that the surface SU44 is located above the upper surface of the capacitor structure 130 included in the memory layer ML1 and below the upper surface of the electrode structure 130c included in the transistor layer TL1.

[0210] [Fifth embodiment]

[0211] Figure 60 to Figure 62 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fifth embodiment. Fig.61 Show that Fig.60 The structure shown is cut along line A5-A5' and is a cross section observed in the direction of the arrow. Fig.62 Show that Fig.60 The structure shown is a cross section cut along the line B5-B5' and viewed in the direction of the arrow. In the following description, the same reference numerals are given to the same parts as those in the third embodiment, and the description thereof will be omitted.

[0212] The semiconductor memory device of the fifth embodiment is basically configured in the same manner as the semiconductor memory device of the third embodiment. However, the semiconductor memory device of the fifth embodiment includes a contact GBLC5 instead of the contact GBLC3.

[0213] The contact point GBLC5 is basically constructed in the same manner as the contact point GBLC3.

[0214] However, if Fig.60 As shown, the contact GBLC5 is provided inside the electrode structure 130c in the transistor layer TL. Fig.61 and Fig.62As shown, the contact GBLC5 is provided so as to penetrate the electrode structure 130c provided in the transistor layer TL2, and the lower surface of the contact GBLC5, namely, the surface SU45, is connected to the conductive layer 133c included in the electrode structure 130c provided in the transistor layer TL1.

[0215] The contact GBLC5 is connected to the conductive layer 133c of the electrode structure 130c included in the transistor layer TL2 on both sides in the X and Y directions. The contact GBLC5 is connected to the conductive layer 133c of the electrode structure 130c included in the transistor layer TL1 from the positive side in the Z direction.

[0216] [Another embodiment]

[0217] The semiconductor memory devices according to the first to fifth embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and specific configurations and the like may be appropriately adjusted.

[0218] For example, in the semiconductor memory devices of the first to fifth embodiments, two transistor layers TL are illustrated which are arranged in the Z direction. However, three or more transistor layers TL may be arranged in the Z direction. Three or more transistors TrB arranged in the three or more transistor layers TL may be connected in parallel between the through-hole wiring 104 (BL) and the global bit line GBL.

[0219] In addition, for example, in the semiconductor storage devices of the first to third embodiments, both side surfaces of the contacts GBLC and GBLC2 in the X direction and one side surface of the contact GBLC3 in the X direction may also have a portion of the side surface. Fig.63 The shape shown as the contact GBLCa. Fig.63 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to another embodiment.

[0220] The side surface of the contact GBLCa on one side in the X direction (the side surface on the negative side in the X direction) is provided so as to enter the electrode structure 130c side. The contact GBLCa is in contact with not only the side surface in the X direction of each conductive layer 133c included in the plurality of electrode structures 130c, but also a part of the upper surface and the lower surface of the conductive layer 133c.

[0221] Similarly, in the semiconductor storage device of the fourth embodiment, the contact GBLC4 may be provided so that the side surface on one side in the Y direction enters the electrode structure 130c and a part thereof contacts the upper and lower surfaces of the electrode structure 130c.

[0222] In addition, regarding the manufacturing method of the contact GBLCa, refer to Fig.48 and Fig.49In the steps described above, when removing a portion of the insulating layers 107, 106, and 103, a portion of the insulating layer 103 located between the layers corresponding to the transistor layer TL is also removed. Fig.50 and Fig.51 In the described steps, the barrier conductive film 206 and the conductive film 207 are formed.

[0223] In addition, in the above description, the capacitor CpC is used as an example of a memory unit connected to the transistor structure 110. However, the memory unit may not be the capacitor CpC. For example, the memory unit may also include ferroelectrics, ferromagnets, chalcogenide materials such as GeSbTe, or other materials, and the properties of these materials are used to record data. For example, in any of the structures described above, the insulating layer between the electrodes forming the capacitor CpC may also include any of these materials.

[0224] Furthermore, the methods for manufacturing the semiconductor memory device according to the first to fifth embodiments can be adjusted as appropriate. For example, any two of the above steps may be switched in order or performed simultaneously.

[0225] [other]

[0226] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and can be omitted, replaced, and changed in various ways without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

[0227] [Explanation of Symbols]

[0228] 102: Conductive layer

[0229] 104: Through-hole wiring

[0230] 111: Semiconductor layer

[0231] 113: Conductive layer

[0232] 120: Conductive layer

[0233] 130:Capacitor structure

[0234] 130c: Electrode structure

[0235] BL: Bit Line

[0236] Cn1: Electrode

[0237] CpC:Capacitor

[0238] GBL: Global Bit Line

[0239] GBLC: contact

[0240] PL: Plate Line

[0241] WL: Word line.

Claims

1. A semiconductor storage device comprising: substrate; A first wiring is provided on one side of a first direction intersecting with a surface of the substrate relative to the substrate and extends in a second direction intersecting with the first direction; a first semiconductor layer provided between the substrate and the first wiring; A plurality of second semiconductor layers are provided between the first semiconductor layer and the first wiring and are stacked in the first direction; a first through-hole wiring extending in the first direction and electrically connected to the first semiconductor layer and the plurality of second semiconductor layers; a first memory portion electrically connected to the first semiconductor layer; a first gate electrode, facing the first semiconductor layer; a second wiring extending in a third direction intersecting the first direction and the second direction and electrically connected to the first gate electrode; A plurality of connection electrodes are provided between the first memory portion and the first wiring, are stacked in the first direction, and are electrically connected to the plurality of second semiconductor layers respectively; A plurality of second gate electrodes are provided between the first gate electrode and the first wiring, are stacked in the first direction, and are respectively opposite to the plurality of second semiconductor layers; a plurality of third wirings, provided between the second wirings and the first wirings, stacked in the first direction, extending in the third direction, and electrically connected to the plurality of second gate electrodes respectively; a fourth wiring extending in the first direction and electrically connected to the first memory portion; a fifth wiring extending along the first direction and electrically connected to the plurality of connection electrodes; as well as The insulating layer is provided between the fourth wiring and the fifth wiring.

2. The semiconductor memory device according to claim 1, wherein The plurality of connection electrodes include a first connection electrode closest to the first memory portion, The fourth wiring has a first surface on a side close to the first wiring in the first direction. The first surface is closer to the first wiring than the surface of the first memory portion on the first connection electrode side. The first surface is farther from the first wiring than a surface of the first connection electrode on the first memory portion side.

3. The semiconductor memory device according to claim 1, wherein The first through-hole wiring has a second surface on a side close to the first wiring in the first direction. The fifth wiring has a third surface on a side close to the first wiring in the first direction. The third surface is closer to the first wiring than the second surface.

4. The semiconductor memory device according to claim 3, wherein The third surface is in contact with the first wiring.

5. The semiconductor memory device according to claim 1, wherein The fifth wiring is electrically connected to the first wiring.

6. The semiconductor memory device according to claim 2, wherein The fifth wiring has a fourth surface on a side away from the first wiring in the first direction. The fourth surface is closer to the first wiring than the surface of the first memory portion on the first connection electrode side. The fourth surface is farther away from the first wiring than a surface of the first connection electrode on the opposite side to the first memory portion.

7. The semiconductor memory device according to claim 2, wherein The plurality of connection electrodes include a second connection electrode that is second closest to the first memory portion, The semiconductor storage device comprises: a second memory section disposed on the substrate side in the first direction relative to the first memory section; a first insulating layer provided between the first memory portion and the second memory portion; a second insulating layer, disposed between the first connection electrode and the second connection electrode; as well as a third insulating layer disposed between the first memory portion and the first connecting electrode; and The thickness of the third insulating layer in the first direction is greater than the thickness of the first insulating layer in the first direction. A thickness of the third insulating layer in the first direction is greater than a thickness of the second insulating layer in the first direction.

8. The semiconductor memory device according to claim 1, wherein The fifth wiring is provided between the fourth wiring and the first wiring.

9. The semiconductor memory device according to claim 1, comprising: a third semiconductor layer, arranged to be spaced apart from the first semiconductor layer in the second direction; a plurality of fourth semiconductor layers, spaced apart from the plurality of second semiconductor layers in the second direction and stacked in the first direction; a second through-hole wiring extending in the first direction and electrically connected to the plurality of third semiconductor layers and the plurality of fourth semiconductor layers; a fourth memory portion electrically connected to the third semiconductor layer; and a plurality of third connection electrodes, which are disposed between the fourth memory portion and the first wiring, are stacked in the first direction, and are electrically connected to the plurality of fourth semiconductor layers respectively; and The fifth wiring is electrically connected to the plurality of third connection electrodes.

10. The semiconductor memory device according to claim 1, wherein The fifth wiring is provided between the first memory section and the first wiring.

11. The semiconductor memory device according to claim 1, wherein The first semiconductor layer and the plurality of second semiconductor layers respectively include at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

12. The semiconductor memory device according to claim 1, wherein At least one of the first memory units is a capacitor.

13. The semiconductor memory device according to claim 1, wherein The first gate electrode faces one or both of the surface on one side and the surface on the other side in the first direction of the first semiconductor layer. The first memory portion is provided on one side of the first semiconductor layer in the second direction. The second wiring is provided on the other side of the first semiconductor layer in the second direction.

14. The semiconductor memory device according to claim 1, wherein The first semiconductor layer includes a first portion and a second portion, The first portion extends in the first direction, and the second portion extends in the second direction and faces the first gate electrode in the first direction.

15. The semiconductor memory device according to claim 1, wherein The plurality of second semiconductor layers respectively include a third portion and a fourth portion, The third portion extends in the first direction, and the fourth portion extends in the second direction and faces the plurality of second gate electrodes in the first direction, respectively.

16. The semiconductor memory device according to claim 1, wherein A first chip and a second chip bonded together via a plurality of bonding electrodes are provided. The first chip comprises: a plurality of the first semiconductor layers, a plurality of the first wirings, the plurality of second semiconductor layers, a plurality of first through-hole wirings, a plurality of the first memory units, a plurality of first gate electrodes, a plurality of the second wirings, The plurality of connecting electrodes, the plurality of second gate electrodes, the plurality of third wirings, The fourth wiring, and a plurality of said fifth wirings, The second chip comprises: A control circuit is electrically connected to the plurality of first wirings.

17. A method for manufacturing a semiconductor storage device, which is a method for manufacturing a semiconductor storage device according to claim 1, the manufacturing method being forming a first opening at a position corresponding to the fourth wiring line; A second opening is formed at a position corresponding to the first memory portion via the first opening, forming a capacitor electrode of the first memory portion inside the second opening, An insulating film is formed inside the first opening and the second opening, and the insulating film covers the one capacitor electrode of the first memory portion inside the second opening. forming a conductive layer covering the insulating film inside the first opening and the second opening, removing a portion of the conductive layer to form another capacitor electrode of the first memory unit and the plurality of connection electrodes, forming the first through-hole wiring, The fifth wiring is formed.

18. A semiconductor storage device comprising: A plurality of first semiconductor layers are stacked in a first direction; a first wiring provided on one side of the first direction with respect to the plurality of first semiconductor layers and extending in a second direction intersecting the first direction; A plurality of second semiconductor layers are provided between the plurality of first semiconductor layers and the first wiring and are stacked in the first direction; a first through-hole wiring extending in the first direction and electrically connected to the plurality of first semiconductor layers and the plurality of second semiconductor layers; A plurality of first memory portions are stacked in the first direction and are electrically connected to the plurality of first semiconductor layers respectively; A plurality of first gate electrodes are stacked in the first direction and respectively face the plurality of first semiconductor layers; a plurality of second wirings, which are stacked in the first direction, extend in a third direction intersecting the first direction and the second direction, and are electrically connected to the plurality of first gate electrodes respectively; a plurality of connection electrodes, provided between the plurality of first memory portions and the first wiring, stacked in the first direction, and electrically connected to the plurality of second semiconductor layers respectively; a plurality of second gate electrodes, provided between the plurality of first gate electrodes and the first wiring, stacked in the first direction, and respectively facing the plurality of second semiconductor layers; a plurality of third wirings, provided between the plurality of second wirings and the first wiring, stacked in the first direction, extending in the third direction, and electrically connected to the plurality of second gate electrodes respectively; a fourth wiring extending in the first direction and electrically connected to the plurality of first memory sections in common; as well as The fifth wiring extends in the first direction and is electrically connected to the plurality of connection electrodes.

19. The semiconductor memory device according to claim 18, wherein The plurality of connection electrodes include a first connection electrode closest to the plurality of first memory portions, The fourth wiring has a first surface on a side close to the first wiring in the first direction. The first surface is closer to the first wiring than a surface of the plurality of first memory sections which is closest to one of the plurality of connection electrodes on the first connection electrode side. The first surface is farther from the first wiring than a surface of the first connection electrode on the plurality of first memory portions side.

20. The semiconductor memory device according to claim 18, wherein The first through-hole wiring has a second surface on a side close to the first wiring in the first direction. The fifth wiring has a third surface on a side close to the first wiring in the first direction. The third surface is closer to the first wiring than the second surface.

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