Programmable device, programmable device array and method of operation, memory

Abstract

The embodiments of the present disclosure provide a programmable device, a programmable device array and an operating method, and a memory, wherein the programmable device comprises: a bit line; a selection transistor, a first source-drain electrode of the selection transistor being electrically connected with the bit line; a selection signal line, the selection signal line being electrically connected with a gate of the selection transistor; a plurality of diodes; a plurality of anti-fuse units, a first end of the anti-fuse unit being electrically connected with a second source-drain electrode of the selection transistor through a corresponding diode; and a plurality of word lines, the word line being electrically connected with a second end of a corresponding anti-fuse unit.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and is related to, but not limited to, a programmable device, a programmable device array and an operation method, and a memory. Background Art

[0002] Dynamic random access memory (DRAM) chips typically have redundant memory cells. These cells can replace defective cells in the DRAM chip to repair the DRAM. DRAM chip repairs often utilize one-time programmable (OPT) devices, such as antifuses. Currently, programmable devices consist of a select transistor and a programming transistor, occupying a large area.

[0003] In addition, with the rapid development of integrated circuit technology, chip size continues to shrink, and the spacing between programmable devices has also decreased. As a result, on the one hand, the programming tube and other adjacent tubes may be accidentally broken down, affecting the repair effect of the anti-fuse unit; on the other hand, the coupling between the programming tube and the selection transistor is serious, affecting the performance of the programmable device. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a programmable device, a programmable device array and an operating method, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a programmable device, including:

[0006] bit lines;

[0007] a selection transistor, wherein a first source and a drain of the selection transistor are electrically connected to the bit line;

[0008] a selection signal line electrically connected to a gate of the selection transistor;

[0009] Multiple diodes;

[0010] a plurality of anti-fuse units, wherein a first end of each anti-fuse unit is electrically connected to the second source and drain of the selection transistor via the corresponding diode;

[0011] A plurality of word lines are electrically connected to the second ends of the corresponding anti-fuse units.

[0012] In some embodiments, the diode is disposed in a substrate and includes a first region disposed adjacent to the anti-fuse unit and a second region disposed adjacent to the first region;

[0013] The second region of the diode corresponding to the anti-fuse unit disposed adjacent to the selection transistor is shared by the second source and drain.

[0014] In some embodiments, further comprising: a metal layer;

[0015] The second region of the diode corresponding to the anti-fuse unit not adjacent to the selection transistor is connected to the second source and drain through the metal layer.

[0016] In some embodiments, the further comprising: a plurality of first conductive pillars;

[0017] The first conductive pillar is connected to the second region, and a plurality of the first conductive pillars are commonly connected to the metal layer.

[0018] In some embodiments, the selection transistor and the plurality of anti-fuse units are disposed in the same active region and are sequentially spaced apart along the first direction; the programmable device further comprises:

[0019] a second conductive column connected between the first source and drain and the bit line;

[0020] a first connection structure connected between the gate of the selection transistor and the selection signal line;

[0021] The second connection structure is connected between the second end of the anti-fuse unit and the word line.

[0022] In some embodiments, the selection transistor includes a first gate dielectric layer and a first gate conductive layer located on a surface of the first gate dielectric layer;

[0023] The anti-fuse unit includes a second gate dielectric layer and a second gate conductive layer located on a surface of the second gate dielectric layer; wherein the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer.

[0024] In some embodiments, the first region and the active region are N-type doped; the second region and the first source and drain are P-type doped.

[0025] In a second aspect, an embodiment of the present disclosure provides a programmable device array, comprising:

[0026] A plurality of programmable devices according to the first aspect arranged sequentially along a second direction;

[0027] The gates of the selection transistors in a row arranged along the second direction are connected to each other; and the second ends of the anti-fuse units in a row arranged along the second direction are connected to each other.

[0028] In some embodiments, gates of the selection transistors in a row arranged along the second direction are connected to the same selection signal line;

[0029] The second ends of the anti-fuse units in a row arranged along the second direction are connected to the same word line.

[0030] In a third aspect, an embodiment of the present disclosure provides an operating method for a programmable device, which is applied to the programmable device described in the first aspect. The method includes:

[0031] During a programming operation, a bit line corresponding to an anti-fuse unit to be programmed is set to a first voltage, a second voltage is applied to the selection signal line, and a third voltage is applied to a word line corresponding to the anti-fuse unit to be programmed, so as to break down the anti-fuse unit to be programmed. At the same time, the first voltage is applied to the other word lines in the programmable device so as not to break down the other anti-fuse units except the anti-fuse unit to be programmed. The anti-fuse unit to be programmed is any one of the plurality of anti-fuse units.

[0032] During a read operation, the bit line corresponding to the anti-fuse unit to be read is set to the first voltage, a second voltage is applied to the selection signal line, and a fourth voltage is applied to the word line corresponding to the anti-fuse unit to be read, so as to read data in the anti-fuse unit to be read. At the same time, the first voltage is applied to the other word lines in the programmable device;

[0033] Among them, the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage; the first voltage is zero voltage or ground voltage; the difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse unit to be programmed; the difference between the second voltage and the first voltage is greater than or equal to the turn-on voltage of the selection transistor.

[0034] In a fourth aspect, an embodiment of the present disclosure provides an operating method for a programmable device array, which is applied to the programmable device array described in the second aspect. The method includes:

[0035] During a programming operation, a bit line corresponding to an anti-fuse unit to be programmed is set to a first voltage, a second voltage is applied to the selection signal line, and a third voltage is applied to a word line corresponding to the anti-fuse unit to be programmed, so as to breakdown the device to be programmed. At the same time, the first voltage is applied to the other word lines in the programmable device array, and a fifth voltage is applied to the other bit lines in the programmable device array, so as not to breakdown the other anti-fuse units except the anti-fuse unit to be programmed. The anti-fuse unit to be programmed is any one of the plurality of anti-fuse units.

[0036] During a read operation, the bit line corresponding to the anti-fuse unit to be read is set to the first voltage, a second voltage is applied to the selection signal line, and a fourth voltage is applied to the word line corresponding to the anti-fuse unit to be read, so as to read data in the anti-fuse unit to be read. At the same time, the first voltage is applied to the other word lines in the programmable device array; and the fourth voltage is applied to the other bit lines in the programmable device array;

[0037] Among them, the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage; the first voltage is zero voltage or ground voltage; the difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse unit to be programmed; the difference between the third voltage and the fifth voltage is less than the breakdown voltage of any one of the anti-fuse units in the programmable device array; the difference between the second voltage and the first voltage is greater than or equal to the turn-on voltage of the selection transistor.

[0038] In a fifth aspect, an embodiment of the present disclosure provides a memory comprising: the programmable device array described in the second aspect above.

[0039] The present disclosure provides a programmable device, a programmable device array, an operating method, and a memory, wherein the programmable device includes: a bit line; a select transistor, wherein the first source and drain of the select transistor are electrically connected to the bit line; a select signal line, wherein the select signal line is electrically connected to the gate of the select transistor; a plurality of diodes; a plurality of anti-fuse units, wherein the first end of the anti-fuse unit is electrically connected to the second source and drain of the select transistor via a corresponding diode; and a plurality of word lines, wherein the word lines are electrically connected to the second end of the corresponding anti-fuse unit. Since the programmable device in the present disclosure includes a select transistor and a plurality of anti-fuse units, the area of ​​the programmable device can be reduced, and the coupling between the select transistor and the anti-fuse unit can be reduced, thereby improving the performance of the programmable device. In addition, since the programmable device in the present disclosure includes a plurality of diodes corresponding to the plurality of anti-fuse units, and the anti-fuse units are connected to the select transistors via diodes, that is, no doped region (e.g., a lightly doped region) is provided below the anti-fuse unit, thus avoiding erroneous breakdown between adjacent anti-fuse units. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0041] Figure 1It is a structural diagram of a programmable device;

[0042] Figure 2 A schematic diagram of the structure of a programmable device provided in an embodiment of the present disclosure Figure 1 ;

[0043] Figure 3 A schematic diagram of the structure of a programmable device provided in an embodiment of the present disclosure Figure 2 ;

[0044] Figure 4 for Figure 3 The equivalent circuit diagram of the programmable device shown;

[0045] Figure 5 A schematic diagram of the structure of a programmable device array provided in an embodiment of the present disclosure;

[0046] Figure 6 for Figure 5 The equivalent circuit diagram of the programmable device array is shown. DETAILED DESCRIPTION

[0047] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0048] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0049] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0050] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the present disclosure necessarily has the first element, component, region, layer, or part.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] Figure 1 A schematic diagram of the structure of a programmable device is shown in FIG. Figure 1 As shown, the programmable device 100 includes a first direction (eg Figure 1 X-axis direction shown) and a second direction (as Figure 1 A plurality of antifuse structures 20 are arranged in an array (in the Y-axis direction shown), for example Figure 1Four antifuse structures 20 are shown. The antifuse structure 20 includes a first antifuse unit and a second antifuse unit. The first antifuse unit and the second antifuse unit are formed on the active region 10. The active region 10 includes at least a first doped region 101, a second doped region 102, and a third doped region 103. The first antifuse unit includes a first selection transistor and a first programming device. The first selection transistor includes a first gate 201, a first doped region 101, and a second doped region 102. The first programming device includes the second gate 202 and the active region 10 below it. The second antifuse unit includes a second selection transistor and a second programming device. The second selection transistor includes a third gate 203, a second doped region 102, and a third doped region 103. The second programming device includes a fourth gate 204 and the active region 10 below it. The first selection transistor and the second selection transistor share the second doped region 102, and the bit line is electrically connected to the second doped region 102 through the connection structure 205. A plurality of first conductive lines 207 are respectively connected to the first gate 201 or the third gate 203, and are used to apply a turn-on voltage (for example, 1.1V) to the first gate 201 or the third gate 203 during programming to turn on the first selection transistor or the second selection transistor. A plurality of second conductive lines 208 are respectively connected to the second gate 202 or the fourth gate 204, and are used to apply a high voltage (for example, about 4 to 5.5 volts) to the first gate 201 or the third gate 203 during programming to break down the first programming device or the second programming device.

[0053] Currently, each antifuse cell in programmable device 100 includes a select transistor and a programming transistor, occupying a large area. Furthermore, with the rapid development of integrated circuit technology, chip sizes are shrinking, and the spacing between programmable devices is decreasing. This can lead to erroneous breakdown of the programming transistor and other adjacent transistors, affecting the repair of the antifuse cell. Furthermore, the coupling between the programming transistor and the select transistor is severe, affecting the performance of the programmable device.

[0054] Based on this, embodiments of the present disclosure provide a programmable device, a programmable device and an operating method, and a memory, wherein the programmable device includes: a bit line; a select transistor, wherein a first source and drain of the select transistor are electrically connected to the bit line; a select signal line, wherein the select signal line is electrically connected to the gate of the select transistor; a plurality of diodes; a plurality of anti-fuse units, wherein a first end of the anti-fuse unit is electrically connected to a second source and drain of the select transistor via a corresponding diode; and a plurality of word lines, wherein the word lines are electrically connected to the second end of a corresponding anti-fuse unit. Because the programmable device in the embodiments of the present disclosure includes a select transistor and a plurality of anti-fuse units, the area of ​​the programmable device can be reduced, and the coupling between the select transistor and the anti-fuse unit can be reduced, thereby improving the performance of the programmable device. In addition, because the programmable device in the embodiments of the present disclosure includes a plurality of diodes corresponding to the plurality of anti-fuse units, and the anti-fuse units are connected to the select transistors via the diodes, that is, no doped regions are provided below the anti-fuse units, thus avoiding erroneous breakdown between adjacent anti-fuse units.

[0055] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0056] Before introducing the embodiments of the present disclosure, the three directions that may be used to describe the three-dimensional structure in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular) with the top and bottom surfaces of the substrate is defined as the third direction. In the directions of the top and bottom surfaces of the substrate (i.e., the plane where the substrate is located), two directions intersecting (e.g., perpendicular to each other) are defined. For example, the arrangement direction of the selection transistor and the antifuse unit can be defined as the first direction, and the plane direction of the substrate can be determined based on the first and second directions. In the embodiments of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular. In the embodiments of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0057] In one embodiment of the present disclosure, Figure 2 and Figure 3 A schematic diagram of the structure of a programmable device provided in an embodiment of the present disclosure is shown in FIG. Figure 2 and Figure 3 As shown, the programmable device 200 includes:

[0058] Bit line 48 (eg Figure 3 shown);

[0059] a selection transistor, wherein a first source and drain 45 of the selection transistor is electrically connected to a bit line 48;

[0060] a selection signal line 40 electrically connected to a gate 44 of the selection transistor;

[0061] a plurality of diodes 32;

[0062] a plurality of anti-fuse units, wherein a first end of the anti-fuse unit is electrically connected to the second source and drain 47 of the selection transistor through a corresponding diode 32;

[0063] A plurality of word lines 36 are electrically connected to the second ends of corresponding anti-fuse units.

[0064] It should be noted that the programmable device 200 in the embodiment of the present disclosure is formed in a substrate 300, which may be, for example, a semiconductor substrate. The semiconductor substrate may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or combinations thereof.

[0065] In some embodiments, a plurality of active regions 31 are formed in the substrate 300, and the plurality of active regions 31 are isolated by shallow trench isolation (STI) 30. The active regions 31 may be ion-doped regions, such as N-type doped regions or P-type doped regions.

[0066] In the embodiment of the present disclosure, the selection transistor is disposed on the active region 31 , and includes a gate 44 , a first source-drain 45 , and a second source-drain 47 . The first source-drain 45 and the second source-drain 47 are formed by ion-doped regions in the active region 31 .

[0067] In the embodiment of the present disclosure, the selection transistor may be a PMOS transistor. In other embodiments, the selection transistor may be an NMOS transistor.

[0068] In some embodiments, see Figure 2The select transistor includes a first gate dielectric layer 441 and a first gate conductive layer 442 located on a surface of the first gate dielectric layer 441. The first gate dielectric layer 441 may be made of silicon oxide or other suitable materials; the first gate conductive layer 442 may be made of any material with good electrical conductivity, such as titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), copper (Cu), or polysilicon.

[0069] In some embodiments, see Figure 2 The diode 32 is disposed in the substrate 300 , specifically, in the active region 31 of the substrate 300 . The diode 32 includes a first region 321 disposed adjacent to the anti-fuse unit and a second region 322 disposed adjacent to the first region 321 .

[0070] It should be noted that the first region 321 is located in the active region 31 below the antifuse unit, that is, the first region 321 is part of the active region 31. Therefore, the doping type of the first region 321 is the same as the doping type of the active region 31. In the embodiment of the present disclosure, the first region 321 and the active region 31 are N-type doped, and the second region 322 and the first source and drain 45 are P-type doped. In this case, the first source and drain 45 are also P-type doped, and the select transistor is a PMOS transistor.

[0071] In other embodiments, the first region 321 and the active region 31 may both be P-type doped. When the first region 321 is P-type doped, the second region 322 is N-type doped, and the second source / drain 47 and the first source / drain 45 are also N-type doped, then the selection transistor is an NMOS transistor.

[0072] In some embodiments, see Figure 2 The antifuse unit includes a second gate dielectric layer 331 and a second gate conductive layer 332 located on a surface of the second gate dielectric layer 331. The second gate dielectric layer 331 may be made of silicon oxide or other suitable materials; the second gate conductive layer 332 may be made of any material with good electrical conductivity, such as titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, copper, or polysilicon.

[0073] It should be noted that the first end of the anti-fuse unit is the end connected to the second gate dielectric layer 331 , and the second end of the anti-fuse unit is the end connected to the second gate conductive layer 332 .

[0074] In some embodiments, the thickness of the second gate dielectric layer 331 is less than the thickness of the first gate dielectric layer 441. Since the second gate dielectric layer 331 needs to be broken down under a high voltage during a programming operation, setting the thickness of the second gate dielectric layer 331 to be less than the thickness of the first gate dielectric layer 441 can not only reduce the energy required to break down the anti-fuse unit, but also prevent the select transistor corresponding to the anti-fuse unit from being broken down, causing the select transistor to fail.

[0075] In the disclosed embodiment, the first end of the antifuse unit is electrically connected to the second source / drain 47 of the select transistor via a corresponding diode 32. When the first end of the antifuse unit is at a high voltage, the diode is cut off, and when the second source / drain 47 is at a high voltage, the diode is turned on. In other words, current can flow through the second source / drain 47 to the second end of the antifuse unit, but cannot flow through the second end of the antifuse unit to the second source / drain 47.

[0076] In the disclosed embodiment, the antifuse unit is connected to the second source and drain 47 of the select transistor via a diode 32. That is, no lightly doped region is provided beneath the antifuse unit. Consequently, when the second gate dielectric layer 331 of the antifuse unit is broken down, the resulting transient high current flows into the underlying first region 321. Furthermore, because current does not flow through the second end of the antifuse unit to the second source and drain, the transient high current cannot flow into the second region 322. In other words, when the second gate dielectric layer 331 of the antifuse unit is broken down, the diode 32 is cut off, thereby preventing erroneous breakdown between adjacent antifuse units.

[0077] In this disclosure, please continue to refer to Figure 2 and Figure 3 The selection transistor and the plurality of anti-fuse units are arranged in the same active region 31 , and the selection transistor and the anti-fuse units are sequentially spaced apart along the X-axis direction; the plurality of anti-fuse units are also sequentially spaced apart along the X-axis direction.

[0078] Since the programmable device in the embodiment of the present disclosure includes a selection transistor and multiple anti-fuse units, the area of ​​the programmable device can be reduced, and the coupling effect between the selection transistor and the anti-fuse unit can be reduced, thereby improving the performance of the programmable device.

[0079] It should be noted that the second region 322 of the diode 32 corresponding to the anti-fuse unit disposed adjacent to the selection transistor is shared with the second source and drain 47. In this way, the area of ​​the anti-fuse structure can be further reduced, thereby achieving miniaturization.

[0080] In some embodiments, see Figure 2 and Figure 3The bit line 48 is connected to the first source and drain of the select transistor, and the word line 36 is connected to the second end of the anti-fuse unit (i.e., the second gate conductive layer 332). The word line 36 is used to apply a high voltage to the second end of the anti-fuse unit during a programming operation, and the bit line 48 provides a low voltage to the first end of the anti-fuse unit during a programming operation. When the voltage difference between the first and second ends of the anti-fuse unit exceeds the breakdown voltage of the anti-fuse unit, the anti-fuse unit is broken down.

[0081] In some embodiments, see Figure 2 and Figure 3 The selection signal line 40 is connected to the gate of the selection transistor, specifically to the first gate conductive layer 442 of the selection transistor; the selection signal line 40 is used to apply voltage to the first gate conductive layer 442 of the selection transistor to turn on the selection transistor during programming operation or reading operation.

[0082] In the embodiment of the present disclosure, the material of the bit line 48, the word line 36 and the selection signal line 40 is any material with good conductivity, such as any one or more combinations of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium and copper.

[0083] In some embodiments, see Figure 2 The programmable device 200 further includes a metal layer 39 ; and a second region 322 of the diode 32 corresponding to the anti-fuse unit not adjacent to the selection transistor is connected to the second source and drain 47 through the metal layer 39 .

[0084] In some embodiments, see Figure 2 and Figure 3 The programmable device 200 further includes: a plurality of first conductive pillars 38 ; the first conductive pillars 38 are connected to the second region 322 , and the plurality of first conductive pillars 38 are commonly connected to the metal layer 39 .

[0085] In the embodiment of the present disclosure, the second end of the anti-fuse unit that is not adjacent to the select transistor can be connected to the second source / drain 47 of the select transistor via the metal layer 39. In this way, multiple anti-fuse units only require one select transistor to control them, which can reduce the area of ​​the programmable device 200 while maintaining the same number of anti-fuses, or increase the number of anti-fuse units while maintaining the same area, thereby improving the integration of the programmable device 200.

[0086] In some embodiments, see Figure 2 and Figure 3 , the programmable device 200 further includes:

[0087] The second conductive pillar 42 is connected between the first source and drain 45 and the bit line 48;

[0088] A first connection structure 43 is connected between the gate 44 of the selection transistor and the selection signal line 40;

[0089] The second connection structure 37 is connected between the second end of the anti-fuse unit and the word line 36 .

[0090] It should be noted that the metal layer 39 is located on the upper layer of the first conductive pillars 38, and the first conductive pillars 38 and the second conductive pillars 42 are located on the same layer. The material of the metal layer 39, the first conductive pillars 38, and the second conductive pillars 42 can be any one or more of tungsten, cobalt, platinum, palladium, ruthenium, and copper.

[0091] The first connection structure 43 and the second connection structure 37 are located on the same layer and are respectively located on the first gate conductive layer 442 and the second gate conductive layer 332. The first connection structure 43 is used to reduce the contact resistance between the gate 44 of the select transistor and the select signal line 40, and the second connection structure 37 is used to reduce the contact resistance between the second end of the antifuse unit and the word line 36, thereby reducing the voltage drop on the select signal line 40 and the word line 36 and reducing power consumption.

[0092] In some embodiments, see Figure 2 The select transistor further includes a lightly doped drain (LDD) 46 disposed in the active region 31 below the gate electrode 44 and connected to the first source / drain 45 and the second source / drain 47, respectively. The lightly doped drain 46 can weaken the drain electric field in the select transistor, thereby improving a series of short channel effects such as the hot electron degradation effect.

[0093] In some embodiments, see Figure 2 The selection transistor further includes a first spacer layer 41 at least arranged on the sidewalls of the first gate conductive layer 442 and the first gate dielectric layer 441. The first spacer layer 41 can, on the one hand, prevent heavily doped ions from being injected into the lightly doped drain region 46 and changing the structure of the lightly doped drain region 46 when heavily doping is performed to form the first source and drain 45 and the second source and drain 47. On the other hand, it can prevent the first gate conductive layer 442 from leaking electricity.

[0094] In some embodiments, see Figure 2 The anti-fuse unit further includes a second spacer 35 disposed at least on the sidewalls of the second gate conductive layer 332 and the second gate dielectric layer 331. The second spacer can at least prevent the second gate conductive layer 332 from leaking electricity.

[0095] In other embodiments, the second spacer 35 may not be provided in the anti-fuse unit.

[0096] It should be noted that the gate of the selection transistor and the anti-fuse unit are disposed in a dielectric layer 34 on the surface of the active region. The material of the dielectric layer 34 may be silicon dioxide, for example.

[0097] It should be noted that Figure 2 The programmable device 200 in FIG. 1 shows only three antifuse units. Figure 3 The programmable device 200 in FIG. 1 only shows eight anti-fuse units. In actual implementation, the programmable device 200 may include more anti-fuse units.

[0098] Another embodiment of the present disclosure further provides an operating method of a programmable device 200, which is applied to Figure 3 The programmable device 200 shown, Figure 4 for Figure 3 The equivalent circuit diagram of the programmable device 200 is shown below. Figure 3 and Figure 4 The following describes an operating method of the programmable device 200 according to an embodiment of the present disclosure. The operating method includes:

[0099] During a programming operation, the bit line 48 corresponding to the anti-fuse cell to be programmed is set to a first voltage, a second voltage is applied to the selection signal line 40, and a third voltage is applied to the word line 36 corresponding to the anti-fuse cell to be programmed, so as to break down the anti-fuse cell to be programmed. At the same time, the first voltage is applied to other word lines 36 in the programmable device so as not to break down other anti-fuse cells except the anti-fuse cell to be programmed. The anti-fuse cell to be programmed is any one of the multiple anti-fuse cells.

[0100] During the reading operation, the bit line 48 corresponding to the anti-fuse unit to be read is set to a first voltage, a second voltage is applied to the selection signal line 40, and a fourth voltage is applied to the word line 36 corresponding to the anti-fuse unit to be read to read the data in the anti-fuse unit to be read. At the same time, the first voltage is applied to other word lines 36 in the programmable device; wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage; the first voltage is zero voltage or ground voltage; the difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse unit to be programmed; and the difference between the second voltage and the first voltage is greater than or equal to the turn-on voltage of the selection transistor.

[0101] In an embodiment of the present disclosure, when programming an anti-fuse unit that needs to be programmed, the first voltage is zero voltage or ground voltage, and the difference between the second voltage and the first voltage is greater than or equal to the turn-on voltage of the selection transistor, so that the selection transistor can be turned on at the second voltage; for example, the second voltage can be 1.1 to 3V. The difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse unit that needs to be programmed and is less than the breakdown voltage of the selection transistor, so that the anti-fuse unit that needs to be broken down can be broken down at the third voltage without breaking down the selection transistor. Here, the third voltage can range from 4 to 5.5V, for example, it can be 4.3V, 4.8V or 5.4V, etc. When reading the anti-fuse unit that needs to be read, the fourth voltage is used to provide a read current, and the fourth voltage can be, for example, the power supply voltage Vdd.

[0102] Below, Figure 4 Taking the anti-fuse unit C0 in the programmable device in FIG. 1 as an example, the specific operation process of the programmable device is described.

[0103] During programming, a first voltage of 0V is applied to the bit line BL, and a second voltage of 1.1V to 3V is applied to the gate X gate of the select transistor to turn on the select transistor. A third voltage of 4 to 5.5V is applied to the word line WL3 corresponding to the anti-fuse cell C0. At this point, the voltage difference across the anti-fuse cell C0 is 4 to 5.5V, which can break down the first gate dielectric layer of the anti-fuse cell C0, completing the programming process. Simultaneously, a first voltage is applied to all word lines in the programmable device except for word line WL3, preventing breakdown of the other anti-fuses.

[0104] During a read operation, a first voltage of 0V is applied to the bit line BL, and a second voltage of 1.1V to 3V is applied to the gate X gate of the select transistor to turn on the select transistor. The power supply voltage Vdd is then applied to the word line WL3 corresponding to the anti-fuse cell C0 as a third voltage. This causes a large current to flow through the bit line BL, enabling the read operation. Simultaneously, a first voltage is applied to all word lines in the programmable device except for word line WL3, preventing current from flowing through the other anti-fuse cells.

[0105] It should be noted that in the embodiment of the present disclosure, there is no other doped region, that is, no LDD, in the first region 321 below the anti-fuse unit adjacent to the anti-fuse unit C0. The diode below the anti-fuse unit C0 includes a reverse PN junction and is cut off. In this way, the transient large current generated after the anti-fuse unit C0 is broken down cannot flow to the second region 322 through the first region 321. Therefore, even if the anti-fuse unit adjacent to the anti-fuse unit C0 is also broken down, the reading process of the anti-fuse unit C0 will not affect the adjacent anti-fuse units.

[0106] In another embodiment of the present disclosure, Figure 5 A schematic diagram of the structure of a programmable device array provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the programmable device array 400 includes:

[0107] A plurality of programmable devices 200 as described in the above embodiments are arranged in sequence along the second direction (Y-axis direction); wherein the gates 44 of a row of selection transistors arranged along the second direction are connected to each other; and the second ends of a row of anti-fuse units arranged along the second direction are connected to each other.

[0108] In some embodiments, see Figure 5 , the gates 44 of the selection transistors in a row arranged along the second direction are connected to the same selection signal line 40 ; the second ends of the anti-fuse units in a row arranged along the second direction are connected to the same word line 36 .

[0109] In the disclosed embodiment, the gates 44 of the select transistors arranged in a row along the second direction are interconnected and connected to the same select signal line 40. This allows multiple select transistors in the same row to be turned on or off via a single control terminal. The second ends of the antifuse cells in a row along the second direction are interconnected and connected to the same word line 36. This allows simultaneous application of programming or reading voltages to multiple antifuse cells in the same row. This simplifies the wiring design of the programmable device array and reduces manufacturing costs.

[0110] In some embodiments, the first gate dielectric layer 331 in the plurality of anti-fuse units arranged along the X-axis direction and the Y-axis direction can have the same size in the X-axis direction. This can avoid the voltage difference being too large when different anti-fuse units are broken down, making it impossible to break down a row of anti-fuse units through the same word line 36.

[0111] In other embodiments, the sizes of the first gate dielectric layers 331 in the plurality of anti-fuse units arranged along the X-axis direction and the Y-axis direction may also be unequal.

[0112] The programmable device 200 in the programmable device array 400 provided in the embodiment of the present disclosure has a structure similar to that of the programmable device 200 in the above embodiment. For technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0113] The embodiments of the present disclosure provide a programmable device array including a plurality of programmable devices. Since the programmable devices have a small area, the area of ​​the programmable device array is relatively small.

[0114] It should be noted that Figure 5Only four columns of programmable devices 200 are shown in the programmable device array 400 . In actual implementation, the programmable device array 400 may include more columns of programmable devices 200 .

[0115] Another embodiment of the present disclosure provides an operating method of a programmable device array 400, which is applied to Figure 5 The programmable device array 400 shown, Figure 6 for Figure 5 The equivalent circuit diagram of the programmable device array 400 is shown below. Figure 5 and Figure 6 The following describes an operating method of the programmable device array 400 according to an embodiment of the present disclosure. The operating method includes:

[0116] During a programming operation, a bit line 48 corresponding to an anti-fuse unit to be programmed is set to a first voltage, a second voltage is applied to a selection signal line 40, and a third voltage is applied to a word line 36 corresponding to the anti-fuse unit to be programmed, so as to break down the device to be programmed. At the same time, a first voltage is applied to other word lines 36 in the programmable device, and a fifth voltage is applied to other bit lines 48 in the programmable device, so as not to break down other anti-fuse units except the anti-fuse unit to be programmed. The anti-fuse unit to be programmed is any one of the multiple anti-fuse units.

[0117] During the reading operation, the bit line 48 corresponding to the anti-fuse unit to be read is set to the first voltage, the second voltage is applied to the selection signal line 40, and the fourth voltage is applied to the word line 36 corresponding to the anti-fuse unit to be read, so as to read the data in the anti-fuse unit to be read. At the same time, the first voltage is applied to the other word lines in the programmable device; and the fourth voltage is applied to the other bit lines in the programmable device; wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage; the first voltage is zero voltage or ground voltage; the difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse unit to be programmed; the difference between the third voltage and the fifth voltage is less than the breakdown voltage of any anti-fuse unit in the programmable device; the difference between the second voltage and the first voltage is greater than or equal to the turn-on voltage of the selection transistor.

[0118] In the disclosed embodiment, when programming an anti-fuse unit to be programmed, the first voltage is zero voltage or ground voltage, the difference between the second voltage and the first voltage is greater than or equal to the turn-on voltage of the select transistor, so that the select transistor can be turned on at the second voltage; for example, the second voltage can be 1.1 to 3V; the difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse unit to be programmed and less than the breakdown voltage of the select transistor, so that the anti-fuse unit to be broken down can be broken down at the third voltage without breaking down the select transistor. Here, the third voltage can range from 4 to 5.5V, for example, 4.3V, 4.8V, or 5.4V. At this time, in order to prevent other anti-fuse cells adjacent to the anti-fuse cell to be programmed from being accidentally broken down, the bit lines 48 of the other anti-fuse cells adjacent to the anti-fuse cell to be programmed need to be set to the fifth voltage, and the word lines 36 of the other anti-fuse cells adjacent to the anti-fuse cell to be programmed need to be set to the first voltage, so that the difference between the fifth voltage and the first voltage is less than the breakdown voltage of any anti-fuse cell in the programmable device array 400. Here, the fifth voltage can be, for example, 2.5V.

[0119] When the anti-fuse unit to be read is read, the fourth voltage is used to provide a read current. The fourth voltage may be, for example, a power supply voltage Vdd.

[0120] Below, Figure 6 The specific operation process of the programmable device array 400 is described by taking the anti-fuse unit C1 in the programmable device array in FIG. 4 as an example.

[0121] During programming, a first voltage of 0V is applied to the bit line BL2 corresponding to the anti-fuse cell C1, and a second voltage of 1.1V to 3V is applied to the gate X gate of the select transistor to turn on all select transistors. A third voltage of 4 to 5.5V is applied to the word line WL3 corresponding to the anti-fuse cell C1. At this time, the voltage difference across the anti-fuse cell C1 is 4 to 5.5V, which can break down the first gate dielectric layer of the anti-fuse cell C1, thus completing the programming process. Simultaneously, a first voltage is applied to the other word lines in the programmable device (e.g., word lines WL1, WL2, and WL4) except for word line WL3, and a fifth voltage of 2.5V is applied to the other BL lines except for bit line BL2 (e.g., bit lines BL1, BL3, and BL4) to prevent breakdown of the other anti-fuses.

[0122] In the disclosed embodiment, when programming antifuse C1, although the bit line BL2 of antifuse C2 and antifuse C4 has a low voltage, the word line WL2 and word line WL4 are also at low voltage, resulting in no voltage difference. Therefore, antifuse C2 and antifuse C4 will not erroneously breakdown. Furthermore, the first region 321 below antifuse C1 lacks an LDD, forming a PN junction. Therefore, the transient current generated by antifuse C1 after breakdown does not affect antifuse C2 and antifuse C4. Therefore, when antifuse C1 is broken down, it does not cause erroneous breakdown of surrounding antifuses.

[0123] During a read operation, a first voltage of 0V is applied to bit line BL2 corresponding to antifuse cell C1, and a second voltage of 1.1V to 3V is applied to the gate X gate of the select transistor to turn on the select transistor. A third voltage, the power supply voltage Vdd, is applied to word line WL3 corresponding to antifuse cell C0. This causes a significant current to flow through bit line BL, enabling the read operation. Simultaneously, a first voltage is applied to the remaining word lines (e.g., word lines WL1, WL2, and WL4) in the programmable device except for word line WL3. A fourth voltage is applied to the remaining bit lines (e.g., bit lines BL1, BL3, and BL4) in the programmable device except for bit line BL2. This prevents current from flowing through the remaining antifuse cells.

[0124] In the disclosed embodiment, when antifuse cell C1 is read, although word line WL3 in antifuse cells C5 and C3 is at Vdd, bit lines BL1 and BL3 are also at Vdd, and no current flows there. Therefore, when antifuse cell C1 is read after programming, it does not affect the surrounding antifuses or cause leakage.

[0125] Another embodiment of the present disclosure further provides a memory, comprising the programmable device array 400 (see Figure 5 ), the programmable device array 400 includes the programmable device 200 in any of the aforementioned embodiments (refer to Figure 3 );

[0126] Among them, the programmable device 200 includes: a bit line 48; a selection transistor, the first source and drain 45 of the selection transistor is electrically connected to the bit line 48; a selection signal line 40, the selection signal line 40 is electrically connected to the gate 44 of the selection transistor; a plurality of diodes 32; a plurality of anti-fuse units, the first end of the anti-fuse unit is electrically connected to the second source and drain 47 of the selection transistor through the corresponding diode 32; and a plurality of word lines 36, the word lines 36 are electrically connected to the second end of the corresponding anti-fuse unit.

[0127] In some embodiments, the memory may include but is not limited to random access memory (RAM), such as dynamic random access memory (DRAM).

[0128] In the embodiment of the present disclosure, the memory includes the aforementioned programmable device array 400. Since the aforementioned programmable device array 400 has a relatively small area, the integration of the memory can be improved, thereby effectively increasing the storage capacity of the memory and improving its performance.

[0129] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in non-targeted ways. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0130] The features disclosed in several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0131] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A programmable device, characterized in that: include: bit lines; a selection transistor, wherein a first source and a drain of the selection transistor are electrically connected to the bit line; a selection signal line electrically connected to a gate of the selection transistor; Multiple diodes; a plurality of anti-fuse units, wherein a first end of each anti-fuse unit is electrically connected to the second source and drain of the selection transistor via the corresponding diode; a plurality of word lines, wherein the word lines are electrically connected to the second ends of the corresponding anti-fuse units; The diode is provided in the substrate and includes a first region provided adjacent to the anti-fuse unit and a second region provided adjacent to the first region; The second region of the diode corresponding to the anti-fuse unit disposed adjacent to the selection transistor is shared by the second source and drain.

2. The device according to claim 1, characterized in that Also includes: Metal layer; The second region of the diode corresponding to the anti-fuse unit not adjacent to the selection transistor is connected to the second source and drain through the metal layer.

3. The device according to claim 2, characterized in that Also includes: a plurality of first conductive pillars; The first conductive pillar is connected to the second region, and a plurality of the first conductive pillars are commonly connected to the metal layer.

4. The device according to claim 3, characterized in that The selection transistor and the plurality of anti-fuse units are arranged in the same active area and spaced apart in sequence along the first direction; the programmable device further includes: a second conductive column connected between the first source and drain and the bit line; a first connection structure connected between the gate of the selection transistor and the selection signal line; The second connection structure is connected between the second end of the anti-fuse unit and the word line.

5. The device according to claim 4, characterized in that The selection transistor includes a first gate dielectric layer and a first gate conductive layer located on a surface of the first gate dielectric layer; The anti-fuse unit includes a second gate dielectric layer and a second gate conductive layer located on a surface of the second gate dielectric layer; wherein the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer.

6. The device according to claim 4 or 5, characterized in that The first region and the active region are N-type doped; the second region and the first source and drain are P-type doped.

7. A programmable device array, characterized in that: include: A plurality of programmable devices according to any one of claims 1 to 6 arranged sequentially along a second direction; The gates of the selection transistors in a row arranged along the second direction are connected to each other; and the second ends of the anti-fuse units in a row arranged along the second direction are connected to each other.

8. The array according to claim 7, characterized in that The gates of the selection transistors in a row arranged along the second direction are connected to the same selection signal line; The second ends of the anti-fuse units in a row arranged along the second direction are connected to the same word line.

9. A method for operating a programmable device, characterized in that: Applicable to the programmable device according to any one of claims 1 to 6; the method comprising: During a programming operation, a bit line corresponding to an anti-fuse unit to be programmed is set to a first voltage, a second voltage is applied to the selection signal line, and a third voltage is applied to a word line corresponding to the anti-fuse unit to be programmed, so as to break down the anti-fuse unit to be programmed. At the same time, the first voltage is applied to the other word lines in the programmable device so as not to break down the other anti-fuse units except the anti-fuse unit to be programmed. The anti-fuse unit to be programmed is any one of the plurality of anti-fuse units. During a read operation, the bit line corresponding to the anti-fuse unit to be read is set to the first voltage, a second voltage is applied to the selection signal line, and a fourth voltage is applied to the word line corresponding to the anti-fuse unit to be read, so as to read data in the anti-fuse unit to be read. At the same time, the first voltage is applied to the other word lines in the programmable device; Among them, the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage; the first voltage is zero voltage or ground voltage; the difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse unit to be programmed; the difference between the second voltage and the first voltage is greater than or equal to the turn-on voltage of the selection transistor.

10. A method for operating a programmable device array, characterized in that: Applicable to the programmable device according to any one of claims 7 or 8; the method comprising: During a programming operation, a bit line corresponding to an anti-fuse unit to be programmed is set to a first voltage, a second voltage is applied to the selection signal line, and a third voltage is applied to a word line corresponding to the anti-fuse unit to be programmed, so as to breakdown the device to be programmed. At the same time, the first voltage is applied to the other word lines in the programmable device array, and a fifth voltage is applied to the other bit lines in the programmable device array, so as not to breakdown the other anti-fuse units except the anti-fuse unit to be programmed. The anti-fuse unit to be programmed is any one of the plurality of anti-fuse units. During a read operation, the bit line corresponding to the anti-fuse unit to be read is set to the first voltage, a second voltage is applied to the selection signal line, and a fourth voltage is applied to the word line corresponding to the anti-fuse unit to be read, so as to read data in the anti-fuse unit to be read. At the same time, the first voltage is applied to the other word lines in the programmable device array; and the fourth voltage is applied to the other bit lines in the programmable device. Among them, the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage; the first voltage is zero voltage or ground voltage; the difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the anti-fuse unit to be programmed; the difference between the third voltage and the fifth voltage is less than the breakdown voltage of any one of the anti-fuse units in the programmable device array; the difference between the second voltage and the first voltage is greater than or equal to the turn-on voltage of the selection transistor.

11. A memory, characterized in that: Comprising a programmable device array as claimed in claim 7 or 8.

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