Multi-layer stacked packaging method of edge AI computing memory chip and related equipment

Abstract

The invention relates to a multi-layer stacking packaging method of edge AI computing and storage chips and related equipment, and the method comprises the following steps: obtaining a preset function demand of the edge AI computing and storage chips, and determining a chip architecture of the edge AI computing and storage chips and a sequence arrangement corresponding to the chip architecture based on the function demand; carrying out TSV etching on a preset wafer through a deep reactive ion etching technology to obtain a through hole array wafer; cutting the through hole array wafer to obtain an independent cutting chip; performing cooling channel construction on the independent cutting chip to obtain a cooling function chip; carrying out multi-chip integration and packaging on the cooling function chips based on the chip architecture and the sequential arrangement corresponding to the chip architecture to obtain edge AI calculation and storage chips; the technical problems that heat in the chips is difficult to dissipate and the chips are easily overheated due to the fact that the heat dissipation channels become long when the stacked chips are close to each other are solved.

Description

Technical Field

[0001] The present invention relates to the field of edge AI computing and storage chip technology, and in particular to a multi-layer stacking packaging method and related equipment for edge AI computing and storage chips. Background Art

[0002] Edge AI computing has developed rapidly in recent years, and has put forward higher and higher requirements for low power consumption, high performance, and miniaturized computing power. When traditional von Neumann architecture chips process large-scale data, especially complex AI-related calculations, data needs to be frequently transferred between the processor and the memory, resulting in serious power consumption and latency problems, which is called the "storage wall" bottleneck. In order to break through this bottleneck, storage-computing integrated technology came into being. It closely combines storage units and computing units, and performs calculations inside the storage units, thereby greatly reducing data transfer, reducing power consumption and latency, and improving computing efficiency. This is crucial for edge AI devices such as autonomous driving, smartphones, and IoT devices, because these devices usually have very strict requirements on power consumption and real-time performance.

[0003] However, as the complexity of edge AI applications continues to increase, the demand for computing power has also increased dramatically. The computing power improvement of a single chip is subject to the slowdown of Moore's Law and power consumption limitations, so multi-chip stacking packaging technology has become the key to further improving computing power. By integrating multiple chips in one package in a three-dimensional stacking manner, the chip's integration and interconnection bandwidth can be significantly improved, thereby achieving higher computing power density and lower system power consumption. However, multi-chip stacking also brings new challenges, such as heat dissipation. The stacked chips are close to each other, and the heat dissipation channel becomes longer, making it difficult for the heat inside the chip to dissipate, which can easily cause the chip to overheat and affect performance and reliability.

[0004] Therefore, how to effectively solve the heat dissipation problem in multi-chip stacking packaging has become the key to realizing high-performance, low-power edge AI computing and storage chips. The "multi-layer stacking packaging method for edge AI computing and storage chips" proposed in the above patent is aimed at this problem, and attempts to improve the heat dissipation efficiency by building cooling channels after chip cutting, thereby realizing the manufacture of high-performance edge AI computing and storage chips. This is of great significance for promoting the development of edge AI technology and meeting the growing demand for computing power. Summary of the invention

[0005] The main purpose of the present invention is to provide a multi-layer stacking packaging method and related equipment for edge AI computing and storage chips, which solves the technical problem that the stacked chips are close to each other, the heat dissipation channel becomes longer, and the heat inside the chip is difficult to dissipate, which easily causes the chip to overheat.

[0006] To achieve the above object, the present invention provides a multi-layer stacking packaging method for an edge AI computing memory chip, comprising the following steps: Obtaining the functional requirements of a preset edge AI computing and storage chip, and determining the chip architecture of the edge AI computing and storage chip and the order of arrangement corresponding to the chip architecture based on the functional requirements; Through deep reactive ion etching technology, TSV etching is performed on the preset wafer to obtain a through-hole array wafer; Cutting the through hole array wafer to obtain independently cut chips; and constructing cooling channels for the independently cut chips to obtain cooling function chips; Based on the chip architecture and the sequential arrangement corresponding to the chip architecture, the cooling function chip is integrated and packaged into multiple chips to obtain an edge AI computing and storage chip.

[0007] Furthermore, the obtaining of the functional requirements of the preset edge AI computing and storage chip, and determining the chip architecture of the edge AI computing and storage chip and the sequence arrangement corresponding to the chip architecture based on the functional requirements, includes: Obtain a preset target application scenario of the AI ​​computing and storage chip, and determine the functional requirements of the AI ​​computing and storage chip based on the target application scenario; wherein the functional requirements include throughput, latency, and power consumption; Performing a hardware architecture search based on the functional requirements by using a preset neural network search algorithm to obtain a candidate architecture set; The candidate architecture set is screened by a preset power consumption evaluation model to obtain a low power consumption architecture; Based on the functional requirements and the target application scenarios, an on-chip storage architecture is designed for the low-power architecture to determine the chip architecture of the edge AI computing and storage chip and the corresponding sequence arrangement of the chip architecture; wherein the on-chip storage architecture design includes determining the type, capacity, bit width, structure of the memory and the data interaction method with the computing unit to meet the data access mode and bandwidth requirements of the target scenario application.

[0008] Furthermore, the method of performing TSV etching on a preset wafer by deep reactive ion etching technology to obtain a through-hole array wafer includes: Based on the optical interferometry method, a thickness measurement is performed on a preset wafer to obtain a wafer thickness map, and a thickness uniformity analysis is performed on the wafer thickness map to obtain a wafer with uniform thickness; Performing TSV initial etching on the wafer with uniform thickness by using deep reactive ion etching technology to obtain an initial etched wafer, and performing sidewall passivation treatment on the initial etched wafer to obtain a passivated wafer; Depositing a barrier layer on the passivation wafer by atomic layer deposition technology to obtain a barrier layer wafer, and performing photolithography patterning on the barrier layer wafer to obtain a patterned wafer; Performing deep hole etching on the patterned wafer based on a Bosch etching process to obtain a deep hole wafer; An insulating layer is deposited on the deep hole wafer by chemical vapor deposition technology to obtain an insulating layer wafer, and the insulating layer wafer is subjected to chemical mechanical polishing to obtain a through hole array wafer.

[0009] Furthermore, the through hole array wafer is cut to obtain independent cut chips; and cooling channels are constructed for the independent cut chips to obtain cooling function chips, including: Scanning the internal structure of the through-hole array wafer by a preset three-dimensional X-ray tomography technology to obtain a three-dimensional structure distribution map, and planning a cutting path for the through-hole array wafer based on the three-dimensional structure distribution map to obtain a cutting path; Using a multi-wavelength laser cutting technology, the through hole array wafer is cut in layers based on the cutting path to obtain preliminary cut chips, and the preliminary cut chips are chamfered to obtain independent cut chips; The independently cut chip is subjected to atomic-level flattening of the surface by atomic layer etching technology to obtain a flattened chip; Using microfluidic channel design technology to construct cooling channel patterns on the flattened chip to obtain a microchannel structure, and anisotropically etching the microchannel structure to obtain a three-dimensional channel network; Performing super-hydrophilic surface modification on the three-dimensional flow channel network to obtain a surface wetting characteristic chip, and performing nano-scale functional coating deposition on the surface wetting characteristic chip to obtain a fluid dynamics chip; Using micro-scale heat flow analysis technology, the heat transfer performance of the fluid dynamics chip is evaluated to obtain thermal resistance and temperature rise distribution data. If the thermal resistance and temperature rise distribution data are within a preset safe working range, a cooling function chip is obtained; If not, the thermal resistance and temperature rise distribution data are deeply analyzed by a preset genetic algorithm to obtain optimized cooling channel structural parameters, and the fluid dynamics chip is optimized based on the optimized cooling channel structural parameters to obtain a cooling function chip.

[0010] Furthermore, the internal structure of the through hole array wafer is scanned by a preset three-dimensional X-ray tomography technology to obtain a three-dimensional structure distribution map, and a cutting path is planned for the through hole array wafer based on the three-dimensional structure distribution map to obtain a cutting path, including: Performing phase contrast X-ray tomography scanning on the through hole array wafer to obtain an original diffraction image, and performing phase reconstruction on the original diffraction image to obtain a multi-layer diffraction spectrum; Digitally reconstructing the multi-layer diffraction spectrum by spatial frequency domain filtering technology to obtain density distribution data, and performing three-dimensional voxel reconstruction on the density distribution data to obtain a voxel distribution map; The voxel distribution map is three-dimensionally reconstructed by a reverse projection algorithm to obtain a three-dimensional structure distribution map, and a cutting area is planned for the three-dimensional structure distribution map to obtain cutting area parameters; wherein the cutting area parameters include a cutting critical point, a stress sensitive area and a material boundary line; The topology optimization technology is used to plan the cutting path of the through hole array wafer based on the cutting area parameters to obtain a cutting path.

[0011] Furthermore, the cooling function chip is integrated and packaged into multiple chips based on the chip architecture and the sequence arrangement corresponding to the chip architecture to obtain an edge AI computing and storage chip, including: Arranging the cooling function chips based on the chip architecture and the sequence arrangement corresponding to the chip architecture to obtain arranged chips; The arranged chips are interconnected by using micro-bump bonding technology to obtain bump interconnected chips, and the bump interconnected chips are bottom-filled to obtain bottom-filled chips; Stacking the bottom-filled chips by high-density three-dimensional stacking technology to obtain a three-dimensional chip stack; Packaging the three-dimensional chip stack to obtain a WLP packaged chip, and wire bonding the WLP packaged chip to obtain a wire-bonded chip; Performing RDL construction on the wire bonding chip by using redistribution layer technology to obtain an RDL chip, and performing electrical testing on the RDL chip to obtain electrical test results; If the electrical test results show that there are RDL chips that do not meet the preset standards, the RDL chips that do not meet the preset standards are removed to obtain qualified RDL chips; The qualified RDL chip is packaged at the system level based on the system-level packaging technology to obtain an edge AI computing and storage chip.

[0012] Furthermore, the arrangement chips are interconnected by using micro-bump bonding technology to obtain bump interconnected chips, and the bump interconnected chips are bottom-filled to obtain bottom-filled chips, including: Sputtering a UBM metal layer on the arranged chip to obtain a UBM structure chip; Growing micro-bumps on the UBM structure chip by ultrasonic assisted electroplating technology to obtain a micro-bump chip; Performing chip alignment on the micro-bump chip to obtain an aligned micro-bump chip, and performing low-temperature pre-bonding on the aligned micro-bump chip to obtain a preliminary bonded chip; Performing thermal compression bonding on the preliminary bonded chip based on thermal compression bonding technology to obtain a bump interconnection chip; The bump interconnect chip is bottom-filled by utilizing capillary action to obtain a filled bump interconnect chip, and the filled bump interconnect chip is solidified to obtain a bottom-filled chip.

[0013] The present invention also provides a multi-layer stacking packaging device for an edge AI computing and storage chip, comprising: An acquisition module, used to acquire the functional requirements of a preset edge AI computing and storage chip, and determine the chip architecture of the edge AI computing and storage chip and the order of arrangement corresponding to the chip architecture based on the functional requirements; A through-hole module is used to perform TSV etching on a preset wafer by deep reactive ion etching technology to obtain a through-hole array wafer; A cutting module is used to cut the through hole array wafer to obtain independently cut chips; and to construct cooling channels for the independently cut chips to obtain cooling function chips; The packaging module is used to integrate and package the cooling function chip into multiple chips based on the chip architecture and the sequential arrangement corresponding to the chip architecture to obtain an edge AI computing and storage chip.

[0014] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0015] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0016] The present invention provides a multi-layer stacking packaging method for edge AI computing and storage chips, including the following steps: obtaining the functional requirements of a preset edge AI computing and storage chip, and determining the chip architecture of the edge AI computing and storage chip and the sequence arrangement corresponding to the chip architecture based on the functional requirements; performing TSV etching on a preset wafer through deep reactive ion etching technology to obtain a through-hole array wafer; cutting the through-hole array wafer to obtain an independently cut chip; and constructing a cooling channel for the independently cut chip to obtain a cooling function chip; based on the chip architecture and the sequence arrangement corresponding to the chip architecture, the cooling function chip is integrated and packaged into multiple chips to obtain an edge AI computing and storage chip; through the above-mentioned technical means, the stacked chips are close to each other, the heat dissipation channel becomes longer, and the heat inside the chip is difficult to dissipate, which easily causes the chip to overheat. The technical effect of realizing the multi-chip stacking packaging can shorten the interconnection distance between chips, thereby increasing the chip interconnection bandwidth, reducing data transmission delay, and improving the overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the steps of a multi-layer stacking packaging method of an edge AI computing and storage chip in one embodiment of the present invention; Figure 2 This is a structural block diagram of a multi-layer stacking packaging device of an edge AI computing and storage chip in one embodiment of the present invention; Figure 3 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0018] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] like Figure 1 As shown, Figure 1 This is a schematic diagram of the steps of a multi-layer stacking packaging method for edge AI computing and storage chips in one embodiment of the present invention; In one embodiment of the present invention, a multi-layer stacking packaging method of an edge AI computing memory chip is provided, comprising the following steps: Step S1, obtain the functional requirements of a preset edge AI computing and storage chip, and determine the chip architecture of the edge AI computing and storage chip and the order of arrangement corresponding to the chip architecture based on the functional requirements.

[0021] Specifically, to achieve the step of "obtaining the functional requirements of the preset edge AI computing and storage chip, and determining the chip architecture of the edge AI computing and storage chip and the order of the chip architecture based on the functional requirements", it is necessary to first clarify the functional requirements of the target edge AI application scenario. For example, in the field of autonomous driving, edge AI chips need to process a large amount of data from sensors such as cameras and radars in real time, and perform complex calculations such as target detection and path planning, so they need high computing power, low latency and low power consumption. In the field of smart home, edge AI chips may focus more on functions such as voice recognition and image processing, with relatively low requirements for computing power, but are more sensitive to cost and power consumption. Therefore, for different application scenarios, it is necessary to clarify specific performance indicator requirements, such as computing power (TOPS), power consumption (W), latency (ms), memory size, etc. After clarifying the functional requirements, it is necessary to determine the architecture of the edge AI computing and storage chip based on these requirements. For example, if high computing power is required, a multi-core processor architecture or a dedicated AI accelerator architecture can be used; if low power consumption is required, a storage and computing integrated architecture can be used to reduce data handling; if a large amount of data needs to be processed, it is necessary to consider increasing the on-chip storage capacity. At the same time, it is also necessary to determine the arrangement order of each module in the chip architecture. This is closely related to the subsequent stacking package. A reasonable arrangement order can optimize the interconnection between chips, reduce the signal transmission distance, and reduce power consumption and latency. For example, the computing unit and the storage unit can be placed close to each other to reduce the overhead of data handling. In addition, the order of chip architecture also needs to consider the needs of heat dissipation design. For example, a module with a larger heat generation can be placed close to the cooling channel to dissipate heat more effectively. For example, in the scenario of autonomous driving, the convolutional neural network accelerator used to process image data usually has high power consumption, so it can be placed close to the cooling channel, while the control unit with relatively low power consumption can be placed away from the cooling channel. In the smart home scenario, the chip used for voice recognition has relatively low power consumption, so it can be placed in the center of the stack, while other modules can be placed on the periphery. In this way, the optimal chip architecture and stacking order can be designed according to different application scenarios and functional requirements to achieve the best balance between performance and power consumption.

[0022] Step S2, performing TSV etching on the preset wafer by deep reactive ion etching technology to obtain a through hole array wafer.

[0023] Specifically, the core of the step of "using deep reactive ion etching technology to perform TSV etching on the preset wafer to obtain a through-hole array wafer" is to use deep reactive ion etching (DRIE) technology to manufacture a large number of TSVs (Through-Silicon Via) on the wafer, and finally form a through-hole array wafer. Deep reactive ion etching is an advanced dry etching technology that combines the advantages of chemical etching and physical etching. It can etch deep holes with high aspect ratio and regular shape on silicon wafers, which is the key technology required for manufacturing TSV. The preset wafer usually refers to a silicon wafer that has undergone some pre-treatment steps, such as cleaning and oxidation, to prepare for subsequent TSV etching. The DRIE process usually adopts the Bosch process, which is a cyclic etching method that alternates etching cycles and passivation cycles. In the etching cycle, the active ions in the plasma will etch the silicon to form through holes; in the passivation cycle, a protective film will be deposited on the etching surface to prevent the sidewalls from being etched. This alternating etching and passivation cycle can ensure that a high aspect ratio TSV is etched and the verticality and smoothness of the sidewalls are maintained. In actual operation, a layer of photoresist is first coated on the surface of the wafer, and then the pre-designed TSV pattern is transferred to the photoresist using photolithography. Next, the exposed silicon is etched using deep reactive ion etching technology with the photoresist pattern as a mask. After etching, the remaining photoresist is removed to obtain the desired TSV through-hole array. During the etching process, the etching parameters, such as etching time, gas flow, power, etc., need to be precisely controlled to ensure that the size and shape of the TSV meet the design requirements. In addition, the etched TSV needs to be cleaned and inspected to remove residues and ensure the quality of the TSV. The resulting through-hole array wafer contains a large number of TSVs, which can be used for electrical connections between different levels inside the chip, such as connecting different chips, connecting chips and substrates, etc. Through TSV technology, three-dimensional chip integration can be achieved, improving the integration and performance of the chip. For example, in high-performance autonomous driving AI chips, high-speed interconnections need to be established between different functional modules inside the chip, and TSV technology can provide high-bandwidth, low-latency interconnection channels. A large number of TSVs are etched on the wafer to form a dense array of through holes, which are used to connect modules such as processor cores, memory, and high-speed interfaces. This makes data transmission inside the chip more efficient, thereby improving the overall performance of the chip. Similarly, in low-power application scenarios such as smart homes, TSV technology can also be used for interconnection within the chip, thereby increasing the integration of the chip and reducing power consumption. Therefore, TSV etching technology is crucial to the manufacture of various edge AI computing and storage chips, and it provides a key connection channel for the three-dimensional integration of chips.

[0024] Step S3, cutting the through hole array wafer to obtain independently cut chips; and constructing cooling channels for the independently cut chips to obtain cooling function chips.

[0025] Specifically, the step of "cutting the through-hole array wafer to obtain independently cut chips; and constructing cooling channels for the independently cut chips to obtain cooling function chips" first involves cutting the wafer that has completed the TSV through-holes and dividing it into independent chip units. These independently cut chips already have a preset TSV through-hole array for subsequent chip interconnection. Then, cooling channels are constructed on these independently cut chips, which is the key to the patented method and an important feature that distinguishes it from traditional packaging methods. The construction method of the cooling channel can adopt different methods according to specific needs. For example, microchannel technology can be used to etch tiny fluid channels on the back or inside of the chip for the circulation of coolant to take away the heat generated by the chip. Alternatively, heat dissipation structures such as micro heat sinks or heat spreaders can be bonded to the surface of the chip to enhance the heat dissipation effect. After the cooling channel is constructed, the independently cut chip is transformed into a chip with cooling function, which provides a good heat dissipation foundation for subsequent multi-chip stacking. This method of constructing cooling channels after cutting can more effectively control the temperature of each chip and avoid mutual influence between chips after stacking, resulting in uneven heat dissipation. For example, in the scenario of autonomous driving, due to the need to process a large amount of image data, the power consumption of AI computing chips is high and the heat generated is also large. By building an independent cooling channel on each chip, the temperature of each chip can be effectively controlled to ensure that the chip runs stably under high load. In the smart home scenario, although the power consumption of the chip is relatively low, it will still generate a certain amount of heat when running for a long time. By pre-building cooling channels, the service life of the chip can be effectively extended and the reliability of the equipment can be improved. Therefore, this method of building cooling channels after cutting is crucial to improving the heat dissipation efficiency of multi-chip stacked packages, and can effectively solve the heat dissipation problem of stacked chips, thereby realizing high-performance, low-power edge AI computing and storage chips.

[0026] Step S4, based on the chip architecture and the sequential arrangement corresponding to the chip architecture, the cooling function chip is integrated and packaged into multiple chips to obtain an edge AI computing and storage chip.

[0027] Specifically, the step of "integrating and packaging the cooling function chip into multiple chips based on the chip architecture and the sequence arrangement corresponding to the chip architecture to obtain an edge AI computing and storage chip" is to stack and integrate the independent chips with cooling function prepared in the previous step according to the pre-designed chip architecture and sequence, and finally package them into a complete edge AI computing and storage chip. In this process, the stacking order of the chips is crucial, which directly affects the interconnection efficiency and heat dissipation performance between chips. According to the previously determined chip architecture, chips with different functions (such as computing units, storage units, control units, etc.) are stacked together in a specific order and interconnected using the previously reserved TSV through holes. For example, the computing unit and the storage unit can be placed close to each other to reduce the data transmission distance and delay, and the high-power consumption chip can be placed close to the cooling channel to improve the heat dissipation efficiency. After the chip stacking is completed, it needs to be packaged to protect the chip and provide an external interface. The packaging process includes selecting a suitable packaging material, designing a packaging structure, and performing packaging testing. The packaging material needs to have good thermal conductivity and electrical insulation properties to ensure the stable operation of the chip. The packaging structure needs to consider factors such as the chip size, the number of pins, and the heat dissipation requirements. For example, in an autonomous driving scenario, in order to achieve higher computing power, multiple AI accelerator chips can be stacked together and tightly integrated with storage chips to form a high-performance computing unit. At the same time, in order to meet the requirements of low power consumption, advanced packaging technologies, such as 2.5D or 3D packaging technology, can be used to reduce the interconnection distance between chips and reduce power consumption. In the smart home scenario, due to the relatively low requirements for computing power, a computing chip can be stacked with multiple storage chips to form a compact system-on-chip (SoC). In this way, the chip architecture and stacking order can be flexibly selected according to different application scenarios and functional requirements, and the appropriate packaging technology can be used to finally obtain an edge AI computing and storage chip that meets specific needs.

[0028] In a specific embodiment, the obtaining of the functional requirements of a preset edge AI computing and storage chip, and determining the chip architecture of the edge AI computing and storage chip and the sequence arrangement corresponding to the chip architecture based on the functional requirements, includes: Obtain a preset target application scenario of the AI ​​computing and storage chip, and determine the functional requirements of the AI ​​computing and storage chip based on the target application scenario; wherein the functional requirements include throughput, latency, and power consumption; Performing a hardware architecture search based on the functional requirements by using a preset neural network search algorithm to obtain a candidate architecture set; The candidate architecture set is screened by a preset power consumption evaluation model to obtain a low power consumption architecture; Based on the functional requirements and the target application scenarios, an on-chip storage architecture is designed for the low-power architecture to determine the chip architecture of the edge AI computing and storage chip and the corresponding sequence arrangement of the chip architecture; wherein the on-chip storage architecture design includes determining the type, capacity, bit width, structure of the memory and the data interaction method with the computing unit to meet the data access mode and bandwidth requirements of the target scenario application.

[0029] Specifically, the step of "obtaining the functional requirements of the preset edge AI computing and storage chip, and determining the chip architecture of the edge AI computing and storage chip and the corresponding order arrangement of the chip architecture based on the functional requirements" covers the complete process from determining the application scenario to the final chip architecture design. First of all, it is necessary to clearly define the target application scenario of the preset AI computing and storage chip, which is the basis for all subsequent steps. Different application scenarios have very different functional requirements for chips. For example, in the field of autonomous driving, edge AI chips need to process a large amount of data from multiple sensors such as cameras, radars, and lidars in real time, and perform complex calculations such as target detection, path planning, and decision control. Therefore, they have extremely high requirements for chip throughput and latency, while also taking into account low power consumption to extend the driving range. In the field of smart homes, the main tasks of edge AI chips may be voice recognition, image processing, simple control logic, etc., with relatively low requirements for throughput, but more emphasis on low cost and low power consumption to extend battery life. Therefore, the first step is to clarify the functional requirements of the chip according to the specific application scenario, including throughput (such as the number of image frames or voice data that can be processed per second), latency (such as the time from data input to result output), and power consumption (such as the average power consumption or peak power consumption of the chip). Next, based on the determined functional requirements, a preset neural network search algorithm is used to search for hardware architectures. The goal of this step is to find a set of candidate architectures that can meet the functional requirements from a large design space. The neural network search algorithm can automatically explore different hardware architectures, such as different computing unit types, quantities, interconnection methods, memory hierarchies, etc., and evaluate the performance of each architecture. Commonly used neural network search algorithms include reinforcement learning, evolutionary algorithms, Bayesian optimization, etc. Through these algorithms, a set of candidate architectures with excellent performance can be efficiently searched. After obtaining the candidate architecture set, further screening is required to determine the final low-power architecture. This is because even if the functional requirements are met, different architectures may have significant differences in power consumption. In order to select the optimal architecture, the candidate architecture set needs to be evaluated using a preset power consumption evaluation model. The power consumption evaluation model can estimate the power consumption of each architecture based on the specific parameters of the architecture, such as the type and number of computing units, the access frequency and power consumption of the memory, the length and power consumption of the interconnection lines, etc. By comparing the power consumption of different architectures, the architecture with the lowest power consumption can be selected as the final low-power architecture. Finally, based on the functional requirements and target application scenarios, the on-chip storage architecture design is performed for the selected low-power architecture. The design of the on-chip memory architecture is crucial to the overall performance and power consumption of the chip. In this step, the type, capacity, bit width, structure of the memory, and the data interaction method with the computing unit need to be determined. The type of memory can be SRAM, DRAM, HBM, etc. The capacity needs to be determined according to the amount of data in the application scenario. The bit width affects the data transmission rate. The structure can be single-port, multi-port or shared memory, etc.In addition, it is also necessary to design efficient data interaction methods, such as DMA (direct memory access) controllers, cache mechanisms, etc., to minimize the overhead of data handling and improve data access efficiency. For example, in the scenario of autonomous driving, in order to meet the requirements of high throughput and low latency, it may be necessary to use large-capacity, high-bandwidth HBM memory and design dedicated data paths to achieve high-speed data transmission. In the smart home scenario, due to the relatively small amount of data, small-capacity, low-power SRAM memory can be used, and a simple bus structure can be used for data interaction. Through the optimized design of the on-chip storage architecture, the performance of the chip can be maximized and power consumption can be reduced. Through the above steps, the chip architecture of the edge AI computing and storage chip and the corresponding order of the chip architecture are finally determined, which provides important guidance for subsequent chip design, manufacturing and packaging. This chip architecture design method driven by application scenarios and functional requirements can effectively improve the performance and efficiency of the chip, reduce power consumption and cost, and better meet the needs of different application scenarios.

[0030] In a specific embodiment, the TSV etching is performed on a preset wafer by deep reactive ion etching technology to obtain a through hole array wafer, including: Based on the optical interferometry method, a thickness measurement is performed on a preset wafer to obtain a wafer thickness map, and a thickness uniformity analysis is performed on the wafer thickness map to obtain a wafer with uniform thickness; Performing TSV initial etching on the wafer with uniform thickness by using deep reactive ion etching technology to obtain an initial etched wafer, and performing sidewall passivation treatment on the initial etched wafer to obtain a passivated wafer; Depositing a barrier layer on the passivation wafer by atomic layer deposition technology to obtain a barrier layer wafer, and performing photolithography patterning on the barrier layer wafer to obtain a patterned wafer; Performing deep hole etching on the patterned wafer based on a Bosch etching process to obtain a deep hole wafer; An insulating layer is deposited on the deep hole wafer by chemical vapor deposition technology to obtain an insulating layer wafer, and the insulating layer wafer is subjected to chemical mechanical polishing to obtain a through hole array wafer.

[0031] Specifically, the step of "performing TSV etching on a preset wafer by deep reactive ion etching technology to obtain a through-hole array wafer" describes how to use deep reactive ion etching technology to etch TSV through holes on a wafer to form a through-hole array wafer. First, the thickness of the preset wafer is measured by optical interferometry to obtain a wafer thickness map. Optical interferometry is a high-precision thickness measurement method that can accurately measure the thickness of different positions of the wafer. Then, the wafer thickness map is subjected to thickness uniformity analysis to screen out wafers with uniform thickness to obtain wafers with uniform thickness. Thickness uniformity is crucial for subsequent etching processes, as it can ensure the depth and uniformity of etching. Next, the wafer with uniform thickness is subjected to TSV initial etching by deep reactive ion etching technology to obtain an initial etched wafer. Deep reactive ion etching is a dry etching technology that can accurately control the depth and shape of etching. The purpose of initial etching is to form the initial shape of the TSV through hole on the surface of the wafer. Then, the initial etched wafer is subjected to sidewall passivation treatment to obtain a passivated wafer. Sidewall passivation can prevent corrosion and collapse of the sidewalls during etching and improve the quality of TSV vias. Afterwards, a barrier layer is deposited on the passivated wafer using atomic layer deposition (ALD) technology to obtain a barrier layer wafer. ALD technology can precisely control the thickness and uniformity of the deposition to form a dense barrier layer. The barrier layer can prevent subsequent etching processes from damaging the wafer. Then, the barrier layer wafer is photolithographically patterned to obtain a patterned wafer. Photolithographic patterning is the process of transferring the pre-designed TSV via pattern to the wafer surface, which provides a template for subsequent deep hole etching. Next, the patterned wafer is deep-hole etched based on the Bosch etching process to obtain a deep hole wafer. The Bosch etching process is a cyclic etching process that can achieve high aspect ratio etching to form deep and narrow TSV vias. Deep hole etching is a key step in TSV manufacturing, which determines the final size and shape of the TSV via. Finally, the deep hole wafer is subjected to an insulating layer deposition by chemical vapor deposition (CVD) technology to obtain an insulating layer wafer. CVD technology can deposit an insulating layer on the inner wall of the TSV through-hole to isolate the TSV through-hole from the surrounding circuits. Then, the insulating layer wafer is subjected to chemical mechanical polishing (CMP) to obtain the final through-hole array wafer. CMP can polish the wafer surface flat, remove excess insulating layer, and expose the opening of the TSV through-hole for subsequent metal filling and interconnection. For example, in high-performance autonomous driving AI chips, high-density TSV through-holes are required to achieve high-speed data transmission between different modules inside the chip. Through the above process flow, a TSV through-hole array with high aspect ratio, high density and high reliability can be manufactured to meet the needs of high-performance chips. Even in low-power application scenarios such as smart homes, high-quality TSV through-hole arrays can improve the integration and performance of chips and reduce power consumption.Therefore, the TSV etching process is crucial for the manufacture of various edge AI computing and storage chips.

[0032] In a specific embodiment, the through hole array wafer is cut to obtain independent cut chips; and cooling channels are constructed for the independent cut chips to obtain cooling function chips, including: Scanning the internal structure of the through-hole array wafer by a preset three-dimensional X-ray tomography technology to obtain a three-dimensional structure distribution map, and planning a cutting path for the through-hole array wafer based on the three-dimensional structure distribution map to obtain a cutting path; Using a multi-wavelength laser cutting technology, the through hole array wafer is cut in layers based on the cutting path to obtain preliminary cut chips, and the preliminary cut chips are chamfered to obtain independent cut chips; The independently cut chip is subjected to atomic-level flattening of the surface by atomic layer etching technology to obtain a flattened chip; Using microfluidic channel design technology to construct cooling channel patterns on the flattened chip to obtain a microchannel structure, and anisotropically etching the microchannel structure to obtain a three-dimensional channel network; Performing super-hydrophilic surface modification on the three-dimensional flow channel network to obtain a surface wetting characteristic chip, and performing nano-scale functional coating deposition on the surface wetting characteristic chip to obtain a fluid dynamics chip; Using micro-scale heat flow analysis technology, the heat transfer performance of the fluid dynamics chip is evaluated to obtain thermal resistance and temperature rise distribution data. If the thermal resistance and temperature rise distribution data are within a preset safe working range, a cooling function chip is obtained; If not, the thermal resistance and temperature rise distribution data are deeply analyzed by a preset genetic algorithm to obtain optimized cooling channel structural parameters, and the fluid dynamics chip is optimized based on the optimized cooling channel structural parameters to obtain a cooling function chip.

[0033] Specifically, to achieve the step of "cutting the through-hole array wafer to obtain an independently cut chip; and constructing a cooling channel for the independently cut chip to obtain a cooling function chip", it is first necessary to accurately cut the through-hole array wafer and construct an efficient cooling channel on this basis. First, the internal structure of the through-hole array wafer is scanned using a preset three-dimensional X-ray tomography technology to obtain a three-dimensional structural distribution map of the TSV through-holes inside the wafer. This step is crucial because the cutting path must avoid the TSV through-holes to avoid damaging these key interconnect structures. Based on the obtained three-dimensional structural distribution map, the cutting path is planned to determine the best cutting path to ensure that the cutting process does not affect the function and performance of the chip. Then, the through-hole array wafer is cut in layers according to the planned cutting path using multi-wavelength laser cutting technology. Multi-wavelength laser cutting technology can achieve high-precision and high-efficiency cutting, and has less damage to the wafer. After the cutting is completed, the preliminary cut chips are obtained, and the edges of these chips need to be chamfered to remove burrs and sharp edges to obtain independently cut chips, in preparation for the subsequent cooling channel construction. Next, the cooling channel is constructed for the independently cut chips. First, the atomic layer etching technology is used to perform atomic-level surface flattening on the independently cut chip to obtain a flattened chip. The atomic layer etching technology can accurately remove the atomic layer on the chip surface to achieve extremely high surface flatness, which is very important for the subsequent microfluidic channel construction. Then, the cooling channel pattern is constructed on the flattened chip surface using the microfluidic channel design technology to form a microchannel structure. The microfluidic channel design technology can accurately control the size and shape of the microchannel to achieve the best cooling effect. Next, the microchannel structure is anisotropically etched to form a three-dimensional channel network. Anisotropic etching can accurately control the etching direction and depth, thereby forming a channel network with a complex three-dimensional structure and improving the cooling efficiency. In order to further improve the cooling performance, the constructed three-dimensional channel network is subjected to superhydrophilic surface modification to give it excellent surface wetting properties. The superhydrophilic surface can promote the flow of coolant in the channel, reduce flow resistance, and improve heat dissipation efficiency. Then, a nano-scale functional coating is deposited on the surface wetting characteristic chip to further optimize the fluid dynamics properties and obtain a fluid dynamics chip. Finally, the heat transfer performance of the fluid dynamics chip is evaluated using microscale thermal flow analysis technology to obtain the thermal resistance and temperature rise distribution data of the chip. These data are compared with the preset safe operating range. If the thermal resistance and temperature rise distribution data are within the safe operating range, the cooling function chip is considered to be completed. If it is not within the safe operating range, the cooling channel structure needs to be optimized. At this time, the preset genetic algorithm is used to deeply analyze the thermal resistance and temperature rise distribution data to find the key parameters affecting the cooling performance and obtain the optimized cooling channel structure parameters.Based on these optimized parameters, the fluid dynamics chip is optimized, the cooling channel is reconstructed, and the heat transfer performance is evaluated again until the thermal resistance and temperature rise distribution data reach the preset safe operating range, and finally a cooling function chip is obtained. For example, in high-performance autonomous driving AI chips, the heat dissipation problem is particularly prominent due to the high power consumption of the chip. The microfluidic cooling system constructed by the above process flow can effectively reduce the chip temperature and ensure the stability and reliability of the chip. In low-power application scenarios such as smart homes, although the heat dissipation pressure is relatively small, an efficient cooling system can still extend the life of the chip and improve the reliability of the system. Therefore, building an efficient cooling system is crucial for various edge AI computing and storage chips.

[0034] In a specific embodiment, the internal structure of the through hole array wafer is scanned by a preset three-dimensional X-ray tomography technology to obtain a three-dimensional structure distribution map, and a cutting path is planned for the through hole array wafer based on the three-dimensional structure distribution map to obtain a cutting path, including: Performing phase contrast X-ray tomography scanning on the through hole array wafer to obtain an original diffraction image, and performing phase reconstruction on the original diffraction image to obtain a multi-layer diffraction spectrum; Digitally reconstructing the multi-layer diffraction spectrum by spatial frequency domain filtering technology to obtain density distribution data, and performing three-dimensional voxel reconstruction on the density distribution data to obtain a voxel distribution map; The voxel distribution map is three-dimensionally reconstructed by a reverse projection algorithm to obtain a three-dimensional structure distribution map, and a cutting area is planned for the three-dimensional structure distribution map to obtain cutting area parameters; wherein the cutting area parameters include a cutting critical point, a stress sensitive area and a material boundary line; The topology optimization technology is used to plan the cutting path of the through hole array wafer based on the cutting area parameters to obtain a cutting path.

[0035] Specifically, the step of "scanning the internal structure of the through-hole array wafer by a preset three-dimensional X-ray tomography technique to obtain a three-dimensional structure distribution map, and planning the cutting path of the through-hole array wafer based on the three-dimensional structure distribution map to obtain a cutting path" is centered on using advanced imaging and analysis techniques to accurately determine the internal structure of the wafer and plan a safe cutting path, thereby avoiding damage to the critical TSV through-hole structure during the cutting process. First, a phase-contrast X-ray tomography scan is performed on the through-hole array wafer. Phase-contrast X-ray tomography is a non-destructive imaging technique that uses the phase difference generated when X-rays pass through the sample to reconstruct the internal structure of the sample. It is particularly suitable for imaging materials with small density differences, such as silicon and TSV filling materials. After scanning, the original diffraction images are obtained. These images contain information about the internal structure of the wafer, but further processing is required to obtain a clear three-dimensional structure. Next, the original diffraction images are phase reconstructed to obtain a multi-layer diffraction spectrum. Phase reconstruction is the process of converting the phase information in the original diffraction image into data that can be used to reconstruct the image. It can improve the contrast and resolution of the image and make the structure of the TSV through-hole more clearly visible. Then, the multi-layer diffraction spectrum is digitally reconstructed by spatial frequency domain filtering technology to obtain density distribution data. Spatial frequency domain filtering technology can remove noise and artifacts in the image and improve the quality of the image. Based on the density distribution data, three-dimensional voxel reconstruction is performed to obtain a voxel distribution map. Voxel is the smallest unit in three-dimensional space. The voxel distribution map can intuitively show the density distribution of different materials inside the wafer. Next, the voxel distribution map is reconstructed in three dimensions by the inverse projection algorithm to obtain a three-dimensional structure distribution map. The inverse projection algorithm is a commonly used three-dimensional reconstruction algorithm that can convert two-dimensional projection data into a three-dimensional image. The obtained three-dimensional structure distribution map clearly shows the location, size, direction and other information of the TSV through-hole inside the wafer. Based on this three-dimensional structure distribution map, the cutting area is planned, the cutting boundary and key area are determined, and the cutting area parameters are obtained. These parameters include the critical point of cutting, that is, the key position that the cutting path must avoid; the stress-sensitive area, that is, the area where stress is easily generated during the cutting process; and the material boundary, that is, the boundary between different materials. Finally, the topology optimization technology is used to plan the cutting path of the through-hole array wafer based on the cutting area parameters to obtain the final cutting path. Topology optimization technology is a mathematical optimization method that can find the best cutting path that can avoid critical structures, minimize the stress generated by cutting, and ensure cutting efficiency. For example, in high-performance autonomous driving AI chips, the density of TSV through holes is very high, and the planning of the cutting path must be very precise to avoid damaging these through holes. Through the above process flow, the location and direction of the TSV through holes can be accurately determined, and a safe cutting path can be planned to ensure the yield and performance of the chip.Even in low-power application scenarios such as smart homes, accurate cutting path planning can improve chip production efficiency and reduce manufacturing costs. Therefore, accurate cutting path planning is crucial for the manufacture of various edge AI computing and storage chips.

[0036] In a specific embodiment, the cooling function chip is integrated and packaged into multiple chips based on the chip architecture and the sequence arrangement corresponding to the chip architecture to obtain an edge AI computing and storage chip, including: Arranging the cooling function chips based on the chip architecture and the sequence arrangement corresponding to the chip architecture to obtain arranged chips; The arranged chips are interconnected by using micro-bump bonding technology to obtain bump interconnected chips, and the bump interconnected chips are bottom-filled to obtain bottom-filled chips; Stacking the bottom-filled chips by high-density three-dimensional stacking technology to obtain a three-dimensional chip stack; Packaging the three-dimensional chip stack to obtain a WLP packaged chip, and wire bonding the WLP packaged chip to obtain a wire-bonded chip; Performing RDL construction on the wire bonding chip by using redistribution layer technology to obtain an RDL chip, and performing electrical testing on the RDL chip to obtain electrical test results; If the electrical test results show that there are RDL chips that do not meet the preset standards, the RDL chips that do not meet the preset standards are removed to obtain qualified RDL chips; The qualified RDL chip is packaged at the system level based on the system-level packaging technology to obtain an edge AI computing and storage chip.

[0037] Specifically, the step of "integrating and packaging the cooling function chip into a complete edge AI computing and storage chip based on the chip architecture and the corresponding sequential arrangement of the chip architecture" describes how to integrate and package multiple cooling function chips into a complete edge AI computing and storage chip. First, the cooling function chips are arranged according to the pre-designed chip architecture and the corresponding sequential arrangement to obtain the arranged chip. The chip architecture defines the connection relationship and functional division between different chips, while the sequential arrangement determines the specific position of the chip in the package. This step lays the foundation for subsequent interconnection and stacking. Next, the arranged chips are interconnected using micro-bump bonding technology to form a bump interconnected chip. Micro-bump bonding technology is a high-density interconnection technology that realizes electrical connection by forming tiny bumps between chips, which can achieve high-bandwidth and low-latency communication between chips. Then, the bump interconnected chip is bottom-filled to obtain a bottom-filled chip. The purpose of the bottom filling is to protect the micro-bumps, enhance the mechanical strength of the chip, and improve the reliability of the chip. After that, the bottom-filled chips are stacked by high-density three-dimensional stacking technology to obtain a three-dimensional chip stack. Three-dimensional stacking technology can stack multiple chips vertically together, thereby significantly improving the integration and performance of the chip. The stacked chips are interconnected through micro-bumps to form a tightly connected whole. Then, the three-dimensional chip stack is packaged to obtain a WLP (wafer-level packaging) packaged chip. WLP packaging technology can be packaged directly on the wafer, which can reduce the size of the chip and reduce the packaging cost. Next, the WLP packaged chip is wire bonded to obtain a wire-bonded chip. Wire bonding is the process of connecting the pads on the chip to the external circuit, which provides an interface for the chip to communicate with the outside world. In order to further improve the interconnection density and performance of the chip, the wire-bonded chip is constructed by redistribution layer (RDL) technology to obtain an RDL chip. RDL technology can construct high-density metal lines on the chip surface to connect different functional modules inside the chip and provide more I / O interfaces for the chip. After the RDL layer is constructed, the RDL chip needs to be electrically tested to verify the quality and reliability of the RDL and obtain electrical test results. If the electrical test results show that there are RDL chips that do not meet the preset standards, these unqualified chips will be eliminated and only qualified RDL chips will be retained. Finally, the qualified RDL chips are packaged in a system-level package based on the system-level package (SiP) technology to obtain the final edge AI computing and storage chip. SiP technology can integrate multiple chips with different functions in one package to form a complete system. Through SiP packaging, the size of the chip can be further reduced, and the integration and performance of the chip can be improved. For example, in high-performance autonomous driving AI chips, multiple processor cores, memory chips, and interface chips need to be integrated together to realize complex computing and data processing functions.Through the above-mentioned multi-chip integration and packaging process, these chips with different functions can be integrated into a compact package to form a high-performance, low-power edge AI computing and storage chip. In low-power application scenarios such as smart homes, multi-chip integration technology can integrate processors, memory, and sensors together to form a highly integrated smart terminal. Therefore, multi-chip integration and packaging technology are crucial to the realization of various edge AI computing and storage chips.

[0038] In a specific embodiment, the arrangement chips are interconnected by using micro-bump bonding technology to obtain bump interconnected chips, and the bump interconnected chips are bottom-filled to obtain bottom-filled chips, including: Sputtering a UBM metal layer on the arranged chip to obtain a UBM structure chip; Growing micro-bumps on the UBM structure chip by ultrasonic assisted electroplating technology to obtain a micro-bump chip; Performing chip alignment on the micro-bump chip to obtain an aligned micro-bump chip, and performing low-temperature pre-bonding on the aligned micro-bump chip to obtain a preliminary bonded chip; Performing thermal compression bonding on the preliminary bonded chip based on thermal compression bonding technology to obtain a bump interconnection chip; The bump interconnect chip is bottom-filled by utilizing capillary action to obtain a filled bump interconnect chip, and the filled bump interconnect chip is solidified to obtain a bottom-filled chip.

[0039] Specifically, the step of "interconnecting the arranged chips by micro-bump bonding technology to obtain a bump interconnected chip, and bottom filling the bump interconnected chip to obtain a bottom filled chip" describes in detail the chip interconnection and subsequent bottom filling process using micro-bump bonding technology. First, the arranged chips are subjected to UBM (Under Bump Metallization) metal layer sputtering to form a UBM structure chip. The UBM layer is usually composed of multiple layers of metals, such as titanium, nickel and gold, which serve as the basis of micro-bumps and provide good conductivity and adhesion. Then, micro-bumps are grown on the UBM structure chip by ultrasonic assisted electroplating technology to obtain a micro-bump chip. The introduction of ultrasonic waves can improve the uniformity and efficiency of electroplating, thereby obtaining high-quality micro-bumps. These micro-bumps will serve as a bridge for electrical connection between chips. Next, chip alignment is performed to ensure that the micro-bumps on the chip to be bonded are accurately aligned with the corresponding pads on the target chip to obtain an aligned micro-bump chip. The accuracy of chip alignment directly affects the quality and reliability of bonding. After alignment, low-temperature pre-bonding is performed to obtain a preliminary bonded chip. Low-temperature pre-bonding can make a preliminary connection between the chips, providing a basis for subsequent hot compression bonding. Then, the preliminary bonded chip is hot-compression bonded based on the hot compression bonding technology to obtain a bump interconnection chip. Hot compression bonding is performed under high temperature and high pressure, which can firmly connect the micro-bumps to the pads on the target chip to form a reliable electrical connection. At this point, the interconnection between the chips is completed. In order to further enhance the mechanical strength and reliability of the chip, it is necessary to bottom fill the bump interconnection chip. The bump interconnection chip is bottom-filled by capillary action to obtain a filled bump interconnection chip. Capillary action can make the filling material automatically fill the gap between the chips and completely wrap the micro-bumps. Then, the filled bump interconnection chip is cured to solidify the filling material to obtain the final bottom-filled chip. The cured filling material can effectively protect the micro-bumps, prevent them from being affected by the external environment, and improve the mechanical strength and impact resistance of the chip. For example, in high-performance autonomous driving AI chips, multiple processor cores, memory chips, and interface chips need to be interconnected through micro-bump bonding technology to achieve high-speed data transmission and collaborative work. Bottom filling can protect these micro-bumps and ensure that the chip can still work stably in harsh environments such as high temperature and high vibration. Even in low-power application scenarios such as smart homes, micro-bump bonding and bottom filling technologies can improve the integration and reliability of chips and extend the service life of products. Therefore, micro-bump bonding and bottom filling technologies are crucial to the manufacture of various edge AI computing and storage chips.

[0040] The above describes the multi-layer stacking packaging method of the edge AI computing and storage chip in the embodiment of the present invention. The following describes the multi-layer stacking packaging device of the edge AI computing and storage chip in the embodiment of the present invention. Figure 2 In one embodiment of the present invention, a multi-layer stacking packaging device of an edge AI computing and storage chip includes: An acquisition module 21 is used to acquire the functional requirements of a preset edge AI computing and storage chip, and determine the chip architecture of the edge AI computing and storage chip and the order of arrangement corresponding to the chip architecture based on the functional requirements; The through-hole module 22 is used to perform TSV etching on a preset wafer by deep reactive ion etching technology to obtain a through-hole array wafer; A cutting module 23 is used to cut the through hole array wafer to obtain independent cut chips; and to construct cooling channels for the independent cut chips to obtain cooling function chips; The packaging module 24 is used to integrate and package the cooling function chip into multiple chips based on the chip architecture and the sequential arrangement corresponding to the chip architecture to obtain an edge AI computing and storage chip.

[0041] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, which will not be repeated here.

[0042] Reference Figure 3 The present invention also provides a computer device in an embodiment, wherein the internal structure of the computer device can be as follows: Figure 3 As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0043] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0044] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0045] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0046] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0047] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A multi-layer stacking packaging method for edge AI computing and storage chips, characterized in that: The following steps are involved: Obtaining the functional requirements of a preset edge AI computing and storage chip, and determining the chip architecture of the edge AI computing and storage chip and the order of arrangement corresponding to the chip architecture based on the functional requirements; Through deep reactive ion etching technology, TSV etching is performed on the preset wafer to obtain a through-hole array wafer; Cutting the through hole array wafer to obtain independently cut chips; and constructing cooling channels for the independently cut chips to obtain cooling function chips; Based on the chip architecture and the sequential arrangement corresponding to the chip architecture, the cooling function chip is integrated and packaged into multiple chips to obtain an edge AI computing and storage chip.

2. The multi-layer stacking packaging method of the edge AI computing and storage chip according to claim 1 is characterized in that: The obtaining of the functional requirements of the preset edge AI computing and storage chip, and determining the chip architecture of the edge AI computing and storage chip and the sequence arrangement corresponding to the chip architecture based on the functional requirements, includes: Obtain a preset target application scenario of the AI ​​computing and storage chip, and determine the functional requirements of the AI ​​computing and storage chip based on the target application scenario; wherein the functional requirements include throughput, latency, and power consumption; Performing a hardware architecture search based on the functional requirements by using a preset neural network search algorithm to obtain a candidate architecture set; The candidate architecture set is screened by a preset power consumption evaluation model to obtain a low power consumption architecture; Based on the functional requirements and the target application scenarios, an on-chip storage architecture is designed for the low-power architecture to determine the chip architecture of the edge AI computing and storage chip and the corresponding sequence arrangement of the chip architecture; wherein the on-chip storage architecture design includes determining the type, capacity, bit width, structure of the memory and the data interaction method with the computing unit to meet the data access mode and bandwidth requirements of the target scenario application.

3. The multi-layer stacking packaging method of the edge AI computing and storage chip according to claim 1 is characterized in that: The method of performing TSV etching on a preset wafer by deep reactive ion etching technology to obtain a through hole array wafer includes: Based on the optical interferometry method, a thickness measurement is performed on a preset wafer to obtain a wafer thickness map, and a thickness uniformity analysis is performed on the wafer thickness map to obtain a wafer with uniform thickness; Performing TSV initial etching on the wafer with uniform thickness by using deep reactive ion etching technology to obtain an initial etched wafer, and performing sidewall passivation treatment on the initial etched wafer to obtain a passivated wafer; Depositing a barrier layer on the passivation wafer by atomic layer deposition technology to obtain a barrier layer wafer, and performing photolithography patterning on the barrier layer wafer to obtain a patterned wafer; Performing deep hole etching on the patterned wafer based on a Bosch etching process to obtain a deep hole wafer; An insulating layer is deposited on the deep hole wafer by chemical vapor deposition technology to obtain an insulating layer wafer, and the insulating layer wafer is subjected to chemical mechanical polishing to obtain a through hole array wafer.

4. The multi-layer stacking packaging method of the edge AI computing and storage chip according to claim 1 is characterized in that: The through hole array wafer is cut to obtain independent cut chips; and cooling channels are constructed for the independent cut chips to obtain cooling function chips, including: Scanning the internal structure of the through-hole array wafer by a preset three-dimensional X-ray tomography technology to obtain a three-dimensional structure distribution map, and planning a cutting path for the through-hole array wafer based on the three-dimensional structure distribution map to obtain a cutting path; Using a multi-wavelength laser cutting technology, the through hole array wafer is cut in layers based on the cutting path to obtain preliminary cut chips, and the preliminary cut chips are chamfered to obtain independent cut chips; The independently cut chip is subjected to atomic-level flattening of the surface by atomic layer etching technology to obtain a flattened chip; Using microfluidic channel design technology to construct cooling channel patterns on the flattened chip to obtain a microchannel structure, and anisotropically etching the microchannel structure to obtain a three-dimensional channel network; Performing super-hydrophilic surface modification on the three-dimensional flow channel network to obtain a surface wetting characteristic chip, and performing nano-scale functional coating deposition on the surface wetting characteristic chip to obtain a fluid dynamics chip; Using micro-scale heat flow analysis technology, the heat transfer performance of the fluid dynamics chip is evaluated to obtain thermal resistance and temperature rise distribution data. If the thermal resistance and temperature rise distribution data are within a preset safe working range, a cooling function chip is obtained; If not, the thermal resistance and temperature rise distribution data are deeply analyzed by a preset genetic algorithm to obtain optimized cooling channel structural parameters, and the fluid dynamics chip is optimized based on the optimized cooling channel structural parameters to obtain a cooling function chip.

5. The multi-layer stacking packaging method of the edge AI computing and storage chip according to claim 4 is characterized in that: The method comprises: scanning the internal structure of the through hole array wafer by a preset three-dimensional X-ray tomography technology to obtain a three-dimensional structure distribution map, and planning a cutting path for the through hole array wafer based on the three-dimensional structure distribution map to obtain a cutting path, including: Performing phase contrast X-ray tomography scanning on the through hole array wafer to obtain an original diffraction image, and performing phase reconstruction on the original diffraction image to obtain a multi-layer diffraction spectrum; Digitally reconstructing the multi-layer diffraction spectrum by spatial frequency domain filtering technology to obtain density distribution data, and performing three-dimensional voxel reconstruction on the density distribution data to obtain a voxel distribution map; The voxel distribution map is three-dimensionally reconstructed by a reverse projection algorithm to obtain a three-dimensional structure distribution map, and a cutting area is planned for the three-dimensional structure distribution map to obtain cutting area parameters; wherein the cutting area parameters include a cutting critical point, a stress sensitive area and a material boundary line; The topology optimization technology is used to plan the cutting path of the through hole array wafer based on the cutting area parameters to obtain a cutting path.

6. The multi-layer stacking packaging method of the edge AI computing and storage chip according to claim 1 is characterized in that: The method of integrating and packaging the cooling function chip into multiple chips based on the chip architecture and the sequence arrangement corresponding to the chip architecture to obtain an edge AI computing and storage chip includes: Arranging the cooling function chips based on the chip architecture and the sequence arrangement corresponding to the chip architecture to obtain arranged chips; The arranged chips are interconnected by using micro-bump bonding technology to obtain bump interconnected chips, and the bump interconnected chips are bottom-filled to obtain bottom-filled chips; Stacking the bottom-filled chips by high-density three-dimensional stacking technology to obtain a three-dimensional chip stack; Packaging the three-dimensional chip stack to obtain a WLP packaged chip, and wire bonding the WLP packaged chip to obtain a wire-bonded chip; Performing RDL construction on the wire bonding chip by using redistribution layer technology to obtain an RDL chip, and performing electrical testing on the RDL chip to obtain electrical test results; If the electrical test results show that there are RDL chips that do not meet the preset standards, the RDL chips that do not meet the preset standards are removed to obtain qualified RDL chips; The qualified RDL chip is packaged at the system level based on the system-level packaging technology to obtain an edge AI computing and storage chip.

7. The multi-layer stacking packaging method of the edge AI computing and storage chip according to claim 6 is characterized in that: The method comprises: interconnecting the arranged chips by using micro-bump bonding technology to obtain a bump interconnection chip, and bottom-filling the bump interconnection chip to obtain a bottom-filled chip, comprising: Sputtering a UBM metal layer on the arranged chip to obtain a UBM structure chip; Growing micro-bumps on the UBM structure chip by ultrasonic assisted electroplating technology to obtain a micro-bump chip; Performing chip alignment on the micro-bump chip to obtain an aligned micro-bump chip, and performing low-temperature pre-bonding on the aligned micro-bump chip to obtain a preliminary bonded chip; Performing thermal compression bonding on the preliminary bonded chip based on thermal compression bonding technology to obtain a bump interconnection chip; The bump interconnect chip is bottom-filled by utilizing capillary action to obtain a filled bump interconnect chip, and the filled bump interconnect chip is solidified to obtain a bottom-filled chip.

8. A multi-layer stacking packaging device for edge AI computing and storage chips, characterized in that: include: An acquisition module, used to acquire the functional requirements of a preset edge AI computing and storage chip, and determine the chip architecture of the edge AI computing and storage chip and the order of arrangement corresponding to the chip architecture based on the functional requirements; A through-hole module is used to perform TSV through-holes on a preset wafer by deep reactive ion etching technology to obtain a through-hole array wafer; A cutting module is used to cut the through hole array wafer to obtain independently cut chips; and to construct cooling channels for the independently cut chips to obtain cooling function chips; The packaging module is used to integrate and package the cooling function chip into multiple chips based on the chip architecture and the sequential arrangement corresponding to the chip architecture to obtain an edge AI computing and storage chip.

9. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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