Insulated gate bipolar transistor with trench gate structure and preparation method thereof

Abstract

The invention relates to an insulated gate bipolar transistor with a trench gate structure and a preparation method of the insulated gate bipolar transistor, and the transistor comprises a substrate, a nucleating layer, a stress adjusting layer, a collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer and a barrier layer which are sequentially stacked, two-dimensional electron gas is formed between the channel layer and the barrier layer; the first emitter metal is in contact with the P-type emitter region, and a dielectric layer is arranged between the first emitter metal and the barrier layer and between the first emitter metal and the channel layer; the second emitter metal covers the first emitter metal and is in contact with the upper surface of the channel layer; the gate metal extends into the N-type drift layer, and a dielectric layer is arranged between the gate metal and the barrier layer, the channel layer, the P-type emitter region and the N-type drift layer; and the collector metal penetrates through the substrate, the nucleating layer and the stress adjusting layer and extends to the lower surface of the collector region. According to the transistor, the scattering effect is reduced, and the mobility of device electrons is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an insulated gate bipolar transistor with a trench gate structure and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN) materials have excellent physical and electrical properties, such as high temperature resistance, radiation resistance, wide bandgap, high breakdown field strength and high electron mobility. GaN trench gate insulated gate bipolar transistors (IGBTs) are widely used in the fields of power semiconductor devices, microwave radio frequency devices, power electronic devices and optoelectronic devices.

[0003] In the field of power semiconductor devices, metal oxide field effect transistors (MOSFETs) have high switching speeds, high input impedance, and low on-state voltage drops, and are often used in low-voltage, high-frequency applications. However, their current carrying capacity is poor, and their performance is poor under high voltage and high current conditions. In addition to metal oxide field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs) are also one of the commonly used electronic components. IGBTs combine the high current density characteristics of bipolar transistors (BJTs) with the voltage control characteristics of MOSFETs. They are transistors with high input impedance, high switching speeds, and low on-state resistance under high voltage conditions.

[0004] However, at the emitter of a conventional IGBT, the electrons are located in the same layer as the ionized donors, which greatly increases the impact of the scattering effect. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides an insulated gate bipolar transistor with a trench gate structure and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] An embodiment of the present invention provides an insulated gate bipolar transistor with a trench gate structure, comprising:

[0007] A substrate, a nucleation layer, a stress adjustment layer, a collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer and a barrier layer are sequentially stacked from bottom to top, and a two-dimensional electron gas is formed between the channel layer and the barrier layer;

[0008] a first emitter metal penetrating the barrier layer, the channel layer and contacting the P-type emitter region, wherein a dielectric layer is disposed between the first emitter metal, the barrier layer and the channel layer; and a second emitter metal covering the first emitter metal and contacting an upper surface of the channel layer;

[0009] A gate metal that penetrates the barrier layer, the channel layer, the P-type emitter region and extends to the inside of the N-type drift layer, and a dielectric layer is provided between the gate metal and the barrier layer, the channel layer, the P-type emitter region and the N-type drift layer; the gate metal is located between adjacent second emitter metals;

[0010] A collector metal penetrates the substrate, the nucleation layer, the stress adjustment layer and extends to the lower surface of the collector region.

[0011] In one embodiment of the present invention, the first emitter metal is disposed in a first emitter groove and in contact with the P-type emitter region, and the first emitter groove extends from the upper surface of the barrier layer to the P-type emitter region;

[0012] The second emitter metal covers the first emitter metal and extends into a second emitter groove, and the second emitter groove extends from the upper surface of the barrier layer to the upper surface of the channel layer;

[0013] The gate metal is arranged in a gate groove, and the gate groove extends from the upper surface of the barrier layer to the inside of the N-type drift layer; the second emitter groove is located between the first emitter groove and the gate groove;

[0014] The collector metal is arranged in the collector groove and extends to the lower surface of the collector region; the collector groove extends from the lower surface of the substrate to the lower surface of the collector region.

[0015] In one embodiment of the present invention, it further comprises an isolation table and an isolation area.

[0016] The isolation mesa is formed by etching the ends of the channel layer and the barrier layer until the surface of the P-type emitter region;

[0017] The isolation region is located at two ends of the P-type emitter region and on the surface of the N-type drift layer.

[0018] In one embodiment of the present invention, it also includes interconnect metal and passivation layer, wherein,

[0019] The interconnection metal contacts the second emitter metal, and a dielectric layer is disposed between the interconnection metal, the isolation region, and the gate metal; the passivation layer covers the interconnection metal.

[0020] In one embodiment of the present invention, the collector region is a P-type collector region.

[0021] In one embodiment of the present invention, a portion of the collector region is a P-type collector region, and another portion is an N-type collector region, and the P-type collector region and the N-type collector region are in contact with each other.

[0022] In one embodiment of the present invention, the materials of the nucleation layer, the stress adjustment layer, the collector region, the N-type buffer layer, the N-type drift layer, the P-type emitter region, and the channel layer all include GaN; the material of the barrier layer includes AlGaN;

[0023] The doping concentrations of the collector region and the P-type emitter region are both 1e16-1e21cm -3 , and the doping concentration of the collector region is less than the doping concentration of the second doping layer. The collector region is a P-type emitter region; the doping concentration of the N-type buffer layer is 1e16-1e21cm -3 The doping concentration of the N-type drift layer is 1e15-1e18cm -3 , and the doping concentration of the N-type buffer layer is greater than the doping concentration of the N-type drift layer;

[0024] The thickness of the nucleation layer is 50-500nm, the thickness of the stress adjustment layer is 100-5000nm, the thickness of the collector region is 50-1000nm, the thickness of the N-type buffer layer is 50-1000nm, the thickness of the N-type drift layer is 500-20000nm, the thickness of the P-type emitter region is 50-1000nm, the thickness of the channel layer is 10-500nm, and the thickness of the barrier layer is 10-50nm.

[0025] Another embodiment of the present invention provides a method for preparing an insulated gate bipolar transistor having a trench gate structure, comprising the steps of:

[0026] A nucleation layer, a stress adjustment layer, a collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer and a barrier layer are sequentially prepared on the substrate from bottom to top;

[0027] Etching the barrier layer and the channel layer in the emitter region until the P-type emitter region forms a first emitter groove;

[0028] Etching the barrier layer, the channel layer, and the P-type emitter region in the gate region, and etching to the inside of the drift layer to form a gate groove;

[0029] Etching the barrier layer and the channel layer of the isolation mesa region until the P-type emitter region forms a mesa isolation;

[0030] Etching the substrate, the nucleation layer, the stress adjustment layer in the collector region to the collector region to form a collector groove;

[0031] Annealing the sample to activate the doping ions in the collector region and the P-type emitter region;

[0032] Growing a first dielectric layer on the upper surface of the barrier layer, in the first emitter groove and in the gate groove;

[0033] Ion implantation is performed in a P-type emitter region in the isolation region to form an isolation region;

[0034] Depositing a gate metal on the upper surface of the first dielectric layer in the gate groove;

[0035] Growing a second dielectric layer on the upper surface of the first dielectric layer and the upper surface of the gate metal;

[0036] Etching the first dielectric layer and the second dielectric layer in the first emitter groove until reaching the P-type emitter region;

[0037] Depositing a first emitter metal on the surface of the second dielectric layer in the first emitter groove so that the bottom of the first emitter metal contacts the P-type emitter region;

[0038] Between the first emitter groove and the gate groove, etching the second dielectric layer, the first dielectric layer, and the barrier layer in the emitter region until reaching the surface of the channel layer to form a second emitter groove;

[0039] Depositing a second emitter metal on the surface of the first emitter metal and in the second emitter groove;

[0040] A collector metal is deposited in the collector groove and on the lower surface of the substrate.

[0041] In one embodiment of the present invention,

[0042] A nucleation layer, a stress adjustment layer, a collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer and a barrier layer are sequentially prepared on the substrate from bottom to top, including:

[0043] Using MOCVD technology, a nucleation layer, a stress adjustment layer, a collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer and a barrier layer are grown in sequence from bottom to top on the substrate, wherein the collector region is a P-type collector region;

[0044] Alternatively, a nucleation layer, a stress adjustment layer and an undoped GaN layer are sequentially grown on the substrate from bottom to top by using an MOCVD process; ion implantation is performed on a portion of the undoped GaN layer to form a P-type collector region, and ion implantation is performed on another portion of the undoped GaN layer to form an N-type collector region, wherein the P-type collector region is in contact with the N-type collector region; an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer and a barrier layer are sequentially grown on the P-type collector region and the N-type collector region from bottom to top by using an MOCVD process.

[0045] In one embodiment of the present invention, the steps are further included:

[0046] Growing a third dielectric layer on the surface of the second emitter metal and the surface of the second dielectric layer;

[0047] Etching the third dielectric layer and the second dielectric layer in the emitter region until the surface of the second emitter metal;

[0048] Depositing interconnection metal on the surface of the second emitter metal and the surface of the third dielectric layer in the gate region;

[0049] A passivation layer is deposited on the surface of the interconnect metal.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] 1. The insulated gate bipolar transistor of the present invention forms a two-dimensional electron gas between the barrier layer and the channel layer by providing a barrier layer and a channel layer. The two-dimensional electron gas is separated from the ionized donors in the barrier layer, thereby greatly reducing the scattering effect and improving the mobility of the device electrons;

[0052] 2. The insulated gate bipolar transistor of the present invention introduces a P-type collector region and an N-type buffer layer, and a PN junction is formed between the P-type collector region and the N-type buffer layer, which combines the advantages of the BJT structure on the basis of MOSFET and improves the current conduction capability of the device;

[0053] 3. The insulated gate bipolar transistor of the present invention short-circuits the N-type collector region at the P-type collector region to form a reverse-conducting IGBT, so that when the IGBT is reverse biased, the PiN diode formed by the N-type collector region, the N-type drift layer, and the P-type emitter region is turned on, providing a channel for excess carriers in the drift layer, thereby shortening the turn-off time of the IGBT. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic structural diagram of an insulated gate bipolar transistor with a trench gate structure provided by an embodiment of the present invention;

[0055] Figure 2 A schematic structural diagram of another insulated gate bipolar transistor with a trench gate structure provided by an embodiment of the present invention;

[0056] Figure 3a-Figure 3r A schematic diagram of a manufacturing process of an insulated gate bipolar transistor with a trench gate structure provided by an embodiment of the present invention;

[0057] Figure 4a-4c A schematic diagram of a partial preparation process of an insulated gate bipolar transistor with a trench gate structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0059] Embodiment 1

[0060] See also Figure 1 , Figure 1 A schematic structural diagram of an insulated gate bipolar transistor with a trench gate structure provided in an embodiment of the present invention.

[0061] The insulated gate bipolar transistor with a trench gate structure includes: a substrate 1, a nucleation layer 2, a stress adjustment layer 3, a collector region 4, an N-type buffer layer 5, an N-type drift layer 6, a P-type emitter region 7, a channel layer 8, a barrier layer 9, a gate metal 12, a first emitter metal 14, a second emitter metal 15 and a collector metal 19.

[0062] Among them, the substrate 1, the nucleation layer 2, the stress adjustment layer 3, the collector region 4, the N-type buffer layer 5, the N-type drift layer 6, the P-type emitter region 7, the channel layer 8 and the barrier layer 9 are stacked in sequence from bottom to top, wherein at least a part of the collector region 4 is a P-type collector region, and a two-dimensional electron gas is formed between the channel layer 8 and the barrier layer 9. The first emitter metal 14 penetrates the barrier layer 9 and the channel layer 8 and contacts the P-type emitter region 7, and a dielectric layer is arranged between the first emitter metal 14 and the barrier layer 9 and the channel layer 8; the second emitter metal 15 covers the first emitter metal 14 and contacts the upper surface of the channel layer 8; the gate metal 12 penetrates the barrier layer 9, the channel layer 8, the P-type emitter region 7 and extends to the inside of the N-type drift layer 6, and a dielectric layer is arranged between the gate metal 12 and the barrier layer 9, the channel layer 8, the P-type emitter region 7 and the N-type drift layer 6; the gate metal 12 is located between adjacent second emitter metals 15; the collector metal 19 penetrates the substrate 1, the nucleation layer 2, the stress adjustment layer 3 and extends to the lower surface of the collector region 4.

[0063] In a specific embodiment, the first emitter metal 14 is arranged in the first emitter groove and contacts the P-type emitter region 7, and the first emitter groove extends from the upper surface of the barrier layer 9 to the P-type emitter region 7; the second emitter metal 15 covers the first emitter metal 14 and extends into the second emitter groove, and the second emitter groove extends from the upper surface of the barrier layer 9 to the upper surface of the channel layer 8; the gate metal 12 is arranged in the gate groove, and the gate groove extends from the upper surface of the barrier layer 9 to the inside of the N-type drift layer 6; the second emitter groove is located between the first emitter groove and the gate groove; the collector metal 19 is arranged in the collector groove and extends to the lower surface of the collector region 4; the collector groove extends from the lower surface of the substrate 1 to the lower surface of the collector region 4.

[0064] Specifically, the first emitter groove penetrates the barrier layer 9 and the channel layer 8, and may extend to the surface of the P-type emitter region 7 or to the inside of the P-type emitter region 7. A dielectric layer is disposed on the side of the first emitter groove, and the dielectric layer extends to the surface of the barrier layer 9. The first emitter metal 14 is disposed in the first emitter groove, and the bottom contacts the P-type emitter region 7, and the side contacts the dielectric layer to form a groove structure, and the first emitter metal 14 extends to the dielectric layer on the surface of the barrier layer 9.

[0065] The gate groove penetrates the barrier layer 9, the channel layer 8, and the P-type emitter region 7, and the bottom is located inside the N-type drift layer 6. The inner surface of the gate groove is covered with a dielectric layer, and the dielectric layer extends to the barrier layer 9 around the gate groove. The gate metal 12 covers the dielectric layer inside the gate groove and extends to overlap the surface of the dielectric layer around the gate groove.

[0066] The second emitter groove is located in the emitter region between the first emitter groove and the gate groove, and its bottom is located on the upper surface of the channel layer 8. The second emitter metal 15 fills the groove structure formed by the first emitter metal 14, and extends from the upper surface of the first emitter metal 14 to the inside of the second emitter groove to contact the channel layer 8.

[0067] It should be noted that the number of gates is n, where n is a positive integer greater than or equal to 1, and correspondingly, the number of emitters is n+1, and the gates are arranged between adjacent emitters. That is, the number of gates can be one or more, depending on the required current size.

[0068] The collector groove is formed at the bottom of the transistor, penetrating the substrate 1, the nucleation layer 2, the stress adjustment layer 3 and reaching the lower surface of the collector region 4. The collector metal 19 covers the surface of the collector groove and extends to the lower surface of the substrate 1.

[0069] Specifically, the collector region 4 serves as the collector of the BJT device, and the first emitter metal 14 serves as the emitter ohmic metal of the BJT device; the N-type buffer layer 5 serves as the drain of the MOSFET device, and the second emitter metal 15 serves as the source ohmic contact metal of the MOSFET device; the first emitter metal 14 and the second emitter metal 15 together form the emitter of the insulated gate bipolar transistor IGBT.

[0070] In this embodiment, an insulated gate bipolar transistor is formed by etching a gate groove as the gate region of the IGBT, etching a first emitter groove in contact with the P-type emitter region 7, and a second emitter groove in contact with the two-dimensional electron gas as the emitter region of the IGBT, and etching a collector groove at the bottom of the substrate as the collector region of the IGBT.

[0071] In a specific embodiment, the insulated gate bipolar transistor also includes an isolation mesa and an isolation region 11, wherein the isolation mesa is formed by etching the ends of the channel layer 8 and the barrier layer 9 until the surface of the P-type emitter region 7; the isolation region 11 is located at both ends of the P-type emitter region 7 and on the surface of the N-type drift layer 6.

[0072] Specifically, the ends of the channel layer 8 and the barrier layer 9 are etched away to form an isolation mesa. The isolation region 11 is formed by ion implantation at the end of the P-type emitter region 7 .

[0073] Furthermore, the dielectric layer between the first emitter metal 14 and the first emitter groove extends to the side of the isolation table and the upper surface of the isolation region 11, and the first emitter metal 14 at the end extends to the isolation region 11 and partially covers the dielectric layer.

[0074] In a specific embodiment, the insulated gate bipolar transistor further includes an interconnect metal 17 and a passivation layer 18 . The interconnect metal 17 contacts the second emitter metal 15 , and a dielectric layer is disposed between the interconnect metal 17 and the isolation region 11 and the gate metal 12 . The passivation layer 18 covers the interconnect metal 17 .

[0075] Specifically, the upper surface of the isolation region 11, the upper surface of the first emitter metal 14 on the isolation region 11, and the surface of the gate metal 12 are all covered with a dielectric layer, and the interconnection metal 17 covers the dielectric layer and is in direct contact with the second emitter metal 15. The passivation layer 18 is located on the upper surface of the interconnection metal 17.

[0076] In a specific embodiment, the collector region 4 is a P-type collector region, that is, the entire region of the collector region 4 is a P-type collector region. Figure 1 shown.

[0077] In a specific embodiment, a portion of the collector region 4 is a P-type collector region 41 , and another portion is an N-type collector region 42 , and the P-type collector region 41 and the N-type collector region 42 are in contact with each other.

[0078] Specifically, P-type ions are implanted into one end of the collector region 4 to form a P-type collector region 41, and N-type ions are implanted into the other end to form an N-type collector region 42, and the P-type collector region 41 and the N-type collector region 42 are short-circuited, thereby forming a reverse-conducting IGBT, such as Figure 2 As shown, Figure 2 A schematic structural diagram of another insulated gate bipolar transistor with a trench gate structure provided by an embodiment of the present invention.

[0079] The insulated gate bipolar transistor of this embodiment short-circuits the N-type collector region at the P-type collector region to form a reverse-conducting IGBT, so that when the IGBT is reverse biased, the PiN diode formed by the N-type collector region, the N-type drift layer, and the P-type emitter region is turned on, providing a channel for excess carriers in the drift layer, thereby shortening the turn-off time of the IGBT.

[0080] In a specific embodiment, the substrate 1 is sapphire, SOI, Si, GaN, AlN, diamond or other composite substrates. The materials of the nucleation layer 2, the stress adjustment layer 3, the collector region 4, the N-type buffer layer 5, the N-type drift layer 6, the P-type emitter region 7, and the channel layer 8 all include GaN. The material of the barrier layer 9 includes AlGaN. It should be noted that the channel layer 8 and the barrier layer 9 of this embodiment can also be made of other materials that can form a two-dimensional electron gas.

[0081] The doping concentrations of the collector region 4 and the P-type emitter region 7 are both 1e16-1e21cm -3 , and the doping concentration of the collector region 4 is less than the doping concentration of the P-type emitter region 7. The doping concentration of the N-type buffer layer 5 is 1e16-1e21cm -3 , the doping concentration of the N-type drift layer 6 is 1e15-1e18cm -3 , and the doping concentration of the N-type buffer layer 5 is greater than the doping concentration of the N-type drift layer 6, that is, the material of the N-type buffer layer 5 is N+GaN, and the material of the N-type drift layer 6 is N-GaN.

[0082] The thickness of the nucleation layer 2 is 50-500nm, the thickness of the stress adjustment layer 3 is 100-5000nm, the thickness of the collector region 4 is 50-1000nm, the thickness of the N-type buffer layer 5 is 50-1000nm, the thickness of the N-type drift layer 6 is 500-20000nm, the thickness of the P-type emitter region 7 is 50-1000nm, the thickness of the channel layer 8 is 10-500nm, and the thickness of the barrier layer 9 is 10-50nm.

[0083] Specifically, when the collector region 4 is a P-type collector region, the doping concentration of the P-type collector region is 1e16-1e21cm -3 When a part of the collector region 4 is a P-type collector region 41 and another part is an N-type collector region 42, the doping concentration of the P-type collector region 41 is 1e16-1e21cm -3 , with a thickness of 50-1000nm, and a doping concentration of the N-type collector region 42 of 1e16-1e21cm -3 , thickness is 50-1000nm.

[0084] The material of the gate metal 12 includes TiN / Ti / Al / Ti stacked metal or Ni / Au stacked metal. The first emitter metal 14, the second emitter metal 15, and the collector metal 19 all include Ti / Al / TiN or other metal combinations based on Ti / Al.

[0085] Need to explain, Figure 1 and Figure 2The insulated gate bipolar transistor shown is a cellular structure, and an actual device is formed by a plurality of cellular structures arranged periodically.

[0086] The insulated gate bipolar transistor of this embodiment forms a two-dimensional electron gas between the barrier layer and the channel layer by setting a barrier layer and a channel layer. The two-dimensional electron gas is separated from the ionized donors in the barrier layer, thereby greatly reducing the scattering effect and improving the mobility of the device electrons.

[0087] The insulated gate bipolar transistor of this embodiment introduces a P-type collector region and an N-type buffer layer, and a PN junction is formed between the P-type collector region and the N-type buffer layer. The advantages of the BJT structure are combined on the basis of MOSFET, thereby improving the current conduction capability of the device.

[0088] Embodiment 2

[0089] On the basis of the first embodiment, this embodiment takes the collector region 4 as a P-type collector region as an example to illustrate a method for preparing an insulated gate bipolar transistor with a trench gate structure.

[0090] See also Figure 3a-Figure 3r , Figure 3a-Figure 3r A schematic diagram of a manufacturing process of an insulated gate bipolar transistor with a trench gate structure provided by an embodiment of the present invention. The manufacturing method comprises the steps of:

[0091] S1. A nucleation layer 2, a stress adjustment layer 3, a collector region 4, an N-type buffer layer 5, an N-type drift layer 6, a P-type emitter region 7, a channel layer 8 and a barrier layer 9 are sequentially prepared on a substrate 1 from bottom to top.

[0092] Specifically, a nucleation layer 2, a stress adjustment layer 3, a P-type collector region 4, an N-type buffer layer 5, an N-type drift layer 6, a P-type emitter region 7, a channel layer 8 and a barrier layer 9 are sequentially grown on a substrate 1 by using an MOCVD process. Figure 3a shown.

[0093] S2, etching the barrier layer 9 and the channel layer 8 in the emitter region until the P-type emitter region 7 forms a first emitter groove, such as Figure 3b shown.

[0094] Specifically, dry etching is used, using BCl 3 / Cl 2 As a reaction gas, the barrier layer 9 and the channel layer 8 of the emitter region are etched to the inside of the P-type emitter region 7 or to the surface of the P-type emitter region 7 to form a first emitter groove.

[0095] S3, etching the barrier layer 9, the channel layer 8, and the P-type emitter region 7 in the gate region, and etching to the inside of the drift layer 6 to form a gate groove, such as Figure 3c shown.

[0096] Specifically, dry etching is used, using BCl 3 / Cl 2 As a reaction gas, the barrier layer 9, the channel layer 8, and the P-type emitter region 7 in the gate region are etched, and a portion of the N-type drift layer 6 is overetched to form a gate groove.

[0097] S4, etching the barrier layer 9 and the channel layer 8 in the isolation mesa region until the P-type emitter region 7 forms an isolation mesa, such as Figure 3d shown.

[0098] Specifically, dry etching is used, using BCl 3 / Cl 2 As a reaction gas, the channel layer 8 and the barrier layer 9 outside the active area are etched to the P-type emitter region 7 to form an isolation mesa.

[0099] S5, etching the substrate 1, the nucleation layer 2, and the stress adjustment layer 3 in the collector region until the collector region 4 forms a collector groove, such as Figure 3e shown.

[0100] Specifically, dry etching is used, using BCl 3 / Cl 2 As the reaction gas, the substrate 1 , the nucleation layer 2 and the stress adjustment layer 3 in the collector region are etched from the substrate 1 .

[0101] S6. Anneal the sample to activate the doped ions in the collector region 4 and the P-type emitter region 7.

[0102] Specifically, the sample is subjected to high-temperature annealing using an annealing process, the annealing temperature being 800-850° C., to activate the doped ions in the collector region 4 and the P-type emitter region 7. Exemplarily, the sample is annealed at 825° C. in a nitrogen atmosphere for 20 minutes to activate the doped Mg ions in the collector region 4 and the P-type emitter region 7 that are passivated by H.

[0103] S7, growing a first dielectric layer 10 on the upper surface of the barrier layer 9, in the first emitter groove and the gate groove, such as Figure 3f shown.

[0104] Specifically, the first dielectric layer 10 is grown on the upper surface of the barrier layer 9, the first emitter groove, the gate groove and the surface of the isolation mesa by using ALD or PECVD process, and is used as a gate dielectric layer. The material of the first dielectric layer 10 includes Al 2 O 3 , HfO 2 、SiO 2 、TiO 2 , AlON, AlTiO or more; the first dielectric layer 10 can also be a multi-layer gate dielectric.

[0105] S8, ion implantation is performed in the P-type emitter region 7 of the isolation region to form an isolation region 11, such as Figure 3g shown.

[0106] Specifically, ion implantation isolation is performed in the P-type emitter region 7 outside the active region through the first dielectric layer 10 , and the implanted ions may be N or Ar, so as to form an isolation region 11 .

[0107] S9, depositing gate metal 12 on the upper surface of the first dielectric layer 10 in the gate groove, such as Figure 3h shown.

[0108] Specifically, the gate metal 12 is deposited on the first dielectric layer 10 in the gate groove by using an electron beam evaporation process.

[0109] S10, growing a second dielectric layer 13 on the upper surface of the first dielectric layer 10 and the upper surface of the gate metal 12, such as Figure 3i shown.

[0110] Specifically, the second dielectric layer 13 is grown on the upper surface of the first dielectric layer 10 and the upper surface of the gate metal 12 using a PECVD process. The material of the second dielectric layer 13 includes Al 2 O 3 , SiO 2 and Si 3 N 4 One or more of .

[0111] S11, etching the first dielectric layer 10 and the second dielectric layer 13 in the first emitter groove until the P-type emitter region 7, such as Figure 3j shown.

[0112] Specifically, dry etching is used, using BCl 3 / Cl 2 As a reaction gas, the first dielectric layer 10 and the second dielectric layer 13 in the first emitter groove are etched until the P-type emitter region 7 at the bottom of the first emitter groove is exposed.

[0113] S12, depositing the first emitter metal 14 on the surface of the second dielectric layer 13 in the first emitter groove, so that the bottom of the first emitter metal 14 is in contact with the P-type emitter region 7, as shown in FIG. Figure 3k shown.

[0114] Specifically, the first emitter metal 14 is deposited on the surface of the second dielectric layer 13 in the first emitter groove by using an electron beam evaporation process, and the bottom of the first emitter metal 14 is in contact with the P-type emitter region 7 .

[0115] S13, between the first emitter groove and the gate groove, the second dielectric layer 13, the first dielectric layer 10, the barrier layer 9 in the emitter region are etched until the surface of the channel layer 8, so as to form a second emitter groove, such as Figure 3l shown.

[0116] Specifically, dry etching is used, using BCl 3 / Cl 2 As a reaction gas, the second dielectric layer 13, the first dielectric layer 10, the barrier layer 9 and even the surface of the channel layer 8 between the first emitter groove and the gate groove are etched to form a second emitter groove.

[0117] S14, depositing the second emitter metal 15 on the surface of the first emitter metal 14 and in the second emitter groove, such as Figure 3m shown.

[0118] Specifically, the second emitter metal 15 is deposited on the surface of the first emitter metal 14 , in the second emitter groove, and on the device surface between the first emitter metal 14 and the second emitter groove by using an electron beam evaporation process.

[0119] Further, after the second emitter metal 15 is prepared, Figure 3o As shown, you can also perform the following steps:

[0120] S15, growing a third dielectric layer 16 on the surface of the second emitter metal 15 and the surface of the second dielectric layer 13, such as Figure 3n shown.

[0121] Specifically, the third dielectric layer 16 is grown on the surface of the second emitter metal 15 and the surface of the second dielectric layer 13 using a PECVD process.

[0122] S16, etching the third dielectric layer 16 and the second dielectric layer 13 in the emitter region until the surface of the second emitter metal 15 is reached. Figure 3o shown.

[0123] Specifically, dry etching is used, using BCl 3 / Cl 2 As a reaction gas, the third dielectric layer 16 and the second dielectric layer 13 in the emitter region are etched until the surface of the second emitter metal 15 .

[0124] S17, depositing interconnection metal 17 on the surface of the second emitter metal 15 and the surface of the third dielectric layer 16 in the gate region, such as Figure 3p shown.

[0125] Specifically, the interconnection metal 17 is deposited on the surface of the second emitter metal 15 and the surface of the third dielectric layer 16 in the gate region by using an electron beam evaporation process.

[0126] S18, depositing a passivation layer 18 on the surface of the interconnect metal 17, such as Figure 3q shown.

[0127] Specifically, the passivation layer 18 is deposited on the surface of the interconnection metal 17 using a PECVD process.

[0128] S19, depositing collector metal 19 in the collector groove and on the lower surface of the substrate 1, such as Figure 3r shown.

[0129] Specifically, the collector metal 19 is deposited in the collector groove and on the lower surface of the substrate 1 using an electron beam evaporation process.

[0130] The insulated gate bipolar transistor of this embodiment forms a two-dimensional electron gas between the barrier layer and the channel layer by setting a barrier layer and a channel layer. The two-dimensional electron gas is separated from the ionized donors in the barrier layer, thereby greatly reducing the scattering effect and improving the mobility of the device electrons.

[0131] The insulated gate bipolar transistor of this embodiment introduces a P-type collector region and an N-type buffer layer, and a PN junction is formed between the P-type collector region and the N-type buffer layer. The advantages of the BJT structure are combined on the basis of MOSFET, thereby improving the current conduction capability of the device.

[0132] Embodiment 3

[0133] Based on the first embodiment, this embodiment takes a part of the P-type collector region 4 as the collector region 41 and the other part as the N-type collector region 42 as an example to illustrate a method for preparing an insulated gate bipolar transistor with a trench gate structure.

[0134] See also Figure 4a-4c , Figure 4a-4c A schematic diagram of a partial preparation process of an insulated gate bipolar transistor with a trench gate structure provided by an embodiment of the present invention. The preparation method comprises the steps of:

[0135] S1. A nucleation layer 2, a stress adjustment layer 3, a collector region 4, an N-type buffer layer 5, an N-type drift layer 6, a P-type emitter region 7, a channel layer 8 and a barrier layer 9 are sequentially prepared on a substrate 1 from bottom to top.

[0136] Specifically, first, a nucleation layer 2, a stress adjustment layer 3 and an undoped GaN layer are grown sequentially from bottom to top on a substrate 1 by using a MOCVD process, such as Figure 4a Then, a portion of the undoped GaN layer is implanted with P-type ions (such as Mg ions) to form a P-type collector region 41, and another portion is implanted with N-type ions (such as Si ions) to form an N-type collector region 42, wherein the P-type collector region 41 and the N-type collector region 42 are in contact, as shown in FIG. Figure 4bNext, an MOCVD process is used to sequentially grow an N-type buffer layer 5, an N-type drift layer 6, a P-type emitter region 7, a channel layer 8 and a barrier layer 9 on the P-type collector region 41 and the N-type collector region 42 from bottom to top, as shown in FIG. Figure 4c shown.

[0137] S2 , etching the barrier layer 9 and the channel layer 8 in the emitter region until the P-type emitter region 7 forms a first emitter groove.

[0138] S3, etching the barrier layer 9, the channel layer 8, and the P-type emitter region 7 in the gate region, and etching to the inside of the drift layer 6 to form a gate groove.

[0139] S4, etching the barrier layer 9 and the channel layer 8 in the isolation mesa region until the P-type emitter region 7 forms an isolation mesa.

[0140] S5 , etching the substrate 1 , the nucleation layer 2 , and the stress adjustment layer 3 in the collector region until the collector region 4 forms a collector groove.

[0141] S6. Anneal the sample to activate the doped ions in the collector region 4 and the P-type emitter region 7.

[0142] S7 . Growing a first dielectric layer 10 on the upper surface of the barrier layer 9 , in the first emitter groove and in the gate groove.

[0143] S8. Perform ion implantation in the P-type emitter region 7 of the isolation region to form an isolation region 11.

[0144] S9, depositing a gate metal 12 on the upper surface of the first dielectric layer 10 in the gate groove.

[0145] S10 , growing a second dielectric layer 13 on the upper surface of the first dielectric layer 10 and the upper surface of the gate metal 12 .

[0146] S11 , etching the first dielectric layer 10 and the second dielectric layer 13 in the first emitter groove until reaching the P-type emitter region 7 .

[0147] S12 , depositing a first emitter metal 14 on the surface of the second dielectric layer 13 in the first emitter groove, so that the bottom of the first emitter metal 14 contacts the P-type emitter region 7 .

[0148] S13 , etching the second dielectric layer 13 , the first dielectric layer 10 , the barrier layer 9 in the emitter region to the surface of the channel layer 8 between the first emitter groove and the gate groove to form a second emitter groove.

[0149] S14, depositing the second emitter metal 15 on the surface of the first emitter metal 14 and in the second emitter groove.

[0150] S15 , growing a third dielectric layer 16 on the surface of the second emitter metal 15 and the surface of the second dielectric layer 13 .

[0151] S16 , etching the third dielectric layer 16 and the second dielectric layer 13 in the emitter region until the surface of the second emitter metal 15 .

[0152] S17 , depositing interconnection metal 17 on the surface of the second emitter metal 15 and the surface of the third dielectric layer 16 in the gate region.

[0153] S18 , depositing a passivation layer 18 on the surface of the interconnect metal 17 .

[0154] S19 , depositing collector metal 19 in the collector groove and on the lower surface of the substrate 1 .

[0155] For the specific implementation of steps S2-S9, please refer to Example 2, which will not be described in detail in this example.

[0156] The insulated gate bipolar transistor of this embodiment short-circuits the N-type collector region at the P-type collector region to form a reverse-conducting IGBT, so that when the IGBT is reverse biased, the PiN diode formed by the N-type collector region, the N-type drift layer, and the P-type emitter region is turned on, providing a channel for excess carriers in the drift layer, thereby shortening the turn-off time of the IGBT.

[0157] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. An insulated gate bipolar transistor having a trench gate structure, characterized in that: include: A substrate (1), a nucleation layer (2), a stress adjustment layer (3), a collector region (4), an N-type buffer layer (5), an N-type drift layer (6), a P-type emitter region (7), a channel layer (8) and a barrier layer (9) stacked in sequence from bottom to top, wherein at least a portion of the collector region (4) is a P-type collector region, and a two-dimensional electron gas is formed between the channel layer (8) and the barrier layer (9); a first emitter metal (14) penetrating the barrier layer (9), the channel layer (8) and in contact with the P-type emitter region (7), wherein a dielectric layer is provided between the first emitter metal (14), the barrier layer (9) and the channel layer (8); and a second emitter metal (15) covering the first emitter metal (14) and in contact with the upper surface of the channel layer (8); a gate metal (12) penetrating the barrier layer (9), the channel layer (8), the P-type emitter region (7) and extending to the inside of the N-type drift layer (6), and a dielectric layer is provided between the gate metal (12) and the barrier layer (9), the channel layer (8), the P-type emitter region (7) and the N-type drift layer (6); the gate metal (12) is located between adjacent second emitter metals (15); A collector metal (19) penetrates the substrate (1), the nucleation layer (2), the stress adjustment layer (3) and extends to the lower surface of the collector region (4).

2. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that: The first emitter metal (14) is arranged in a first emitter groove and contacts the P-type emitter region (7), and the first emitter groove extends from the upper surface of the barrier layer (9) to the P-type emitter region (7); The second emitter metal (15) covers the first emitter metal (14) and extends into a second emitter groove, and the second emitter groove extends from the upper surface of the barrier layer (9) to the upper surface of the channel layer (8); The gate metal (12) is arranged in a gate groove, and the gate groove extends from the upper surface of the barrier layer (9) to the inside of the N-type drift layer (6); the second emitter groove is located between the first emitter groove and the gate groove; The collector metal (19) is arranged in a collector groove and extends to the lower surface of the collector region (4); the collector groove extends from the lower surface of the substrate (1) to the lower surface of the collector region (4).

3. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that: Also includes an isolation table and an isolation area (11), The isolation mesa is formed by etching the ends of the channel layer (8) and the barrier layer (9) until the surface of the P-type emitter region (7); The isolation region (11) is located at both ends of the P-type emission region (7) and on the surface of the N-type drift layer (6).

4. The insulated gate bipolar transistor with a trench gate structure according to claim 3, characterized in that: It also includes an interconnect metal (17) and a passivation layer (18), wherein: The interconnection metal (17) is in contact with the second emitter metal (15), and a dielectric layer is provided between the interconnection metal (17) and the isolation region (11) and the gate metal (12); The passivation layer (18) covers the interconnection metal (17).

5. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that: The collector region (4) is a P-type collector region.

6. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that: A portion of the collector region (4) is a P-type collector region (41), and another portion is an N-type collector region (42), and the P-type collector region (41) and the N-type collector region (42) are in contact with each other.

7. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that: The materials of the nucleation layer (2), the stress adjustment layer (3), the collector region (4), the N-type buffer layer (5), the N-type drift layer (6), the P-type emitter region (7), and the channel layer (8) all include GaN; the material of the barrier layer (9) includes AlGaN; The doping concentrations of the collector region (4) and the P-type emitter region (7) are both 1e16-1e21 cm -3 The doping concentration of the collector region (4) is less than the doping concentration of the P-type emitter region (7); the doping concentration of the N-type buffer layer (5) is 1e16-1e21cm -3 The doping concentration of the N-type drift layer (6) is 1e15-1e18cm -3 , and the doping concentration of the N-type buffer layer (5) is greater than the doping concentration of the N-type drift layer (6); The thickness of the nucleation layer (2) is 50-500nm, the thickness of the stress adjustment layer (3) is 100-5000nm, the thickness of the collector region (4) is 50-1000nm, the thickness of the N-type buffer layer (5) is 50-1000nm, the thickness of the N-type drift layer (6) is 500-20000nm, the thickness of the P-type emitter region (7) is 50-1000nm, the thickness of the channel layer (8) is 10-500nm, and the thickness of the barrier layer (9) is 10-50nm.

8. A method for preparing an insulated gate bipolar transistor having a trench gate structure, characterized in that: Includes steps: A nucleation layer (2), a stress adjustment layer (3), a collector region (4), an N-type buffer layer (5), an N-type drift layer (6), a P-type emitter region (7), a channel layer (8) and a barrier layer (9) are sequentially prepared on a substrate (1) from bottom to top; Etching the barrier layer (9) and the channel layer (8) in the emitter region until the P-type emitter region (7) forms a first emitter groove; Etching the barrier layer (9), the channel layer (8), and the P-type emitter region (7) in the gate region, and etching to the inside of the drift layer (6) to form a gate groove; Etching the barrier layer (9) and the channel layer (8) in the isolation mesa region until the P-type emitter region (7) forms an isolation mesa; Etching the substrate (1), the nucleation layer (2), the stress adjustment layer (3) in the collector region to the collector region (4) to form a collector groove; Annealing the sample to activate the doping ions in the collector region (4) and the P-type emitter region (7); Growing a first dielectric layer (10) on the upper surface of the barrier layer (9), in the first emitter groove and in the gate groove; Performing ion implantation in a P-type emission region (7) of the isolation region to form an isolation region (11); Depositing a gate metal (12) on the upper surface of the first dielectric layer (10) in the gate groove; Growing a second dielectric layer (13) on the upper surface of the first dielectric layer (10) and the upper surface of the gate metal (12); Etching the first dielectric layer (10) and the second dielectric layer (13) in the first emitter groove until reaching the P-type emitter region (7); Depositing a first emitter metal (14) on the surface of the second dielectric layer (13) in the first emitter groove, so that the bottom of the first emitter metal (14) contacts the P-type emitter region (7); Between the first emitter groove and the gate groove, etching the second dielectric layer (13), the first dielectric layer (10), the barrier layer (9) in the emitter region until the surface of the channel layer (8) forms a second emitter groove; Depositing a second emitter metal (15) on the surface of the first emitter metal (14) and in the second emitter groove; A collector metal (19) is deposited in the collector groove and on the lower surface of the substrate (1).

9. The method for preparing an insulated gate bipolar transistor with a trench gate structure according to claim 8, characterized in that: A nucleation layer (2), a stress adjustment layer (3), a collector region (4), an N-type buffer layer (5), an N-type drift layer (6), a P-type emitter region (7), a channel layer (8) and a barrier layer (9) are sequentially prepared on a substrate (1) from bottom to top, comprising: A nucleation layer (2), a stress adjustment layer (3), a collector region (4), an N-type buffer layer (5), an N-type drift layer (6), a P-type emitter region (7), a channel layer (8) and a barrier layer (9) are grown in sequence from bottom to top on the substrate (1) by using an MOCVD process, wherein the collector region (4) is a P-type collector region; Alternatively, a MOCVD process is used to sequentially grow a nucleation layer (2), a stress adjustment layer (3) and an undoped GaN layer on the substrate (1) from bottom to top; Performing P-type ion implantation on a portion of the undoped GaN layer to form a P-type collector region (41), and performing N-type ion implantation on the other portion to form an N-type collector region (42), wherein the P-type collector region (41) and the N-type collector region (42) are in contact with each other; An MOCVD process is used to sequentially grow an N-type buffer layer (5), an N-type drift layer (6), a P-type emitter region (7), a channel layer (8) and a barrier layer (9) from bottom to top on the P-type collector region (41) and the N-type collector region (42).

10. The method for preparing an insulated gate bipolar transistor with a trench gate structure according to claim 8, characterized in that: Also includes the steps: Growing a third dielectric layer (16) on the surface of the second emitter metal (15) and the surface of the second dielectric layer (13); Etching the third dielectric layer (16) and the second dielectric layer (13) in the emitter region until the surface of the second emitter metal (15) is reached; Depositing interconnection metal (17) on the surface of the second emitter metal (15) and the surface of the third dielectric layer (16) in the gate region; A passivation layer (18) is deposited on the surface of the interconnection metal (17).

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