Display panel, manufacturing method thereof and display device

Abstract

The invention relates to a display panel, a manufacturing method thereof and a display device. The display panel includes: a substrate; the plurality of thin film transistors are arranged on one side of the substrate, and each thin film transistor comprises a semiconductor part, a gate insulating layer, a first gate, a second gate, a source and a drain; wherein the semiconductor part and the gate insulation layer are stacked in the direction perpendicular to the plane where the substrate is located, the first gate and the second gate are spaced and arranged on the side, away from the semiconductor part, of the gate insulation layer on the same layer, and the source and the drain are electrically connected with the semiconductor part. The display panel can solve the problems of high switching voltage, low switching speed and low stability of the thin film transistor of the display panel in the prior art.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Liquid Crystal Display (LCD) panels have the advantages of light weight, thin thickness, low power consumption, easy to drive, and no harmful rays. They have been widely used in modern information devices such as televisions, laptops, mobile phones, personal digital assistants, and have broad development prospects.

[0003] However, in the prior art, display panels have problems such as high switching voltage, low switching speed and low stability of thin film transistors. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a manufacturing method thereof, and a display device to address the problems of high switching voltage, low switching speed and low stability of thin film transistors in the display panel in the prior art.

[0005] According to a first aspect of the present application, a display panel is provided, comprising:

[0006] substrate;

[0007] A plurality of thin film transistors are disposed on one side of the substrate, wherein the thin film transistors include a semiconductor portion, a gate insulating layer, a first gate, a second gate, a source electrode, and a drain electrode;

[0008] The semiconductor part and the gate insulating layer are stacked in a direction perpendicular to the plane of the substrate, the first gate and the second gate are spaced apart and arranged in the same layer on a side of the gate insulating layer away from the semiconductor part, and the source and the drain are electrically connected to the semiconductor part respectively.

[0009] In some embodiments, the semiconductor portion is disposed on one side of the substrate;

[0010] The gate insulating layer is disposed on a side of the semiconductor portion away from the substrate;

[0011] The first gate and the second gate are arranged on a side of the gate insulating layer away from the substrate;

[0012] The display panel further includes a first insulating layer, and the first insulating layer is disposed on a side of the first gate and the second gate away from the substrate;

[0013] The source electrode and the drain electrode are arranged on a side of the first insulating layer away from the substrate, and the source electrode and the drain electrode are electrically connected to the semiconductor part through via holes in the first insulating layer respectively.

[0014] In some embodiments, the semiconductor portion includes a source region and a drain region, the source is electrically connected to the source region, and the drain is electrically connected to the drain region;

[0015] The orthographic projection of the first gate on the substrate and the orthographic projection of the second gate on the substrate are both located between the orthographic projection of the source region on the substrate and the orthographic projection of the drain region on the substrate.

[0016] In some embodiments, the first gate and the second gate are arranged in parallel on a plane parallel to the substrate.

[0017] In some embodiments, the display panel further includes a plurality of scan signal lines, and the first gate and the second gate of the same thin film transistor are connected to the same scan signal line.

[0018] In some embodiments, a material of the semiconductor part includes a metal oxide semiconductor.

[0019] According to a second aspect of the present application, a display device is provided, comprising any one of the display panels described above.

[0020] According to a third aspect of the present application, a method for manufacturing a display panel is provided, comprising:

[0021] providing a substrate;

[0022] Forming a plurality of thin film transistors on one side of the substrate, including forming a semiconductor portion, forming a gate insulating layer, forming a first gate and a second gate, and forming a source electrode and a drain electrode;

[0023] The semiconductor part and the gate insulating layer are stacked in a direction perpendicular to the plane of the substrate, the first gate and the second gate are spaced apart and arranged in the same layer on a side of the gate insulating layer away from the semiconductor part, and the source and the drain are electrically connected to the semiconductor part respectively.

[0024] In some embodiments, forming a plurality of thin film transistors on one side of the substrate includes:

[0025] forming the semiconductor portion on one side of the substrate;

[0026] forming the gate insulating layer on a side of the semiconductor portion away from the substrate;

[0027] Forming the first gate and the second gate on a side of the gate insulating layer away from the substrate;

[0028] forming a first insulating layer on a side of the first gate and the second gate away from the substrate;

[0029] The source electrode and the drain electrode are formed on a side of the first insulating layer away from the substrate, and the source electrode and the drain electrode are electrically connected to the semiconductor part through via holes in the first insulating layer.

[0030] In some embodiments, further comprising:

[0031] A plurality of scanning signal lines are formed, and the first gate electrode and the second gate electrode of the same thin film transistor are connected to the same scanning signal line

[0032] In the embodiment of the present application, the first gate and the second gate are spaced apart and arranged in the same layer on the side of the gate insulating layer away from the semiconductor part, that is, the present application is a double gate design. On the one hand, through the double gate design, the first gate and the second gate can control the carriers in the first sub-channel region and the second sub-channel region respectively or simultaneously, and when the thin film transistor is turned on, the concentration of the carriers in the first sub-channel region and the second sub-channel region of the semiconductor part can be increased, so that the current in the first sub-channel region and the second sub-channel region becomes larger, and when the thin film transistor is turned off, the first gate and the second gate can be controlled respectively or simultaneously to reduce the concentration of the carriers in the first sub-channel region and the second sub-channel region of the semiconductor part, so that the thin film transistor is turned off more thoroughly, so that the thin film transistor has the effects of improved carrier mobility, improved switching current ratio, reduced switching voltage, and improved switching speed. On the other hand, the first gate and the second gate are in the same layer and spaced apart, and only the same mask is needed to manufacture the first gate and the second gate, and the manufacturing process is not increased, and the manufacturing process steps are simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A partial top view schematic diagram of a display panel provided in some embodiments of the present application.

[0035] Figure 2 A partial cross-sectional schematic diagram of a display panel provided for some embodiments of the present application.

[0036] Figure 3 A schematic diagram of a first process step of a method for manufacturing a display panel provided in the present application.

[0037] Figure 4 A schematic diagram of a second process step of a method for manufacturing a display panel provided in the present application.

[0038] Figure 5 A schematic diagram of a first process of a method for manufacturing a display panel provided in the present application.

[0039] Figure 6 A schematic diagram of a second process of a method for manufacturing a display panel provided in the present application.

[0040] Figure 7 A third process schematic diagram of a method for manufacturing a display panel provided in the present application. DETAILED DESCRIPTION

[0041] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0042] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0043] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0044] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0045] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0046] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0047] In the related art, in the prior art, the liquid crystal display panel has the problems of high switching voltage, low switching speed and low stability.

[0048] Based on the above problems, the present application provides a display panel and a manufacturing method thereof, and a display device.

[0049] Figure 1 A partial top view schematic diagram of a display panel provided in some embodiments of the present application. Figure 2 A partial cross-sectional schematic diagram of a display panel provided for some embodiments of the present application. Figure 2 for Figure 1 It should be noted that in order to more clearly observe the structure of the thin film transistor, Figure 1 Only some of the membrane structure is shown in the figure, for example Figure 1 The first insulating layer 15 is not shown in FIG. Figure 1The entire pattern of the gate insulating layer 13 is not shown.

[0050] In a first aspect, the present application provides a display panel 100, which includes a substrate 11 and a plurality of thin film transistors T1 (TFT). The plurality of thin film transistors T1 are arranged on one side of the substrate 11, and the thin film transistors T1 include a semiconductor portion 121, a gate insulating layer 13, a first gate 141, a second gate 142, a source 161, and a drain 162; wherein the semiconductor portion 121 and the gate insulating layer 13 are stacked in a direction perpendicular to the plane where the substrate 11 is located, the first gate 141 and the second gate 142 are spaced apart and arranged on the same layer on a side of the gate insulating layer 13 away from the semiconductor portion 121, and the source 161 and the drain 162 are electrically connected to the semiconductor portion 121, respectively.

[0051] By way of example, the display panel 100 may include a display area and a non-display area.

[0052] For example, the display area may be an area including pixels that display an image. The pixels may be arranged in a matrix form. The pixels may have a rectangular shape, a diamond shape, or a square shape in a plan view, but the embodiment is not limited thereto.

[0053] By way of example, the non-display area may be an area where no image is displayed. The non-display area may be arranged near (or around) the display area. The non-display area may surround the display area, but the embodiment is not limited thereto.

[0054] For example, the non-display area may include a gate driving circuit area and a peripheral area, and the gate driving circuit area is located on at least one side of the display area, such as the gate driving circuit area is located on one side of the display area, or the gate driving circuit area is located on the opposite side of the display area.

[0055] For example, when the display panel 100 is a liquid crystal display panel, the display panel 100 may include an array substrate and an opposing substrate (color filter substrate) that are arranged opposite to each other. The partial film layer structure of the array substrate may be as follows: Figure 2 As shown, liquid crystal (not shown in the figure) is arranged between the display panel 100 and the opposite substrate.

[0056] For example, the display panel 100 may also be other display panels other than the liquid crystal display panel. For example, the display panel 100 is an organic light-emitting diode display panel (Organic Light-Emitting Diode, OLED for short), but the implementation is not limited thereto.

[0057] Illustratively, the material of the substrate 11 may be glass, but the embodiment is not limited thereto.

[0058] For example, the semiconductor portion 121 and the gate insulating layer 13 are stacked in a direction perpendicular to the plane where the substrate 11 is located. Figure 2 It is illustrated that the gate insulating layer 13 is disposed on the side of the semiconductor portion 121 away from the substrate 11 , but the invention is not limited thereto. For example, the semiconductor portion 121 may also be disposed on the side of the gate insulating layer 13 away from the substrate 11 .

[0059] For example, the first gate 141 and the second gate 142 are arranged in the same layer on the side of the gate insulation layer 13 away from the semiconductor part 121, that is, the first gate 141 and the second gate 142 are made of the same material and the same process, and the first gate 141 and the second gate 142 are located between the same two adjacent film layers.

[0060] For example, the first gate 141 and the second gate 142 are spaced apart, that is, the orthographic projection of the first gate 141 on the substrate and the orthographic projection of the second gate 142 on the substrate are spaced apart, and in a direction parallel to the plane where the substrate 11 is located, there is a certain distance between the first gate 141 and the second gate 142.

[0061] For example, the source 161 and the drain 162 are electrically connected to the semiconductor portion 121 respectively, and other components of the display panel can be electrically connected through the source 161 and the drain 162. For example, the source 161 can be electrically connected to the data signal line, and the drain 162 can be electrically connected to the pixel electrode.

[0062] For example, Figure 2 As shown, the semiconductor portion 121 includes a channel region 1211, and the channel region 1211 includes a first sub-channel region 1211a and a second sub-channel region 1211b. In a direction perpendicular to the plane where the substrate 11 is located, the first sub-channel region 1211a and the first gate 141 are stacked, and the second sub-channel region 1211b and the second gate 142 are stacked. The first gate 141 can control the carriers in the first sub-channel region 1211a, and the second gate 142 can control the carriers in the second sub-channel region 1211b.

[0063] In the embodiment of the present application, the first gate 141 and the second gate 142 are spaced apart and arranged on the same layer at a side of the gate insulating layer 13 away from the semiconductor portion 121 , that is, the present application is a double-gate design. On the one hand, through the dual-gate design, the first gate 141 and the second gate 142 can control the carriers in the first sub-channel region 1211a and the second sub-channel region 1211b respectively or simultaneously, so that when the thin film transistor T1 is turned on, the concentration of carriers in the first sub-channel region 1211a and the second sub-channel region 1211b of the semiconductor portion 121 can be increased, so that the current in the first sub-channel region 1211a and the second sub-channel region 1211b becomes larger; when the thin film transistor T1 is turned off, the first gate 141 and the second gate 142 can control respectively or simultaneously so that the concentration of carriers in the first sub-channel region 1211a and the second sub-channel region 1211b of the semiconductor portion 121 is reduced, so that the thin film transistor T1 is turned off more thoroughly, so that the thin film transistor T1 has the effects of improved carrier mobility, improved switching current ratio, reduced switching voltage, and improved switching speed. Secondly, the first gate 141 and the second gate 142 are in the same layer and are spaced apart, and only the same photomask is needed to manufacture the first gate 141 and the second gate 142 , without increasing the manufacturing process and simplifying the manufacturing process steps.

[0064] In some embodiments, the semiconductor portion 121 is disposed on one side of the substrate 11; the gate insulating layer 13 is disposed on the side of the semiconductor portion 121 away from the substrate 11; the first gate 141 and the second gate 142 are disposed on the side of the gate insulating layer 13 away from the substrate 11; the display panel 100 also includes a first insulating layer 15, and the first insulating layer 15 is disposed on the side of the first gate 141 and the second gate 142 away from the substrate 11; the source 161 and the drain 162 are disposed on the side of the first insulating layer 15 away from the substrate 11, and the source 161 and the drain 162 are respectively electrically connected to the semiconductor portion 121 through the via 151 in the first insulating layer 15.

[0065] For example, Figure 2 The film layer structure of the display panel 100 shown in the example includes a semiconductor layer 12, a gate insulating layer 13, a first metal layer 14, a first insulating layer 15, and a second metal layer 16 which are stacked in sequence.

[0066] For example, Figure 2 As shown, the display panel 100 includes a thin film transistor T1 (Thin Film Transistor, TFT for short), the semiconductor layer 12 includes a semiconductor portion 121 of the thin film transistor T1, the first metal layer 14 includes a first gate 141 and a second gate 142 of the thin film transistor T1, the first insulating layer 15 includes a plurality of vias 151, and the second metal layer 16 includes a source 161 and a drain 162 of the thin film transistor T1.

[0067] For example, the material of the first insulating layer 15 may be one or more combinations of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON).

[0068] By way of example, the material of the first metal layer 14 and the second metal layer 16 may be, for example, tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), copper-niobium (CuNb) alloy, etc., or may be, for example, a stack of copper (Cu) and molybdenum (Mo), a stack of copper (Cu) and molybdenum-titanium (MoTi) alloy, a stack of copper (Cu) and titanium (Ti), a stack of aluminum (Al) and molybdenum (Mo), a stack of molybdenum (Mo) and tantalum (Ta), a stack of molybdenum (Mo) and tungsten (W), a stack of molybdenum (Mo)-aluminum (Al)-molybdenum (Mo), etc.

[0069] By way of example, the material of the semiconductor layer 12 may be any one of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), and an oxide semiconductor, but the material of the semiconductor layer 12 is not limited thereto.

[0070] In some embodiments, the semiconductor portion 121 includes a source region 1212 and a drain region 1213, the source 161 is electrically connected to the source region 1212, and the drain 162 is electrically connected to the drain region 1213; the orthographic projection of the first gate 141 on the substrate 11 and the orthographic projection of the second gate 142 on the substrate 11 are both located between the orthographic projection of the source region 1212 on the substrate 11 and the orthographic projection of the drain region 1213 on the substrate 11.

[0071] For example, the semiconductor portion 121 includes a source region 1212 and a drain region 1213 . The source region 1212 and the drain region 1213 may be doped regions, for example, the source region 1212 and the drain region 1213 may be heavily doped regions.

[0072] For example, in some embodiments, in the semiconductor portion 121 , the first sub-channel region 1211 a and the second sub-channel region 1211 b are non-doped regions, and other regions may all be doped regions, for example, other regions may all be heavily doped regions.

[0073] For example, Figure 2 As shown, the orthographic projection of the first gate 141 on the substrate 11 and the orthographic projection of the second gate 142 on the substrate 11 are both located between the orthographic projection of the source region 1212 on the substrate 11 and the orthographic projection of the drain region 1213 on the substrate 11, that is, in a top view or on a plane parallel to the substrate 11, the first gate 141 and the second gate 142 are both located between the source region 1212 and the drain region 1213.

[0074] For example, Figure 2As shown, the semiconductor portion 121 includes a channel region 1211 , which is located between a source region 1212 and a drain region 1213 , and the first gate 141 and the second gate 142 are both arranged to overlap with the channel region 1211 in a direction perpendicular to the plane where the substrate 11 is located.

[0075] In some embodiments, the first gate 141 and the second gate 142 are disposed in parallel on a plane parallel to the substrate 11 .

[0076] For example, on a plane parallel to the substrate 11, the first gate 141 and the second gate 142 are arranged in parallel, that is, the orthographic projection of the first gate 141 on the substrate 11 and the orthographic projection of the second gate 142 on the substrate 11 are arranged at intervals, for example, the orthographic projection of the first gate 141 on the substrate 11 and the orthographic projection of the second gate 142 on the substrate 11 are parallel and arranged at intervals, so that the first gate 141 and the second gate 142 can regulate the channel region 1211 to form two sub-channel regions (a first sub-channel region 1211a and a second sub-channel region 1211b), and the carriers of the two sub-channel regions are respectively controlled by the first gate 141 and the second gate 142. When the thin film transistor T1 is turned on, the concentration of the carriers in the two sub-channel regions can be increased, so that the current in the channel region 1211 becomes larger, and when the thin film transistor T1 is turned off, the concentration of the carriers in the two sub-channel regions can be reduced, so that the thin film transistor T1 is turned off more thoroughly, so that the thin film transistor T1 has the effects of improved carrier mobility, improved switching current ratio, reduced switching voltage, and improved switching speed.

[0077] In some embodiments, Figure 1 As shown, the display panel 100 further includes a plurality of scanning signal lines 163 , and the first gate electrode 141 and the second gate electrode 142 of the same thin film transistor T1 are connected to the same scanning signal line 163 .

[0078] For example, the first gate 141 and the second gate 142 of the same thin film transistor T1 are connected to the same scanning signal line 163, so that the same scanning signal line 163 can simultaneously control the signal size of the first gate 141 and the second gate 142 of the same thin film transistor T1, that is, simultaneously control the two sub-channel regions corresponding to the first gate 141 and the second gate 142, so that the opening and closing of the thin film transistor T1 are faster.

[0079] For example, in some embodiments, the first metal layer 14 includes a first gate 141, a second gate 142 and a scanning signal line 163, that is, the first gate 141, the second gate 142 and the scanning signal line 163 can be set in the same layer and the same material and patterned in the same process step, which can reduce the steps of the manufacturing process.

[0080] For example, in some other embodiments, the scan signal line 163 may be located in a different conductive layer from the first gate 141 and the second gate 142 .

[0081] In some embodiments, the material of the semiconductor portion 121 includes a metal oxide semiconductor.

[0082] For example, the material of the metal oxide semiconductor may be indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), hafnium indium zinc oxide (HIZO), or the like.

[0083] For example, the material of the semiconductor portion 121 includes a metal oxide semiconductor, which is very suitable for Figure 2 The dual-gate structure shown.

[0084] In a second aspect, the present application further provides a display device, which includes the display panel 100 of any one of the above items.

[0085] For example, the display device may be an electronic product, and the electronic product includes any one of the display panels 100 described above. For example, the display device may be any one of a television, a mobile phone, and a computer.

[0086] See also Figures 3 to 7 , Figure 3 A schematic diagram of a first process step of a method for manufacturing a display panel provided in the present application. Figure 4 A schematic diagram of a second process step of a method for manufacturing a display panel provided in the present application. Figure 5 A schematic diagram of a first process of a method for manufacturing a display panel provided in the present application. Figure 6 A schematic diagram of a second process of a method for manufacturing a display panel provided in the present application. Figure 7 A third process schematic diagram of a method for manufacturing a display panel provided in the present application.

[0087] In a third aspect, the present application further provides a method for manufacturing a display panel, and any of the display panels 100 described above can be manufactured using the method for manufacturing a display panel. The method for manufacturing a display panel includes step S100 and step S200.

[0088] Step S100, providing a substrate.

[0089] Illustratively, a substrate 11 is provided.

[0090] Step S200, forming a plurality of thin film transistors on one side of the substrate, including forming a semiconductor portion, forming a gate insulating layer, forming a first gate and a second gate, and forming a source and a drain;

[0091] The semiconductor part and the gate insulating layer are stacked in a direction perpendicular to the plane of the substrate, the first gate and the second gate are spaced apart and arranged in the same layer on a side of the gate insulating layer away from the semiconductor part, and the source and the drain are electrically connected to the semiconductor part respectively.

[0092] For example, a plurality of thin film transistors T1 are formed on one side of the substrate 11, including forming a semiconductor portion 121, forming a gate insulating layer 13, forming a first gate 141 and a second gate 142, and forming a source 161 and a drain 162; wherein the semiconductor portion 121 and the gate insulating layer 13 are stacked in a direction perpendicular to the plane of the substrate 11, the first gate 141 and the second gate 142 are spaced apart and arranged on the same layer on a side of the gate insulating layer 13 away from the semiconductor portion 121, and the source 161 and the drain 162 are electrically connected to the semiconductor portion 121, respectively.

[0093] In some implementations, step S200 includes step S210, step S220, step S230, step S240, and step S250.

[0094] Step S210: forming the semiconductor portion on one side of the substrate.

[0095] For example, Figure 5 As shown, a semiconductor portion 121 is formed on one side of a substrate 11 .

[0096] For example, a semiconductor layer 12 is formed on one side of the substrate 11 , and the semiconductor layer 12 is patterned to form a plurality of semiconductor portions 121 of a plurality of thin film transistors T1 .

[0097] Step S220 , forming the gate insulating layer on a side of the semiconductor portion away from the substrate.

[0098] For example, Figure 6 As shown, a gate insulating layer 13 is formed on a side of the semiconductor portion 121 away from the substrate 11 .

[0099] Step S230 , forming the first gate and the second gate on a side of the gate insulating layer away from the substrate.

[0100] For example, Figure 6 As shown, a first gate 141 and a second gate 142 are formed on a side of the gate insulating layer 13 away from the substrate 11 .

[0101] For example, a first metal layer 14 is formed on a side of the gate insulating layer 13 away from the substrate 11 , and the first metal layer 14 is patterned to form a plurality of first gate electrodes 141 and a plurality of second gate electrodes 142 of a plurality of thin film transistors T1 .

[0102] For example, the first gate 141 and the second gate 142 are arranged in the same layer on the side of the gate insulation layer 13 away from the semiconductor part 121, that is, the first gate 141 and the second gate 142 are made of the same material and the same process, and the first gate 141 and the second gate 142 are located between the same two adjacent film layers.

[0103] Step S240: forming a first insulating layer on a side of the first gate and the second gate away from the substrate.

[0104] For example, Figure 7 As shown, a first insulating layer 15 is formed on a side of the first gate 141 and the second gate 142 away from the substrate 11 .

[0105] For example, Figure 7 As shown, when the first insulating layer 15 is formed, the first insulating layer 15 is patterned to form a plurality of via holes 151 at the same time.

[0106] Step S250 , forming the source electrode and the drain electrode on a side of the first insulating layer away from the substrate, wherein the source electrode and the drain electrode are electrically connected to the semiconductor part through via holes in the first insulating layer.

[0107] For example, Figure 7 and Figure 2 As shown, a source electrode 161 and a drain electrode 162 are formed on a side of the first insulating layer 15 away from the substrate 11 , and the source electrode 161 and the drain electrode 162 are electrically connected to the semiconductor portion 121 through via holes 151 in the first insulating layer 15 .

[0108] For example, the second metal layer 16 is formed on a side of the first insulating layer 15 away from the substrate 11 , and the second metal layer 16 is patterned to form a plurality of source electrodes 161 and a plurality of drain electrodes 162 of a plurality of thin film transistors T1 .

[0109] In some embodiments, please also refer to Figure 1 The manufacturing method of the display panel further includes: forming a plurality of scanning signal lines 163, wherein the first gate electrode 141 and the second gate electrode 142 of the same thin film transistor T1 are connected to the same scanning signal line 163.

[0110] For example, a first metal layer 14 is formed on a side of the gate insulating layer 13 away from the substrate 11 , and the first metal layer 14 is simultaneously patterned to form a plurality of first gates 141 and a plurality of second gates 142 of a plurality of thin film transistors T1 , and a plurality of small scanning signal lines 163 .

[0111] For example, the first gate 141 and the second gate 142 of the same thin film transistor T1 are connected to the same scanning signal line 163, so that the same scanning signal line 163 can simultaneously control the signal size of the first gate 141 and the second gate 142 of the same thin film transistor T1, that is, simultaneously control the two sub-channel regions corresponding to the first gate 141 and the second gate 142, so that the opening and closing of the thin film transistor T1 are faster.

[0112] It should be noted that the display panel manufactured using the display panel manufacturing method of the present application can have the same structure and effect as the display panel 100 in the above embodiment, and the structure and effect of the display panel manufactured using the display panel manufacturing method of the present application will not be repeated here.

[0113] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: substrate; A plurality of thin film transistors are disposed on one side of the substrate, wherein the thin film transistors include a semiconductor portion, a gate insulating layer, a first gate, a second gate, a source electrode, and a drain electrode; The semiconductor part and the gate insulating layer are stacked in a direction perpendicular to the plane of the substrate, the first gate and the second gate are spaced apart and arranged in the same layer on a side of the gate insulating layer away from the semiconductor part, and the source and the drain are electrically connected to the semiconductor part respectively.

2. The display panel according to claim 1, characterized in that: The semiconductor portion is disposed on one side of the substrate; The gate insulating layer is disposed on a side of the semiconductor portion away from the substrate; The first gate and the second gate are arranged on a side of the gate insulating layer away from the substrate; The display panel further includes a first insulating layer, and the first insulating layer is disposed on a side of the first gate and the second gate away from the substrate; The source electrode and the drain electrode are arranged on a side of the first insulating layer away from the substrate, and the source electrode and the drain electrode are electrically connected to the semiconductor part through via holes in the first insulating layer respectively.

3. The display panel according to claim 2, characterized in that: The semiconductor portion includes a source region and a drain region, the source is electrically connected to the source region, and the drain is electrically connected to the drain region; The orthographic projection of the first gate on the substrate and the orthographic projection of the second gate on the substrate are both located between the orthographic projection of the source region on the substrate and the orthographic projection of the drain region on the substrate.

4. The display panel according to claim 3, characterized in that: The first gate and the second gate are arranged in parallel on a plane parallel to the substrate.

5. The display panel according to claim 3, characterized in that: The display panel further includes a plurality of scanning signal lines, and the first gate electrode and the second gate electrode of the same thin film transistor are connected to the same scanning signal line.

6. The display panel according to claim 2, characterized in that: The material of the semiconductor portion includes a metal oxide semiconductor.

7. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 6.

8. A method for manufacturing a display panel, characterized in that: include: providing a substrate; Forming a plurality of thin film transistors on one side of the substrate, including forming a semiconductor portion, forming a gate insulating layer, forming a first gate and a second gate, and forming a source electrode and a drain electrode; The semiconductor part and the gate insulating layer are stacked in a direction perpendicular to the plane of the substrate, the first gate and the second gate are spaced apart and arranged in the same layer on a side of the gate insulating layer away from the semiconductor part, and the source and the drain are electrically connected to the semiconductor part respectively.

9. The method for manufacturing a display panel according to claim 8, characterized in that: The method of forming a plurality of thin film transistors on one side of the substrate comprises: forming the semiconductor portion on one side of the substrate; forming the gate insulating layer on a side of the semiconductor portion away from the substrate; Forming the first gate and the second gate on a side of the gate insulating layer away from the substrate; forming a first insulating layer on a side of the first gate and the second gate away from the substrate; The source electrode and the drain electrode are formed on a side of the first insulating layer away from the substrate, and the source electrode and the drain electrode are electrically connected to the semiconductor part through via holes in the first insulating layer.

10. The method for manufacturing a display panel according to claim 9, wherein: Also includes: A plurality of scanning signal lines are formed, and the first gate electrode and the second gate electrode of the same thin film transistor are connected to the same scanning signal line.

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