Laminated cell and preparation method thereof
By forming an interface modification layer with a success function lower than the conductive film layer on the conductive film layer of the perovskite/crystalline silicon stacked solar cell, the energy level difference problem of ITO/HTL interface is solved, and the carrier tunneling efficiency and battery efficiency are improved.
Patent Information
- Application Number
- CN202411784529.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-05
- Publication Date
- 2025-03-21
AI Technical Summary
In existing perovskite/crystalline silicon stacked solar cells, the energy level difference in the ITO/HTL interface leads to poor band bending, affecting battery efficiency.
By forming an interface modification layer on the conductive film layer, the work function of the material is smaller than the work function of the material of the conductive film layer, a composite knot is formed to improve band bending.
The carrier tunneling efficiency of the composite junction is improved, the performance of the stacked battery is improved, and the battery efficiency is improved.
Smart Images
Figure CN119677311A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of battery technology, and in particular to a laminated battery and a method for preparing the same. Background Art
[0002] At present, the highest efficiency of perovskite / Si (silicon) solar cells publicly reported has reached 33.9%, breaking the efficiency limit of about 29% of traditional crystalline silicon solar cells and showing good application prospects. Unlike single-junction solar cells, stacked cells have additional requirements for the series connection of top / bottom cells. To achieve this, a composite junction (RJ) is prepared between the top / bottom cells to electrically connect the sub-cells in series. In order to achieve optimal cell performance, in addition to good current matching of the top and bottom cells, the energy level arrangement of the RJ is also a very important factor. Inappropriate RJ will likely affect the short-circuit current density, fill factor and open circuit voltage at the same time.
[0003] For the current mainstream perovskite / crystalline silicon tandem solar cells, the ETL (electron transport layer) side is generally used as the light-entering surface, and ITO (indium tin oxide semiconductor transparent conductive film) is used to interconnect the top and bottom cells. Therefore, the RJ structure is generally an ITO / HTL (hole transport layer) structure. The work function of ITO is generally around 4.7eV, while the HOMO (in solar cells, it refers to the highest occupied molecular orbital, which is the occupied molecular orbital with the highest energy in the molecule) energy level of HTL is generally around 5.5eV. There is a significant energy level difference between the two. The energy band bending of the ITO / HTL interface is very likely to fail to flatten the energy level, which will significantly affect the efficiency of the tandem cell. Summary of the invention
[0004] The purpose of the embodiments of the present application is to provide a stacked battery and a method for preparing the same, which can effectively improve the carrier tunneling characteristics of the top and bottom battery interfaces and improve the battery efficiency.
[0005] According to one aspect of an embodiment of the present application, a stacked battery is provided, comprising a substrate structure, a composite junction and a top battery structure stacked in sequence; wherein the composite junction comprises a conductive film layer, an interface modification layer and a hole transport layer stacked in sequence on the substrate structure, and the work function of the material of the interface modification layer is smaller than the work function of the material of the conductive film layer.
[0006] Optionally, the coverage of the conductive film layer by the interface modification layer is between 50% and 75%.
[0007] Optionally, the thickness of the interface modification layer along the stacking direction is 0 to 20 angstroms.
[0008] Optionally, the material of the interface modification layer includes at least one or more of n-type amorphous silicon, n-type microcrystalline silicon, n-type microcrystalline silicon oxide, zinc oxide, lithium fluoride, and magnesium fluoride.
[0009] Optionally, the thickness of the conductive film layer along the stacking direction is 1 nm to 20 nm.
[0010] Optionally, the substrate structure at least includes a substrate conductive film layer, a p+ emitter, a first passivation layer, a substrate, a second passivation layer and an n + The emitter, the conductive film layer is located at the n + On the emitter.
[0011] Optionally, the conductive film layer is + The coverage of the emitter is between 30% and 100%.
[0012] Optionally, the top cell structure comprises at least a perovskite layer, an electron transport layer and a top conductive film layer stacked in sequence, and the perovskite layer is located on the hole transport layer.
[0013] Optionally, the band gap of the perovskite layer is 1.65 eV to 1.72 eV, and the thickness along the stacking direction is 500 nm to 900 nm.
[0014] Another aspect of the embodiment of the present application provides a method for preparing a laminated battery, which is used to prepare the laminated battery, comprising: forming a conductive film layer on a substrate structure;
[0015] An interface modification layer is formed on the conductive film layer, so that the work function of the material of the interface modification layer is smaller than the work function of the material of the conductive film layer, and the coverage rate of the interface modification layer on the conductive film layer is between 50% and 75%;
[0016] The interface modification layer is sequentially stacked to form a hole transport layer and a top battery structure.
[0017] In the laminated battery and the preparation method thereof provided in the embodiment of the present application, the conductive film layer, the interface modification layer, and the hole transport layer form a composite junction, and the work function of the material of the interface modification layer is smaller than the work function of the material of the conductive film layer. The conductive film layer material in the composite junction is surface modified by using the interface modification layer of low work function material, and an ultra-thin interface modification layer of low work function material is introduced at the interface of the composite junction. The conductive film layer / hole transport layer structure is designed to achieve better energy band bending, which can improve the carrier tunneling efficiency of the composite junction and improve the performance of the laminated battery. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0019] Figure 1 is a schematic diagram of the structure of the laminated battery provided in this embodiment;
[0020] Figure 2 is a top view of the laminated battery composite junction provided in this embodiment;
[0021] Figure 3 This is a simulation diagram of the optical transmittance of the laminated battery composite junction provided in this embodiment.
[0022] Icon: 100A-substrate structure; 100B-composite junction; 100C-top cell structure; 101-substrate conductive film layer; 102-p+ emitter; 103-first passivation layer; 104-substrate; 105-second passivation layer; 106-n + Emitter; 107 - conductive film layer; 108 - interface modification layer; 109 - hole transport layer; 110 - perovskite layer; 111 - electron transport layer; 112 - buffer layer; 113 - top conductive film layer; 114 - electrode. DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0024] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0025] It should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0026] Please refer to Figure 1 As shown, an embodiment of the present application provides a stacked battery, comprising: a substrate structure 100A, a composite junction 100B and a top battery structure 100C stacked in sequence; wherein the composite junction 100B comprises a conductive film layer 107, an interface modification layer 108 and a hole transport layer 109 stacked in sequence on the substrate structure 100A, and the work function of the material of the interface modification layer 108 is smaller than the work function of the material of the conductive film layer 107.
[0027] The substrate structure 100A, the conductive film layer 107, the interface modification layer 108, the hole transport layer 109 and the top battery structure 100C are stacked in sequence; for example, the conductive film layer 107 can be ITO (indium tin oxide semiconductor transparent conductive film); the interface modification layer (LWF) 108 uses LWF technology to focus the ion beam on the photoresist, and achieves precise patterning by controlling the shape and energy of the ion beam.
[0028] In the present application, the conductive film layer 107, the interface modification layer 108, and the hole transport layer (HTL) 109 form a composite junction 100B, and the work function of the material of the interface modification layer 108 is less than the work function of the material of the conductive film layer 107. The work function refers to the difference between the vacuum electron energy level E0 and the Fermi level EF of the semiconductor. The size of the work function is usually about half of the ionization energy of the free atom of the metal, and the work function reflects the minimum energy required for electrons to move from the inside of the solid to the surface.
[0029] The present application utilizes an interface modification layer 108 of a low work function material to perform surface modification on the conductive film layer 107 material in the composite junction 100B, introduces an ultra-thin interface modification layer 108 of a low work function material at the interface of the composite junction 100B, and designs the I TO / HTL structure to achieve better energy band bending, thereby improving the carrier tunneling efficiency of the composite junction 100B and improving the performance of the stacked battery.
[0030] The low work function material of the interface modification layer 108 includes any one or more of n-type amorphous silicon, n-type microcrystalline silicon, n-type microcrystalline silicon oxide, zinc oxide, lithium fluoride, magnesium fluoride and the like.
[0031] It should be noted that the low work function material of the interface modification layer 108 means that the work function of the material of the interface modification layer 108 is lower than the work function of the material of the conductive film layer 107 .
[0032] Furthermore, the coverage of the conductive film layer 107 by the interface modification layer 108 is between 50% and 75%, and can be fine-tuned according to the thickness and coverage of the conductive film layer 107 in the stacking direction.
[0033] The interface modification layer 108 material should avoid overlapping with the top battery structure 100C in the stacking direction. The optical simulation results show that the introduction of the interface modification layer 108 material (the thickness in the stacking direction is 2nm) increases the optical transmittance in the range of 800nm to 1200nm. The increase in transmittance indicates that more photons can be absorbed by the substrate structure 100A (bottom battery), thereby converting them into electron-hole pairs, thereby improving the long-wave optical response of the substrate structure 100A (bottom battery).
[0034] In order to avoid the introduction of the interface modification layer 108 material significantly reducing the direct contact between the conductive film layer 107 and the hole transport layer 109, it is necessary to optimize the coverage of the interface modification layer 108 material. Figure 2 As shown, it can be seen from the simulation results that the higher the coverage of the interface modification layer 108 on the conductive film layer 107, the better the anti-reflection effect. However, when the coverage of the interface modification layer 108 on the conductive film layer 107 exceeds 50% to 75%, the anti-reflection effect has reached the optimal value of 99.7% to 99.9%. Therefore, the coverage of the interface modification layer 108 on the conductive film layer 107 is defined between 50% and 75%.
[0035] For the substrate structure 100A, refer to Figure 1 In some embodiments, the substrate structure 100A at least includes a substrate conductive film layer 101, a p+ emitter, a first passivation layer 103, a substrate 104, a second passivation layer 105 and an n+ emitter 106 stacked in sequence, and a conductive film layer 107 is located on the n+ emitter 106. The coverage of the conductive film layer 107 on the n+ emitter 106 is between 30% and 100%, such as Figure 3 As shown, the conductive film layer 107 does not fully cover the n+ emitter 106, a portion of the n+ emitter 106 is exposed, and the exposed n+ emitter 106 is 1-(30% to 100%).
[0036] In some embodiments, the top cell structure 100C includes at least a perovskite layer (PVSK) 110 , an electron transport layer (ETL) 111 , and a top conductive film layer 113 stacked in sequence, and the perovskite layer 110 is located on the hole transport layer 109 .
[0037] In some other embodiments, a buffer layer 112 may be further disposed between the electron transport layer 111 and the top conductive film layer 113 .
[0038] PVSK refers to mixed perovskite, a material with an ABX3 structure, where the A position is usually a monovalent organic or inorganic cation, B is a metal cation, and X is a halogen anion. Mixed perovskite materials have excellent performance in photovoltaic (PV) applications, especially in solar cells, due to their high optical absorption coefficient, high carrier mobility, and long carrier diffusion length.
[0039] The material of the electron transport layer 111 can be C60 (known as carbon 60 or Fullerene, a non-metallic single material), or C40, titanium dioxide, tin oxide, zinc oxide, zinc oxide-zinc sulfide or doped C60, etc.; and the buffer layer 112 is mainly atomic layer deposited tin oxide (ALD-SnOx, atomic layer deposition SnOx).
[0040] The stacked battery of the present application is also provided with electrodes 114 at the top and bottom along the stacking direction, respectively, and the stacked battery is electrically connected through the electrodes 114 .
[0041] Based on this, an embodiment of the present application further provides a method for preparing a stacked battery, which is used to prepare the above-mentioned stacked battery, and the method comprises:
[0042] Step 200: A conductive film layer 107 is formed on the substrate structure 100A.
[0043] By way of example, the substrate structure 100A includes a substrate conductive film layer 101 , a p+ emitter, a first passivation layer 103 , a substrate 104 , a second passivation layer 105 and an n+ emitter 106 which are stacked in sequence.
[0044] Step 200 - 1 : Texturing and cleaning the substrate 104 ; the bottom may be an N-type single crystal silicon substrate 104 (Sub).
[0045] Step 200-2: Surface passivation is performed on both sides of the substrate 104 to form a first passivation layer 103 and a second passivation layer 105, respectively, which are denoted as Sub1; the passivation material can be amorphous silicon or silicon oxide, and the deposition method can be PECVD (plasma enhanced chemical vapor deposition), HWCVD (hot wire chemical vapor deposition) or thermal oxidation, etc.
[0046] Step 200 - 3: prepare a p+ emitter and an n+ emitter 106 on both sides of Sub1, respectively, which is denoted as Sub2;
[0047] The side of the first passivation layer 103 away from the substrate 104 forms a p+ emitter, and the side of the second passivation layer 105 away from the substrate 104 forms an n+ emitter 106; the emitter material can be amorphous silicon, microcrystalline silicon or polycrystalline silicon.
[0048] Step 200 - 4 : preparing a contact electrode 114 (substrate conductive film layer 101 ) on one side of the Sub2 p+ emitter 102 , which is denoted as Sub3 ; forming a substrate conductive film layer 101 on the side of the p+ emitter away from the first passivation layer 103 .
[0049] If it is TOPCon (Tunneling Oxide Passivation Contact), a new type of solar cell technology first demonstrated at the 28th International Conference on Solar Cells in 2013), the back structure should be SiOx (silicon oxide) / Poly-Si (polycrystalline silicon) / SiNx (silicon nitride) / metal contact.
[0050] If it is a HJT (heterojunction cell) structure, the back structure should be a-Si (amorphous silicon) / μc-Si (microcrystalline silicon) / I TO (indium tin oxide semiconductor transparent conductive film) / Metal contact.
[0051] Step 200-5: forming a conductive film layer 107 on the Sub3 n+ emitter 106; wherein the thickness of the conductive film layer 107 along the stacking direction is 1nm-20nm, and the coverage of the conductive film layer 107 on the n+ emitter 106 is between 30% and 100%; specifically, an RPD reactive plasma deposition process can be used.
[0052] Step 201: forming an interface modification layer 108 on the conductive film layer 107, so that the work function of the material of the interface modification layer 108 is smaller than the work function of the material of the conductive film layer 107, and the coverage of the interface modification layer 108 on the conductive film layer 107 is between 50% and 75%.
[0053] The thickness of the interface modification layer 108 along the stacking direction is 0 to 20 angstroms. The material of the interface modification layer 108 should be a periodic or non-periodic rectangular structure, a circular structure, an elliptical structure or an arbitrary polygonal structure.
[0054] The coverage of the conductive film layer 107 by the interface modification layer 108 is between 50% and 75%, which means that in the top view direction perpendicular to the stacking direction, the interface modification layer 108 does not fully cover the conductive film layer 107, and the proportion of the uncovered conductive film layer 107 is 1-(50% to 75%). When the coverage of the conductive film layer 107 is low, the thickness of the low work function material of the interface modification layer 108 is smaller, or even zero.
[0055] Step 202 : A hole transport layer 109 and a top battery structure 100C are sequentially stacked on the interface modification layer 108 .
[0056] Step 202-1: Prepare a perovskite hole transport layer 109 (HTL) on the low work function material of the interface modification layer 108; the hole material can be a self-assembled layer SAM (semiconductor saturable absorber), a polymer PTAA (poly [bis (4-phenyl) (2,4,6-trimethylphenyl) amine], an organic p-type semiconductor material), etc.
[0057] Step 202 - 2 : The top cell structure 100C is prepared on the hole transport layer 109 , thereby completing the preparation of the stacked cell.
[0058] The top cell structure 100C at least includes a perovskite layer 110 , an electron transport layer 111 , a buffer layer 112 and a top conductive film layer 113 stacked in sequence, and the perovskite layer 110 is located on the hole transport layer 109 .
[0059] In some embodiments, for perovskite / crystalline silicon stacked cells, the band gap of the perovskite layer 110 is between 1.65eV and 1.72eV, and the thickness along the stacking direction is 500nm to 900nm; the preparation method can be spin coating, slit coating, thermal evaporation, blade coating, etc.
[0060] For structures such as full perovskite stack, perovskite / organic stack, perovskite / CI GS stack, etc., the bandgap width and thickness of the perovskite layer 110 can be adjusted according to the principle of current matching.
[0061] It should be pointed out that Figure 1 Only the structure of a perovskite / SHJ stacked battery proposed in this application is listed. It is obvious that the inventor cannot enumerate all stacked battery structures. All stacked batteries adopting the RJ structure proposed in this application should be within the protection scope of this application.
[0062] In summary, the present application proposes a stacked battery and a preparation method thereof, targeting the carrier transport characteristics of perovskite / crystalline silicon stacked batteries, which can effectively improve the carrier tunneling characteristics of the top and bottom battery interfaces and improve battery efficiency.
[0063] The method for preparing the laminated battery has the same structure and beneficial effects as the laminated battery in the aforementioned embodiment. The structure and beneficial effects of the laminated battery have been described in detail in the aforementioned embodiment and will not be repeated here.
[0064] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A laminated battery, characterized in that: include: A substrate structure, a composite junction and a top cell structure are sequentially stacked; wherein the composite junction comprises a conductive film layer, an interface modification layer and a hole transport layer sequentially stacked on the substrate structure, and the work function of the material of the interface modification layer is smaller than the work function of the material of the conductive film layer.
2. The laminated battery according to claim 1, characterized in that: The coverage rate of the interface modification layer on the conductive film layer is between 50% and 75%.
3. The laminated battery according to claim 1, characterized in that: The thickness of the interface modification layer along the stacking direction is 1 angstrom to 20 angstroms.
4. The laminated battery according to claim 1, characterized in that: The material of the interface modification layer includes at least one or more of n-type amorphous silicon, n-type microcrystalline silicon, n-type microcrystalline silicon oxide, zinc oxide, lithium fluoride, and magnesium fluoride.
5. The laminated battery according to claim 1, characterized in that: The thickness of the conductive film layer along the stacking direction is 1 nm to 20 nm.
6. The laminated battery according to any one of claims 1 to 5, characterized in that: The substrate structure at least includes a substrate conductive film layer, a p+ emitter, a first passivation layer, a substrate, a second passivation layer and an n + The emitter, the conductive film layer is located at the n + On the emitter.
7. The laminated battery according to claim 6, characterized in that: The conductive film layer is connected to the n + The coverage of the emitter is between 30% and 100%.
8. The stacked battery according to any one of claims 1 to 5, characterized in that: The top cell structure at least includes a perovskite layer, an electron transport layer and a top conductive film layer stacked in sequence, and the perovskite layer is located on the hole transport layer.
9. The laminated battery according to claim 8, characterized in that: The band gap of the perovskite layer is 1.65 eV to 1.72 eV, and the thickness along the stacking direction is 500 nm to 900 nm.
10. A method for preparing a laminated battery, used for preparing the laminated battery according to any one of claims 1 to 9, characterized in that: The method comprises: forming a conductive film layer on the substrate structure; An interface modification layer is formed on the conductive film layer, so that the work function of the material of the interface modification layer is smaller than the work function of the material of the conductive film layer, and the coverage rate of the interface modification layer on the conductive film layer is between 50% and 75%; The interface modification layer is sequentially stacked to form a hole transport layer and a top battery structure.