Memory device, operating method thereof, and memory system

Abstract

The embodiment of the invention provides a memory device, an operation method of the memory device and a memory system, and the memory device comprises a memory unit array and a peripheral circuit coupled with the memory unit array. An operating method of a memory device includes: receiving a first instruction instructing dummy data to be written at a specified location in a memory cell array; in response to the first instruction, generating to-be-written dummy data; and writing the dummy data to be written into the specified position.

Description

Memory device and operation method thereof, and memory system Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory device, an operating method thereof, and a memory system. Background Art

[0002] Memory devices and systems are used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has become a mainstream product in the memory market due to its high storage density, manageable production costs, suitable programming and erasing speeds, and high data retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems.

[0004] Application Contents

[0005] Embodiments of the present disclosure provide a memory device, an operating method thereof, and a memory system.

[0006] In a first aspect, an embodiment of the present disclosure provides a memory device, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein:

[0007] The peripheral circuit is configured as follows:

[0008] receiving a first instruction instructing to write dummy data at a specified location in the memory cell array;

[0009] generating dummy data to be written in response to the first instruction; and

[0010] The dummy data to be written is written into the designated location.

[0011] In one embodiment, the first instruction is configured by a set feature command; or, the first instruction includes a first flag set on a reserved field of a write command.

[0012] In one embodiment, when the first instruction is configured through the set feature command, the command in which the first instruction is located does not include dummy data to be written;

[0013] When the first instruction includes a first flag set on a reserved field of a write command, the peripheral circuit is configured to: in response to the first instruction, not receive data information included in the write command, and directly generate dummy data to be written.

[0014] In one embodiment, the peripheral circuit is configured as follows:

[0015] Randomly generating the dummy data to be written;

[0016] or,

[0017] The dummy data to be written is generated according to the data stored at a position adjacent to the designated position in combination with a preset algorithm.

[0018] In one embodiment, the preset algorithm is related to coupling between memory cells in the memory cell array.

[0019] In one embodiment, the memory cell array includes a plurality of memory blocks; each of the memory blocks includes a plurality of valid memory pages and a plurality of dummy memory pages;

[0020] The specified location includes one of the following:

[0021] at least one memory block among the plurality of memory blocks;

[0022] at least one valid storage page in an erased state in one of the storage blocks;

[0023] At least one of the dummy storage pages in one of the storage blocks.

[0024] In one embodiment, the designated location includes at least one valid storage page in the storage block that is in an erased state; and a storage page adjacent to the designated location is in a programmed state.

[0025] In one embodiment, the peripheral circuit is further configured to:

[0026] receiving a second instruction, wherein the second instruction instructs to perform a read operation on data in the memory cell array;

[0027] In response to the second instruction, the data to be read is returned; wherein, when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header portion of the returned data frame; the second flag indicates that the read data includes dummy data.

[0028] In one embodiment, the peripheral circuit is further configured to:

[0029] After writing the dummy data to be written into the designated location, saving the designated location;

[0030] Before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the stored designated location;

[0031] When the address corresponding to the data to be read is within the address range corresponding to the stored designated position, it is determined that the data to be read includes dummy data.

[0032] In another aspect, an embodiment of the present disclosure provides a memory system, including:

[0033] One or more memory devices as described in the above embodiments of the present disclosure; and

[0034] A memory controller is coupled to the memory device and controls the memory device.

[0035] In one embodiment, the memory system includes a solid-state drive.

[0036] In another aspect, an embodiment of the present disclosure provides a memory system, comprising: at least one memory device and a memory controller coupled to and controlling the memory device;

[0037] The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array;

[0038] The memory controller is configured to: send a first command, the first command including a first instruction and a plurality of address instructions; the first instruction instructs to write dummy data at designated locations corresponding to the plurality of address instructions;

[0039] The peripheral circuit in the memory device is configured to: receive the first command, generate dummy data to be written in response to the first command; and write the dummy data to be written into designated locations corresponding to the multiple address instructions.

[0040] In one embodiment, the memory controller is configured to: send a second command, the second command including a second instruction, the second instruction instructing to perform a read operation on data in the memory cell array;

[0041] The peripheral circuit is configured to: receive the second instruction, and return the data to be read in response to the second instruction; wherein, when the data to be read includes dummy data, set a second flag on a reserved field in a frame header portion of the returned data frame; the second flag indicates that the read data includes dummy data;

[0042] The memory controller is further configured to: receive the returned data to be read, and when the second flag exists in the returned data frame, stop receiving the remaining data frames or do not perform a decoding operation on the returned data to be read.

[0043] In one embodiment, the memory controller is configured to: send a second command, the second command including a second instruction, the second instruction instructing to perform a read operation on data in the memory cell array;

[0044] The peripheral circuit is configured to: receive the second instruction, and return data to be read in response to the second instruction; wherein the data to be read includes dummy data;

[0045] The memory controller is further configured to: receive the returned data to be read, and discard the data to be read when decoding of the returned data to be read fails.

[0046] In another aspect, an embodiment of the present disclosure provides a method for operating a memory device, the method comprising:

[0047] receiving a first instruction instructing to write dummy data at a specified location in a memory cell array of the memory device;

[0048] generating dummy data to be written in response to the first instruction; and

[0049] The dummy data to be written is written into the designated location.

[0050] In one embodiment, the first instruction is configured by a set feature command; or, the first instruction includes a first flag set on a reserved field of a write command.

[0051] In one embodiment, when the first instruction is configured through the set feature command, the command in which the first instruction is located does not include dummy data to be written;

[0052] When the first instruction includes a first flag set on a reserved field of a write command, in response to the first instruction, data information included in the write command is not received, and dummy data to be written is directly generated.

[0053] In one embodiment, generating dummy data to be written includes:

[0054] Randomly generating the dummy data to be written;

[0055] or,

[0056] The dummy data to be written is generated according to the data stored at a position adjacent to the designated position in combination with a preset algorithm.

[0057] In one embodiment, the method further comprises:

[0058] receiving a second instruction, wherein the second instruction instructs to perform a read operation on data in the memory cell array;

[0059] In response to the second instruction, the data to be read is returned; wherein, when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header portion of the returned data frame; the second flag indicates that the read data includes dummy data.

[0060] In one embodiment, the method further comprises:

[0061] After writing the dummy data to be written into the designated location, saving the designated location;

[0062] Before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the stored designated location;

[0063] When the address corresponding to the data to be read is within the address range corresponding to the stored designated position, it is determined that the data to be read includes dummy data.

[0064] In an embodiment of the present disclosure, a memory device, an operating method thereof, and a memory system are proposed. The operating method of the memory device includes: receiving a first instruction, the first instruction instructing to write dummy data at a specified location in a memory cell array of the memory device; generating dummy data to be written in response to the first instruction; and writing the dummy data to be written to the specified location. After receiving the dummy data to fill the specified location, the memory device in the embodiment of the present disclosure generates dummy data based on its own characteristics and stores the dummy data at the specified location. In this way, the memory device generates dummy data based on its own characteristics, which can replace the memory controller in transmitting dummy data to the memory device. This can save the transmission time of the dummy data, reduce the time of filling the dummy data, and improve the throughput of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0066] FIG2 a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0067] FIG2 b is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0068] FIG3 a is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0069] FIG3 b is a schematic diagram of an exemplary memory device including peripheral circuits according to an embodiment of the present disclosure;

[0070] FIG4 is a cross-sectional schematic diagram of a memory cell array including a NAND memory according to an embodiment of the present disclosure;

[0071] FIG5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present disclosure;

[0072] FIG6 is a schematic diagram of an exemplary memory system including a memory controller and a memory device according to an embodiment of the present disclosure;

[0073] FIG7 is a schematic diagram of a flowchart of an operating method for a memory device according to an embodiment of the present disclosure;

[0074] FIG8 is a schematic diagram of a write command when a memory device performs a write operation according to an embodiment of the present disclosure;

[0075] FIG9 is a schematic diagram of address information of a write command corresponding to a three-bit memory cell (TLC) provided by an embodiment of the present disclosure;

[0076] FIG10 is a schematic diagram of a read instruction when a memory device performs a read operation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0078] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0079] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0080] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0081] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0082] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0083] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0084] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0085] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host 108 and a memory system 102, and memory system 102 has one or more memory devices 104 and a memory controller 106. Host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 108 can be configured to send data to or receive data from memory device 104.

[0086] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0087] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) on data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced MiniDisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0088] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end-use electronic products. In one example, as shown in FIG2a, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS card, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ). In another example, as shown in FIG2b, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. SSD 206 may also include an SSD connector 208 that couples SSD 206 to a host (eg, host 108 in FIG. 1 ). In some implementations, SSD 206 has a greater storage capacity and / or operating speed than memory card 202.

[0089] Figure 3a illustrates a schematic structural diagram of a memory cell array of a three-dimensional NAND memory. As shown in Figure 3a, the memory cell array of the three-dimensional NAND memory comprises several parallel, staggered rows of memory cell rows parallel to gate isolation structures. Every two rows of memory cell rows are separated by a gate isolation structure and an upper select gate isolation structure, and each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. The multiple second gate isolation structures may divide the memory blocks into multiple finger storage areas. An upper select gate isolation structure disposed between each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. The memory block shown in Figure 3a includes six memory slices. In practical applications, the number of memory slices in a memory block is not limited to this.

[0090] In some embodiments, each memory block can be coupled to multiple word lines, and multiple memory cells coupled to each individually controlled word line constitute a memory page (Page). The memory page mentioned here is a physical page (Physical Page). For example, in Figure 3a, all memory cells coupled to a word line in each memory slice constitute a memory page.

[0091] It should be noted that the number of memory cell rows between the gate isolation structure and the upper select gate isolation structure shown in FIG3a is merely illustrative and does not limit the number of memory cell rows contained in a finger storage area of ​​the 3D NAND memory disclosed herein. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted based on actual conditions, such as 2, 4, 8, or 16.

[0092] FIG3 b shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. For illustration, memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0093] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also known as a two-bit memory cell, Double-Level Cell), three bits per cell (also known as a three-bit memory cell (TLC), four bits per cell (also known as a four-bit memory cell (QLC), five bits per cell (also known as a five-bit memory cell (PLC), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0094] As shown in FIG3b , each memory string 308 may include a lower select transistor 310 (also known as a source-side select transistor, which includes a source select gate BSG) at its source terminal and an upper select transistor 312 (also known as a drain-side select transistor, which includes a drain select gate TSG) at its drain terminal. The source select transistor BSG310 and the drain select transistor TSG312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0095] As shown in FIG3 b , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, referring to FIG. 3 a , multiple memory cells are isolated from each other by an upper select gate isolation structure and a gate isolation structure. The memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, with each memory cell row being parallel to the gate isolation structure and the upper select gate isolation structure. The memory cells in a memory slice sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page based on the storage mode of the corresponding memory cell 306 (e.g., SLC or MLC as described above). The logical page can constitute the basic data unit for programming and reading operations.

[0096] 3a and 3b, each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (eg, top selection transistor (TSG) 312).

[0097] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308, according to some aspects of the present disclosure. As shown in FIG4 , the NAND memory cell array 301 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically extending through the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0098] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0099] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0100] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0101] 3 b , peripheral circuitry 302 may be coupled to memory cell array 301 via bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, FIG5 shows some exemplary peripheral circuits, where the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an I / F interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in FIG5 may also be included.

[0102] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0103] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0104] The control logic 512 can be coupled to each of the other parts in the peripheral circuit described above and is configured to control the operation of each of the other parts in the peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0105] It should be understood that in the process of writing data, multiple steps are required, and the performance and correctness of data writing are important characteristics of the memory system, so the process of writing data has high requirements. In the existing data writing process, in order to ensure the stability of the data, some special processing can be performed, such as filling the memory cell array with dummy data (Dummy Data) and the like. The dummy data here can be any random data. The dummy data is not used for reading, but plays a specific role, such as alleviating the coupling effect of the storage page with unwritten data on the adjacent storage page with written data, thereby improving the data retention in the written storage cell.

[0106] A memory system may include a memory controller and a memory device, the memory device may include a memory cell array and peripheral circuits, the memory cell array may include multiple memory blocks, each memory block including multiple memory pages; during the data writing process, some memory blocks in the memory device may not be fully written with data, and the physical characteristics of the memory system require that when power is off (or shut down) or under certain conditions, the partially written memory blocks must be filled with dummy data to ensure the stability of the written data. In some embodiments, the method of filling the dummy data includes: the memory controller sends a special command to the memory device, the special command indicating that dummy data is to be filled in certain memory pages in the memory device, and sending corresponding dummy data to be written to the memory device. When the memory device receives the special command and the dummy data to be written, the received dummy data is filled in the memory pages that need to be filled with dummy data. However, the process of filling the dummy data consumes a long time, and the content of the filled dummy data is data that the user does not care much about.

[0107] To address one or more of the above-mentioned issues, embodiments of the present disclosure provide a memory device, an operating method thereof, and a memory system. Referring to FIG. 1 and FIG. 6 , a memory system 102 includes at least one memory device 104 and a memory controller 106 coupled to and controlling the memory device. The memory controller 106 can access or control the memory device 104 according to certain timing rules. The memory controller 106 can enable a host 108 (a device accessing the memory device) to use the storage resources on the memory device 104 according to its requirements through address signals (address information / address instructions, ADDR), data signals (data instructions, DATA), control signals (control instructions, CTRL), and various command signals (CMD). The memory device 104 includes a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. Referring to FIG. 7 , the operating method of the memory device includes:

[0108] Step S701: receiving a first instruction, wherein the first instruction instructs writing dummy data into a specified location in the memory cell array 301;

[0109] Step S702: generating dummy data to be written in response to the first instruction; and

[0110] Step S703: writing the dummy data to be written into the designated location.

[0111] The memory cell array 301 may include multiple memory planes, each memory plane may include multiple memory blocks, each memory block may include multiple memory pages, a memory page is the minimum unit for read and write (i.e., programming) operations, and a memory block is the minimum unit for erase operations. In some embodiments, each memory block may include multiple valid memory pages and multiple dummy memory pages. It can be understood that the aforementioned memory pages are a general term for valid memory pages and dummy memory pages. The valid memory pages are memory pages contained in the area corresponding to the word lines (WL) or channel holes (CH), and are used to store user data (actual data). Here, a memory channel structure is formed in the memory channel hole. The dummy memory pages are memory pages contained in the area corresponding to the dummy word lines (DWL) or dummy channel holes (DCH), and are generally used for special functions such as support, fault repair, bad block processing, etc., and are not used to store actual data. Here, a dummy channel structure is formed in the dummy channel hole. The multiple valid storage pages and the multiple dummy storage pages may be arranged at intervals or adjacently. It should be understood that the multiple valid storage pages and the multiple dummy storage pages are all physical pages.

[0112] The peripheral circuit 302 may include any suitable digital, analog, and / or mixed-signal circuitry configured to facilitate various operations such as reading, writing, and erasing of the memory device. For example, the peripheral circuit may include control logic (e.g., a control circuit or controller), a data buffer, a decoder (a decoder may also be referred to as a decoder), a driver, and a read / write circuit. When the control logic receives a read / write operation command and address data, the decoder, under the control of the control logic, may apply a corresponding voltage from the driver to the corresponding bit line or word line based on the decoded address to implement data reading and writing, and exchange data with the outside world through the data buffer.

[0113] It should be noted that the execution entities of steps S701 to S703 may include peripheral circuits. Referring to Figure 5, more specifically, the I / F interface 516 is used to receive a first instruction and transmit the first instruction to the control logic 512. The control logic 512 is used to generate dummy data according to the first instruction. The page buffer / sense amplifier 504, the column decoder / bit line driver 506, the row decoder / word line driver 508, the voltage generator 510 and the control logic 512 are used to jointly execute the writing of dummy data.

[0114] In step S701 , a first instruction is received.

[0115] In some embodiments, when there is an unfilled memory block in the memory cell array, the memory controller or host sends a first instruction to instruct the specified location of the memory device to be filled with dummy data. Here, the first command may include a first instruction CMD and multiple address instructions ADDR; here, the memory device 104 is used to receive the first instruction, and the first instruction CMD is used to instruct the writing of dummy data at the specified location in the memory cell array 301. Exemplarily, referring to Figure 8, the multiple address instructions ADDR include a four-bit row address (R1, R2, R3, R4), which is the address of the specified location in the memory cell array 301. In some embodiments, the first instruction is configured via a Set Features command; or, the first instruction includes a first flag set in a reserved field of a write command.

[0116] In some specific embodiments, the first instruction is configured by setting a feature command. Here, the premise is that the memory device supports setting feature commands, and setting feature commands can also be supported by the memory controller or the host. Under this premise, the first instruction can be directly configured by setting feature commands. By setting feature commands, a custom protocol such as the first instruction can be directly edited to realize communication between the memory device and the memory controller or the host regarding the first instruction. It should be noted that when the first instruction is configured by the setting feature command, the command where the first instruction is located does not contain dummy data to be written. The command where the first instruction is located contains a page programming command, i.e., a dummy data write command and the address of the dummy data to be written. For example, the first command of the dummy data write command in the ONFI protocol is the 81h command.

[0117] In some specific embodiments, the first instruction includes a first flag set on a reserved field of a write command. That is, in some embodiments, the first instruction can be embedded in a regular write command of the memory device. A conventional write command may include a first part and a second part, wherein the first part includes an address instruction (address information) and the second part includes data information. In the embodiment of the present disclosure, the first instruction includes a first flag set on a reserved field of the write command, that is, the first instruction is embedded in the reserved field of the write command (this type of write command will be referred to as a special write command later). For example, referring to Figure 9, Figure 9 shows a schematic diagram of the address information of the write command corresponding to a three-bit storage cell (TLC); the write command includes 6 groups of address information (First, Second, Third, Fourth, Fifth, Sixth), wherein the sixth group (Sixth) of address information is provided with multiple reserved addresses (such as the multiple LOWs shown in the dotted box in Figure 9), and the reserved field of the write command can be any one of the multiple reserved addresses in the sixth group (Sixth) of address information. In other words, any one of the multiple reserved addresses shown in the dotted box in Figure 9 can be used to set the first flag.

[0118] When the first instruction includes a first flag set in a reserved field of a write command, the peripheral circuit, in response to the first instruction, does not receive the data information contained in the write command and directly generates dummy data to be written. Because the memory device does not receive data information, the memory controller or host can randomly generate invalid data information to meet the format requirements of the write command when generating the corresponding special write command. Furthermore, when transmitting these special write commands, the memory controller or host can also only transmit the address instruction without transmitting the data information; in this way, the memory device can receive only the address information through the first instruction, without receiving the data information.

[0119] In other embodiments, the first instruction can also be configured via a vendor command. A vendor-unique command is a command that is not available to the general public but is only used by a specific agreed-upon vendor, such as a manufacturer. A vendor-unique command is only available when the user is the agreed-upon vendor. When configuring via a vendor command, the protocols on the memory device and the memory controller need to be updated, i.e., the two parties must re-agreed on the protocol. Similarly, the command containing the first instruction does not need to contain data information.

[0120] In some embodiments, when the memory controller or the host sends the first instruction to instruct to write dummy data at a designated location in the memory cell array, the memory controller or the host does not generate dummy data.

[0121] Here, the designated location may be any location in the memory cell array of the memory device where no data is written. In some embodiments, the designated location includes one of the following:

[0122] at least one memory block among the plurality of memory blocks;

[0123] at least one valid storage page in an erased state in one of the storage blocks;

[0124] At least one of the dummy storage pages in one of the storage blocks.

[0125] Exemplarily, the designated location may include at least one of the plurality of storage blocks. When one or more storage blocks of the memory cell array do not store any data (i.e., blank blocks) and some special test operations need to be performed, such as verifying whether the program erase count is normal, verifying the erase time, etc., it is necessary to write data in these storage blocks, but the written data itself is not of concern. In this case, dummy data can be written in these storage blocks to achieve the purpose of rapid testing. Exemplarily, the designated location may include at least one valid storage page in an erased state in one of the storage blocks; the storage page adjacent to the designated location is in a programmed state. It can be understood that when data is written to a part of the storage pages in a storage block, that is, a part of the storage pages are in a programmed state, and data is not written to the remaining part of the storage pages, that is, the other part of the storage pages are in an erased state, the voltage level of the storage page in the erased state is different from that of the storage page in the programmed state, so that the electrons in the storage page in the programmed state adjacent to the storage page in the erased state are offset, that is, an electronic coupling effect is generated, which reduces the retention force of the data in the storage page in the programmed state; based on this, after data is written to a part of the storage pages in the storage block, dummy data is stored in one or more storage pages without data written adjacent to the storage page with written data, so that the electronic coupling effect of the storage page in the programmed state can be reduced.

[0126] Exemplarily, the designated location may include all remaining valid memory pages in an erased state in a memory block. It is understood that a memory block is generally the smallest execution unit for performing an erase operation. During an erase operation on a memory block, not only are the memory pages in the erase block with written data erased, but also the valid memory pages in the erased state that have no data written to them. This may cause over-erasure of the valid memory pages in the erased state, thereby causing problems such as leakage current in the memory cell. In this case, writing dummy data to all remaining valid memory pages in the erased state in the memory block can reduce the probability of over-erasure and improve the performance of the memory device. For example, as previously mentioned, multiple memory pages in a memory block are divided into valid memory pages and dummy memory pages; wherein, valid memory pages are memory pages used to store data, and dummy memory pages are used for special functions such as support, fault repair, bad block processing, etc. It is understandable that when dummy memory pages are arranged adjacent to valid data pages, the dummy memory pages may also have the aforementioned electronic coupling effect on the valid data pages, and when the dummy memory pages do not store data and are in an erased state, the aforementioned over-erasure problem also exists. In this case, storing dummy data in the dummy memory pages can reduce the electronic offset of the valid memory pages adjacent to the dummy memory pages and alleviate the over-erasure problem, thereby improving the performance of the memory device.

[0127] In step S702 , the memory device autonomously generates dummy data to be written in response to the first instruction.

[0128] In some embodiments, generating dummy data to be written includes:

[0129] The dummy data to be written is randomly generated; or the dummy data to be written is generated according to data stored at a position adjacent to the designated position in combination with a preset algorithm.

[0130] It is understandable that users do not care much about the content of the dummy data, and the dummy data does not need to be read and reused later. Based on this, the dummy data can be randomly generated by the memory device according to its own characteristics, or calculated according to its actual needs.

[0131] In some specific embodiments, the randomly generated dummy data may be all “0”, or all “1”, or a random combination of “1” and “0”.

[0132] In other specific embodiments, to reduce electronic coupling effects between adjacent memory pages, a set of dummy data can be calculated based on data in a programmed memory page in combination with a preset algorithm. Here, the adjacent memory pages can be a memory page with written data and an adjacent memory page with no written data; the preset algorithm is related to the coupling effects between memory cells in the memory cell array.

[0133] It can be understood that when the storage data corresponding to the storage unit of a certain storage page includes "1" or "0", the electrons are in different layers of the channel structure. At this time, if the adjacent storage page is in an erased state, the position of the electrons is fixed, and the electrons in the fixed position have different coupling effects on the adjacent electrons in different layers. At this time, the virtual data that minimizes the coupling effect can be inferred based on the data in the storage page where the data is written, so as to obtain more accurate virtual data to be written, thereby more accurately reducing the electron coupling effect between adjacent storage pages and improving data stability.

[0134] In step S703 , the generated dummy data to be written is written to a designated location.

[0135] It should be noted that the generated dummy data to be written will also first enter the page buffer (Pagebuffer), and then be written from the page buffer to the storage unit at the designated location.

[0136] Based on this, after receiving the first instruction instructing to fill the designated position with dummy data, the memory device in the above-mentioned embodiment of the present disclosure generates dummy data according to its own characteristics and stores the dummy data at the designated position. In this way, on the one hand, the memory device generates dummy data according to its own characteristics, which can replace the memory controller to transmit dummy data to the memory device, thereby saving the transmission time of dummy data, reducing the time to fill dummy data, and improving the throughput of the memory system; on the other hand, storing dummy data at the designated position can reduce the coupling effect between the storage page where data is written and the storage page where data is not written in the memory device, thereby improving the stability of the written data.

[0137] In practice, some application scenarios require reading data from a memory cell array. For example, after a memory device experiences an abnormal power outage, all currently stored data in the memory device is read. Based on the read results, a post-power-out data recovery strategy is determined. The following describes how to handle the situation in these scenarios when dummy data previously stored in the memory device is read.

[0138] In some embodiments, the method further includes: receiving a second instruction, the second instruction instructing to perform a read operation on the data in the memory cell array;

[0139] In response to the second instruction, the data to be read is returned; wherein, when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header portion of the returned data frame; the second flag indicates that the read data includes dummy data.

[0140] The second instruction received by the memory device is a read instruction, which includes address information for performing a read operation. For example, referring to FIG. 10 , the read instruction shown in FIG. 10 includes data bus DQ[7:0], a read cycle type (Cycle Type) for the read operation, column address information (C1, C2), row address information (R1, R2, R3, R4), and wait times tWB, tR, and tRR after sending the read instruction. The memory device reads the memory page corresponding to the column address information (C1, C2) and row address information (R1, R2, R3, R4) according to the second instruction. After reading the data in the corresponding memory page, the memory device returns the read data to the memory controller or host. Based on the returned data, the memory controller or host can determine whether the read data includes dummy data.

[0141] Exemplarily, when the data to be read includes dummy data, a second flag is set in a reserved field of a frame header portion of a returned data frame. Upon receiving the returned data to be read, the memory controller or host determines whether to perform a decoding operation on the returned data to be read based on whether the second flag is present in the returned data frame. When the second flag is present in the returned data frame, it indicates that the returned data to be read includes dummy data. In this case, the memory controller or host stops receiving the remaining data frames or does not perform a decoding operation on the returned data to be read. When the second flag is not present in the returned data frame, it indicates that the returned data to be read does not include dummy data. In this case, the memory controller or host continues receiving the remaining data frames and performs a decoding operation on the returned data to be read.

[0142] It should be noted that there are two situations in the returned data. One is that there is no dummy data in the returned data (all actual data). In this case, the memory controller performs normal operations. The other is that there is dummy data in the returned data. In this case, there are two methods to distinguish the dummy data. The first is that if the returned dummy data carries a corresponding flag, such as the second flag mentioned above, the dummy data can be selected by the flag; the second is that if the returned dummy data does not have any flag, in this case, considering that the dummy data is generated by the memory device according to its own characteristics, its address is not stored in the logical-physical mapping table (LTP). In this case, the actual data can be selected according to the logical-physical mapping table, and the remaining data is dummy data.

[0143] It should also be noted that when writing dummy data into the memory device, the dummy data is not encoded like normal data. Based on this, the writing time of the dummy data is shorter than the writing time of normal valid data. However, when decoding the dummy data, there will be decoding failures. Since the user does not care about the dummy data, the dummy data can be discarded directly.

[0144] In some embodiments, the method further includes: after writing the dummy data to be written to the designated location, saving the designated location; before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the saved designated location; when the address corresponding to the data to be read is within the address range corresponding to the saved designated location, determining that the data to be read includes dummy data.

[0145] That is, after writing the dummy data to a designated location in a memory cell array of the memory device, the memory device saves the address corresponding to the designated location; after reading the data to be read from the memory cell array according to the instruction of the second instruction, the memory device checks whether the address corresponding to the data to be read is within the address range corresponding to the saved designated location; if the address corresponding to the data to be read is within the address range corresponding to the saved designated location, it indicates that the data to be read includes dummy data, and a second flag can be set in a reserved field of a frame header portion of a returned data frame; if the address corresponding to the data to be read is not within the address range corresponding to the saved designated location, it indicates that the data to be read does not include dummy data, and the second flag is not set in the reserved field of a frame header portion of a returned data frame. In this way, a basis can be provided for determining whether the returned data includes dummy data.

[0146] On the other hand, an embodiment of the present disclosure further provides a memory device, which includes: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein,

[0147] The peripheral circuit is configured as follows:

[0148] receiving a first instruction instructing to write dummy data at a specified location in the memory cell array;

[0149] generating dummy data to be written in response to the first instruction; and

[0150] The dummy data to be written is written into the designated location.

[0151] In some embodiments, the first instruction is configured by a set feature command; or, the first instruction includes a first flag set on a reserved field of a write command.

[0152] In some embodiments, when the first instruction is configured through the set feature command, the command in which the first instruction is located does not contain dummy data to be written;

[0153] When the first instruction includes a first flag set on a reserved field of a write command, the peripheral circuit is configured to: in response to the first instruction, not receive data information included in the write command, and directly generate dummy data to be written.

[0154] In some embodiments, the peripheral circuit is configured to:

[0155] Randomly generating the dummy data to be written;

[0156] or,

[0157] The dummy data to be written is generated according to the data stored at a position adjacent to the designated position in combination with a preset algorithm.

[0158] In some embodiments, the predetermined algorithm is related to coupling between memory cells in the memory cell array.

[0159] In some embodiments, the memory cell array includes a plurality of memory blocks; each of the memory blocks includes a plurality of valid memory pages and a plurality of dummy memory pages;

[0160] The specified location includes one of the following:

[0161] at least one memory block among the plurality of memory blocks;

[0162] at least one valid storage page in an erased state in one of the storage blocks;

[0163] At least one of the dummy storage pages in one of the storage blocks.

[0164] In some embodiments, the designated location includes at least one valid storage page in the storage block that is in an erased state; and a storage page adjacent to the designated location is in a programmed state.

[0165] In some embodiments, the peripheral circuit is further configured to:

[0166] receiving a second instruction, wherein the second instruction instructs to perform a read operation on data in the memory cell array;

[0167] In response to the second instruction, the data to be read is returned; wherein, when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header portion of the returned data frame; the second flag indicates that the read data includes dummy data.

[0168] In some embodiments, the peripheral circuit is further configured to:

[0169] After writing the dummy data to be written into the designated location, saving the designated location;

[0170] Before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the stored designated location;

[0171] When the address corresponding to the data to be read is within the address range corresponding to the stored designated position, it is determined that the data to be read includes dummy data.

[0172] In some embodiments, the memory device comprises a NAND-type memory.

[0173] It should be noted that the above hardware part and conventional working principle of the memory device can be understood with reference to the aforementioned Figures 3a to 5, and the above method of processing dummy data by the memory device can refer to the method of processing dummy data in the aforementioned operating method of the memory device.

[0174] On the other hand, the present disclosure also discloses a memory system, which includes one or more memory devices as described in the above embodiments of the present disclosure, and

[0175] A memory controller is coupled to the memory device and controls the memory device; the memory controller is used to control the memory device to perform read, write, and erase operations. The memory controller and the memory device can be coupled in any suitable manner. In the disclosed embodiments, the memory device can be a semiconductor memory that stores non-volatile data, such as a NAND memory. The memory system is connected to a host, which can be an electronic device such as a personal computer or a mobile terminal.

[0176] In some embodiments, the memory system includes a universal flash storage (UFS) device or a solid-state drive (SSD).

[0177] In another aspect, the present disclosure also discloses a memory system, comprising: at least one memory device and a memory controller coupled to and controlling the memory device;

[0178] The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array;

[0179] The memory controller is configured to: send a first command, the first command including a first instruction and a plurality of address instructions; the first instruction instructs to write dummy data at designated locations corresponding to the plurality of address instructions;

[0180] The peripheral circuit in the memory device is configured to: receive the first command, generate dummy data to be written in response to the first command; and write the dummy data to be written into designated locations corresponding to the multiple address instructions.

[0181] Here, in this embodiment, the first command is issued by the memory controller.

[0182] In some embodiments, the memory controller is configured to: send a second command, the second command including a second instruction, the second instruction instructing to perform a read operation on data in the memory cell array;

[0183] The peripheral circuit is configured to: receive the second instruction, and return the data to be read in response to the second instruction; wherein, when the data to be read includes dummy data, set a second flag on a reserved field in a frame header portion of the returned data frame; the second flag indicates that the read data includes dummy data;

[0184] The memory controller is further configured to: receive the returned data to be read, and when the second flag exists in the returned data frame, stop receiving the remaining data frames or do not perform a decoding operation on the returned data to be read.

[0185] Here, in this embodiment, the second command is issued by the memory controller.

[0186] In some embodiments, the memory controller is configured to: send a second command, the second command including a second instruction, the second instruction instructing to perform a read operation on data in the memory cell array;

[0187] The peripheral circuit is configured to: receive the second instruction, and return data to be read in response to the second instruction; wherein the data to be read includes dummy data;

[0188] The memory controller is further configured to: receive the returned data to be read, and discard the data to be read when decoding of the returned data to be read fails.

[0189] An embodiment of the present disclosure provides a storage medium having executable instructions stored thereon. When the executable instructions are executed by a memory controller, the steps of the method described in any one of the above embodiments can be implemented.

[0190] In the embodiments of the present disclosure, the storage medium may be a NAND memory in a memory device, and the NAND memory may store executable instructions, which may be the firmware in the above embodiments. Thus, the memory controller may execute the executable instructions in the storage medium, thereby implementing the steps of any of the methods in the above embodiments.

[0191] It should be understood that “some embodiments” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in some embodiments” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0192] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory device, comprising: A memory cell array and a peripheral circuit coupled to the memory cell array; wherein, The peripheral circuit is configured as: receiving a first instruction, wherein the first instruction instructs writing dummy data at a specified location in the memory cell array; In response to the first instruction, generating dummy data to be written; and The dummy data to be written is written into the designated location.

2. The memory device according to claim 1, wherein: The first instruction is configured by a set feature command; or, the first instruction includes a first flag set on a reserved field of a write command.

3. The memory device according to claim 2, wherein: When the first instruction is configured through the set feature command, the command in which the first instruction is located does not contain dummy data to be written; When the first instruction includes a first flag set on a reserved field of a write command, the peripheral circuit is configured to: in response to the first instruction, not receive data information included in the write command, and directly generate dummy data to be written.

4. The memory device according to claim 1, wherein: The peripheral circuit is configured as: Randomly generate the dummy data to be written; or, The dummy data to be written is generated according to the data stored at the adjacent position of the designated position in combination with a preset algorithm.

5. The memory device according to claim 4, wherein: The preset algorithm is related to the coupling between the memory cells in the memory cell array.

6. The memory device according to claim 1, wherein: The memory cell array includes a plurality of memory blocks; each of the memory blocks includes a plurality of valid memory pages and a plurality of dummy memory pages; The specified location includes one of the following: at least one storage block among the plurality of storage blocks; at least one of the valid storage pages in one of the storage blocks is in an erased state; At least one of the dummy storage pages in one of the storage blocks.

7. The memory device according to claim 6, wherein: The designated position includes at least one of the valid storage pages in the storage block that is in an erased state; and the storage page adjacent to the designated position is in a programmed state.

8. The memory device according to claim 1, wherein: The peripheral circuit is further configured as: receiving a second instruction, wherein the second instruction instructs to perform a read operation on data in the memory cell array; In response to the second instruction, the data to be read is returned; wherein, when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header portion of the returned data frame; and the second flag indicates that the read data includes dummy data.

9. The memory device according to claim 8, wherein: The peripheral circuit is further configured as: After writing the dummy data to be written into the designated location, saving the designated location; Before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the stored designated position; When the address corresponding to the data to be read is within the address range corresponding to the stored designated position, it is determined that the data to be read includes dummy data.

10. A memory system comprising: One or more memory devices as claimed in any one of claims 1 to 9; as well as A memory controller is coupled to the memory device and controls the memory device.

11. The memory system according to claim 10, wherein: The memory system includes a solid state drive.

12. A memory system comprising: at least one memory device and a memory controller coupled to and controlling the memory device; The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array; The memory controller is configured to: send a first command, the first command including a first instruction and a plurality of address instructions; the first instruction instructs to write dummy data at a specified location corresponding to the plurality of address instructions; The peripheral circuit in the memory device is configured to: receive the first command, generate dummy data to be written in response to the first command; and write the dummy data to be written into designated locations corresponding to the multiple address instructions.

13. The memory system according to claim 12, wherein: The memory controller is configured to: send a second command, the second command comprising a second instruction, the second instruction instructing to perform a read operation on data in the memory cell array; The peripheral circuit is configured to: receive the second instruction, and return the data to be read in response to the second instruction; wherein, when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header portion of the returned data frame; the second flag indicates that the read data includes dummy data; The memory controller is further configured to: receive the returned data to be read, and when the second flag exists in the returned data frame, stop receiving the remaining data frames or do not perform a decoding operation on the returned data to be read.

14. The memory system according to claim 12, wherein: The memory controller is configured to: send a second command, the second command comprising a second instruction, the second instruction instructing to perform a read operation on data in the memory cell array; The peripheral circuit is configured to: receive the second instruction, and return the data to be read in response to the second instruction; wherein the data to be read includes dummy data; The memory controller is further configured to: receive the returned data to be read, and when decoding of the returned data to be read fails, discard the data to be read.

15. A method for operating a memory device, comprising: receiving a first instruction instructing to write dummy data at a specified location in a memory cell array of the memory device; In response to the first instruction, generating dummy data to be written; as well as The dummy data to be written is written into the designated location.

16. The operating method according to claim 15, wherein: The first instruction is configured by a set feature command; or, the first instruction includes a first flag set on a reserved field of a write command.

17. The operating method according to claim 16, wherein: When the first instruction is configured through the set feature command, the command in which the first instruction is located does not contain dummy data to be written; When the first instruction includes a first flag set on a reserved field of a write command, in response to the first instruction, data information included in the write command is not received, and dummy data to be written is directly generated.

18. The operating method according to claim 17, wherein: The generating of dummy data to be written comprises: Randomly generate the dummy data to be written; or, The dummy data to be written is generated according to the data stored at the adjacent position of the designated position in combination with a preset algorithm.

19. The operating method according to claim 15, wherein: The method further comprises: receiving a second instruction, wherein the second instruction instructs to perform a read operation on data in the memory cell array; In response to the second instruction, the data to be read is returned; wherein, when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header portion of the returned data frame; and the second flag indicates that the read data includes dummy data.

20. The operating method according to claim 19, wherein: The method further comprises: After writing the dummy data to be written into the designated location, saving the designated location; Before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the stored designated position; When the address corresponding to the data to be read is within the address range corresponding to the stored designated position, it is determined that the data to be read includes dummy data.

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