FPGA-based inductosyn closed-loop tracking type position solver and design method thereof

Abstract

The invention discloses an inductosyn closed-loop tracking type position solver based on an FPGA and a design method thereof, and belongs to the field of industrial automation. The position solver comprises a detection module, a tracker module and a sine and cosine transformation module which are in signal connection. Wherein the detection module is used for respectively carrying out carrier multiplication and filtering processing on two-phase output electromotive force of the inductosyn; the tracker module is used for performing cross multiplication on the filtered signal and the output of the sine and cosine transformation module and then performing subtraction to obtain a result as output, and the output of a proportional-integral tracker is used as a tracking angle through an integrator cascade proportional-integral controller and is used as output for subsequent compensation; and the sine and cosine transformation module is used for taking a result obtained by performing amplitude periodication on the tracking angle according to 360 degrees as input of sine and cosine solving, and then taking output of the sine and cosine solving as a feedback signal to be transmitted to the tracker module. According to the invention, the anti-interference capability is enhanced by optimizing the algorithm structure, and the real-time performance of the algorithm is ensured by using the parallel processing technology.

Description

Technical Field

[0001] The invention belongs to the field of industrial automation, and in particular relates to an FPGA-based inductive synchronizer closed-loop tracking position solver and a design method thereof. Background Art

[0002] In recent years, with the development of science and technology, the industrial automation field has increasingly higher requirements for the real-time and precision of the angle measurement systems used. In the field of harsh environments, certain requirements are also put forward for the reliability of angle measurement components. For application scenarios where high-precision positioning and high reliability requirements coexist, inductive synchronizers are a more suitable choice.

[0003] According to the calculation structure, the induction synchronizer angle calculation method is mainly divided into two types: open-loop and closed-loop. The open-loop structure is relatively simple and has a fast calculation speed. It is often used in scenarios where the device requirements are not high and the environmental changes are slight. The closed-loop structure has stronger anti-interference ability at the system level and is more suitable for some complex environments.

[0004] FPGA is a programmable logic device that can be programmed at the hardware level. It has high flexibility and reconfigurability. It contains a large number of programmable logic units and interconnection resources. It can be designed and programmed using a hardware description language. Its advantages lie in its strong parallel processing capabilities, low latency, low power consumption, and the ability to implement complex logic and algorithms.

[0005] The inductive synchronizer processing system has very high requirements for the sampling speed and accuracy of the signal. The subsequent angle solution structure is relatively complex and has certain constraints on the real-time performance of each internal module. The properties of FPGA can meet the requirements. Summary of the invention

[0006] The purpose of the present invention is to solve the above problems existing in the prior art and to provide an FPGA-based induction synchronizer closed-loop tracking position solver and a design method thereof.

[0007] The present invention enhances the anti-interference capability by optimizing the algorithm structure and ensures the real-time performance of the algorithm by utilizing the parallel processing technology.

[0008] To achieve the above object, the technical solution adopted by the present invention is:

[0009] An FPGA-based induction synchronizer closed-loop tracking position solver, the position solver comprises a detection module, a tracker module and a sine-cosine transform module which are sequentially connected in signal; wherein:

[0010] The detection module is used to obtain the envelope signals of the sine phase and the cosine phase by synchronous demodulation method from the collected induced electromotive force digital signals of the sine phase and the cosine phase orthogonal to each other, and transmit the envelope signals to the tracker module;

[0011] The tracker module is used to cross-multiply the envelope signals of the sine phase and cosine phase with the cosine and sine of the output angle fed back, and then make a difference. The result is sent to the integrator and proportional-integral controller in sequence as the tracking error, and the final tracked value is output to complete the angle tracking process. The data is passed to the sine-cosine transformation module for feedback processing and as an output for subsequent compensation;

[0012] The sine-cosine transform module is used to build the CORDIC IP core. It transforms the angle output by the tracker module into sine and cosine respectively, and feeds them back to the input end respectively.

[0013] Furthermore, the detection module includes a carrier multiplication module and a filtering module, and the carrier multiplication module and the filtering module are signal-connected; wherein:

[0014] The carrier multiplication module is used to multiply the collected two-phase output electromotive force with the same-phase carrier signal corresponding to the output potential. The specific formula is as follows:

[0015]

[0016] The multiplication is implemented using the multiplier IP core, E A With E B The induced electromotive force of the sine and cosine phases output by the induction synchronizer is orthogonal to each other, E A The phase ratio E B Lag 90°; E′ A and E′ B It is the signal after multiplying the sine and cosine two-phase carriers and waiting for low-pass filtering, ω is the excitation frequency of the induction synchronizer, β is the phase of the excitation signal of the induction synchronizer; the sin(ωt+β) signal is generated by the DDS IP core;

[0017] The filtering module is used to filter the envelope signal after carrier multiplication through a FIR low-pass filter, and pass the filtered envelope signal to the tracker module.

[0018] Furthermore, the filtering module is used to filter the envelope signal after carrier multiplication through an FIR low-pass filter, and pass the filtered envelope signal to the tracker module, specifically:

[0019] The filter module converts E′ A and E′ BThrough the FIR low-pass filter, the sampling frequency, cutoff frequency, window function and filter order of the FIR low-pass filter are set in the MATLAB filter designer. After the cutoff frequency is 1 / 10 of the excitation frequency of the induction synchronizer, the filter coefficients are derived and loaded into the FIR Compiler IP core. The sine phase and cosine phase envelope signals are filtered and used as the signal E″ of the input tracker module. A With E″ B .

[0020] Further, the tracker module includes a comparison module and a type II tracker, and the comparison module is signal-connected to the type II tracker; wherein:

[0021] Comparison module, used to convert signal E″ A With E″ B Multiply the cosine and sine values ​​of the final output signal φ respectively, and then make a difference to get the processed result ∈rror; the specific formula is as follows:

[0022] ∈rror=E″ A cosφ-E″ B sinφ

[0023] in: The cosine and sine values ​​are implemented with the CORDIC IP core to determine the number of bits of the final output angle. Based on the required delay, the number of bits and accuracy of the CORDIC output value are determined.

[0024] The multiplication in the above formula is implemented using the multiplier IP core, and the error data uses a 32-bit fixed-point number with 27 decimal places;

[0025] The type II tracker is used to take the error result processed by the comparison module as input, first send it to the integrator, multiply it by a coefficient, and then send it to the proportional-integral controller; assuming that the input of the proportional-integral link is r(t) and the output is c(t), the expression is:

[0026] c(t)=K p r(t)+K i ∫r(t)dt

[0027] Among them: the integrator is implemented by an accumulator, and a gain needs to be cascaded at the front end of the accumulator. A multiplier IP core is shared between the gain and the integrator as input to compensate for the sampling frequency of the accumulator multiplied by the integrator; the proportional link of the proportional-integral controller adopts a multiplier IP core, and the integral link has the same structure as the integrator. The addition of the proportional and integral results needs to be implemented using an adder IP core, and the output of the proportional-integral is the tracking angle output value φ.

[0028] Furthermore, the sine-cosine transformation module is used to transform the angle output by the tracker module into sine and cosine respectively, and feed them back to the input end respectively; specifically:

[0029] The sine-cosine transform module performs a signal carry transformation on the tracking angle output value φ of the tracker module according to an amplitude of 360° as a cycle, and inputs the result of this transformation into the CORDIC IP core as the final output angle.

[0030] A design method for a closed-loop tracking position solver of an induction synchronizer based on FPGA, the design method comprising the following steps:

[0031] Step 1: Use the model library under Simulink and write functions to simulate the closed-loop tracking position solver, and use this as the evaluation standard for hardware function simulation;

[0032] Step 2: Use Verilog HDL language to implement the closed-loop tracking position solver module;

[0033] Step 3: The closed-loop tracking position solver module involves addition, multiplication, and sine and cosine operations, which are processed by calling the IP core in the Vivado environment;

[0034] Step 4: Perform functional simulation of the angle calculation algorithm built with the hardware description language under Vivado's SIMULATION, and compare the simulation results with those of the simulink model to determine the correctness of the algorithm function.

[0035] The beneficial effect of the present invention over the prior art is that the design method of the present invention has obvious advantages over the currently commonly used DSP software architecture. The method has the following advantages:

[0036] 1. The algorithm structure has strong anti-interference ability;

[0037] 2. The entire algorithm can be integrated into one FPGA;

[0038] 3. The system has strong real-time performance.

[0039] The FPGA-based induction synchronizer closed-loop tracking position solver proposed in the present invention can achieve high-precision and high-stability position measurement, and is particularly suitable for the field of industrial automation. The solver of the present invention reduces the user's difficulty of use through modular design, and only needs to configure the corresponding adjustment parameters to meet the use requirements. At the same time, it can realize dynamic adjustment of the induction synchronizer to achieve high-precision measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1It is a flow chart of the design method of the FPGA-based induction synchronizer closed-loop tracking position solver of the present invention.

[0041] Figure 2 This is the Sinulink simulation model diagram of the closed-loop tracking method.

[0042] Figure 3 This is the Simulink simulation result diagram.

[0043] Figure 4 This is the simulation result diagram under Vivado environment.

[0044] Figure 5 It is the FPGA flow chart of the implementation example. DETAILED DESCRIPTION

[0045] Specific implementation method 1: This implementation method discloses a closed-loop tracking position solver based on FPGA, the position solver includes a detection module, a tracker module and a sine-cosine transformation module connected in sequence; the detection module, the tracker module and the sine-cosine transformation module are connected in sequence according to Figure 1 Build the system using hardware description language;

[0046] The detection module is used to obtain the envelope signals of the sine phase and the cosine phase by using the synchronous demodulation method (which is the prior art) of the collected sine phase and cosine phase two-phase mutually orthogonal induced electromotive force digital signals, and transmit the envelope signals to the tracker module;

[0047] The tracker module is used to cross-multiply the envelope signals of the sine phase and cosine phase with the cosine and sine of the output angle fed back (the sine phase is multiplied by the cosine of the output angle fed back, and the cosine phase is multiplied by the sine of the output angle fed back), and then make a difference, and send the result as the tracking error to the integrator and the proportional-integral controller in sequence, output the final tracked value, complete the angle tracking process, and pass the data to the sine-cosine transform module for feedback processing and as an output for subsequent compensation;

[0048] The sine-cosine transform module is used to build the CORDIC IP core. It transforms the angle output by the tracker module into sine and cosine respectively, and feeds them back to the input end respectively.

[0049] Furthermore, the detection module includes a carrier multiplication module and a filtering module, and the carrier multiplication module and the filtering module are signal-connected (the detection module improves the efficiency and accuracy of signal processing by combining the carrier multiplication module and the filtering module); wherein:

[0050] The carrier multiplication module is used to multiply the collected two-phase output electromotive force with the same-phase carrier signal corresponding to the output potential. The specific formula is as follows:

[0051]

[0052] The multiplication (i.e., the two brackets on the right side of the equal sign are multiplication relations) is implemented using the multiplier IP core, E A With E B The induced electromotive force of the sine and cosine phases output by the induction synchronizer is orthogonal to each other, E A The phase ratio E B Lag 90°; E′ A and E′ B It is the signal after multiplying the sine and cosine two-phase carriers and waiting for low-pass filtering, ω is the excitation frequency of the induction synchronizer, β is the phase of the excitation signal of the induction synchronizer; the sin(ωt+β) signal is generated by the DDS IP core;

[0053] The filtering module is used to filter the envelope signal after carrier multiplication through a FIR low-pass filter (to ensure the quality of the signal and the accuracy of tracking), and pass the filtered envelope signal to the tracker module.

[0054] Furthermore, the filtering module is used to filter the envelope signal after carrier multiplication through an FIR low-pass filter, and pass the filtered envelope signal to the tracker module, specifically:

[0055] The filter module converts E′ A and E′ B Through the FIR low-pass filter, the sampling frequency, cutoff frequency, window function and filter order of the FIR low-pass filter are set in the MATLAB filter designer. After the cutoff frequency is 1 / 10 of the excitation frequency of the induction synchronizer, the filter coefficients are derived and loaded into the FIR Compiler IP core. The sine phase and cosine phase envelope signals are filtered and used as the signal E″ of the input tracker module. A With E″ B The effect is: improving the efficiency and effect of filtering, ensuring the quality of the signal and the accuracy of tracking.

[0056] Further, the tracker module includes a comparison module and a type II tracker, and the comparison module is signal-connected to the type II tracker; wherein:

[0057] Comparison module, used to convert signal E″ A With E″ B Multiply the cosine and sine values ​​of the final output signal φ respectively, and then make a difference to get the processed result error; the specific formula is as follows:

[0058] error=E″ A cosφ-E″ Bsinφ

[0059] Among them: the cosine and sine values ​​of φ are implemented using the CORDIC IP core, the number of bits of the final output angle is determined, and the number of bits and accuracy of the CORDIC output value are determined based on the required delay;

[0060] The multiplication in the above formula is implemented using the multiplier IP core, and the error data uses a 32-bit fixed-point number with 27 decimal places;

[0061] The type II tracker is used to take the error result processed by the comparison module as input, first send it to the integrator (the first-level integral link), multiply it by a coefficient, and then send it to the proportional-integral controller (the second-level proportional-integral link); set the input of the proportional-integral link to r(t) and the output to c(t), then the expression is:

[0062] c(t)=K p r(t)+K i ∫r(t)dt

[0063] Among them: the integrator is implemented by an accumulator, and a gain needs to be cascaded at the front end of the accumulator. A multiplier IP core is shared between the gain and the integrator as input to compensate for the sampling frequency of the accumulator multiplied by the integrator; the proportional link of the proportional-integral controller (the second-level proportional-integral link) uses a multiplier IP core, and the integral link has the same structure as the integrator. The addition of the proportional and integral results needs to be implemented by an adder IP core (here, the output of the proportional link and the integral link is guaranteed, that is, the data format of the two inputs of the adder should be as consistent as possible, which is achieved by data truncation). The output of the proportional-integral is the tracking angle output value φ. The accuracy of angle tracking and the stability of the system are improved.

[0064] Furthermore, the sine-cosine transformation module is used to transform the angle output by the tracker module into sine and cosine respectively, and feed them back to the input end respectively; specifically:

[0065] The sine-cosine transform module transforms the tracking angle output value φ of the tracker module according to the amplitude of 360° as a cycle, and inputs the result of this transformation into the CORDIC IP core as the final output angle, thus realizing periodic signal processing.

[0066] Specific implementation method 2: This implementation method is a design method of a closed-loop tracking position solver for an induction synchronizer based on FPGA as described in specific implementation method 1. The present invention uses matlab software in a simulink environment to model and simulate a system of an induction synchronizer running at a constant speed. The simulation mainly analyzes the two-phase output and position solution of the induction synchronizer to verify the rationality and correctness of the algorithm and the entire system construction. The design method includes the following steps:

[0067] Step 1: Use the model library under Simulink and write functions to realize the simulation of the closed-loop tracking position solver (angle solving algorithm), and use this as the evaluation standard for hardware (FPGA) function simulation;

[0068] Step 2: Use Verilog HDL language to implement the closed-loop tracking position solver module;

[0069] Step 3: The closed-loop tracking position solver module involves addition, multiplication, and sine and cosine operations, which are processed by calling the IP core in the Vivado environment;

[0070] Step 4: Perform functional simulation of the angle calculation algorithm built with the hardware description language under Vivado's SIMULATION, and compare the simulation results with those of the simulink model to determine the correctness of the algorithm function.

[0071] The present invention uses matlab software in simulink environment to model and simulate the system of induction synchronizer running at a constant speed. The simulation mainly analyzes the two-phase output and position decoding of the induction synchronizer to verify the rationality and correctness of the algorithm and the construction of the entire system.

[0072] The design method of the present invention utilizes the model library and programming functions under Simulink to realize the simulation of the closed-loop tracking angle solving algorithm, and uses this as the evaluation standard of the FPGA function simulation test. According to the analysis of the closed-loop tracking solving algorithm, it can be concluded that the position solver mainly includes a detection module, a tracking module and a sine-cosine solving module. Figure 2 The following is a Sinulink simulation model diagram of the closed-loop tracking method (i.e., the simulink simulation model diagram of the feedback tracking solution algorithm). Based on the design concept from top to bottom, the various modules of the closed-loop tracking position solver are designed in the Vivado environment. Based on the previous analysis of the algorithm, the basic framework of the FPGA to implement the closed-loop tracking position solver (closed-loop tracking angle solution algorithm) can be designed.

[0073] During the design and coding process, each functional module is simulated and verified step by step, and the results of FPGA simulation test correspond to the results of Simulink model simulation. The present invention selects Xilinx xc7z020clg400-2 as the loading carrier of the bit stream.

[0074] Embodiment 1:

[0075] This embodiment discloses a design method of an induction synchronizer closed-loop tracking position solver based on FPGA, which generally includes the following steps:

[0076] 1) Analyze the characteristics of the two-phase output signal of the induction synchronizer, determine the demodulation scheme and the characteristics of the angle change, and determine the type of tracker.

[0077] 2) Using MATLAB software in the Simulink environment, the feedback tracking method is modeled and simulated. The simulation results are as follows: Figure 3 As shown in the figure, it mainly includes tracking error and tracking angle. The simulation results of the model are used as the reference standard for FPGA algorithm design.

[0078] 3) Xilinx xc7z020clg400-2 chip is selected as the hardware platform, and Verilog HDL is used to implement the feedback tracking algorithm.

[0079] 4) Compile the code in the Vivado2017.4 environment and simulate each module of the software. On the premise that the functions of each module are correct, perform an overall simulation and compare the simulation results with those of Simulink.

[0080] 5) Comprehensively implement the module and generate bitstream to download to the board for onboard debugging.

[0081] The details of Example 1 include the following steps:

[0082] 1) The modules subdivided on FPGA are as follows Figure 5 As shown, the DDS IP core is used to simulate the digital signal of the two-phase electromotive force of the induction synchronizer input by the 16-bit AD converter in the actual system.

[0083] 2) The two-phase electromotive force is transmitted to the detection module respectively, that is, the two-phase output signal is multiplied by the sine signal generated by the DDS IP core with the same frequency and phase as the induction synchronizer excitation signal, and then passed through a FIR filter to obtain the waveform after detection. After the FIR filter adjusts the corresponding frequency characteristics in the filter designer in matlab, the parameter file of the filter is generated, and then the file is imported into the FIR compiler IP core in vivado to realize the function of the digital filter.

[0084] 3) Multiply the filtered signal with the cosine and sine values ​​of the final output, and perform the difference through the subtractor to obtain the input of the tracking system. The sine and cosine transform of the final output angle is implemented using the CORDIC IP core.

[0085] 4) Determine that the tracker is a type II tracker, multiply the input of the tracking system and the gain through a multiplier, and input the multiplication result into the accumulator of the first stage.

[0086] 5) The output result of the accumulator in the first stage is input into the subsequent proportional and integral modules respectively. The proportional module multiplies the output result of the accumulator in the first stage by the proportional gain to obtain the integral output result; the integral module multiplies the result of the accumulator in the first stage by the integral gain, inputs the multiplication result into the accumulator, and the output of the accumulator is used as the integral output result; the proportional output result and the integral output result are added by the adder to obtain the tracking result.

[0087] 6) Normalize the tracking results periodically, use them as input to the CORDIC IP core, and get the final output results, such as Figure 4 As shown, Figure 4 It includes the demodulated output signal of the induction synchronizer, the tracking error and the normalized angle tracking signal.

[0088] The number of bits of all data in the above process is Figure 5 format to set.

[0089] The above specific implementation methods or examples are only used to explain the technical solutions of the present invention, and are not intended to limit the present application. The detailed description parts are regarded as conventional technical means or common knowledge in the field. Ordinary technicians in this field should understand that based on the design concept of the present application, the technical solutions recorded in the aforementioned implementation methods should be adaptively modified, or some or all of the technical features therein should be replaced by equivalents. These modifications and replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

[0090] The above are only preferred specific implementation modes of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and inventive concepts of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. An FPGA-based induction synchronizer closed-loop tracking position solver, characterized in that: The position solver comprises a detection module, a tracker module and a sine-cosine transform module which are connected in sequence; wherein: The detection module is used to obtain the envelope signals of the sine phase and the cosine phase by synchronous demodulation method from the collected induced electromotive force digital signals of the sine phase and the cosine phase orthogonal to each other, and transmit the envelope signals to the tracker module; The tracker module is used to cross-multiply the envelope signals of the sine phase and cosine phase with the cosine and sine of the output angle fed back, and then make a difference. The result is sent to the integrator and proportional-integral controller in sequence as the tracking error, and the final tracked value is output to complete the angle tracking process. The data is passed to the sine-cosine transformation module for feedback processing and as an output for subsequent compensation; The sine-cosine transform module is used to build the CORDICIP core. It transforms the angle output by the tracker module into sine and cosine respectively, and feeds them back to the input end respectively.

2. The position resolver according to claim 1, characterized in that: The detection module includes a carrier multiplication module and a filtering module, and the carrier multiplication module and the filtering module are signal-connected; wherein: The carrier multiplication module is used to multiply the collected two-phase output electromotive force with the same-phase carrier signal corresponding to the output potential. The specific formula is as follows: The multiplication is implemented using the multiplier IP core, E A With E B The induced electromotive force of the sine and cosine phases output by the induction synchronizer is orthogonal to each other, E A The phase ratio E B Lag 90°; E' A With E' B It is the signal after multiplying the sine and cosine two-phase carriers and waiting for low-pass filtering, ω is the excitation frequency of the induction synchronizer, β is the phase of the excitation signal of the induction synchronizer; the sin(ωt+β) signal is generated by the DDS IP core; The filtering module is used to filter the envelope signal after carrier multiplication through a FIR low-pass filter, and pass the filtered envelope signal to the tracker module.

3. The position resolver according to claim 2, characterized in that: The filtering module is used to filter the envelope signal after carrier multiplication through a FIR low-pass filter, and pass the filtered envelope signal to the tracker module, specifically: The filter module will E' A With E' B Through the FIR low-pass filter, the sampling frequency, cutoff frequency, window function and filter order of the FIR low-pass filter are set in the MATLAB filter designer. After the cutoff frequency is 1 / 10 of the excitation frequency of the induction synchronizer, the filter coefficients are derived and loaded into the FIR Compiler IP core. The sine phase and cosine phase envelope signals are filtered and used as the signal E″ of the input tracker module. A With E″ B .

4. The position resolver according to claim 3, characterized in that: The tracker module includes a comparison module and a type II tracker, and the comparison module is connected to the type II tracker signal; wherein: Comparison module, used to convert signal E″ A With E″ B The final output signal The cosine and sine values ​​of are multiplied respectively, and then the difference is taken to obtain the processed result error; the specific formula is as follows: in: The cosine and sine values ​​are implemented with the CORDIC IP core to determine the number of bits of the final output angle. Based on the required delay, the number of bits and accuracy of the CORDIC output value are determined. The multiplication in the above formula is implemented using the multiplier IP core, and the error data uses a 32-bit fixed-point number with 27 decimal places; The type II tracker is used to take the error result processed by the comparison module as input, first send it to the integrator, multiply it by a coefficient, and then send it to the proportional-integral controller; assuming that the input of the proportional-integral link is r(t) and the output is c(t), the expression is: c(t)=K p r(t)+K i ∫r(t)dt Among them: the integrator is implemented by an accumulator, and a gain needs to be cascaded at the front end of the accumulator. A multiplier IP core is shared between the gain and the integrator as input to compensate for the sampling frequency of the accumulator multiplied by the integrator; the proportional link of the proportional-integral controller uses a multiplier IP core, and the integral link has the same structure as the integrator. The addition of the proportional and integral results needs to be implemented using an adder IP core, and the output of the proportional-integral is the tracking angle output value 5. The position resolver according to claim 4, characterized in that: The sine-cosine transform module is used to transform the angle output by the tracker module into sine and cosine respectively, and feed them back to the input end respectively; specifically: The sine-cosine transform module converts the tracking angle output value of the tracker module The signal is transformed according to the amplitude of 360° as a cycle, and the result of this transformation is input into the CORDIC IP core as the final output angle.

6. A design method for a closed-loop tracking position solver of an induction synchronizer based on FPGA according to any one of claims 1 to 5, characterized in that: The design method comprises the following steps: Step 1: Use the model library under Simulink and write functions to simulate the closed-loop tracking position solver, and use this as the evaluation standard for hardware function simulation; Step 2: Use Verilog HDL language to implement the closed-loop tracking position solver module; Step 3: The closed-loop tracking position solver module involves addition, multiplication, and sine and cosine operations, which are processed by calling the IP core in the Vivado environment; Step 4: Perform functional simulation of the angle calculation algorithm built with the hardware description language under Vivado's SIMULATION, and compare the simulation results with those of the simulink model to determine the correctness of the algorithm function.

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