PWM wave output device based on PCIE bus

Abstract

The invention discloses a PWM (Pulse Width Modulation) wave output device based on a PCIE (Peripheral Component Interface Express) bus. The PWM wave output device comprises a PCIE bus controller, a control module, a plurality of digital isolation modules and a bus driving module, the PCIE bus controller is connected with the control module through a PCIE bus, the control module is respectively connected with the digital isolation module and the bus driving module, and the digital isolation module is also connected with the bus driving module; wherein the PCIE bus controller is used for generating an initial PWM (Pulse Width Modulation) signal and sending the initial PWM signal to the control module; the control module is used for adjusting the initial PWM signal according to a preset control requirement; the digital isolation module is used for modifying the voltage of the adjusted PWM signal to a preset voltage and performing ground wire isolation; and the bus driving module is used for modifying the voltage of the adjusted PWM signal to a preset current to obtain a target PWM signal. Data transmission is carried out through the PCIE bus, and no extra controller needs to be arranged.

Description

Technical Field

[0001] The present application relates to the field of waveform control technology, and more specifically, to a PWM wave output device based on a PCIE bus. Background Art

[0002] PWM (Pulse Width Modulation) is a technology that modulates the width of a series of pulses to equivalently obtain the required waveform (including shape and amplitude). It can digitally encode the analog signal level, that is, adjust the change of signal, energy, etc. by adjusting the change of duty cycle. The configuration and implementation of PWM wave output device usually involves the configuration of timer, the setting of comparison register and automatic reload register, etc.

[0003] The core of the PWM wave output device is to control the average power or analog quantity of the output signal by adjusting the duty cycle of the pulse signal. Generally speaking, the PWM wave output device usually includes a microprocessor or controller, a timer and an output circuit, wherein the microprocessor or controller is responsible for generating the PWM signal and performing precise time control on it, the timer is used to set the period and duty cycle of the PWM signal, and the output circuit converts the PWM signal into the required analog quantity or power output.

[0004] However, in the prior art, a microprocessor or controller generally adopts FPGA, and a separate controller needs to be set for the duty cycle and frequency of the initial PWM signal input from the FPGA to generate the initial PWM signal, which increases the structure and volume of the PWM wave output device and increases the hardware cost of the PWM wave output device. Summary of the invention

[0005] In response to at least one defect or improvement need of the prior art, the present invention provides a PWM wave output device based on a PCIE bus, which is used to solve the problem in the prior art that a separate controller needs to be set up to generate an initial PWM signal, which increases the structure and volume of the PWM wave output device and increases the hardware cost of the PWM wave output device.

[0006] To achieve the above object, according to a first aspect of the present invention, a PWM wave output device based on a PCIE bus is provided, comprising: a PCIE bus controller, a control module, a plurality of digital isolation modules and a bus driver module; the PCIE bus controller is connected to the control module via the PCIE bus, the control module is respectively connected to the digital isolation module and the bus driver module, and the digital isolation module is also connected to the bus driver module;

[0007] Wherein, the PCIE bus controller is used to generate an initial PWM signal and send the initial PWM signal to the control module;

[0008] The control module is used to adjust the initial PWM signal according to the preset control requirements;

[0009] The digital isolation module is used to modify the voltage of the adjusted PWM signal to a preset voltage and perform ground isolation;

[0010] The bus driver module is used to modify the voltage of the adjusted PWM signal to a preset current to obtain a target PWM signal.

[0011] In a possible implementation, the control module includes a chip U1, and a first pin, a second pin, a third pin, a fourth pin, a fifth pin, and a sixth pin of the chip U1 are connected to a PCIE bus controller.

[0012] In a possible implementation, the chip U1 is a FPGA chip.

[0013] In one possible implementation, the digital isolation module includes a chip U2, resistors R1, R2, R9, and R10; the second pin and the third pin of the chip U2 are connected to the chip U1; one end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R1 is connected to the second pin of the chip U2, and the other end of the resistor R2 is connected to the third pin of the chip U2; the sixth pin of the chip U2 is connected to one end of the resistor R10, the other end of the resistor R10 is connected to one end of the resistor R9, and the other end of the resistor R9 is connected to the seventh pin of the chip U2; the first pin of the chip U2 is connected to the first preset voltage, and the eighth pin of the chip U2 is connected to the second preset voltage.

[0014] In one possible implementation, the bus driver module includes a chip U6; the first pin and the twenty-fourth pin of the chip U6 are connected to a second preset voltage; the second pin and the twenty-second pin of the chip U6 are connected to the chip U1; the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin, the ninth pin, and the tenth pin of the chip U6 are connected to the digital isolation module; the fourteenth pin, the fifteenth pin, the sixteenth pin, the seventeenth pin, the eighteenth pin, the nineteenth pin, the twentieth pin, and the twenty-first pin of the chip U6 are connected to the controlled device.

[0015] In a possible implementation, the FPGA chip is an XC7K325T-2FFG900I chip.

[0016] In a possible implementation, the chip U2 is a dual-channel digital isolation chip ADuM3200.

[0017] In a possible implementation, the chip U6 is a bus driver chip SN74LVCC3245DW.

[0018] In a possible implementation, the first preset voltage is 3.3V.

[0019] In a possible implementation, the second preset voltage is 5V.

[0020] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0021] The present invention provides a PWM wave output device based on PCIE bus, which transmits data through PCIE bus. PCIE bus can ensure high-speed and stable transmission of PWM signal with its high bandwidth and low delay characteristics, and improve the performance of the overall device. In particular, in occasions where fast response and high-precision control are required, PCIE bus has good compatibility as a widely used interface standard, so that the device can be easily integrated into various devices based on PCIE bus, reducing the difficulty and cost of device integration. The control module can adjust the initial PWM signal according to the preset control requirements. The user can adjust the frequency, duty cycle, etc. of the PWM signal according to specific application requirements to meet different control requirements. The adjustment process of the initial PWM signal is completed inside the control module without external intervention, which simplifies the operation process and improves the stability and reliability of the device. The digital isolation module modifies the voltage of the adjusted PWM signal to the preset voltage and performs ground isolation, which not only ensures the integrity of the signal during transmission, but also effectively prevents the intrusion of electrical noise and interference, improves the anti-interference ability of the device, and the ground isolation further enhances the safety of the device, especially when dealing with high voltage or high power applications, it can prevent potential electrical faults from causing damage to the device. The bus driver module modifies the voltage of the adjusted PWM signal to the preset current to obtain the target PWM signal, ensuring that the PWM signal has precise current control characteristics when driving the load. Precise current control helps improve the energy efficiency and stability of the device, while reducing the risk of load damage caused by current fluctuations. At the same time, the PCIE bus provided by the control module is connected to the PCIE controller, which has a high degree of intelligence and does not require a separate PCIE controller, saving hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic structural diagram of an embodiment of a PWM wave output device based on a PCIE bus provided by the present invention;

[0024] Figure 2 A schematic diagram of the structure of an embodiment of a control module provided by the present invention;

[0025] Figure 3 A schematic structural diagram of an embodiment of a digital isolation module provided by the present invention;

[0026] Figure 4 This is a schematic structural diagram of an embodiment of a bus driver module provided by the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, device, product or equipment that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or equipment.

[0029] See also Figure 1 , Figure 1 A schematic diagram of a structure of an embodiment of a PWM wave output device based on a PCIE bus provided by the present invention. In a specific embodiment of the present invention, a PWM wave output device 100 based on a PCIE bus is disclosed, comprising: a PCIE bus controller 110, a control module 120, a plurality of digital isolation modules 130 and a bus driver module 140; the PCIE bus controller 110 is connected to the control module 120 via a PCIE bus, the control module 120 is respectively connected to the digital isolation module 130 and the bus driver module 140, and the digital isolation module 130 is also connected to the bus driver module 140;

[0030] The PCIE bus controller 110 is used to generate an initial PWM signal and send the initial PWM signal to the control module 120;

[0031] The control module 120 is used to adjust the initial PWM signal according to the preset control requirements;

[0032] The digital isolation module 130 is used to modify the voltage of the adjusted PWM signal to a preset voltage and perform ground isolation;

[0033] The bus driving module 140 is used to modify the voltage of the adjusted PWM signal to a preset current to obtain a target PWM signal.

[0034] In the above embodiment, the PCIE bus controller 110 is responsible for generating the initial PWM signal, which is transmitted at high speed through the PCIE bus, ensuring the efficiency and stability of signal transmission. The PCIE bus controller, with its high bandwidth and low latency characteristics, makes the generation and transmission process of the PWM signal more efficient and reliable.

[0035] The control module 120 is closely connected to the PCIE bus controller 110, and receives the initial PWM signal sent by the PCIE bus controller 110. Inside the control module 120, the initial PWM signal is adjusted according to the preset control requirements, and the frequency, duty cycle or phase of the signal can be changed to meet the application requirements of a specific controlled device 200. The flexibility of the control module 120 enables the device to adapt to a variety of different application scenarios.

[0036] During the PWM signal transmission process, the digital isolation module 130 receives the adjusted PWM signal from the control module 120 and modifies the voltage of the signal to a preset voltage level. At the same time, the digital isolation module 130 also implements ground isolation, effectively preventing the intrusion of electrical noise and interference, ensuring the integrity and stability of the PWM signal during transmission, and improving the anti-interference ability of the device.

[0037] The bus driver module 140 receives the adjusted PWM signal from the digital isolation module 130 and further modifies the voltage of the signal to a preset current level, thereby obtaining a target PWM signal. The design of the bus driver module 140 ensures that the PWM signal has precise current control characteristics when driving the load, which is critical for applications that require precise control of the load state.

[0038] Compared with the prior art, the PWM wave output device 100 based on the PCIE bus provided in this embodiment transmits data through the PCIE bus. The PCIE bus, with its high bandwidth and low latency characteristics, can ensure high-speed and stable transmission of PWM signals, and improve the performance of the overall device. In particular, in situations where fast response and high-precision control are required, the PCIE bus, as a widely used interface standard, has good compatibility, so that the device can be easily integrated into various PCIE bus-based devices, reducing the difficulty and cost of device integration. The control module 120 can adjust the initial PWM signal according to the preset control requirements. The user can adjust the frequency, duty cycle, etc. of the PWM signal according to specific application requirements to meet different control requirements. The adjustment process of the initial PWM signal is completed inside the control module 120 without external intervention, which simplifies the operation process and improves the stability and reliability of the device. The digital isolation module 130 modifies the voltage of the adjusted PWM signal to a preset voltage and performs ground isolation, which not only ensures the integrity of the signal during transmission, but also effectively prevents the intrusion of electrical noise and interference, improves the anti-interference ability of the device, and further enhances the safety of the device, especially when dealing with high voltage or high power applications, it can prevent potential electrical faults from causing damage to the device. The bus driver module 140 modifies the voltage of the adjusted PWM signal to a preset current to obtain a target PWM signal, ensuring that the PWM signal has precise current control characteristics when driving the load. Precise current control helps to improve the energy efficiency and stability of the device, while reducing the risk of load damage caused by current fluctuations. At the same time, the PCIE bus of the control module 120 is connected to the PCIE controller, which has a high degree of intelligence and does not require a separate PCIE controller, saving hardware costs.

[0039] See also Figure 2 , Figure 2 This is a structural schematic diagram of an embodiment of the control module provided by the present invention. In some embodiments of the present invention, the control module 120 includes a chip U1, and the first pin, the second pin, the third pin, the fourth pin, the fifth pin, and the sixth pin of the chip U1 are connected to the PCIE bus controller 110.

[0040] In the above embodiment, the multi-pin design of the chip U1 enables it to achieve efficient data transmission and signal control with other key device components. Specifically, the first pin, the second pin, the third pin, the fourth pin, the fifth pin and the sixth pin of the chip U1 are all used to establish a direct and stable connection with the PCIE bus controller 110, which not only ensures the high speed of data transmission, but also greatly improves the overall response speed and stability of the device.

[0041] In some embodiments of the present invention, the chip U1 is a FPGA chip.

[0042] In the above embodiment, the FPGA chip is known for its high flexibility and programmability. It can be configured according to specific application requirements to implement complex logic functions. Using FPGA as the chip U1 means that the control module 120 can flexibly adjust its internal logic structure according to the data processing requirements in different scenarios, thereby optimizing performance and improving efficiency. In addition, FPGA also has powerful parallel processing capabilities and can handle a large number of concurrent tasks or high-speed data streams. Therefore, selecting FPGA chip U1 as the core of the control module 120 can improve the overall performance and flexibility of the device.

[0043] See also Figure 3 , Figure 3 A structural schematic diagram of an embodiment of the digital isolation module provided by the present invention. In some embodiments of the present invention, the digital isolation module 130 includes a chip U2, resistors R1, R2, R9, and R10; the second pin and the third pin of the chip U2 are connected to the chip U1; one end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R1 is connected to the second pin of the chip U2, and the other end of the resistor R2 is connected to the third pin of the chip U2; the sixth pin of the chip U2 is connected to one end of the resistor R10, the other end of the resistor R10 is connected to one end of the resistor R9, and the other end of the resistor R9 is connected to the seventh pin of the chip U2; the first pin of the chip U2 is connected to the first preset voltage, and the eighth pin of the chip U2 is connected to the second preset voltage.

[0044] In the above embodiment, chip U2 serves as the core of the digital isolation module 130, and its second pin and third pin are designed to be connected to chip U1 (usually the core chip in the control module 120), allowing control signals to be transmitted safely and efficiently between chips U1 and U2 while maintaining electrical isolation to prevent potential current interference or short circuit risks.

[0045] Resistors R1 and R2 play the role of voltage division and current limiting in the circuit. One end of each of them is connected to form a series circuit. The other end of resistor R1 is connected to the second pin of chip U2, while the other end of resistor R2 is connected to the third pin of chip U2. This configuration helps to ensure the stability and accuracy of the signal during transmission, while protecting chip U2 from damage caused by excessive current.

[0046] In addition, another voltage divider circuit is formed between the sixth pin and the seventh pin of the chip U2 through resistors R9 and R10. One end of the resistor R10 is connected to the sixth pin of the chip U2, and the other end is connected to one end of the resistor R9. The other end of the resistor R9 is connected to the seventh pin of the chip U2. The design of this voltage divider circuit is also to protect the chip U2 and ensure the stability and accuracy of the signal during transmission.

[0047] Finally, the first pin of the chip U2 is designed to receive a first preset voltage, which is a stable DC voltage source for providing the necessary working voltage for the chip U2. The eighth pin of the chip U2 receives a second preset voltage, which is used as a reference voltage or ground voltage of the chip to ensure that the chip can work normally.

[0048] It should be noted that multiple digital isolation modules 130 may be provided in the present invention. In a specific embodiment of the present invention, four digital isolation modules 130 are provided, and two by two are used in a group to provide forward PWM waves and reverse PWM waves.

[0049] See also Figure 4 , Figure 4 This is a structural schematic diagram of an embodiment of the bus driver module provided by the present invention. In some embodiments of the present invention, the bus driver module 140 includes a chip U6; the first pin and the twenty-fourth pin of the chip U6 are connected to the second preset voltage; the second pin and the twenty-second pin of the chip U6 are connected to the chip U1; the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin, the ninth pin, and the tenth pin of the chip U6 are connected to the digital isolation module 130; the fourteenth pin, the fifteenth pin, the sixteenth pin, the seventeenth pin, the eighteenth pin, the nineteenth pin, the twentieth pin, and the twenty-first pin of the chip U6 are connected to the controlled device 200.

[0050] In the above embodiment, in the pin configuration of chip U6, the first pin and the twenty-fourth pin are designed to receive a second preset voltage, and the second preset voltage is usually a stable DC power supply, which is used to provide the necessary operating voltage for chip U6 to ensure its normal operation, which not only ensures the stable operation of the chip, but also helps to improve the reliability of the entire device.

[0051] The second pin and the twenty-second pin of the chip U6 are connected to the chip U1 (usually the core chip in the control module 120), allowing the control signal to be efficiently transmitted between the chips U1 and U6, thereby realizing precise control of the bus driver module 140. Through the chip U1, the device can flexibly adjust the working state of the bus driver module 140 to meet the needs of different application scenarios.

[0052] In addition, the third to tenth pins of the chip U6 are designed to be connected to the digital isolation module 130, and these pins are electrically isolated from the controlled device 200 through the digital isolation module 130, thereby improving the anti-interference ability and safety of the device. The resistors and chip components in the digital isolation module 130 work together to ensure the stability and accuracy of the signal during transmission.

[0053] At the same time, the 14th to 21st pins of the chip U6 are directly connected to the controlled device 200, and these pins are responsible for transmitting the amplified and processed signals to the controlled device 200 to drive it to work normally. By accurately controlling the signals on these pins, the device can achieve accurate control of the controlled device 200, thereby meeting the needs of various application scenarios.

[0054] In some embodiments of the present invention, the FPGA chip is a XC7K325T-2FFG900I chip.

[0055] In the above embodiment, the FPGA chip is XC7K325T-2FFG900I, which is a high-performance FPGA with rich logic units, high-speed I / O interfaces and powerful processing capabilities, suitable for complex digital signal processing and control tasks. Using XC7K325T-2FFG900I as the core processing chip not only improves the processing speed of the device, but also enhances its flexibility and scalability, providing strong support for the development of high-performance electronic equipment.

[0056] In some embodiments of the present invention, the chip U2 is a dual-channel digital isolation chip ADuM3200.

[0057] In the above embodiment, the core chip U2 of the digital isolation module 130 is a dual-channel digital isolation chip ADuM3200, which has excellent electrical isolation performance and low power consumption. The dual-channel design of ADuM3200 enables it to provide two independent isolation channels in a single package, thereby simplifying circuit design and reducing costs. In addition, its high-speed transmission capability and high anti-interference performance ensure the stability and accuracy of the signal during transmission, providing a strong guarantee for the stable operation of the device.

[0058] In some embodiments of the present invention, the chip U6 is a bus driver chip SN74LVCC3245DW.

[0059] In the above embodiment, chip U6 is a bus driver chip SN74LVCC3245DW, which is a high-performance bus transceiver that supports 3.3V and 5V voltage conversion, has low power consumption, high-speed transmission and strong anti-interference ability. The design of SN74LVCC3245DW enables it to achieve efficient transmission and precise control of signals in complex electronic devices, thereby improving the overall performance and stability of the device.

[0060] In some embodiments of the present invention, the first preset voltage is 3.3V.

[0061] In the above embodiment, the first preset voltage is set to 3.3V, which is usually used as a power supply voltage for digital circuits because it can provide enough energy to drive transistors in digital circuits while maintaining low power consumption and heat generation. In addition, the voltage value of 3.3V is also compatible with most modern digital circuits and microprocessors, making the device more flexible and scalable in design.

[0062] In some embodiments of the present invention, the second preset voltage is 5V.

[0063] In the above embodiment, the second preset voltage is set to 5V, which is usually used as a power supply voltage for analog circuits or certain specific digital circuits because it can provide higher energy to drive a larger load or achieve higher signal integrity. In the bus driver module 140 and the digital isolation module 130, the voltage value of 5V helps to ensure the stability and accuracy of the signal during transmission, while improving the anti-interference ability of the device.

[0064] In summary, the present invention provides a PWM wave output device 100 based on the PCIE bus, which transmits data through the PCIE bus. The PCIE bus, with its high bandwidth and low latency characteristics, can ensure high-speed and stable transmission of PWM signals, thereby improving the performance of the overall device, especially in situations where fast response and high-precision control are required. As a widely used interface standard, the PCIE bus has good compatibility, so that the device can be easily integrated into various PCIE bus-based devices, reducing the difficulty and cost of device integration. The control module 120 can adjust the initial PWM signal according to the preset control requirements. The user can adjust the frequency, duty cycle, etc. of the PWM signal according to specific application requirements to meet different control requirements. The adjustment process of the initial PWM signal is completed inside the control module 120 without external intervention, which simplifies the operation process and improves the stability and reliability of the device. The digital isolation module 130 modifies the voltage of the adjusted PWM signal to a preset voltage and performs ground isolation, which not only ensures the integrity of the signal during transmission, but also effectively prevents the intrusion of electrical noise and interference, improves the anti-interference ability of the device, and further enhances the safety of the device, especially when dealing with high voltage or high power applications, it can prevent potential electrical faults from causing damage to the device. The bus driver module 140 modifies the voltage of the adjusted PWM signal to a preset current to obtain a target PWM signal, ensuring that the PWM signal has precise current control characteristics when driving the load. Precise current control helps to improve the energy efficiency and stability of the device, while reducing the risk of load damage caused by current fluctuations. At the same time, the PCIE bus of the control module 120 is connected to the PCIE controller, which has a high degree of intelligence and does not require a separate PCIE controller, saving hardware costs.

[0065] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0066] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0067] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0068] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0069] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0070] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, disk or optical disk and other media that can store program code.

[0071] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0072] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

[0073] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A PWM wave output device based on PCIE bus, characterized in that: include: PCIE bus controller, control module, several digital isolation modules and bus driver module; The PCIE bus controller is connected to the control module via a PCIE bus, the control module is connected to the digital isolation module and the bus driver module respectively, and the digital isolation module is also connected to the bus driver module; The PCIE bus controller is configured to generate an initial PWM signal and send the initial PWM signal to the control module; The control module is used to adjust the initial PWM signal according to a preset control requirement; The digital isolation module is used to modify the voltage of the adjusted PWM signal to a preset voltage and perform ground isolation; The bus driving module is used to modify the voltage of the adjusted PWM signal to a preset current to obtain a target PWM signal.

2. The PWM wave output device based on PCIE bus according to claim 1, characterized in that: The control module includes a chip U1 , and a first pin, a second pin, a third pin, a fourth pin, a fifth pin, and a sixth pin of the chip U1 are connected to the PCIE bus controller.

3. The PWM wave output device based on PCIE bus according to claim 2, characterized in that: The chip U1 is an FPGA chip.

4. The PWM wave output device based on PCIE bus according to claim 2, characterized in that: The digital isolation module includes a chip U2, resistors R1, R2, R9, and R10; the second pin and the third pin of the chip U2 are connected to the chip U1; one end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R1 is connected to the second pin of the chip U2, and the other end of the resistor R2 is connected to the third pin of the chip U2; the sixth pin of the chip U2 is connected to one end of the resistor R10, the other end of the resistor R10 is connected to one end of the resistor R9, and the other end of the resistor R9 is connected to the seventh pin of the chip U2; the first pin of the chip U2 is connected to a first preset voltage, and the eighth pin of the chip U2 is connected to a second preset voltage.

5. The PWM wave output device based on PCIE bus according to claim 4, characterized in that: The bus driving module includes a chip U6; the first pin and the twenty-fourth pin of the chip U6 are connected to the second preset voltage; the second pin and the twenty-second pin of the chip U6 are connected to the chip U1; the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin, the ninth pin and the tenth pin of the chip U6 are connected to the digital isolation module; the fourteenth pin, the fifteenth pin, the sixteenth pin, the seventeenth pin, the eighteenth pin, the nineteenth pin, the twentieth pin and the twenty-first pin of the chip U6 are connected to the controlled device.

6. The PWM wave output device based on PCIE bus according to claim 3, characterized in that: The FPGA chip is an XC7K325T-2FFG900I chip.

7. The PWM wave output device based on PCIE bus according to claim 4, characterized in that: The chip U2 is a dual-channel digital isolation chip ADuM3200.

8. The PWM wave output device based on PCIE bus according to claim 5, characterized in that: The chip U6 is a bus driver chip SN74LVCC3245DW.

9. The PWM wave output device based on PCIE bus according to claim 4, characterized in that: The first preset voltage is 3.3V.

10. The PWM wave output device based on PCIE bus according to claim 4 or 5, characterized in that: The second preset voltage is 5V.

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